TWI246788B - Electromechanical memory array using nanotube ribbons and method for making same - Google Patents
Electromechanical memory array using nanotube ribbons and method for making same Download PDFInfo
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- TWI246788B TWI246788B TW092100450A TW92100450A TWI246788B TW I246788 B TWI246788 B TW I246788B TW 092100450 A TW092100450 A TW 092100450A TW 92100450 A TW92100450 A TW 92100450A TW I246788 B TWI246788 B TW I246788B
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- Prior art keywords
- nanotube
- layer
- circuit
- conductive
- support
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C23/00—Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
- G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H1/00—Contacts
- H01H1/0094—Switches making use of nanoelectromechanical systems [NEMS]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/10—Resistive cells; Technology aspects
- G11C2213/16—Memory cell being a nanotube, e.g. suspended nanotube
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/81—Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/724—Devices having flexible or movable element
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
- Y10S977/742—Carbon nanotubes, CNTs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/788—Of specified organic or carbon-based composition
- Y10S977/795—Composed of biological material
- Y10S977/796—Composed of biological material for electrical or electronic purpose
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10S977/00—Nanotechnology
- Y10S977/84—Manufacture, treatment, or detection of nanostructure
- Y10S977/849—Manufacture, treatment, or detection of nanostructure with scanning probe
- Y10S977/855—Manufacture, treatment, or detection of nanostructure with scanning probe for manufacture of nanostructure
- Y10S977/856—Manufacture, treatment, or detection of nanostructure with scanning probe for manufacture of nanostructure including etching/cutting
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10S977/888—Shaping or removal of materials, e.g. etching
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/943—Information storage or retrieval using nanostructure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24893—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including particulate material
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Description
1246788 A7 B7 五、發明說明(1 ) 4r 相關申請案之相互參考: 本申請案係相關於以下的申請案,所有以下的申請案 均在與此申請案所提出申請的相同日期上提出申請,所有 以下的申請案係讓受給本申請案的讓受人,而且其係在此 5 完全引用併入本案做為參考: 具有奈米管機電記憶體的混合電路(美國專利申請案 序號,尚未讓受);以及 具有以奈米管技術構成之功能電路胞選擇電路的機電 記憶體(美國專利申請案序號,尚未讓受)。 10 發明背景: 1. 本發明所屬之技術領域: 本發明一般係關於使用作為電子裝置之記憶體儲存的 非揮發性記憶體裝置,而且更特別地關於使用機電元件作為 15 個別記憶體單元的非揮發性記憶體陣列。 2. 先前技術: 經濟部智慧財產局員工消費合作社印製 電子裝置之記憶體單元的重要特徵係為低成本、非揮 發性、高密度、低功率以及高速率。習知的記憶體解釋包括 20 唯讀記憶體(ROM)、可程式唯讀記憶體(PROM)、電子 式可程式記憶體(EPROM)、電子式可拭除可程式唯讀記 憶體(EEPROM)、動態隨機存取記憶體(DRAM)以及靜 態隨機存取記憶體(SRAM)。 ROM相當低成本,但卻無法寫入。PROM可電子式程 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1246788 A7 B7 五、發明說明(2 ) 式化’但部具有單—寫人循環。EPROM 具有相對於ROM 與PROM寫入猶環而言快速的讀取循環,但卻僅在一些重 複寫入/靖取循%上具有相當長的拭除時間與可靠度。 EEPROM (或快閃記憶體々)花費不多,並具有低功率損 5耗’但相車乂於DRAM或SRAM卻具有長寫入循環(ms)與 低相對速度。快閃記憶體同樣具有導致低長期可靠度之有限 數目的⑼取/;^人循環。RQM、PRQM、⑽以及 EEPROM均為非揮發性,其係意味著假如將到記憶體之功 率中斷的A ’違記憶體將保留儲存於記憶體單元中的資訊。 ίο DRAM儲存用作電容器之電晶體閘門上的電荷,但卻 在電容裔放電之]Iff,7 #丄& 必/員猎由舄要分隔電路以、、更新〃記憶 體内今1¾電子式地更新每稍許毫秒的複雜系統設計。 SRAM不需要更新,而且相對於dram來說是快速的,但 卻相對於DRAM具有較低密度,而且更貴。SRAM與 15 DRA二兩者均為揮發性,其係意味著假如將到記憶體的功 率中斷士的居,違,己憶體將損失儲存於記憶體單元中的資訊。 、、口果現存技術係為非揮發性,但卻無法隨機存取, 亚且具有低松度、两成本、與限制性能力,以允許具有電路 經濟部智慧財產局員工消費合作社印製 功此之回可罪度的多重寫人’或者它們為揮發性以及複雜系 20統設計,或者具有低密度。一些出現的技術則已經嘗試對付 這些缺點。 例如,磁RAM ( MRAM )或強磁RAM ( FRAM )應用 磁化的疋向或強磁化區域,以產生非揮發性記憶體單元。 MRAM應用一抗磁記憶體元件,其係包含產生非揮發性之 -4- 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公复) 1246788 A7 B7 五、發明說明(3) 強磁性材料的各向異性抗磁性以及巨大磁阻性。所有這些型 態的記憶體單元具有相當高的阻抗以及低密度。同樣以將取 決於磁通道連接的不同記憶體單元作檢測,但其卻已經無法 導致大規模商品化的MRAM裝置。FRAM使用類似DRAM 5 的電路結構,但DRAM卻使用薄膜鐵電電容器。此電容器 意圖在將外部施加電場移除,以產生非揮發性記憶體之後, 保留它的電極性。FRAM受限於大的記憶體單元尺寸,而將 其製成大型積體元件則有困難。參見美國專利案第 4,853,893 號;第 4,888,630 號;第 5,198,994 號。 10 另一具有非揮發性記憶體的技術是相位改變記憶體。 此技術經由合併譬如硒或碲元素之薄膜合金的結構性相位改 變而儲存資訊。這些合金意圖在結晶與非結晶的兩狀態中保 持穩定,以允許雙穩定切換器的形成。當碰上非揮發性情況 時,此技術看起來好像會因操作速度慢、製造困難度與可靠 15 度而更糟,而且沒有達到商品化的狀態。參見美國專利案第 3,488,302 號;第 4,845,533 號;第 4,876,667 號;第 6,044,008 號。 經濟部智慧財產局員工消費合作社印製 同樣已經提出線交錯式記憶體(MWCM)。參見美國 專利案第 6,128,214 號;第 6,159,620 號;第 6,198,655 號。 20 這些記憶體計晝將分子想像成雙穩定切換器。兩線(金屬或 半導體型態)具有分子或分子化合物層夾於其間。將化學組 件以及電化氧化或還原使用,以產生一''開啟〃或 ''關閉〃 狀態。此型式的記憶體需要高度特殊化的線連接,並且因為 在氧化還原過程中所發現的固有不穩定性而可能不保留非揮 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 1246788 八7 B7 五、發明說明(4) 發性。 目前,已經提出使用奈米線的記憶體裝置,譬如單牆碳 奈米管,以形成交錯連接來當作記憶體單元。參見 W001/03208,以奈米線為基礎的裝置、陣列、以及它們的 5 製造方法;以及Thomas Rueckets等人的、'分子計算用之以 碳奈米管為基礎的非揮發性隨機存取記憶體〃科學,第289 冊,第94-97頁,民國89年7月7日。於下文將這些裝置 稱為奈米管線交錯式記憶體(NTWCMs)。在這些計畫之 下,懸掛於其他導線上的個別單牆奈米管線定義出記憶體單 10 元。將電信號寫入到一或兩導線,以使它們彼此物理式地接 觸或排斥。各物理狀態(亦即,相吸或相斥的導線)對應一 電狀態。相斥的導線係為一開啟電路連接。相吸導線則為形 成一整流連接的關閉狀態。當將電力從該連接移除時,該導 線則維持它們的物理(以及因此的電性)狀態,從而形成一 15 非揮發性記憶體單元。 經濟部智慧財產局員工消費合作社印製 迄今為止的NTWCM計畫取決於直接成長或化學自動 組裝技術,以成長記憶體單元所需的個別奈米管。令人相信 的是,這些技術在使用現代技術的商業規格上應用有其困難 度。更者,它們可能包含固有的限制,譬如使用這些技術而 20 可能可靠成長的奈米管長度,而且它可能很難控制如此成長 之奈米管線之幾何結構的靜態變化。 發明内容: 本發明提供機電電路,譬如記憶體單元及其製造方法。 -6- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1246788 ____ B7 五、發明說明(5 ) 該電路包括具有導電軌條的結構,以及從該基板表面延伸的 支撐物,以及由橫越導電軌條之支撐物所懸掛的奈米管帶, 其中各帶包含一或更多奈米管。 根據本發明一態樣,機電電路元件係藉由提供具有導 5電軌條與支撐物的結構所製成,其中該支撐物則從該基板的 表面延伸。將一奈米管層設置於支撐物上,而且將該奈米管 層部份選擇性地移除,以形成橫越該導電執條的奈米管帶。 各帶包括一或更多個奈米管。 實施方式 經濟部智慧財產局員工消費合作社印製 本發明之較佳具體實施例提供新機電記憶體陣列及其 製造方法。特別地,將機電記憶體單元產生,其操作起來 類似揭露於W001/03208的NTWC1V[裝置,在此完全引用 併入於本文中。不過,不像在W001/03208中所揭露的 15 NTWCM裝置,本發明之具體實施例以從一不整齊的奈米 管層或一不織布奈米管組織製得的新帶來替代使用於 NTWCM裝置中的懸掛奈米線。這些新裝置在此稱為奈米 管帶交錯式記憶體(NTRCMs)。新奈米管帶狀結構確信 可更簡單地以希望程度的整合與尺度來予以建立(以製成 20的裝置數目),而且該幾何結構能更簡單地予以控制。 因為新奈米管帶交錯型記憶體裝置類似NTWCM地 操作,所以對它們操作結構與原理之說明則會簡短。將為 了更完整的說明與背景而參考W001/03208。 圖1說明根據本發明較佳具體實施例之原理而構成的 -7- 本紙張尺度適用中國國家標準(CNS)A4規格(2i〇X297公髮) 1246788 —___B7 五’發明說明(6 ) " -- 示範性機電記憶體陣列1〇〇。 該陣列具有可處於、、開啟々狀態1〇5或、'關閉,,狀能 106的複數個非揮發性記憶體單元1〇3。此等單元的真= 數目對暸解本發明來說不重要,但是該技術卻可能支'貫呈 5有相等或大於現代非揮發性電路裴置之訊息儲存容晋沾= 置。 的裝 各記憶體單it 1〇3包括由例如1〇4之電性軌條或導線 上的一或更多個支撐物102所懸掛的奈米管帶1〇1。、、 帶101以及例如104之導線的各交叉形成交錯連接 1〇處並且疋義一圮憶體單元。在某些具體實施例之下,各 單元可能藉由將電流與或電壓施加到電極112而讀取並寫 ^ ’電極112係與帶1〇1電性互連,或者經由電極(未顯 示).而與軌條或導線1〇4互連。支撐物1〇2係由氮化矽 (SlgN4)層108製成。在層1〇8之下的是將仏摻雜矽軌 15條ι〇4與打底矽晶圓11〇分隔的閘門氧化物層109。 經濟部智慧財產局員工消費合作社印製 共同參考圖1-2B,連接處1〇6說明在第一物理與電性 狀恶中的單元,其中奈米管帶101係與相對應的軌條104 隔開連接處105說明在第二物理與電性狀態中的單元, 其2奈米管帶101係朝著相對應軌條1〇4而偏斜。在第一 2〇狀怨巾’该連接處是—開啟電路,當如此定址時,該連接 處可能在帶1〇1或軌條1〇4本身上予以感應。在第二狀態 中,该連接處是一整流連接處(例如,8〇11(^]^或 PN)而當如此定址時,該連接處可能在管101或軌條 1〇4本身上予以感應。 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 1246788 五、發明說明(7) 在某具體實施例之下,奈米管帶HH可能藉由摩捧力 而固持於支承物上的適當位置。在另外的具體實施例中, 帶可能由其它構件所固持,譬如藉由使帛_髓__ 10 15 經濟部智慧財產局員工消費合作社印製 20 者而來將帶加關切物。此賴力可經由化學相互作用 之使用而增加’包括經由譬如⑼其它化學反應種類之碳 化物之使用的共價鍵合。蒸發或自旋塗敷材料,譬如金 屬、半導體、或絕緣物,尤其是石夕、鈦、氧化石夕、或者聚 醯亞胺,其係可同樣地加進,以增加自旋強度。奈米管帶 或個別奈米管,其係可同樣經由黏合到表面的使用晶圓而 予以扣住。參見IU.Chen等人之 ''蛋白質固定狀單牆碳 奈米管的非共價邊牆函數化" J.Am.Chem.S〇C”123,2001,3838-39 與 Dai 等人的
ApPl.Phys Lett.,77,2000,3015_17,用於經由金屬而扣住並 塗敷奈米官用的示範性技術。同樣參見W001/03208之技 術。 在圖2A-B所示的某較佳具體實施例之下,奈米管帶 101具有大約180nm的寬度,其係並且扣住到較佳由氮化 矽製成的支撐物102。於帶101下面之執條1〇4的局部區 域形成了 η-摻雜矽電極,其係並且靠近支撐物1〇2地放 置,而且較佳地沒有寬於奈米管帶,例如180nm。從支樓 物102頂部到奈米管帶ιοί附著到電極2〇6之偏斜位置的 相對間隔208 (見圖2B)應該大約為5-50nm。間隔208 之量值係設定成適合記憶體裝置的機電切換性能。就此具 體實施例而言,5_50nm之間隔較佳地用於應用由碳奈来 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 五、 發明說明(8) 但是其它的間隔則可能 趣結能量之間的相互二張力能 10 15 20 常較小(或較大)的尺寸,以反映出製造有非 I之,成長或化學式— 佳,體^施例應用包含薄膜與微影的製造技術。此製造^ 法‘致匕本身產生於大表面上,尤其是至少六英忖的晶 f (反t於超過次毫米距離之距離上成長個別奈米 :在見在疋不可行的)。該些奈米管帶應該於個別奈米 &上顯現改善的容錯,其乃藉由提供包含於奈米管帶之傳 =路t的几餘性。(假如一個別奈米管打斷肋部内之其它 官而提供傳導路徑的話,假設單一奈米管使用該單元將是 錯誤的。)再者,因為帶可能製成具有比個別奈米管還更 大的截面面積,所以帶的電阻應該明顯地低於個別奈米管 的電阻,從而降低它的阻抗。 圖3說明製造NTRCM裝置1〇〇之某些具體實施例的 方法。將一第一中間結構302產生或提供。在所說明的具 體實施例中,結構3〇2包括具有絕緣層1〇9 (譬如二氧化 砂)的石夕基板110,以及定義複數個支撐物102的氮化矽 -10- 本紙張尺度適用中國國家標準(CNS)A4規格(21〇χ297公釐) 1246788 A7
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^6788 、發明說明 , 某些成:傾向:相對地稀少。在 化,以協助成長具有特定:产劑3°8可能圖案 奈米总。各 、么又如希望更大或更小密度的 時間:善:制時化::二的情況、成長環境、與 單層奈米管的_特定二二=均句地分佈於主要為一 制,其係包括伸並未;二田的成長需要參數之控 面之乐童催化劑化合物與濃度、打底表 數 真^錄讀(長度與RPM (每分鐘轉 10 15 經濟部智慧財產局員工消費合作社印製 20 ^)、成長時間、溫度與氣體濃度。 3U ^^==到層312並圖案化’以在奈米管 ?不正,的層中定義帶。帶圖案越過(例如,垂直 的1=條104。將光阻移除,以使不織布奈米管組織 '置於平表面306上,以形成第四中間結構318。 的=L中間結構318具有如所示暴露之打底犧牲層304 ^伤320。隨後將該結構318以譬如氫氟酸的酸來處 Μ =除犧牲層则,包括在帶1〇1以下的部份,從而 陣==於執條104上並由支標物1〇2所支擇之帶ι〇ι的 :能:用嶋生的金屬化,以形成定址 如 圖1所不的112。 以上技術之-態樣係為種種成長、圖案化、 作可能使用習知技術,譬如微影 在二二, 可能需要大約一和〜4二 如,帶101之寬度),但是假如製造性能允許的話,該元 -12^ 本紙張尺度適用中國國家標準(CNS)A4規格(210x297^Jy Ϊ246788 B7 五 發明說明(n ) 件的物理特性則能修改到甚至更小的特徵尺寸。 誠如將於以下所說明的,有許多產生如上述之中間結 構或類似結構的可能方法。例如圖4顯示產生第一中間結 構302的一方法。 5 10 15 20 —矽晶圓400設有一氧化物層402。該氧化物層的厚 度較仏地為少許奈米,但卻可以是1 # m那麼多。氮化石夕 (SisN4)層404沈積於氧化物表面402頂部。氮化矽層較 佳地至少30nm厚。 氮化矽層404隨後予以圖案化與蝕刻,以產生空穴 6以形成支撐結構407。由於現代技術,該空穴寬度可 旎大約180nm寬或者更小。剩下的氮化矽材料則界定出該 支撐物102 (例如,為行,或者列)。 隨後將η-摻雜矽的遮蓋物408沈積,以填滿該空穴 =6。示範性具體實施例用的遮蓋物4〇8可能大約為 厚,但卻可能為30nm那樣的厚度。 、,Ik後將遮蓋物408加工處理,例如藉由厚矽層的自動 弄平’或者藉由退火,以產生上述的平表面,以形成 結構411。在自動弄平的情形中,可能將具有終點制 *EPD)的反應性離子钮刻(RIE)應用,直到達到触刻 氮化石夕的上表面41〇為止。 隨後將該結構411氧化,以形成並界定深入平表面 大約10-2Gnm深的Si〇2犧牲層3〇4。 不轉變的矽剩下部份則形成執條1〇4。 β頁丁可月b使用來產生某些具體實施例之 -13- 1246788 Λ7 B7 五、發明說明(12 ) 裝置100的另一方法。將像相關於圖4而說明的支撐結構 407設置。隨後使用CVD製程、濺射、或電鍍而將卜摻 雜石夕層514加入。在某些具體實施例下,將層514加入到 大約一半Si3N4支撐物1〇2的高度。 5 在加入層514之後,將退火步驟執行,以產生平面化 表面306 ’以形成像上述說明的結構411。退火步驟導致 石夕層514流入空穴406内。 相關於圖4而說明者,隨後將結構411氧化,以形成 並定義深入平表面306内大約l〇-20nm的Si〇2犧牲層 10 304 。 圖6顯示用來形成一替代性第一中間結構3〇2,的另一 方法。在此具體貫施例中,石夕基板6〇〇係覆蓋以高度604 至少30nm的氮化矽層602。 隨後將氮化矽層602圖案化與蝕刻,以產生間隙 15 606,並且定義支撐物102。該蝕刻製程暴露出矽基板6〇〇 表面的部份608。 將暴露出的石夕表面608氧化,以產生厚度為些許nm 的一氧化石夕(Si〇2)層610。這些層610最終與執條 經濟部智慧財產局員工消費合作社印製 絕緣,其係與絕緣層1〇9為了上述結構302而進行的方式 20 類似。 旦已經將絕緣層610產生的話,軌條1 〇4則可能以 各種方式的任一種來產生。圖6說明產生此等軌條以說明 此觀點所使用之圖4-5的製程步驟。 圖7顯示形成第一中間結構302所用的另一方法。具 -14- 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 五、發明說明(13) 有二氧化矽層702與氮化矽層7〇4的矽基板7〇〇接收一圖 案化的光阻層706。例如,可能將光阻層自旋塗敷於層 704上’隨後並曝光以及微影顯影。 曰 隨後可能使用反應性離子蝕刻(RIE)或類似方法, 5以蝕刻叫队層704,以形成空穴708並且定義支撐物 102。 # 之後’可能將η-摻雜矽710沈積於空穴yog中。在某 些具體實施例下,將矽沈積到大約與SbN4支撐物1〇2之 咼度712相等的高度。 1〇 隨後將光阻706與光阻706頂部的矽710剝去,以形 成與上述類似的中間結構411。 乂 隨後將結構411氧化,以產生犧牲si〇2層3〇4。 圖8顯示用來形成第一中間結構3〇2的另一方法。在 此方法之下,設置了起始結構8〇〇,其係具有最低矽層 15 802,而最低二氧化矽層804係在其頂部。第二矽層8曰〇6 係在層804頂部,而第二二氧化石夕| _則在第 806頂部。 曰 將頂邛一氧化矽(Si〇2)層8〇8藉由光微影而圖案 化以產生RIE遮罩810。使用該遮罩,以將第二矽層 2〇 806之暴露部份812向下關到第一二氧化石夕層_。曰此 蝕刻產生空穴814並且定義執條104。 3亥空穴814係充填並覆蓋以氮化矽(Si3N4) 816。
Si3&遮蓋物816係以RIE而往後蝕刻到與遮蓋&摻雜 矽電極104之Si〇2層8〇6剩下部份的相同高度818 (其係 1246788
形成犧牲層304)。 圖9顯不形成—替代性第一中間結構302,,的、 在此方法之下,類似4〇7 (顯示於圖4,但非方法。 則予以設置。纽情形中,_4支糾1(^ )的制 10 15 經濟部智慧財產局員工消費合作社印制衣 20 3〇mn的高度。薄金屬層9()2係沈積於秘、=約 部,以及如項目903所描述,在空穴9〇4底牙頂 吨頂部。金屬9〇2與903形成暫時電極份 9〇6隨後可能由電鍍而來沈積或成長,遮蓋該電=層亩 到矽906達到在支撐物1〇2頂部的高度9〇8為止、 觸電極術。該成絲程可能由流動於下與上接 902,3之間之電流的開始所控制。 …α 隨後可能將該暴露的金屬電極變藉由濕、 或乾式化學方法而移除。這會形成像上述結構川^中間 結構411,,但卻具有隱埋電極9〇3,以作為石夕成長製程^ 加工品。 隨後如上述地,將結構411,氧化,以形成犧牲層3〇4 於石夕的暴露部份。例如,可能將層綱長到大約丨〇 厚度。 圖10顯不形成第一中間結構3〇2用的另一方法。具 有二氧化矽層1004於其頂部以及第二矽層1〇〇6 (〜摻/、 雜)於層1004頂部的矽基板1〇〇2係使用為起始材料。遮 罩層1008係光微影地圖案化於層1〇〇6頂部。 使用氮化技術,η-摻雜矽層1〇〇6的暴露部份1〇1〇係 化學式地轉換成SbN4支撐物1〇2。層1〇〇6的未轉換部份 -16- 1246788 A7 B7
則形成軌條1〇4。 5 10 15 經濟部智慧財產局員工消費合作社印製 20 類似上述,將遮罩1008移除,以形成結構4ιι ㈣表面的暴露部份㈣氧化,成s㈣ 圖11顯示形成-替代第一中間結構302”用的方法。 在此方法之下,將石夕基板102塗層以薄膜11(M,以 作為-起始結構。在氮化石夕層1104頂部,n_摻雜石夕藉由 RIE而予以加入並且微影圖案化,以形成軌條104。 將執條104表面氧化以形成Si〇2層11〇6,該s幻声 1106則以犧牲層304,的替代形式起作用。 2每 將该結構長滿8丨3队11〇8並且往後蝕刻,以形成平表 面且形成替代㈣—巾縣構地,,。誠如將為孰諸 ^技連者所明瞭的’在此方法下,當隨後將犧牲層移除 時’執條1〇4縣與支撐4勿1〇2隔開。可能應曰: 其它變化,以產生軌條1G4的替代橫截面。例如 =04產生,以具有環形頂部’或者具有三角形:弟 形截面。此外,該截面可能具有其它形式,譬如具有錐形 邊的二角形。 誠如以上所說明的,一旦將一第一中間結構形成的 話,例如302,不整齊的奈米管層312則設置於結7構川二 的平表面306上。在較佳具體實施例中,不織布二織 312則經由催化劑3〇8之使用以及成長環境之控制3 於該結構上。其它具體實施例則可能分別提供不整1成^ 米管層312,並且將它直接地施加於結構3〇2上。"^然不
本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
1246788 A7
則可能非必要 10 15 3二致此等奈米管之下邊接觸中間結構 302的千表面3〇6,所以它們則如圖12所建議,顯干一 '、自動寺徵。特別是’各別奈米管傾向於黏 當積極有利時它們所成長的表面,以致於 、背來形成。-些奈米管可能成長於另一夺;管二 如此該單㈣令人不輕是完美的。各別奈 、w ’但卻因為凡得瓦力而確實彼此黏附。圖 為真貫奈米管不織布組織的大概描述。因為奈米管的小特 徵尺寸’所以甚至現代的掃聪電子顯微術還是無法直 實組織、'縣〃而不失其準確性;奈米管具有與1·2_1 樣小的特徵尺寸’其係小於SEM (掃瞒型電子顯微鏡)之 準確度。圖12例如,建議該組織的不整齊的特性;不 經 濟 部 智 慧 財 產 局 員 工 20 過’從該W式所不清楚的是,馳織可能具有不連續的小 區域而沒有管存在。各管基本上具有直徑(從而定 義出大約l-2nm的組織層),但卻可能具有些許微米的長 度,,可能與200微米一樣長。該管可能彎曲,而且偶爾 彼此父又。管經由凡得瓦力而彼此黏附。 消 費 合 作 社 印 製 在某些具體實施例下,奈米管實質無抑制地在^與 y-軸方向中成長,但卻因為自動組裝特徵而在軸上(垂 直圖12的頁面)實質地受限。其它具體實施例可能由於 %疋向或流動定向成長技術之使用而將以上方法增補到成 -18- 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 1246788 A7
1246788 A7 ----- Β7 五 、發明說明 18 法之下,§己憶體結構將不僅以非揮發方式來儲存記憶體内 容’而且亦將固有地儲存最後的記憶體位址。 10 15 經濟部智慧財產局員工消費合作社印製 20 以奈米管為基礎的記憶體單元具有雙穩定性,其特徵 為在0〃與、、1〃狀態之間的高比例電阻。這些狀態之間 的切換係由橫越奈米管帶或導線以及打底軌條之特定電壓 的施加所完成,其中至少其中之一個記憶體單元元件是奈 米管或奈米管帶。在一方法中,將一、、讀出電流//施加, 而且越過此連接處的電壓則由、、感應放大器〃所決定。讀 取是非破壞性的,其係意味該單元保持它的狀態,而且如 同以dram來進行的,沒有回寫操作是需要的。 圖14說明一分叉二元選擇系統,或解碼器14⑻。誠 如將於以下所說明的,解碼器14〇〇可能以奈米管或奈米 管帶技術來實施。再者,解碼器可能架構在例如說㈤ 或NTWCM之奈米管記憶體單元陣列的相同電路元件上。 如點1402所描述之兩線14〇4與14〇6的垂直交會 處,指示了兩奈米管或奈米管帶的連接處。在此關係曰上, 該交會處類似在CMOS與其它_巾職_、、傳遞電晶 體,其中該交會處可能開啟或關閉。 s如1420的位置,在此—奈米管或奈米管帶可能彼 此交錯,但卻不打算產生—縱橫的連減,可能由於元件 間之微影圖案化的絕緣體而彼此絕緣。 為了清楚,所說明的解碼器係用於運行於定址線 1408上的3位元二元位址。兮六 位址4父會處(點)將取決於該解 碼值而予以切換,則;t僅產生感應電流〗所可能通過的一 本紙張尺度適用中國國家標準(CNS)A4l^r(2丨〇 -20- 1246788 j—--— —_ B7 五、發明說1摩 路徑,以選擇線1418。 為了使用此技術,二元位址之各位元的、、雙軌〃表像 係在外部成形,以致於各位址位元1410以真實與互 補的形式來呈現。因此,線1406可能是位址線14〇8a的 5邏輯真實版本,而且線1407可能是位址線1408a的邏輯 補充。表像1408的電壓值則符合如上述將一縱橫連接處 切換到Μ或〃 、、〇〃狀態所需要者。 ’、 七在此方式中,可能將一位址14〇8使用,以供應感應電 流I到一陣列中的一位元或成排的位元,例如到奈米管或 10奈米管帶。同樣地,可能使用相同方法,以感應出一特定 的軌條,例如選擇具體陣列的列,以結合行之選擇而讀取 感應。因此,此方法可能使用於讀取與寫入操作兩者用的 X與/或Υ解碼。 經濟部智慧財產局員工消費合作社印制衣 本發明某些具體實施例提供一混合式技術電路 15丨5〇〇其係顯示於圖丨5中。核心記憶單元陣列1502係使 用NTWCM或者NTRCM來構成,而且該核心由形成X 與Y位址解碼器15〇4與15〇6 ; χ與γ緩衝器l5〇8與 1510 ;控制邏輯1512與輸出緩衝器1514的半導體電路所 圍繞。圍繞NTWCM或NWB CM核心的電路可能使用於 20習知的相互功能,包括提供讀取電流與感應輸出電壓。 在另外的具體實施例中,X與γ位址解碼器15〇4與 1506可肖匕以上述的奈米管導線或帶式定址技術來取代。在 运些具體實施例中,該核心將包括記憶體單元與定址邏 輯。 -21- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) " -- 1246788 A7 B7 五、發明說明(2〇 ) 在某些具體實施例中,混合式電路15〇〇可能經由使 用一奈米管核心(僅具有記憶體單元或記憶體單元與定址 邏輯)以及經由執行使用現場可程式閘門陣列的環繞電路 來形成。假如希望的話,該核心與閘門陣列電路可能包含 5於單一的物理式封裝中。或者,它們可能予以個別地封 裝。例如’密封式封裝奈米管電路(具有記憶體或記憶體 與定址邏輯)可能與PLD (可程式邏輯裝置)/FPga (現 場可程式閘門陣列)/ASIC (特殊應用積體電路)結合, 其中則包含有I/O (輸入/輸出)介面邏輯。最終的小型晶 10片組對該產品使用者所用之NT (奈米管)記憶體的優點 提供存取’而卻將、、現成”技術之使用最大化,其係可能 經由製造商而根據需要為基礎來應用。 圖16說明混合式技術的一可能實施過程1600。包含 緩衝與控制邏輯(上述)的FPGA晶片16〇2,其係經由一 15 (或許多層)印刷電路板上(PCB) 1604的傳導軌條,而 連接到包含記憶體單元與定址邏輯的一奈米管(NT)晶 片 1606 。 經濟部智慧財產局員工消費合作社印製 建議此特別的具體實施例符合典型為今日個人電腦的 PCI匯流排標準。其它被動電路系統,譬如電容器、電阻 20器、變壓器等等(未圖式),其係將同樣必須符合PCI標 準。將200MHZ-400MHZ的前側匯流排速度作注釋,其係 建議此一晶片組可能運行之外部時脈速度的種類。此速度 係由PCB (印刷電路板)互連與FpGA/pLD/ASIC速度, 以及同樣地晶片封裝,而非Ντ (奈米管)記憶體單元速 •22- 本紙張尺度_中_家標準((:>^^721叭297公^ 1246788 A7 五、發明說明(2] 度所限制 其它具體實施例 除了碳奈米管之外,具有適合機電切換之電子與機械 特性的其它材料是可以想像的。這些材料將具有類似碳奈 米官的特性,但卻具有不同以及很可能降低的張力強度。 口玄材料的張力應變與黏著能量必須位於一範圍内,以允許 連接處與機電切換特性的雙穩定性,以存在於可接受容差 内。 10 15 經濟部智慧財產局員工消費合作社印製 20 為了整合用來定址之CMOS邏輯之目的,可想像兩 種方法。在第一具體實施例中,奈米管陣列將在金屬化之 前,㈣卩在CMOS邏輯裝置之離子植从及平面化以後整 合。第二方法包含在包含離子植入與高溫退火步驟之 CMOS裝置製造以前的奈米管陣列成長。在這些步驟完成 之後’奈米管帶與CMOS裝置兩者的最後金屬化則將使用 標準與廣泛使用的協定而立即進行。 由某金屬或半導體線頂部之n_摻雜频成的電極則可 同樣地令人想像。這仍將提供在QN狀齡的整流連接 處,以致於沒有複數條電流路徑存在。 除了整流連接處之外,還有其它廣泛接受與使用的方 法,以避免電性串音(亦即’複數條電流路徑)之發生於 縱橫陣列中。在靜態、微影製造之電極頂部上的通道阻障 物,其係避免歐姆開啟狀態的形成。在零偏壓上,將沒有 漏電流之發生’但是-小偏壓則必須施加於電體,以 -23- 1246788 A7 B7 五、發明說明(22 ) 克服此阻障物以及交叉線之間的通道。 可想像經由使用離子、共價、或其它力而增加黏著能 量的方法,以改變與電極表面的交互作用。這些方法可使 用來以這些連接處而擴展雙穩定性的範圍。 5 奈米管可以用譬如焦油腦的平面結合碳氫化合物而功 能化,該平面結合碳氫化合物隨後可能有助於增進帶内、 奈米管之間的内部黏著。 某些上述態樣,譬如用於定址的混合式電路以及奈米 管技術,其係可應用到個別奈米管(例如,使用直接成長 10 技術等等)或奈米管帶。 將進一步理解的是,本發明之範圍並不受限於上述具 體實施例,但卻確切地由附加申請專利範圍所定義,而且 這些申請專利範圍將包含已經予以說明的修改與改善。 15 圖式之簡單說明: 在圖中, 圖1說明根據本發明某具體實施例而設計之奈米管帶 交錯記憶體裝置; 經濟部智慧財產局員工消費合作社印製 圖2A-B說明根據本發明某具體實施例而設計之記憶體 20 單元的兩狀態; 圖3說明根據本發明某具體實施例來製造記憶體裝置 的動作; 圖4-11說明根據本發明某具體實施例,產生用來製造 記憶體裝置之中間結構的各種型式; -24- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) A7 1246788 B7 五、發明說明(23 ) 圖12說明製造本發明某具體實施例所使用之不織布奈 米管組織,或者不整齊的奈米管層; 圖13說明與本發明某具體實施例之隱藏、打底軌條有 關的不整齊的奈米管層; 5 圖14說明本發明某具體實施例的定址邏輯; 圖15說明本發明之混合技術具體實施例,其中該記憶 體核心使用奈米管技術;以及 圖16說明本發明之混合技術具體實施例,其中該記憶 體核心與定址線則使用奈米管帶技術。 10 15 經濟部智慧財產局員工消費合作社印製 20 -25- 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 1246788 A7 B7 五、發明說明(24 ) 圖式之代號說明: 示範性機電記憶體陣列100 奈米管帶101 支撐物102 5 非揮發性記憶體單元103 電性軌條或導線104 連接處105 連接處106 打底矽晶圓110 10 氮化矽(Si3N4)層108 閘門氧化物層109 電極112 電極206 間隔208 15 第一中間結構302 替代性第一中間結構302’ 替代性第一中間結構302” 經濟部智慧財產局員工消費合作社印製
Si〇2犧牲層304 犧牲層304’ 20 平表面306 催化劑308 第二中間結構310 奈米管不整齊層312 第三中間結構314 -26- 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 1246788 A7 B7 五、發明說明(25 ) 第四中間結構318 暴露之打底犧牲層的部份320 陣列322 矽晶圓400 5 氧化物層402 氮化矽(Si3N4)層404 空穴406 支撐結構407 遮蓋物408 10 上表面410 結構411 結構411’ η-摻雜矽層514 ^夕基板600 15 氮化矽層602 高度604 間隙606 經濟部智慧財產局員工消費合作社印製 暴露出的矽表面608 二氧化矽(Si〇2)層610 20 矽基板700 二氧化矽層702 氮化矽層704 圖案化的光阻層706 空穴708 -27- 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 1246788 A7 B7 五、發明說明(26 ) η-摻雜矽710 高度712 起始結構800 最低矽層802 5 最低二氧化矽層804 第二矽層806 第二二氧化矽層808 RIE遮罩810 暴露部份812 10 空穴814 經濟部智慧財產局員工消費合作社印製 氮化矽(Si3N4) 816 高度818 薄金屬層902 金屬903 15 空穴904 矽906 高度908 矽基板1002 二氧化矽層1004 20 第二矽層1006 遮罩層1008 暴露部份1010 矽表面的暴露部份1012 Si3N4 薄膜 1104 -28- 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 1246788 Λ7 B7 五、發明說明(27 )
Si〇2 層 1106 Si3N41108 解碼器1400 點 1402 5 線 1404 線 1406 定址線1408 位址線1408a 位址位元1410 10 線 1418 位置1420 經濟部智慧財產局員工消費合作社印製 混合式技術電路1500 核心記憶單元陣列1502 X位址解碼器1504 15 Y位址解碼器1506 X緩衝器1508 Y緩衝器1510 控制邏輯1512 輸出緩衝器1514 20 實施過程1600 FPGA 晶片 1602 印刷電路板上(PCB) 1604 奈米管(NT)晶片1606 互連結構1706 -29- 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) A7 1246788 B7 五、發明說明(28 ) 中間結構1800 奈米管帶圖案1802 中間結構1804 電子製程位置或邏輯1806 5 中間結構1808 矽基板1900 二氧化矽層1902 圖案化光阻層1904 空穴1906 10 遮罩圖案1908 光阻1912 光阻頂部的材料1914 氧化鋁(Al2〇3) 1916 中間結構1918 15 Si02 層 1920 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
1246788 A8 B8 C8 D8 六、申請專利範圍 1. 一種製造機電電路元件的方法,包含提供具有導電執條 與支樓物之結構的動作’該支撐物從該基板的表面延 伸; 提供奈米管層於該支撐物上;以及 5 選擇性地移除該奈米管層部份,以形成橫越該導電 軌條的奈米管帶,其中該帶包含一或更多個奈米管。 2. 如申請專利範圍第1項之方法,其中提供結構之動作係 提供一結構,在該結構中該導電軌條係為摻雜矽的軌 10 條。 3. 如申請專利範圍第1項之方法,其中提供結構之動作係 提供一結構,在該結構中該導電軌條係為奈米管。 15 4.如申請專利範圍第1項之方法,其中提供結構之動作係 提供一結構,在該結構中該導電軌條係為奈米管帶。 經濟部智慧財產局員工消費合作社印製 5. 如申請專利範圍第1項之方法,其中提供結構之動作係 提供一結構,在該結構中,該支撐結構係形成為多列的 20 材料,而且其中該些導電軌條實質平行該些列。 6. 如申請專利範圍第5項之方法,其中該軌條與該支撐物 隔開。 -31 - 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 1246788 A8 B8 C8 D8 六、申請專利範圍 7. 如申請專利範圍第5項之方法,其中該軌條接觸該支撐 物。 8. 如申請專利範圍第1項之方法,其中該執條與該支撐物 5 係隔開。 9. 如申請專利範圍第1項之方法,其中該執條接觸該支撐 物。 10 10.如申請專利範圍第1項之方法,其中提供結構之動作 係提供一結構,在該結構中,該支撐物係由氮化矽製 成。 11. 如申請專利範圍第1項之方法,其中提供結構之動作 15 係提供一結構,在該結構中,導電軌條位於絕緣材料層 上,以將該些軌條彼此相對地電氣隔離。 經濟部智慧財產局員工消費合作社印製 12. 如申請專利範圍第1項之方法,其中提供結構之動作 係提供一結構,在該結構中,各導電執條均在絕緣材料 20 上,以電氣隔離該些執條。 13. 如申請專利範圍第1項之方法,其中提供奈米管層的 動作係提供一不織布式的奈米管組織。 -32 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1246788 A8 B8 C8 D8 六、申請專利範圍 14. 如申請專利範圍第13項之方法,其中該組織係成長於 該結構上。 15. 如申請專利範圍第13項之方法,其中該結構包括在該 5 些執條上的一犧牲層材料,而且其中該組織係成長於該 犧牲層上。 16. 如申請專利範圍第14項之方法,其中該結構處理以催 化劑,以促進該組織之成長。 10 17. 如申請專利範圍第15項之方法,其中該犧牲層之上表 面係處理以一催化劑,以促進該組織之成長。 18·如申請專利範圍第1項之方法,其中選擇性移除之動 15 作係包括將奈米管層圖案化與蝕刻以形成該些帶的動 作。 經濟部智慧財產局員工消費合作社印製 19. 如申請專利範圍第13項之方法,其中選擇性移除之動 作包括將奈米管組織圖案化與蝕刻以形成該些帶的動 20 作。 20. 如申請專利範圍第14項之方法,其中該奈米管之成長 實質地不受限於該結構之表面上。 -33 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1246788 A8 B8 C8 D8 六、申請專利範圍 21. 如申請專利範圍第18項之方法,其中圖案化與蝕刻之 動作使用經由該組織而擴散的I虫刻劑。 22. 如申請專利範圍第1項之方法,其中該奈米管層實質 5 上是一單層。 23. —種機電電路,包含: 具有導電軌條的結構,以及從該基板之表面延伸的支撐 物; 10 由該支撐物所懸掛的奈米管帶,該支撐物橫越該導電軌 條,其中各奈米管帶包含一或更多個奈米管。 24. 如申請專利範圍第23項之電路,其中該導電軌條係為 摻雜矽的軌條。 15 25. 如申請專利範圍第23項之電路,其中該導電軌條係為 奈米管。 經濟部智慧財產局員工消費合作社印製 26. 如申請專利範圍第23項之電路,其中該導電執條係為 20 奈米管帶。 27. 如申請專利範圍第23項之電路,其中該些支撐物係為 多列的材料,而且其中該些軌條實質平行該些列。 -34 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1246788 A8 B8 C8 D8 六、申請專利範圍 28. 如申請專利範圍第27項之電路,其中該些軌條與該些 支撐物隔開。 29. 如申請專利範圍第27項之電路,其中該些軌條接觸該 5 些支撐物。 30. 如申請專利範圍第23項之電路,其中該些支撐物由氮 化矽製成。 10 31.如申請專利範圍第23項之電路,其中該些導電執條係 在一絕緣材料層上,以將該些執條彼此電氣隔離。 32. 如申請專利範圍第23項之電路,其中該些導電軌條各 個均在絕緣材料上,以將該些執條電氣隔離。 15 33. 如申請專利範圍第23項之電路,其中該些帶係為一不 織布式的奈米管組織。 經濟部智慧財產局員工消費合作社印製 34. 如申請專利範圍第23項之電路,其中該些帶實質地為 20 —單層奈米管。 -35 - 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐)
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US20040214366A1 (en) | 2004-10-28 |
KR100945403B1 (ko) | 2010-03-04 |
KR20040035691A (ko) | 2004-04-29 |
CN100466181C (zh) | 2009-03-04 |
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CN1557016A (zh) | 2004-12-22 |
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US7511318B2 (en) | 2009-03-31 |
TW200412685A (en) | 2004-07-16 |
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