TWI234854B - Flip chip-in-leadframe package and process - Google Patents

Flip chip-in-leadframe package and process Download PDF

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Publication number
TWI234854B
TWI234854B TW090105620A TW90105620A TWI234854B TW I234854 B TWI234854 B TW I234854B TW 090105620 A TW090105620 A TW 090105620A TW 90105620 A TW90105620 A TW 90105620A TW I234854 B TWI234854 B TW I234854B
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Taiwan
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lead frame
bumps
die
patent application
item
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TW090105620A
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English (en)
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Rajendra Pendse
Marcos Karnezos
Jr Walter A Bush
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Chippac Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

A7 B7 [234854 7340pif.d〇c/〇Q8 五、發明說明（ 本申請案主張美國專利60/188564號『導線架型覆晶 封裝及其製程』，申請日爲2000年3月10日之優先權。 本申請案與與美國申請代理人案號60084-300201『封裝結 構及其封裝方法』以及案號60084-300301『覆晶接合結構』 一起提出申請；上述二申請案與本申請案有相同的申請 曰’其所有之內容倂入參考。 本發明是有關於一種以導線架爲基礎之封裝 —---—— .................. ...... ...... (leadframe_based package )，且特別是有關於一種將晶片 ..一•-一 .….. 以覆晶接合技術連接到導線架上的封裝。 ^+由於以導線架爲基礎之封裝具有較低的製作成本， 因此被廣泛的應用於電子封裝上。典型的第一階段（the first level )之接合通常以靜線（wire bonding )的方式完成。 近來，基於增進元件電性表現的考量，特別是應用於射頻 方面之元件（RF device )，衍伸出將晶片以『覆晶』接合 技術連接到導線架上的封裝。 傳統以覆晶接合封裝之元件使用凸塊（bump )作爲晶 粒（die )與導線架上內導腳（bonding finger )之間的電性接 點（contact)。由於凸塊製程成本較高且在凸塊與導線架銲 接的製程中會出現技術上的問題如銲料不足（nin-mit )等， 所以以凸塊進行封裝之元件在很多方面仍無法應用。因此 需要一種將晶片以覆晶接合技術連接到導線架上的封裝結 構，且其必須維持著相當於傳統製程的低製作成本。 因此，本發明的目的在提出一種導線架型覆晶封裝 (flip chip-in-leadframe package )包括一具有凸塊之晶片， (請先閱讀背面之注意事項再填寫本頁) 裝 經濟邨智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A丨規格（210 X 297公釐） A7 1234854 7340pif.doc/008 ______B7_____ 五、發明說明（Ί/ ) 且晶片直接與導線架上的接腳接合。本發明的凸塊係以鑲 嵌凸塊技術（stud-bumping technical )形成於晶粒上，其材 質例如爲金；而將凸塊以熱壓合（thermo-compression )的 方式與導線架之內導腳接合，使得晶片貼附於導線架上。 因此，本發明的特徵之一爲將晶粒連接至導線架的 方式，晶粒連接至導線架的方式包括於晶粒上形成金屬凸 塊，將凸塊與導線架上之內導腳接合，對凸塊進行加熱， 以及將凸塊壓合於內導腳上。熱壓合製程會造成凸塊的形 變（deformation ) 〇 部分的實施例中，凸塊係以晶片封裝習知領域的銲 線機（wire bonding machine )進行『鑲嵌凸塊』技術製作 出來。而凸塊之材質可以爲各種不同種類之金屬以及具有 大可塑性之合金。在特定實施例中，製作凸塊之金屬包括 金。 舉例而言，凸塊可以直接藉由提供一熱源於晶粒上 進行加熱。 本發明部分實施例中的晶粒是以晶穴向下（cavity down )的方式配置，導線架之內導腳以一基板支撐住，而 晶粒的背面以一壓印治具（press )支撐住，並提供一外力 於壓印治具上使得晶粒與基板互相靠近，以達到凸塊與內 導腳壓合的目的。凸塊經過足夠的加熱後，在壓力作用的 條件下凸塊材質會允許出現原凸塊高度的15%至20%的 塑形形變（plastic deformation )程度。壓力與加熱溫度組 合選擇的根據視其所選擇的金屬或合金而定；舉例而言， 5 本紙張尺度綱巾酬家鮮（CNS)A‘丨祕（21()χ 297公餐) " 一 (請先閱讀背面之注意事項再填寫本頁) ^-------I ^ · 11--— — ΙΛ 1234854 Λ7 7340pif.doc/008 五、發明說明（> ) 以金作爲凸塊之材質，凸塊的加熱溫度約介於180艽至400 °C，而施加於每一個凸塊上之垂直分力（vertical loading ) 相當於10克至250克。基於便利性的考量’基板在導線 架的黏貼面上可以具有一黏著表面（adhesive surface )，且 基板可以爲片狀結構（sheet )或是一薄膜結構（film )。在 特定的實施例中，基板上會具有釋放黏著層（releasable adhesive )，使得基板在凸塊與接腳接合之後可以被移除。 如此作法可以將導線架上的接點（lands )暴露出來以利電 性連接。 於晶粒與基板之間提供一機械支撐（mechanical support )爲一可取的作法。本發明部分實施例中，在凸塊 與內導腳接合之前塗佈一定量的膠塡材質，以使得晶粒與 基板在受力互相靠近時，晶粒與基板之間的膠塡材質會被 壓縮。較佳的膠塡材質包括黏著樹脂（adhesive resin )。膠 塡材質亦塡充於形變後凸塊的下方，以使得凸塊材質與內 導腳材質直接接觸。通常會塗佈足夠量的膠塡材質以使得 晶粒與基板之間所定義出的體積能夠被塡滿。膠塡材質的 塗佈方式例如包括網板印刷方式與噴嘴擠出方式或是其他 各種塗佈技術。 以傳統覆晶封裝中的封裝膠體作爲膠塡材質 (underfill )所完成之導線架型覆晶封裝具要很高的信賴 性’因此可以延長晶粒與基板間接合（joint )的壽命。此外， 本製程與傳統塑膠封裝製程相容。 本發明的另一特徵爲形成多個導線架型覆晶封裝的 6 本紙張尺度適用中國國家標準（CNS)A 1規格（210 X 297公餐) " ' ~ 1 " ------------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂· · Λ7 B7 1234854 7 340pif.doc/008 五、發明說明（w) 方法，藉由提卷多個具有多組內導腳之導線架，提供多個 具有一組金屬凸塊之晶粒，將導線架置於一支撐上，I並將 晶粒置於導線架上使得各組凸塊與各組內導腳接觸，對凸 塊進行力〗熱’以及施加壓力於晶粒與導線架上使得凸塊與 內導腳壓合。 口[5分貫施例中’以傳統的轉移式封膠（的]18如]11〇1(16(1) 技術可形成需要的封裝型態，如有導腳結構或無導腳結 構。在部分實施例中，晶片是以晶穴向上（Cavity_up )的方 式配置，而在其他實施例中，晶片是以晶穴向上（cavity-down )的方式配置。在部分實施例中，晶粒背面暴露以增 進散熱表現或其他優點。 本發明之導線架型覆晶封裝適用於晶粒上銲墊 (bonding pad )的最小間距（pitch )大到可與導線架內導腳 的最小間距一致的情況。目前導線架之內導腳所能夠達到 的最小間距通常爲150微米之等級。 本發明的另一特徵爲藉由下列步驟形成一導線架型 覆晶封裝’包括提供一具有一組金屬凸塊之晶粒，提供一 具有內導腳之導線架，並將晶粒置於導線架上使得凸塊與 內導腳接觸，對凸塊進行加熱，以及施加壓力以使得凸塊 與內導腳壓合。 本發明之封裝製程較傳統的銲線製程快速，且由於 只形成一個接點而不是銲線製程的兩個接點，故使用較少 的金（或其他的貴金屬）。此外，覆晶的貼合不需要貼附 之材質以及後續的固化動作。本發明之覆晶接合係以標準 - 7 1¾尺度適用中國國家標準（CNS)/V1規格（21〇χ 297公釐） (請先閱讀背面之注意事項再填寫本頁)
經齊即智慧財4局員工消費合作钍印製 1234854 Λ7 7340pif.doc/008 ^ 五、發明說明（含） 之銲線製程完成，因此不需要對導線架進行額外的處理。
爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下Z 圖式之簡單說明： 第1圖繪示爲依照本發明一較佳實施例晶穴向下型 態之導線架型覆晶封裝結構俯視圖，其具有導腳且向外延 伸； 第2圖繪示爲第1圖中導線架型覆晶封裝結構在2-2 剖面之剖面圖； 第3圖繪示爲依照本發明另一較佳實施例晶穴向下 型態之導線架型覆晶封裝結構之剖面圖，其爲無導腳結 構，且晶片座（die pad )配置於封裝結構邊緣而接點配置 於封裝結構的中央； 第4圖繪示爲依照本發明另一較佳實施例晶穴向下 型態之導線架型覆晶封裝結構之剖面圖，其爲無導腳結 構，且晶片座配置於封裝結構中央而接點配置於封裝結構 的邊緣； 第5圖繪示爲依照本發明另一較佳實施例晶穴向上 型態之導線架型覆晶封裝結構之剖面圖，其爲無導腳結 構，且晶片座配置於封裝結構邊緣而接點配置於封裝結構 的中央；以及 第6圖繪示爲依照本發明另一較佳實施例晶穴向上 型態之導線架型覆晶封裝結構之剖面圖，其爲無導腳結 8 本紙張尺度適用中國國家標準（CNS)AI規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)
A7 B7 1234854 7340pif.doc/008 五、發明說明（1 ) 影響對本發明之理解，故在圖式中都省略，且圖式並未依 照並未比例繪示。 請參照圖式，第1圖繪示爲依照本發明導線架型覆 晶封裝10之俯視圖，而第2圖繪示爲依照本發明導線架 型覆晶封裝之剖視圖，其具有導腳結構且向外延伸。導線 架型覆晶封裝10包括一具有凸塊14之晶粒12，以及一導 線架16。晶粒12係藉由凸塊14與內導腳22接合而貼附 於導線架16上。第1圖與第2圖所繪示之實施例中，晶 粒12、凸塊14以及部分的導線架16被包覆於塑膠封裝膠 體18中，以將導腳的末端20暴露在封裝膠體之周圍以利 電性連接。 凸塊14例如藉由任何各種不同的技術所形成，包括 熟習此藝者所熟知的技術。凸塊14較佳的形成方式例如 是以金鑲嵌凸塊製程（gold stud-bumping )或是電鑛製程。 而凸塊14例如是以類似銲線操作方式之金鑲嵌凸塊技術 所形成。 塑膠封裝膠體18例如藉由任何各種不同的技術所形 成，包括熟習此藝者所熟知的技術。塑膠封裝膠體18較 佳是以傳統的塑膠封裝製程（plastic packaging process )所 形成，以使得經第12與部分的導線架16可以被轉移式封 裝塑膠（transfer molded plastic )中。 本發明於各種不同無導腳結構之導線架型覆晶封裝 十分有用。例如第3圖中所繪示爲一晶穴向下無導腳之封 裝架構30，其中凸塊36係配置於晶粒之邊緣（peripherally 本紙張尺度適用中國國家標準（CNS)A4規格（21〇χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) -------—訂!1!1·. 1234854 Λ7 7340pif.doc/008 β7 五、發明說明（l ) located )，而導線架38上與銲球（solder ball )37電性連接 之接點39係配置於晶粒之中央（centrally located )。 (請先閱讀背面之注意事項再填寫本頁) 而例如第4圖中所繪示爲一晶穴向下無導腳之封裝 架構40，其中凸塊46係配置於晶粒之中央，而導線架48 上與銲球47電性連接之接點49係配置於晶粒之邊緣。 而例如第5圖中所繪示爲一晶穴向上無導腳之封裝 架構50，其中凸塊56係配置於晶粒之中央，而導線架58 上之接點59係配置於晶粒之邊緣。 而例如第6圖中所繪示爲一晶穴向上無導腳之封裝 架構60，其中凸塊66係配置於晶粒之中央，而導線架68 上之接點69係配置於晶粒之邊緣。 上述各種結構中之任何一種結構，可以藉由銲球製 作於接點上而製作成於球格陣列（ball grid array )的形式， 或是不於接點上製作銲球直接以接點做電性連接的接點格 狀陣列（land grid array )形式。 本發明在低輸入/輸出腳位（low I/O application )之小 型封裝方面的應用十分有用。典型例如應用於低於100之 接腳（pin )、膠體厚度小於1毫米且膠體面積介於3至12 平方毫米之封裝上。諸如類比元件（analog )，射頻元件（RF ) 砷化鎵（GaAs )，SiGe，邏輯元件（logic )，微控制器 (Microcontroller )，快閃記憶體，RDRAM，以及 EEPROM 或其他方面之應用。 本發明的製造流程包括下列步驟。提供一暫時性的 黏著貼帶（adhesive tape )於導線架上，用以做爲支撐用的 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 1234854 Λ7 7340pif.doc/008 B7 _____ 五、發明說明（1 ) 基板，以針筒或是網板印刷的方是將一定量之膠塡材質置 於基板上。將晶粒對準於導線架上之內導腳之後放置於基 板上，接著進行熱壓合的步驟以將晶粒壓合於導線架上； 在熱壓合的同時黏著材質（adhesive )被分散並固化。接著 選擇性地以一聚合物（polymer )進行封膠的動作，以將晶 粒與導線架包覆於內。典型的封裝係同時進行多個陣列的 製作然後才進行切割（singulate ) ° 本發明的製作成本較低，特別是以銅金屬爲導線架 時。本發明可以改進封裝的散熱與電性表現。本發明導線 架上的線路（trace )可以維持很短的路徑，以增進電性屌 面降低寄生電容效應，而在一些架構中，由於銅導線架與 晶粒下方銲球的使用可以增進散熱表現。在使用中央分佈 型態接點（land )的架構中，即使是使用較大的晶粒以可以 達到良好的信賴性（reliability )。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) _ 裝 訂· •線」 本紙張尺度適用中國國家標準（CNS)A‘1規格（210 x 297公餐）

Claims (1)

1234854 第〇901〇562〇號專利申請案 S 中文申請專利範圍替換本(93年3月）思 、申清專利範圍
1 · 一種連接一晶粒至一導線架之方法，至少包栝： 形成複數個金屬凸塊於該晶粒上； 將該些凸塊與該導線架上之複數個内導腳接觸；
加熱但不熔化該些凸塊；以及 將該些凸塊壓合於該些内導腳上。 2.如申請專利範圍第l·項之連接一晶粒至導線架之方法，其 中孩些凸塊的形成幸驟包括鑲嵌凸塊製程。 3 ·如申請專利範圍第丨項之連接一晶粒至導線架之方法，其 中該些凸塊的形成步驟包括電鍍製程。 4 ·如申請專利範圍第1項之連接一晶粒至導線架之方法，其 中該些凸塊之材質包括金。 5 ·如申請專利範圍第1項之連接一晶粒至導線架之方法，其 中該些凸塊加熱步驟包括對該晶粒加熱。 6 .如申請專利範圍第1項之連接一晶粒至導線架之方法，更 包括： 將該些内導腳支撐於一基板上；以及 將該晶粒以一壓印治具支撐， 其中，將該些凸塊壓合於該些内導腳之步驟包括施力 於該晶粒與該基板上。 7·如申請專利範圍第1項之連接一晶粒至導線架之方法，其 中該加熱與該壓合的步驟係在一足以讓凸塊材質形變程 度為原凸塊向度1 5 %至2 0 %之溫度與壓力條件下完成。 8·如申請專利範圍第丨項之連接一晶粒至導線架之方法，其 中該些金屬凸塊材質包括金，該加熱步驟包括以C至 1234854 A B c D 申請專利範圍 4 0 0 C加熱該些凸塊，而該壓合步驟包括施加每一個凸塊 一 10克至250克之垂直分力。 9·如申請專利範圍第1項之連接一晶粒至導線架之方法，其 中將該些凸塊壓合於該些内導腳上之前更包括： 將该導線架支撐於一基板上；以及 塗佈一定量之膠填材料於該基板上之該導線架的該些 内導腳間。 1 0 ·如申請專利範圍第9項之連接一晶粒至導線架之方法，其 中該膠填材料包括一黏著樹脂。 11·一種形成複數導線架型覆晶封裝之方法，至少包括： 提供複數個導線架，每一該些導線架具有複數組内導 腳； 提供複數個晶粒，每一該些晶粒具有一組金屬凸塊； 將該些導線架置於一支撐上； 將該些晶粒置於該些導線架上，使得每一該組凸塊與 每一該組内導腳接觸； 對該些組凸塊進行加熱但不熔化；以及 施加一壓力於該些晶粒與該些導線架上，使得該些凸 塊與該些内導腳壓合。 1 2 ·如申請專利範圍第1 1項之所述之形成複數導線架型覆晶 封裝之方法，其中該些金屬凸塊材質包括金，該加熱步 驟包括以1 0 0 °c至4 0 0 °c加熱該些凸塊，而該壓合步驟包 括施加每一個凸塊一 1〇克至250克之垂直分力。 1 3 ·如申請專利範圍第i i項之形成複數導線架型覆晶封裝之 -2 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 1234854 A8 B8 C8 Γ________ D8 六、申請專利範圍 方法’其中將該些凸塊壓合於該些内導腳上之前更包 括： 將該導線架支撐於一基板上；以及 塗佈一足量之膠填材料於該基板上之該導線架的該些 内導腳間。 人一 1 4·如申請專利範圍第丨丨項之形成複數導線架型覆晶封之方 法，更包括一切割該些複數個導線架型覆晶封裝之步 驟。 15.如申請專利範圍第η項所述之方法，其中該加熱及施加 壓力之步騾係在一足夠形成該凸塊材料變形至原凸塊高 度之15/>及20%之間之溫度及壓力下進行。 16·種導線架型覆晶封裝，係依照如申請專利範圍第丨4項 所述之方法製作。 η•如申請專利範圍第16項所述之封裝，其中該晶粒相對於 該組内導腳而言，係以晶穴向上的方式配置。 •如申請專職圍㈣項所述之封裝，其中該晶粒相⑼ 該組内導腳而言，係以晶穴向下的方式配置。 .如申請專利範圍第16項所述之封裝，^中該等導腳係向 内延伸。 20.如申請專利範圍第16項所述之封裳，其中該等導腳 外延伸。 -3 - 本紙張尺度適用中國國家標準(CNS) Α4规格(210 X 297公^ ---—- 1234854
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