CN101043009B - 封装半导体管芯的方法 - Google Patents

封装半导体管芯的方法 Download PDF

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CN101043009B
CN101043009B CN2007100047277A CN200710004727A CN101043009B CN 101043009 B CN101043009 B CN 101043009B CN 2007100047277 A CN2007100047277 A CN 2007100047277A CN 200710004727 A CN200710004727 A CN 200710004727A CN 101043009 B CN101043009 B CN 101043009B
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adhesive tape
semiconductor dies
tube core
introducing needle
suture introducing
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CN101043009A (zh
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阿米杜丁·伊斯梅尔
奇·森格·富恩格
汝在尼·伊波欣
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

本申请涉及一种封装半导体管芯(10)的方法，包括提供在其底面(14)上具有隆起连接(12)的倒装芯片管芯(10)。将胶带(18)贴到平板表面(16)并且在胶带(18)上形成引线针(20)。在胶带(18)上放置管芯(10)使得管芯(10)上的隆起(12)接触胶带(18)上的各自对应的引线针(20)。对管芯(10)、胶带(18)和平板(16)执行回流过程，这形成C5类型的互连接。在管芯(10)和胶带(18)上形成模塑封料(24)，并且然后移除胶带(18)和平板(16)。

Description

封装半导体管芯的方法
技术领域
本发明涉及集成电路(IC)的封装，并且更具体地涉及不使用引线框或基片封装半导体管芯的方法。
背景技术
在半导体封装中，引线框和基片广泛地用于半导体管芯的载体。除了提供机械支撑，引线框和基片也用作半导体管芯的电接口。引线框和基片通常永久性地包括在半导体封装的最终结构中，并且因此构成每个半导体封装的固定材料成本中相当大的部分。因此，为了降低封装成本，需要有一种不使用引线框或基片封装半导体管芯的方法。
发明内容
本发明提供了一种封装半导体管芯的方法，包括步骤：提供在底面上具有隆起连接的倒装芯片管芯；将胶带贴到平板表面并且在胶带上形成引线针；在胶带上放置管芯使得管芯上的隆起接触胶带上的各自对应的引线针；对管芯、胶带和平板执行回流过程；然后执行成型过程使得在管芯和胶带上形成模塑封料；最后，移除胶带和平板。
本发明还提供了一种封装半导体管芯的方法，包括步骤：提供在底面上具有隆起连接的倒装芯片管芯；将胶带贴到平板表面并且在胶带上形成引线针；在胶带上放置管芯使得管芯上的隆起接触胶带上的各自对应的引线针；对管芯、胶带和平板执行回流过程，其使得隆起转变成互连接；执行成型过程使得在管芯和胶带上形成模塑封料；最后，移除胶带和平板，从而形成半导体封装；可以对封装进行打磨和抛光以暴露该互连接。
本发明还提供一种封装半导体管芯的方法，包括步骤：提供在底面上具有隆起连接的倒装芯片管芯；将胶带贴到平板表面并且在胶带上形成引线针和热沉；在胶带上放置管芯使得管芯由热沉支撑并且管芯上的隆起接触胶带上的各自对应的引线针；对管芯、胶带和平板执行回流过程；在回流过程期间隆起和引线针熔化并且冷却时形成控制塌陷芯片载体连接(C5)类型的互连接；执行成型过程使得在管芯和胶带上形成模塑封料；最后，移除胶带和平板。
附图说明
结合附图阅读时将更好地理解后面具体描述的本发明的优选实施例。本发明以实例的方式示出，并且不受附图的限制，附图中相似的参考标号表示相似的元件。应理解，附图不是按比例绘制的，并且为了便于本发明的理解而进行了简化。
图1是根据本发明的实施例的放置在平板上的半导体管芯的放大横截面图；
图2是正经历回流过程的图1的管芯和平板的放大横截面图；
图3是正由模塑封料(molding compound)进行密封的图2的管芯的放大横截面图；
图4是移除了平板的图3的半导体封装的放大横截面图；
图5是图4的半导体封装的放大底部视图；
图6是根据本发明另一实施例的表面贴有胶带(tape)的平板的放大横截面图；
图7是正经历回流过程的图6的平板的放大横截面图；
图8是使用图7的平板形成的半导体封装的放大横截面图；以及
图9是移除了平板的图8的半导体封装的放大横截面图。
具体实施方式
以下结合附图阐述的具体说明旨在作为本发明的当前优选实施例的说明，并且不旨在表示实践本发明的唯一形式。应理解，包括在本发明的精神和范围内的不同实施例可以完成相同或等价的功能。在附图中，相似的标号遍及附图用于指代相似的元件。
图1至4是示出根据本发明的实施例的封装半导体管芯的方法的放大横截面图。
现在参考图1，提供了在其底面14上具有隆起连接12的倒装芯片管芯10。另外，还提供了在其表面贴有胶带18的平板16。在胶带18上形成引线针20。然后，在胶带18上放置管芯10，使得管芯10的隆起连接12接触胶带18上各自对应的引线针20。
管芯10可以是任何类型的电路，比如，数字信号处理器(DSP)或专门功能电路。管芯10不限于比如CMOS的特殊技术或者得自任何特殊晶片技术。此外，本发明可以适应各种尺寸的管芯，例如，管芯10可以是大约10mm乘10mm的尺寸。隆起12由比如金、铜、或合金的传导金属制成，并且使用已知的晶片隆起形成工艺形成在管芯10上。本领域的普通技术人员已知这种倒装芯片隆起管芯，并且因此不做对完整理解本发明所不必要的进一步解释。
平板16可由较坚固并且耐热，比如执行回流操作的温度，的任何适当材料制成。这样的材料的实例是陶瓷、不锈钢、铜等。可以根据成本和传导性的考虑而使用铜。在其它例子中，可以优选地使用陶瓷，因为陶瓷能够经受连续的重复使用。平板16优选地是可重复使用的。贴到平板16的胶带18优选地是高温胶带，其能够抵抗大于约360℃的温度。这种胶带对本领域的普通技术人员是已知的，并且易于商业应用。通过焊料包层，即，通过使用比如不锈钢模板的模板在胶带18的预定区域上丝网印刷一层焊料浆料，并使焊料浆料经过回流过程，在胶带18上形成引线针20。引线针20可具有大约18微米的厚度T1，并且优选地由回流温度大约在160℃到大约230℃范围内的共熔焊料包层材料，比如回流温度大约为183℃的Pb63Sn37焊料形成。
通过将管芯10上的隆起12置于胶带18上各自对应的引线针20上面，可以在管芯10和胶带18之间形成较高的离板高度(standoff)。该较高的离板高度有利于在后续的成型过程(molding process)中模塑封料在隆起之间的流动，并且能够防止在所构成的半导体封装中形成空间(void)。
现在参考图2，使用回流炉在管芯10、平板16和胶带18上执行回流过程。在这个具体实例中，在大于220℃的温度回流管芯10、平板16和胶带18。然而，本领域的技术人员将理解，本发明不受回流过程的温度所限制。回流过程的目的是熔化隆起12和引线针20以形成控制塌陷芯片载体连接(C5)类型的互连接22。用于回流的温度范围通常低于大约360℃，在平板16由铜制造的情况中该温度恰当地低于铜的熔点。
现在参考图3，在图2的管芯10上执行成型过程。更具体地，在管芯10和胶带18上形成模塑封料24，使得其覆盖或密封管芯10、互连接22和部分胶带18，因而形成半导体封装26。模塑封料24包括已熟知的商用模塑材料，比如塑胶或环氧树脂。
现在参考图4，从半导体封装26移除平板16和胶带18，这在封装26的底面30上暴露了C5互连接22的底面28。因为胶带18和模塑封料24的残留量会保留在封装26的底面30上，所以可以执行打磨或抛光以暴露C5互连接22的底面28。
如从上面的描述中显见的，本发明通过使用平板16和胶带18作为临时的基片替代品而不需要引线框或基片用于封装半导体管芯10。通过从封装过程中排除引线框和基片的使用而降低了封装成本。此外，因为平板16是可重复使用的，所以本发明可以实现额外的成本节约。
现在参考图5，示出图4的半导体封装26的放大底部视图。如所示，此具体实例中的C5互连接28是周边(perimeter)阵列结构的。然而，本领域的技术人员将理解，本发明不受互连接28的结构所限制。在其它实施例中，互连接28可以是区域(area)阵列结构的。在本发明的一个实施例中，封装26具有大约2.9mm的长度L和大约2.8mm的宽度W、大约75个输入和输出(IO)、大约115μm的管脚间距(pitch)P和大约110mm的互连接直径D。然而，尽管在此描述了封装26的特定尺寸，本领域的技术人员将理解，本发明不受所述尺寸的限制。
图6至9是示出根据本发明的另一实施例的封装半导体管芯的方法的放大横截面图。
现在参考图6，示出了其表面贴有胶带52的平板50。在胶带52上形成引线针54，并且热沉58的第一或底表面56贴于胶带52上。在各自对应的引线针54上放置球60以便为后续的引线接合步骤提供更大的表面积。使用将焊料球应用于基片的已熟知的方法在引线针上形成球60。或者，如以下所讨论的，特别地，使用在引线针54上形成球形接合的球形接合过程，可以在引线接合过程期间形成球60。
平板50可以由比如金属、合金或陶瓷的任何适当的基片材料制成。贴到平板50的胶带52优选地是能够抵抗大于约360℃的温度的高温胶带。通过焊料包层，即，通过使用比如不锈钢模板的模板在胶带52的预定区域上丝网印刷一层焊料浆料，并使焊料浆料经过回流过程，在胶带52上形成引线针54。引线针54可具有大约4-5mil的厚度T2，并且优选地由回流温度在大约160℃到大约230℃的范围内的共熔焊料包层材料形成。热沉58可以由铜或其它热传导材料制成并且以胶或任何其它已知方式被贴到胶带52上。或者，可以以与引线针54相同的方式和相同的材料在胶带52上形成热沉58。球60是用于形成控制塌陷芯片载体连接(C5)的类型的焊料球，并且直径约为25mil。
现在参考图7，通过将平板50穿过回流炉在图6的平板50上执行回流过程。在此具体实例中，在约220℃的温度下回流平板50。然而，应理解本发明不受回流过程的温度所限制。球60和胶带52上的引线针在回流过程期间熔化，并且冷却时形成隆起62。
现在参考图8，示出了使用图7的平板50形成的半导体封装64。半导体管芯66放置在热沉58上并附到热沉58的第二或顶表面68。管芯66上的接合片(未示出)以多条线70电连接至胶带52上的各自对应的隆起62。在一个实施例中，线70通过引线接合被连接到管芯66的接合片和隆起62，例如以热声波跳焊到隆起62。在其它实施例中，在隆起62中打出用于容纳线70的一端的孔(未示出)。在另一实施例中，通过在引线针54上制成的球形接合形成隆起62，并且然后进行回流以形成隆起62。管芯66、线70、部分隆起62、热沉58和胶带52的表面由模塑封料72覆盖或密封以形成半导体封装64。
管芯66可以是任何类型的电路，比如，数字信号处理器(DSP)或专门功能电路，并且不限于比如CMOS的特殊技术或者得自任何特殊晶片技术。管芯66以已知的方式，比如以粘性材料层或者胶带贴到热沉58。线70可以由本领域中已知的和商用的金(Au)、铜(Cu)、铝(Al)或其它电传导材料制成。模塑封料72可包括熟知的商用模塑材料，比如塑胶或环氧树脂。
现在参考图9，从图8的封装64的底面74移除胶带52和平板50以暴露热沉58的底面56，以及封装64的底面74上的球62的底面76。因为胶带52的残留量会保留在封装64的底面74上，所以可以执行打磨或抛光以暴露球62的底面76。
应注意，对于以上参考图1-4讨论的封装26，像热沉58的热沉可以贴到胶带18上，并且管芯10附到这样的热沉上。在这种情况下，相对于隆起的阵列模式，所使用的管芯10可具有围绕其外围排列的倒装芯片隆起。
如从前述讨论中显见的，本发明提供了一种封装半导体管芯的便宜方法。由于在本发明中不需要引线框和基片而基本上降低了封装成本。另外，本发明的封装过程是简单的，因为其不包括比如锯切金属引线框这样的复杂的处理步骤。
已经为了说明和描述的目的表述了本发明的优选实施例，但其不旨在无遗漏地描述，或将本发明限制在所公开的形式。本领域的技术人员应意识到，在不脱离本发明的广泛的发明概念的情况下可以对上述的实施例做出更改。例如，尽管描述了QFN封装，本发明也可形成比如接点删格阵列(LGA)封装的其它封装类型。因此应理解，本发明不限于所公开的特殊实施例，而是应覆盖所附权利要求所限定的本发明的精神和范围内的修改。

Claims (11)

1.一种封装半导体管芯的方法，包括：
将胶带贴到平板表面；
在胶带上形成引线针；
在胶带上形成热沉；
提供在其顶面上具有接合片的半导体IC管芯；
在热沉上放置管芯的底面；
以多根线电连接各个的管芯接合片和相应的胶带引线针，其中线到引线针的连接是球形接合；
对管芯、胶带和平板执行回流工艺，其中在回流工艺期间球形接合和引线针熔化并且在冷却时形成控制塌陷芯片载体连接类型的互连接；
执行成型工艺，其中在管芯和胶带上形成模塑封料；以及
移除胶带和平板，使得暴露热沉和控制塌陷芯片载体连接类型的互连接的表面。
2.如权利要求1的封装半导体管芯的方法，还包括打磨封装的管芯以暴露控制塌陷芯片载体连接类型的互连接。
3.如权利要求1的封装半导体管芯的方法，其中通过焊料包层在胶带上形成引线针和热沉。
4.如权利要求3的封装半导体管芯的方法，其中引线针具有18微米的厚度。
5.如权利要求1的封装半导体管芯的方法，其中胶带是高温胶带。
6.如权利要求5的封装半导体管芯的方法，其中胶带能够抵抗大于360℃的温度。
7.如权利要求1的封装半导体管芯的方法，其中在220℃的温度下回流管芯、胶带和平板。
8.如权利要求1的封装半导体管芯的方法，其中平板是可重复使用的。
9.如权利要求8的封装半导体管芯的方法，其中平板由铜、陶瓷、和不锈钢之一制成。
10.如权利要求1的封装半导体管芯的方法，其中球形接合是区域阵列和外围阵列结构之一。
11.如权利要求10的封装半导体管芯的方法，其中管芯尺寸小于或等于10mm乘10mm。
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