KR20020089378A - 플립칩 내장형 리드프레임 패키지 및 그 처리과정 - Google Patents
플립칩 내장형 리드프레임 패키지 및 그 처리과정 Download PDFInfo
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- KR20020089378A KR20020089378A KR1020027011616A KR20027011616A KR20020089378A KR 20020089378 A KR20020089378 A KR 20020089378A KR 1020027011616 A KR1020027011616 A KR 1020027011616A KR 20027011616 A KR20027011616 A KR 20027011616A KR 20020089378 A KR20020089378 A KR 20020089378A
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- Prior art keywords
- leadframe
- die
- bump
- bumps
- package
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 230000013011 mating Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 239000000945 filler Substances 0.000 claims description 4
- 239000004840 adhesive resin Substances 0.000 claims description 2
- 229920006223 adhesive resin Polymers 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 238000007731 hot pressing Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000004033 plastic Substances 0.000 description 6
- 229920003023 plastic Polymers 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 241001133184 Colletotrichum agaves Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 150000001875 compounds Chemical group 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 239000002991 molded plastic Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
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- H—ELECTRICITY
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (19)
- 다이(die)를 리드프레임(leadframe)에 연결하기 위한 방법으로서,- 다이 위에 금속 범프(metal bump)를 형성하고,- 상기 범프들을 리드프레임 위 결합 핑거와 접촉시키며,- 범프들을 가열하고, 그리고- 결합 핑거에 대해 범프를 압착시키는,이상의 단계를 포함하는 것을 특징으로 하는 방법.
- 제 1 항에 있어서, 금속 범프를 형성하는 단계가 스터드 범핑(stud bumping)을 포함하는 것을 특징으로 하는 방법.
- 제 1 항에 있어서, 금속 범프를 형성하는 단계가 전기도금(electroplating)을 포함하는 것을 특징으로 하는 방법.
- 제 1 항에 있어서, 금속 범프가 금을 포함하는 것을 특징으로 하는 방법.
- 제 1 항에 있어서, 범프를 가열하는 단계가 다이를 가열하는 과정을 포함하는 것을 특징으로 하는 방법.
- 제 1 항에 있어서, 상기 방법은,- 기판 위에서 결합 핑거를 지지하고, 그리고- 프레스에 의해 다이를 지지하는,이상의 단계를 포함하고, 이때 결합 핑거에 대해 범프를 압착하는 상기 단계는 다이와 기판을 서로를 향해 움직이도록 힘을 가하는 과정을 포함하는 것을 특징으로 하는 방법.
- 제 1 항에 있어서, 가열 단계와 압착 단계는 원래 범프 높이의 15~20% 사이까지 범프 물질을 변형시키기에 충분할 만큼 큰 온도와 압력에서 실행되는 것을 특징으로 하는 방법.
- 제 7 항에 있어서, 금속 범프가 금을 포함하고, 가열 단계는 섭씨 100~400도의 온도로 범프를 가열하는 과정을 포함하며, 압착 단계는 범프당 10~250 그램 범위의 수직 하중과 동등한 힘을 가하는 과정을 포함하는 것을 특징으로 하는 방법.
- 제 1 항에 있어서, 범프를 리드프레임의 결합 핑거와 접촉시키기 전에,- 기판 위에서 리드프레임을 지지하고, 그리고- 리드프레임 결합 핑거 내 기판에 정해진 양의 충진 물질을 분포시키는,이상의 단계들을 추가로 포함하는 것을 특징으로 하는 방법.
- 제 9 항에 있어서, 상기 충진 물질이 접착성 수지(adhesive resin)를 포함하는 것을 특징으로 하는 방법.
- 다수의 칩 내장 리드프레임 패키지를 형성하는 방법으로서,- 리드프레임마다 결합 핑거 세트를 포함하는 다수의 리드프레임을 제공하고,- 다이마다 금속 범프 세트가 형성되는 다수의 다이를 제공하며,- 지지체 위에 리드프레임을 위치시키고,- 각각의 범프 세트가 결합 핑거 세트와 접촉하도록 리드프레임 위에 다이를 위치시키며,- 범프를 가열하고, 그리고- 결합 핑거에 대해 범프에 압력을 가하기 위해 리드프레임에 대해 다이를 압착시키는,이상의 단계들을 포함하는 것을 특징으로 하는 방법.
- 제 11 항에 있어서, 금속 범프는 금을 포함하고, 가열 단계는 섭씨 100~400도의 온도로 범프를 가열하는 과정을 포함하며, 압착 단계는 범프당 10~250그램의 수직 하중과 동등한 힘을 가하는 과정을 포함하는 것을 특징으로 하는 방법.
- 제 11 항에 있어서, 범프를 리드프레임의 결합 핑거와 접촉시키기 전에,- 기판 위에서 리드프레임을 지지하고, 그리고- 각 세트의 리드프레임 결합 핑거 내 기판에 정해진 양의 충진 물질을 분포시키는,이상의 단계들을 추가로 포함하는 것을 특징으로 하는 방법.
- 제 11 항에 있어서, 칩 내장형 리드프레임 패키지를 개별화하는 단계를 추가로 포함하는 것을 특징으로 하는 방법.
- 제 14 항의 방법에 따라 제작되는 칩 내장형 리드프레임 패키지.
- 제 15 항에 있어서, 다이가 결합 핑거 세트에 관련하여 위쪽으로 구멍나도록 놓이는 것을 특징으로 하는 패키지.
- 제 15 항에 있어서, 다이가 결합 핑거 세트에 관련하여 아래쪽으로 구멍나도록 놓이는 것을 특징으로 하는 패키지.
- 제 15 항에 있어서, 리드가 안쪽방향으로 부채꼴 배치되는 것을 특징으로 하는 패키지.
- 제 15 항에 있어서, 리드가 바깥쪽 방향으로 부채꼴 배치되는 것을 특징으로하는 패키지.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18856400P | 2000-03-10 | 2000-03-10 | |
US60/188,564 | 2000-03-10 | ||
US09/802,443 US6828220B2 (en) | 2000-03-10 | 2001-03-09 | Flip chip-in-leadframe package and process |
US09/802,443 | 2001-03-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020089378A true KR20020089378A (ko) | 2002-11-29 |
KR100787678B1 KR100787678B1 (ko) | 2007-12-21 |
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ID=26884221
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020027011616A KR100787678B1 (ko) | 2000-03-10 | 2001-03-09 | 플립칩 내장형 리드프레임 패키지 및 그 처리과정 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6828220B2 (ko) |
EP (1) | EP1295328A4 (ko) |
JP (1) | JP2004511081A (ko) |
KR (1) | KR100787678B1 (ko) |
TW (1) | TWI234854B (ko) |
WO (1) | WO2001068304A2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100725175B1 (ko) * | 2004-08-05 | 2007-06-07 | 옵티멈 케어 인터내셔널 테크 인코포레이티드 | 칩 리드프레임 모듈 |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020110354A1 (en) * | 1997-01-09 | 2002-08-15 | Osamu Ikeda | Image recording and editing apparatus, and method for capturing and editing an image |
US6525405B1 (en) | 2000-03-30 | 2003-02-25 | Alphatec Holding Company Limited | Leadless semiconductor product packaging apparatus having a window lid and method for packaging |
SG109495A1 (en) * | 2002-04-16 | 2005-03-30 | Micron Technology Inc | Semiconductor packages with leadfame grid arrays and components and methods for making the same |
FR2851374B1 (fr) * | 2003-02-18 | 2005-12-16 | St Microelectronics Sa | Boitier-semi-conducteur a puce de circuits integres portee par les pattes de connexion electrique |
US7037805B2 (en) * | 2003-05-07 | 2006-05-02 | Honeywell International Inc. | Methods and apparatus for attaching a die to a substrate |
US6903449B2 (en) * | 2003-08-01 | 2005-06-07 | Micron Technology, Inc. | Semiconductor component having chip on board leadframe |
US8319323B2 (en) * | 2004-12-20 | 2012-11-27 | Semiconductor Components Industries, Llc | Electronic package having down-set leads and method |
US7148086B2 (en) * | 2005-04-28 | 2006-12-12 | Stats Chippac Ltd. | Semiconductor package with controlled solder bump wetting and fabrication method therefor |
US7169641B2 (en) * | 2005-05-03 | 2007-01-30 | Stats Chippac Ltd. | Semiconductor package with selective underfill and fabrication method therfor |
US7439100B2 (en) * | 2005-08-18 | 2008-10-21 | Semiconductor Components Industries, L.L.C. | Encapsulated chip scale package having flip-chip on lead frame structure and method |
US7399658B2 (en) * | 2005-10-21 | 2008-07-15 | Stats Chippac Ltd. | Pre-molded leadframe and method therefor |
US20070093000A1 (en) * | 2005-10-21 | 2007-04-26 | Stats Chippac Ltd. | Pre-molded leadframe and method therefor |
US7361531B2 (en) * | 2005-11-01 | 2008-04-22 | Allegro Microsystems, Inc. | Methods and apparatus for Flip-Chip-On-Lead semiconductor package |
US7678609B2 (en) * | 2005-11-03 | 2010-03-16 | International Rectifier Corporation | Semiconductor package with redistributed pads |
US7790504B2 (en) * | 2006-03-10 | 2010-09-07 | Stats Chippac Ltd. | Integrated circuit package system |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
US8193034B2 (en) | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
US8133762B2 (en) | 2009-03-17 | 2012-03-13 | Stats Chippac, Ltd. | Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core |
US20080237814A1 (en) * | 2007-03-26 | 2008-10-02 | National Semiconductor Corporation | Isolated solder pads |
US20080241991A1 (en) * | 2007-03-26 | 2008-10-02 | National Semiconductor Corporation | Gang flipping for flip-chip packaging |
US7491625B2 (en) * | 2007-03-26 | 2009-02-17 | National Semiconductor Corporation | Gang flipping for IC packaging |
US20080308933A1 (en) * | 2007-06-14 | 2008-12-18 | Lionel Chien Hui Tay | Integrated circuit package system with different connection structures |
US8629539B2 (en) | 2012-01-16 | 2014-01-14 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US9494660B2 (en) | 2012-03-20 | 2016-11-15 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US9799589B2 (en) | 2012-03-23 | 2017-10-24 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with a grid array with a leadframe and method of manufacture thereof |
ITMI20130473A1 (it) | 2013-03-28 | 2014-09-29 | St Microelectronics Srl | Metodo per fabbricare dispositivi elettronici |
US9411025B2 (en) | 2013-04-26 | 2016-08-09 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame and a magnet |
US11291146B2 (en) | 2014-03-07 | 2022-03-29 | Bridge Semiconductor Corp. | Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same |
US9899290B2 (en) | 2016-03-23 | 2018-02-20 | Nxp Usa, Inc. | Methods for manufacturing a packaged device with an extended structure for forming an opening in the encapsulant |
US10991644B2 (en) | 2019-08-22 | 2021-04-27 | Allegro Microsystems, Llc | Integrated circuit package having a low profile |
EP3817044A1 (en) * | 2019-11-04 | 2021-05-05 | Infineon Technologies Austria AG | Semiconductor package with a silicon carbide power semiconductor chip diffusion soldered to a copper leadframe part and a corresponding manufacturing method |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3670396A (en) * | 1971-04-12 | 1972-06-20 | Us Navy | Method of making a circuit assembly |
US4010885A (en) * | 1974-09-30 | 1977-03-08 | The Jade Corporation | Apparatus for accurately bonding leads to a semi-conductor die or the like |
US4605833A (en) * | 1984-03-15 | 1986-08-12 | Westinghouse Electric Corp. | Lead bonding of integrated circuit chips |
US5196268A (en) * | 1987-03-19 | 1993-03-23 | Texas Instruments Incorporated | Integrated circuit interconnect leads releasably mounted on film |
US4867715A (en) * | 1988-05-02 | 1989-09-19 | Delco Electronics Corporation | Interconnection lead with redundant bonding regions |
JP2513052B2 (ja) * | 1990-01-17 | 1996-07-03 | 富士電機株式会社 | フリップチップ用実装装置 |
US5583375A (en) * | 1990-06-11 | 1996-12-10 | Hitachi, Ltd. | Semiconductor device with lead structure within the planar area of the device |
US5172851A (en) * | 1990-09-20 | 1992-12-22 | Matsushita Electronics Corporation | Method of forming a bump electrode and manufacturing a resin-encapsulated semiconductor device |
JP2518569B2 (ja) * | 1991-09-19 | 1996-07-24 | 三菱電機株式会社 | 半導体装置 |
JPH06151616A (ja) * | 1992-11-14 | 1994-05-31 | Toshiba Corp | 半導体集積回路装置及びその製造方法 |
JPH06236956A (ja) * | 1993-02-09 | 1994-08-23 | Hitachi Constr Mach Co Ltd | 半導体装置及びその製造方法 |
JP3238004B2 (ja) * | 1993-07-29 | 2001-12-10 | 株式会社東芝 | 半導体装置の製造方法 |
JP3243116B2 (ja) * | 1994-05-17 | 2002-01-07 | 株式会社日立製作所 | 半導体装置 |
JPH08116016A (ja) * | 1994-10-15 | 1996-05-07 | Toshiba Corp | リードフレーム及び半導体装置 |
JPH08213434A (ja) * | 1995-02-08 | 1996-08-20 | Toshiba Corp | ボンディング装置およびボンディング方法 |
TW289145B (en) | 1995-07-07 | 1996-10-21 | Wenn-Tarn Lei | Method of packaging integrated circuit and device thereof |
US5696033A (en) * | 1995-08-16 | 1997-12-09 | Micron Technology, Inc. | Method for packaging a semiconductor die |
JP3670371B2 (ja) * | 1995-12-20 | 2005-07-13 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
US5946590A (en) * | 1996-12-10 | 1999-08-31 | Citizen Watch Co., Ltd. | Method for making bumps |
JP2953424B2 (ja) * | 1997-03-31 | 1999-09-27 | 日本電気株式会社 | フェイスダウンボンディング用リードフレーム |
US6114763A (en) * | 1997-05-30 | 2000-09-05 | Tessera, Inc. | Semiconductor package with translator for connection to an external substrate |
US6008532A (en) | 1997-10-23 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having bond fingers with alternate bonding areas |
SG71734A1 (en) * | 1997-11-21 | 2000-04-18 | Inst Materials Research & Eng | Area array stud bump flip chip and assembly process |
US6574858B1 (en) * | 1998-02-13 | 2003-06-10 | Micron Technology, Inc. | Method of manufacturing a chip package |
US6172419B1 (en) * | 1998-02-24 | 2001-01-09 | Micron Technology, Inc. | Low profile ball grid array package |
US6150724A (en) * | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
JP3176580B2 (ja) * | 1998-04-09 | 2001-06-18 | 太陽誘電株式会社 | 電子部品の実装方法及び実装装置 |
JPH11340373A (ja) * | 1998-05-27 | 1999-12-10 | Seiko Instruments Inc | 薄小型樹脂封止パッケージ |
US6376352B1 (en) * | 1998-11-05 | 2002-04-23 | Texas Instruments Incorporated | Stud-cone bump for probe tips used in known good die carriers |
SG88747A1 (en) | 1999-03-01 | 2002-05-21 | Motorola Inc | A method and machine for underfilling an assembly to form a semiconductor package |
US6410415B1 (en) * | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
US6181569B1 (en) * | 1999-06-07 | 2001-01-30 | Kishore K. Chakravorty | Low cost chip size package and method of fabricating the same |
US6258622B1 (en) * | 1999-06-07 | 2001-07-10 | Apack Technologies Inc. | Flip clip bonding leadframe-type packaging method for integrated circuit device and a device formed by the packaging method |
US6369448B1 (en) * | 2000-01-21 | 2002-04-09 | Lsi Logic Corporation | Vertically integrated flip chip semiconductor package |
US6348399B1 (en) * | 2000-07-06 | 2002-02-19 | Advanced Semiconductor Engineering, Inc. | Method of making chip scale package |
-
2001
- 2001-03-09 WO PCT/US2001/040273 patent/WO2001068304A2/en active Application Filing
- 2001-03-09 JP JP2001566843A patent/JP2004511081A/ja active Pending
- 2001-03-09 EP EP01927393A patent/EP1295328A4/en not_active Withdrawn
- 2001-03-09 US US09/802,443 patent/US6828220B2/en not_active Expired - Lifetime
- 2001-03-09 KR KR1020027011616A patent/KR100787678B1/ko active IP Right Grant
- 2001-04-23 TW TW090105620A patent/TWI234854B/zh not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100725175B1 (ko) * | 2004-08-05 | 2007-06-07 | 옵티멈 케어 인터내셔널 테크 인코포레이티드 | 칩 리드프레임 모듈 |
Also Published As
Publication number | Publication date |
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US6828220B2 (en) | 2004-12-07 |
WO2001068304A2 (en) | 2001-09-20 |
TWI234854B (en) | 2005-06-21 |
US20020031902A1 (en) | 2002-03-14 |
WO2001068304A3 (en) | 2002-09-12 |
JP2004511081A (ja) | 2004-04-08 |
KR100787678B1 (ko) | 2007-12-21 |
EP1295328A2 (en) | 2003-03-26 |
EP1295328A4 (en) | 2010-01-06 |
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