TWI226116B - Multi-chip package with outer leads and outer contact pads - Google Patents
Multi-chip package with outer leads and outer contact pads Download PDFInfo
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- TWI226116B TWI226116B TW92114024A TW92114024A TWI226116B TW I226116 B TWI226116 B TW I226116B TW 92114024 A TW92114024 A TW 92114024A TW 92114024 A TW92114024 A TW 92114024A TW I226116 B TWI226116 B TW I226116B
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- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
1226116_ 五、發明說明（1) ------- 【發明所屬之技術領域】 本發明係有關於—種多晶片封裝構造〔Multi-Chip 曰ackage〕，特別係有關於一種具有外引腳與外接墊之多 曰曰片封裝構造。 【先前技術】 習知多晶 數個半導體晶 或導線架，並 晶片封裝構造 之设計’如原 封裝構造製造 基板或導線架 連接該第一晶 再堆疊並固定 銲線連接該第 置，以製成一 在該些上層銲 夠之支撐，當 時，壓觸壓力 用以連接銲線 置，該承載裝 我國專利 揭示出另一種 片固定接合於 以單一封膠體密封 之上板佔用空間， 申請人於我國專利 方法」所揭示之多 之承載裝置上固定 片由鎳層與金層構 一晶 i -Ch i p Package 片承載件上，如 該些晶片，為了 遂有將多個晶片 公告第48 1 90 1號 晶片封裝構造， 第一晶片，再以 成之凸塊至該承 第一日日片至该第一晶片之正面 二晶片由鎳層與金層構成 多晶片封裝構造，然而該 線之形成過程如何對第二 打線壓接工具壓觸該第二 了成造成晶片之損傷，此 之導電引線應配合該些晶 置無法沿用習知單晶片封 公告第453 5 1 8號「堆疊式 多晶片封裝構造，其係區 基板承 之凸塊至 專利前案 晶片之周 晶片之周 外，該承 片之凸塊 裝之承載 電子構裝 分為複數 載一晶片 〕係將複 封裝基板 減少該多 立體堆疊 「多晶片 其係在一 下層銲線 載裝置， 再以上層 該承載裝 係未揭示 邊產生足 邊凸塊 載裝置係 作適當配 基板。 裝置」則 個個別之 油以一封 構裝單70，第一構裝單元係以一1226116_ V. Description of the invention (1) ------- [Technical field to which the invention belongs] The present invention relates to a multi-chip package structure [Multi-Chip], in particular to a device having external pins There are many chip packaging structures with external pads. [Previous technology] Knowing the design of several polycrystalline semiconductor or lead frames, and the design of the chip package structure 'such as the original package structure manufacturing substrate or lead frame connected to the first crystal and then stacked and fixed bonding wire connected to the first set to make Cheng Yi supported the welding on these upper layers. At that time, the pressing pressure was used to connect the welding wire. The Chinese patent for this loading device revealed that another piece was fixedly joined to the upper plate sealed with a single gel. The applicant occupies space. The "fixed method of our country's patent method" reveals that many of the fixing devices on the carrier device are composed of a nickel layer and a gold layer on a crystal i-Ch ip Package chip carrier, such as these wafers. No. 1 wafer package structure, the first wafer, and then the bumps to the first day to the front of the first wafer. The second wafer is a multi-chip package structure composed of a nickel layer and a gold layer. However, the formation of the line How does the process press the second wire crimping tool against the second chip and cause damage to the wafer? The conductive leads should be used with these wafers. The conventional single chip seal announcement No. 453 5 1 8 Stacked multi-chip package structure, which is from the area of the substrate to the bump of the wafer before the patent, the wafer-bearing package of the carrier is divided into a plurality of wafers. The substrate is reduced by the multi-dimensional stacking. "Multi-chips are attached to the lower layer of the wire-loading device, and the upper layer of the load-bearing system is not disclosed. The foot-side bump-bearing device is used as a suitable substrate. The device" is an individual oil. One construction sheet 70, the first construction unit is a
第5頁 1226116 發明說明（2) 裝膠體構，，纟該基板之另_表面形成有電連接之鋒球， 第二構，單元係以一引腳架承載另一晶片並以一封裝膠體 巴覆該日日片，该引腳架之外引腳係外露於該封裝膠體且銲 ;於該基板上，該引腳架之外引腳無法作為整：：晶片封 裝構造f外部電性連接端，並且該基板需要額外設計出用 二!I ί β上外引腳之連接墊，每一構裝單元需要個別之封 膠，對封裝膠體之消耗用量大，並且封裝膠體之數量 增加亦會增加模具内膠體廢料。 【發明内容】 本發 墊之多晶 線架與'^ 固定至少 接墊，以 導線架亦 伸彎折至 第二外部 間，且減 本發 墊之多晶 定與電性 與該導線 引腳，以 以增進晶 明之主要目的係在於提 片封裝構造，利用一壓 電路基板，該導線架與 一晶片’該電路基板係 作為該多晶片封裝構造 具有顯露於該封膠體之 該電路基板之外周邊， 連接端，達到減少多晶 少該封膠體耗用量之成 明之次一目的係在於提 片封裝構造，利用一電 連接對應之晶片，並以 架，旅顯露該電路基板 構成一具有外引腳與外 片承載元件之通用性以 供 種具有外引腳與外接* 模形成之封膠體 該電路基板係供 具有顯露於該封 之第一外部連接 外引腳，該外引 作為該多晶片封 片封裝構造之上 本降低。 供一種具有外引 路基板與一導線 一封膠體結合該 之外接墊及該導 接墊之多晶片封 及封裝製程之彈 結合一導 個別承載 膠體之外 端，且該 .1 Λ ； 腳該係延 裝構造之 板佔用空 腳與外接 架個別固 電路基板 線架之外 裝構造， 性。 1226116 五、發明說明（3) 勺人=發明具有外引腳與外婦之多晶片封裝構造，其 第二晶片，該電路基…有一上表面J — ; =至 =該電路板基板之上表面並且電性連接4通 外弓tim該導線架係包含有複數個内引腳及複數個 外引腳，較佳地，該導線架另包含有一晶片承座，以 方式承載該第二晶片，而該第二晶片係結合於該導線架且 電：連接至該導線架之對應内引腳，該封膠體係密封該第 一晶片、第二晶片、該些内引腳以及該電路基板之上表 面，以結合該導線架與該電路基板，並且顯露該電路基板 之下表面之該些外接墊及該導線架之該些外引腳，該些外 引腳係由該封膠體之侧邊延伸彎折至該電路基板之外^ 邊。 【實施方式】 參閱所附圖式’本發明將列舉以下之實施例說明。 请參閱第1圖’本發明之具有外引腳與外接塾之多晶 片封裝構造1 0 0係主要包含有一第一晶片J J 〇、一第二晶片 120、一電路基板130、一導線架14〇及一封膠體17〇，其中 該電路基板130係用以承載固定該第一晶片11〇，該導線架 140係用以承載固定該第二晶片12〇，該封膠體17〇係用以 結合該電路基板130與該導線架14〇並密封該第一晶片11() 與該第二晶片120，其詳述如后。 该電路基板130係具有一上表面Hi及一下表面132 , 第7頁 1226116 五、發明說明（4) 該上表面131係形成有複數個内接墊133，該下表面132係 形成有複數個供表面接合之外接墊134〔outer contact pad〕’且該電路基板130係具有適當之線路佈局〈圖未繪 出〉，以連接導通對應之内接墊133與外接墊134，該電路 基板1 3 0係可由玻璃纖維強化樹脂製成之印刷電路板或是 陶瓷電路基板。該第一晶片110係固設於該電路基板丨3〇之 上表面131，該第一晶片11〇係具有一主動面丨^及一背面 11 2，在本實施例中，該第一晶片丨丨〇之主動面丨j 1係具有 複數個位於周邊之銲墊113，當該第一晶片no之背面112 以熱固性黏膠或膠片黏固於該電路基板丨3〇之上表面131之 後，可利用打線形成之第一銲線1 51電性連接該第一晶片 110之該些銲墊113與該電路基板130之該些内接墊133，由 於本實施例中，該第一晶片11 〇係其主動面丨丨i朝上方式打 線電性連接，較佳地，可在該第一晶片11 〇之主動面11 1另 ό又置有一介電性間隔材160〔dielectric spacer〕，如虛 晶片〔dummy die〕、熱固膠層，或者該間隔材160亦可為 一散熱片〔heat sink〕，該間隔材160係具有一高於該些 第一銲線1 5 1打線弧高之厚度，以間隔該第一晶片1 1 〇與該 第二晶片120並防止該導線架140壓迫損壞該些第一銲線 151 〇 在該第一晶片110上方係結合有一導線架140，該導線 架係包含有複數個内引腳141〔 inner lead〕及複數個外 引腳142〔outer lead〕，較佳地，該導線架140可包含有 一如銅、鐵或其合金等金屬質晶片承座143〔die pad〕，Page 5 1226116 Description of the invention (2) A colloidal structure is used to form a ball with electrical connections on the other surface of the substrate. In the second structure, the unit uses a lead frame to carry another chip and a packaging gel. After the daily film, the pins outside the lead frame are exposed to the packaging gel and soldered; on the substrate, the pins outside the lead frame cannot be treated as a whole :: chip package structure f external electrical connection terminal Moreover, the substrate needs to be designed with two additional I! Β upper and outer pin connection pads. Each packaging unit requires a separate sealant, which consumes a large amount of packaging gel, and the number of packaging gels will increase. Colloidal waste in the mold. [Summary of the invention] The polycrystalline wire frame of the hair pad is fixed to at least the pad, and the lead frame is also extended and bent to the second outer space, and the polycrystalline fixing and electrical properties of the hair pad and the lead pin are reduced. The main purpose of improving the crystal is to lift the package structure, using a circuit board, the lead frame and a wafer. The circuit board is used as the multi-chip package structure with the circuit substrate exposed in the sealing compound. The outer periphery, the connection end, and the second purpose of reducing polycrystalline and reducing the consumption of the sealing colloid is to improve the packaging structure of the chip, use an electrical connection to the corresponding chip, and use a rack to reveal that the circuit substrate constitutes a The universality of the outer pin and the outer sheet bearing component for a kind of sealing gel formed with the outer pin and the outer * mold. The circuit board is provided with a first external connection outer pin exposed in the seal. The cost of the multi-chip package structure is reduced. Provided is an outer guide substrate with a wire and a gel to combine the outer pad and the multi-chip encapsulation and packaging process of the lead pad with a spring of an individual bearing colloid, and the .1 Λ; The extended structure board occupies empty feet and external fixed frame circuit boards. 1226116 V. Description of the invention (3) Spoon = Invented a multi-chip package structure with external pins and wives, the second chip, the circuit base ... has an upper surface J —; = to = the upper surface of the circuit board substrate In addition, the lead frame includes a plurality of inner pins and a plurality of outer pins electrically connected to the four-way outer bow tim. Preferably, the lead frame further includes a chip holder for carrying the second chip in a manner, and The second chip is coupled to the lead frame and is electrically connected to the corresponding inner pins of the lead frame. The sealing system seals the first chip, the second chip, the inner pins, and the upper surface of the circuit substrate. To combine the lead frame with the circuit substrate, and expose the external pads on the lower surface of the circuit substrate and the outer pins of the lead frame, the outer pins extending from the side of the sealing compound Fold to the outside of the circuit board ^. [Embodiment] The present invention will be described with reference to the attached drawings. Please refer to FIG. 1 'The multi-chip package structure 100 with external pins and external pins according to the present invention includes a first chip JJ 0, a second chip 120, a circuit substrate 130, and a lead frame 14. And a colloid 170, wherein the circuit substrate 130 is used for carrying and fixing the first wafer 110, the lead frame 140 is used for carrying and fixing the second wafer 120, and the encapsulant 170 is used for combining the The circuit substrate 130 and the lead frame 14o seal the first wafer 11 () and the second wafer 120, which will be described in detail later. The circuit substrate 130 has an upper surface Hi and a lower surface 132. Page 7 1226116 V. Description of the invention (4) The upper surface 131 is formed with a plurality of internal pads 133, and the lower surface 132 is formed with a plurality of supply pads. Outer contact pads 134 are surface-bonded, and the circuit board 130 has a proper circuit layout (not shown) to connect the corresponding internal pads 133 and external pads 134. The circuit board 1 3 0 It is a printed circuit board or ceramic circuit board made of glass fiber reinforced resin. The first wafer 110 is fixed on the circuit substrate 丨 30. The first wafer 110 has an active surface ^ and a back surface 112. In this embodiment, the first wafer 丨丨 〇's active surface 丨 j 1 has a plurality of solder pads 113 located on the periphery. When the back surface 112 of the first chip no is fixed to the circuit substrate with thermosetting adhesive or film 丨 the upper surface 131, The first bonding wires 151 formed by wire bonding are used to electrically connect the bonding pads 113 of the first chip 110 and the internal bonding pads 133 of the circuit substrate 130. Since the first chip 110 is in this embodiment, The active side of the first side is connected electrically with i facing upward. Preferably, a dielectric spacer 160 such as a dummy chip can be placed on the active side 11 1 of the first chip 11 〇. [Dummy die], a thermosetting adhesive layer, or the spacer 160 may also be a heat sink. The spacer 160 has a thickness higher than the arc height of the first welding wires 151, Space the first wafer 110 and the second wafer 120 and prevent the lead frame 140 from compressing and damaging these The first bonding wire 151 is bonded with a lead frame 140 above the first chip 110, and the lead frame includes a plurality of inner leads 141 and a plurality of outer leads 142, preferably Ground, the lead frame 140 may include a die pad 143, such as copper, iron, or an alloy thereof.
1226116 五、發明說明（5) 其係與該些内引腳丨41與外引腳丨42為相同材質，並且具有 1同一致厚度為較佳，而該第二晶片丨2 〇係黏固於，該導、線 架140之晶片承座i 43，該第二晶片12〇係具有一主動面121 及一對應之背面1 2 2，於本實施例中，該第二晶片j 2〇之背 面1 2 2係黏固於該晶片承座j 4 3，以被該晶片承座j 4 3所承 載’ 4間隔材1 6 0又黏貼結合於該晶片承座1 4 3，以結合該 導線架140與該電路基板130，該第二晶片12〇之主動面κι 係形成有複數個銲墊1 2 3，其係以打線形成之第二銲線丨5 2 電f生速接至對應之该些内引腳141 ’此外，該導線架之攔 條〔dam bar〕與外框〈圖未繪出〉係在形成該封膠體17〇 之後已被移除。 請參閱第2圖，其係在結合該導線架1 4 0與該電路基板 1 30之步驟之後，打線電性連接第二晶片1 2〇與該導線架 140之步驟，用以形成第二銲線丨52之打線壓接工具2〇 〔wire bonding tool〕係熱壓觸在該第二晶片120之銲塾 1 2 3，由於該第二晶片1 2 0係已被該金屬質晶片承座j 4 3有 效剛性支撐，該打線壓接工具20之壓觸力量不易造成該第 二晶片之破裂、損傷或翹起，故本發明之多晶片封裝構造 1 0 0係適用於各式晶片尺寸之多晶片堆疊封裝，其中又以 該第二晶片120尺寸不小於該第一晶片11〇尺寸為較佳。 該封膠體170係以壓模〔molding〕成形，以結合該導 線架1 4 0與該電路基板1 3 0，該封膠體1 7 0係密封第一晶片 110、第二晶片120、該些内引腳141及該電路基板13〇之上 表面13 1，並且該電路基板1 30之下表面132係顯霧於該封1226116 V. Description of the invention (5) It is the same material as the inner pins 丨 41 and outer pins 丨 42, and it is better to have the same thickness, and the second chip is fixed to The wafer holder i 43 of the guide and wire frame 140, the second wafer 120 has an active surface 121 and a corresponding back surface 1 2 2. In this embodiment, the back surface of the second wafer j 2 0 1 2 2 is fixed to the wafer holder j 4 3 so as to be carried by the wafer holder j 4 3 '4 spacer 1 6 0 and then bonded to the wafer holder 1 4 3 to be combined with the lead frame. 140 and the circuit substrate 130, the active surface κι of the second wafer 120 is formed with a plurality of bonding pads 1 2 3, which are second bonding wires formed by wire bonding 5 2 electrical f is connected to the corresponding The inner pins 141 ′ In addition, the dam bar and the outer frame (not shown) of the lead frame have been removed after forming the sealing body 170. Please refer to FIG. 2, which is a step of electrically connecting the second chip 120 and the lead frame 140 after the step of combining the lead frame 140 and the circuit substrate 130 to form a second solder. The wire bonding tool 2 of the line 52 is a wire bonding tool 1 2 3 which is thermally pressed against the second wafer 120. Since the second wafer 1 2 0 is already held by the metal wafer j 4 3 The effective rigid support, the pressing force of the wire crimping tool 20 is not easy to cause the second chip to crack, damage or warp. Therefore, the multi-chip package structure 100 of the present invention is suitable for various types of chip sizes. A chip stack package, in which the size of the second wafer 120 is not less than the size of the first wafer 110 is preferred. The sealing compound 170 is formed by molding to combine the lead frame 140 and the circuit substrate 130. The sealing compound 170 seals the first wafer 110, the second wafer 120, and the inner wafers. The pins 141 and the upper surface 13 1 of the circuit substrate 130 and the lower surface 132 of the circuit substrate 1 30 are foggy on the seal.
12261161226116
以達/到同一步驟之外部電性接合，故該多晶片封裝構造 1 00係以一封膠體1 70結合該導線架丨40與該電路基板丨3{)並 在該封膠體1 7 0外部形成有複數個外接墊1 3 4以及複數個外 引腳1 4 2，以縮小該多晶片封裝構造之上板佔據空間，同 時本發明之多晶片封裝構造1〇〇係具有降低封膠體17〇消耗 暈之成本降低之功效。 膠體170，使得該電路基板丨3〇之外接墊丨 :該多晶片封裝構造100之第一外部導接端，導： 架140之外引腳142係由該封膠體17〇之側邊171延伸彎折至 該，路基板130之外周邊，作為該多晶片封裝構造1〇〇之第 一外部導接端，該些外引腳丨42係可與該電路基板丨3〇呈非 電性導接之關係，較佳地，該些外接墊丨34係結合有複數 個銲球180〔solder ball〕，以供上板之表面接合，並且 該些外引腳142係彎折至與該些銲球18〇位於同一平面3〇，The external electrical bonding is performed to / from the same step, so the multi-chip package structure 100 uses a piece of gel 1 70 to combine the lead frame 丨 40 and the circuit substrate 丨 3 {) and is outside the sealing plastic 1.7 A plurality of external pads 1 3 4 and a plurality of external pins 1 4 2 are formed to reduce the space occupied by the upper board of the multi-chip package structure. At the same time, the multi-chip package structure 100 of the present invention has a lower sealing body 17. The effect of reducing the cost of halo consumption. The plastic body 170 makes the circuit substrate 丨 3〇 external pads 丨: the first external lead terminal of the multi-chip package structure 100, and the leads 142 outside the frame 140 extend from the side 171 of the sealing body 17 〇 Bend to the outer periphery of the circuit substrate 130, as the first external lead terminal of the multi-chip package structure 100, the external pins 丨 42 can be non-conductive with the circuit substrate 丨 30 Preferably, the external pads 34 are combined with a plurality of solder balls 180 for soldering on the surface of the upper board, and the outer pins 142 are bent to be soldered to the solder pads. The ball 18o is located on the same plane 30.
此外，本發明之多晶片封裝構造i 〇〇係具有封裝製造 上之流程彈性，除了依序固定結合該第一晶片110、該導 線架1 4 0及該第二晶片1 2 0之製造流程外，亦可先個別固定 與電性連接第一晶片11 〇於該電路基板1 3 0以及個別固定與 電性連接第二晶片1 20於該導線架1 4 0，之後再以該封膠體 170結合該導線架140與該電路基板1 30，該導線架140與該 電路基板1 30係可沿用一般適用於單晶片封裝之導線架與 電路板’不需要針對不同型態多晶片封裝構造特別設計對 應專屬之晶片承載元件，其組成構件之通用性以及封裝製 程彈性係遠高於習知之多晶片封裝構造。In addition, the multi-chip package structure i 00 of the present invention has process flexibility in package manufacturing, in addition to sequentially fixing the manufacturing process of the first chip 110, the lead frame 140, and the second chip 120. Alternatively, the first chip 11 can be individually fixed and electrically connected to the circuit board 130 and the second chip 120 can be individually fixed and electrically connected to the lead frame 1 40, and then combined with the sealing compound 170. The lead frame 140 and the circuit substrate 1 30, the lead frame 140 and the circuit substrate 1 30 can follow the lead frame and the circuit board generally suitable for single-chip packaging, and do not need to be specially designed for different types of multi-chip packaging structures. The exclusive chip-bearing component, the versatility of its constituent components and the flexibility of the packaging process are much higher than the conventional multi-chip packaging structure.
第10頁 1226116 五、發明說明（7) _ ' 再者，本發明並不局限該封膠體丨7〇内包含晶片之數 量’該導線架或該電路基板130係可固定一個以主之半導 體晶片，以構成一包含有兩個晶片以上之多晶片封裝構 造° 請再參閱第3圖，於本發明之第二具體實施例中，一 種具有外引腳與外接墊之多晶片封裝構造2 〇 〇係包含有一 第一晶片210 、一第二晶片220、一固定該第一晶片21〇之 電路基板2 30、一固定該第二晶片220之導線架240及一封 膠體270，該第一晶片21 〇係以凸塊2 51覆晶接合於該電路 基板23 0之上表面231之内接墊23 3，使得該第一晶片21 〇之 主動面211朝向該電路基板2 30，較佳地，在該第一晶片 210之主動面211與該電路基板230之上表面231之間填充有 一底部填充材260〔underfilling material〕，該導線架 240係形成於該第一晶片210之背面212上方，該第二晶片 220之背面22 2係固設於該導線架240之晶片承座243，該第 二晶片220之主動面221係形成有複數個銲墊223 ,並以鲜 線252連接該些銲墊223與該導線架240之内引腳241 ,利用 該封膠體270結合該已電性連接有晶片210、220之電路基 板230與該導線架2 40，並且顯露該電路基板230之下表面 232之外接墊234以及該導線架240之該些外引腳242，該些 外引腳242係由該封膠體270之側邊2 71延伸彎折至該電路 基板23 0之外周邊，較佳地，在該電路基板23〇之外接墊 234係接植有複數個銲球280，使得該多晶片封襄結構2〇0 係具有外接墊234與外引腳2 42。Page 10 1226116 V. Description of the invention (7) _ 'Furthermore, the present invention does not limit the number of wafers contained in the sealing compound 丨 70' The lead frame or the circuit substrate 130 can fix a main semiconductor wafer In order to form a multi-chip package structure including more than two chips, please refer to FIG. 3 again. In a second specific embodiment of the present invention, a multi-chip package structure with external pins and external pads is provided. The system comprises a first wafer 210, a second wafer 220, a circuit board 2 30 for fixing the first wafer 21, a lead frame 240 for fixing the second wafer 220, and a colloid 270. The first wafer 21 〇 is connected to the inner surface of the upper surface 231 of the circuit substrate 23 0 by bump 2 51 flip chip bonding pad 23 3 so that the active surface 211 of the first wafer 21 〇 faces the circuit substrate 2 30, preferably, at An underfilling material 260 is filled between the active surface 211 of the first chip 210 and the upper surface 231 of the circuit substrate 230. The lead frame 240 is formed above the back surface 212 of the first chip 210. Back of the second wafer 220 22 2 The wafer holder 243 fixed on the lead frame 240, the active surface 221 of the second wafer 220 is formed with a plurality of pads 223, and the fresh pads 252 are connected to the pads 223 and the inner lead of the lead frame 240. Pin 241, uses the sealing compound 270 to combine the circuit substrate 230 with the chips 210 and 220 electrically connected to the lead frame 2 40, and exposes the pad 234 outside the lower surface 232 of the circuit substrate 230 and the lead frame 240. The outer pins 242 are extended and bent from the side 2 71 of the sealing compound 270 to the periphery of the circuit substrate 230. Preferably, pads are connected outside the circuit substrate 230. The 234 series is implanted with a plurality of solder balls 280, so that the multi-chip sealing structure 2000 series has an external pad 234 and an external pin 242.
第11頁 1226116 五、發明說明（8) 本發明之保護範圍當視後附之申請專利範圍所界定者 為準，任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。Page 11 1226116 V. Description of the invention (8) The scope of protection of the present invention shall be determined by the scope of the appended patent application. Any person skilled in the art will make any changes without departing from the spirit and scope of the present invention. Changes and modifications all belong to the protection scope of the present invention.
第12頁 1226116_ 圖式簡單說明 【圖式簡單說明】 第1圖：本發明之第一具體實施例，一種具有外引腳與外 接墊之多晶片封裝構造之截面示意圖。 第2圖：本發明之第一具體實施例，該具有外引腳與外接 墊之多晶片封裝構造在其導線架上晶片打線連接 過程之截面示意圖。 第3圖：本發明之第二具體實施例，一種具有外引腳與外 接墊之多晶片封裝構造之截面示意圖。 元件 符 號 簡 單說I 明： 100 多 晶 片 封裝構造 110 第 一 晶 片 111 主 動 面 112 背 面 113 銲 墊 120 第 - 晶 片 121 主 動 面 122 背 面 123 銲 墊 130 電 路 基 板 131 上 表 面 132 下 表 面 133 内 接 墊 134 外 接 墊 140 導 線 架 141 内 引 腳 142 外 引 腳 143 晶 片 承座 151 第 - 銲 線 152 第 二 銲 線 160 間 隔 材 170 封 膠 體 171 側 邊 180 鮮 球 20 銲 線 壓 接工 具30 平 面 200 多 晶 片 封裝 構造 210 第 -— 晶 片 211 主 動 面 212 背 面Page 12 1226116_ Brief description of the drawings [Simplified description of the drawings] Figure 1: A first specific embodiment of the present invention, a schematic cross-sectional view of a multi-chip package structure with external pins and external pads. Fig. 2: In a first embodiment of the present invention, the multi-chip package structure with external pins and external pads is a schematic cross-sectional view of a chip wire connection process on its lead frame. Fig. 3: A second embodiment of the present invention, a schematic cross-sectional view of a multi-chip package structure with external pins and external pads. Brief description of the component symbols I: 100-chip package structure 110 First chip 111 Active surface 112 Back surface 113 Welding pad 120 First-Wafer 121 Active surface 122 Back surface 123 Welding pad 130 Circuit board 131 Upper surface 132 Lower surface 133 Inner pad 134 External pad 140 Lead frame 141 Inner pin 142 Outer pin 143 Wafer holder 151 First-bonding wire 152 Second bonding wire 160 Spacer 170 Sealing gel 171 Side 180 Fresh ball 20 Welding wire crimping tool 30 Plane 200 Multichip Package Structure 210--Chip 211 Active Surface 212 Back
1226116 圊式簡單說明 220 第二晶片 221 主動面 222 背面 230 電路基板 231 上表面 232 下表面 233 内接墊 234 外接墊 240 導線架 241 内引腳 242 外引腳 24 3 晶片承座 251 凸塊 252 銲線 260 底部填充材 270 封膠體 271 側邊 280 鮮球1226116 Simple instructions 220 Second chip 221 Active surface 222 Back 230 Circuit board 231 Upper surface 232 Lower surface 233 Inner pad 234 Outer pad 240 Lead frame 241 Inner pin 242 Outer pin 24 3 Chip holder 251 Bump 252 Welding wire 260 Underfill 270 Sealing gel 271 Side 280 Fresh ball
第14頁Page 14
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| TW92114024A TWI226116B (en) | 2003-05-23 | 2003-05-23 | Multi-chip package with outer leads and outer contact pads |
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| TW92114024A TWI226116B (en) | 2003-05-23 | 2003-05-23 | Multi-chip package with outer leads and outer contact pads |
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| TWI420626B (en) * | 2009-07-01 | 2013-12-21 | Advanced Semiconductor Eng | Package structure and package process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI420626B (en) * | 2009-07-01 | 2013-12-21 | Advanced Semiconductor Eng | Package structure and package process |
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