TWI222731B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- TWI222731B TWI222731B TW092107374A TW92107374A TWI222731B TW I222731 B TWI222731 B TW I222731B TW 092107374 A TW092107374 A TW 092107374A TW 92107374 A TW92107374 A TW 92107374A TW I222731 B TWI222731 B TW I222731B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor wafer
- semiconductor
- wafer
- semiconductor device
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
Description
1222731 砍、發明說明 【發明所屬之技術領域】 本發明係關於半導體裝置。更具體而言,係關於在半導 體裝置內層合並搭載著2層以上半導體晶片的半導體裝 置。 此 圖 ο 視 圖透 意分 示 部 面含 剖之 的用 用置 置裝 裝體 體導 導半 半知 知習 習明 明 說 說 供 供係 1 係示 術示所 技所 6 前 5 圖 先圖, t 外 的上視示意圖。又,圖7所示係供說明習知屬於代表性的 記憶體之dram構造用的示意圖。 如圖5所示,在半導體裝置3 00中,於基板42上搭載 著下層半導體晶片44,並在下層半導體晶片44中央處搭 載著上層半導體晶片46。 在基板42背面上形成焊球5 0。此外,如圖6所示,沿 半導體晶片44、46外周圍分別將搭接銲墊52、54排列成 四角形。另外,如圖5、圖6所示,搭接靜墊5 2、5 4分別 耦接於電線5 6、5 8的一端,而電線5 6、5 8的另一端則鍋 接於焊球5 0上。 【發明內容】 (發明所欲解決之問題) 如上述,在各半導體晶片44、4 6中,沿其外周圍將搭 接銲墊5 2、5 4配置成四角形。當將此種半導體晶片44、 4 6如半導體裝置3 0 0般的層合搭載爲2層的情況時,配置 於下層的下層半導體晶片44之搭接銲墊5 2需要耦接於電 6 312/發明說明書(補件)/92-06/92107374 1222731 線5 6,所以,在搭接銲墊5 2上便有不產生上層半導體晶 片46重疊的必要。因此必需將上層半導體晶片46縮小到 僅爲搭接銲墊52的排列空間之較下層半導體晶片44爲小 之大小。 所以,當如半導體裝置3 00構造的情況時,上層半導體 晶片與下層半導體晶片便無法設定爲同一者或相同尺寸 者。即,無法將相同尺寸的記憶體1C搭載2層或複數層在 半導體裝置內,而因爲上層的半導體晶片尺寸受限制,因 此記憶體1C的容量提昇亦受限制。 再者,如圖7所示,在習知代表性記憶體的DRAM上所 搭載的半導體晶片60,多數情況爲在其中央部分處配置著 一列搭接銲墊62。此種情況下,若在半導體晶片60上方 更重疊相同半導體晶片,則將導致搭接銲墊62上重疊著上 層的半導體晶片。所以,當搭載著此種半導體晶片的情況 時,便無法複數層重疊地搭載著半導體晶片。 有鑑於斯,本發明係爲解決上述問題,可達成半導體裝 置之小型化且增大記憶體容量,因而提案可高密度安裝半 導體晶片的半導體裝置。 (解決問題之手段) 本發明的半導體裝置係具備有: 配置於上述基板,並供電耦接於外部電極用的外部電極 端子; 載置於上述基板上方,並在主面上配置著複數電極銲墊 的第1半導體晶片; 7 312/發明說明書(補件)/92-06/92107374 1222731 載置於上述第1半導體晶片上方,且主面上配置著複數 電極銲墊的第2半導體晶片;以及 將上述電極銲墊與上述外接電極端子進行耦接的連接 線; 依上述第1半導體晶片主面的其中一部份,與上述第2 半導體晶片主面的相反側面呈相對向,且上述第1半導體 晶片的電極銲墊上不致重疊著上述第2半導體晶片之方 式,將上述第1、第2半導體晶片錯開而配置。 再者,本發明的半導體裝置係將上述第1半導體晶片的 上述電極銲墊,在上述第1半導體晶片相對向之二邊以平 行地同一方向配置爲1列; 而上述第2半導體晶片係重疊於上述第1半導體晶片的 上述相對向二邊之其中一邊與上述配置爲1列的電極銲墊 之間。 再者,本發明的半導體裝置係於上述第2半導體晶片下 方之未重疊於上述第1半導體晶片的部分,具備有與上述 第1半導體晶片相同高度的虛設晶片。 再者,本發明的半導體裝置係上述第丨半導體晶片與上 述第2半導體晶片爲相同大小者。 【實施方式】 以下,參照圖式,針對本發明之實施形態進行說明。另 外,在各圖中,就相同或相當的部分賦予相同元件符號, 並簡化或省略其說明。 (實施形態1) 8 312/發明說明書(補件)/92-〇6/921〇7374 1222731 圖1所示係供說明本發明實施形態1中之半導體裝置 1 〇〇用的剖面示意圖。又,圖2所示係供說明在半導體裝 置100上搭載有半導體晶片4、6之搭載狀態用之從上面觀 察的透視圖。 如圖1所示,半導體裝置100係包含有下述而構成:基板 2;下層半導體晶片4;上層半導體晶片6;虛設晶片8; 電線1 〇、1 2及合成樹脂1 4。具體而言,在基板2上搭載 下層半導體晶片4與虛設晶片8,並在下層半導體晶片4 與虛設晶片8之上方搭載上層半導體晶片6。此外,在上、 下半導體晶片4、6與基板2之間,分別連接著電線1 〇、 1 2。在此狀態下,利用合成樹脂1 4進行樹脂封裝,而構成 半導體裝置1〇〇。另外,在此實施形態1中,下層半導體 晶片4與上層半導體晶片6係爲相同尺寸的相同晶片。另 外,下層半導體晶片4與虛設晶片8具有相同高度。 在基板2背面上形成有焊球1 6。焊球1 6係當作供耦接 於外部電極用之端子使用。在銜接於基板2背面焊球i 6 的部分,分別設有貫通基板2表面的導線1 8。 在基板2表面的一部份,透過黏晶材料20而搭載著下 層半導體晶片4。此外,在基板2的其餘部分,則在與下 層半導體晶片4具間隔之狀態下,透過黏晶材料22而黏接 著虛設晶片8。即,在圖1所不狀態中’於基板2左側搭 載著下層半導體晶片4,並隔開間隔,在右側載置著虛設 晶片8。另外,其中虛設晶片係由S i所形成。 再者,從下層半導體晶片4表面橫跨虛設晶片8表面, 9 312/發明說明書(補件)/92-06/92107374 1222731 透過黏晶材料24、26而搭載上層半導體晶片6。即,在上 層半導體晶片6與下層半導體晶片4表面的銜接部分,利 用黏晶材料2 4而黏接。此外,在上層半導體晶片6與虛設 晶片8表面的銜接部分則利用黏晶材料2 6而黏接。 如圖2所示,搭接銲墊2 8係通過下層半導體晶片4表 面中央’且朝與下層半導體晶片4相對向之二邊的平行方 向,呈一列地配置。此外,搭接銲墊3 0係在上層半導體晶 片6表面的中央位置處,呈1列地配置。 如圖1、圖2所示,在利用配置於下層半導體晶片4中 央處的搭接銲墊2 8,而被區分爲二個區域的部分中,上層 半導體晶片6僅單側部分透過黏晶材料24而黏接。此外, 上層半導體晶片6亦在虛設晶片8上透過黏晶材料26而黏 接。 即,在圖1、圖2所示狀態中,下層半導體晶片4係利 用配置於中央處的搭接銲墊28而被區分爲左右二個部 分。上層半導體晶片6背面的左側係僅黏接於下層半導體 晶片4之右側部分。又,上層半導體晶片6背面的右側利 用黏晶材料3 0而黏接虛設晶片8上。依此,上層半導體晶 片6便利用下層半導體晶片4與虛設晶片8而支撐著。 各電線1 0係在其一端上耦接著下層半導體晶片4的各 搭接銲墊2 8,而另一端則耦接於基板2表面的導線1 8。電 線1 〇於被搭接銲墊2 8區隔之二個部份中,係配置成通過 搭載著上層半導體晶片6部分的另一側(即’圖1、圖2中 下層半導體晶片4左側部分)上方之狀態,並將導線1 8與 10 312/發明說明書(補件)/9106/921 〇7374 1222731 搭接銲墊2 8予以耦接。 各電線1 2係在其一端上耦接著上層半導體晶片6的各 搭接銲墊3 0,而另一端則耦接於基板2的導線1 8。電線 1 2於上層半導體晶片6之經搭接銲墊3 0區隔之二個部份 中,係配置成通過黏接著下層半導體晶片4側部分的另一 側(即,圖1、圖2中上層半導體晶片6右側部分)上方之 狀態,並將導線1 8與搭接銲墊3 0予以耦接。 如上述說明,依照本實施形態,則下層半導體晶片4與 上層半導體晶片6分別配置成中心錯開,且上層半導體晶 片6不致重疊著下層半導體晶片4的搭接銲墊2 8之狀態。 依此,即便在採用在中央處設置著搭接銲墊之半導體晶片 的情況下,仍可將半導體晶片重疊二層以上。此外,此情 況下,上下層亦可重疊著相同半導體晶片。所以,可獲得 記憶體容量較大,且小型化的半導體裝置& 另外,在實施形態1中,針對下層半導體晶片4與上層 半導體晶片6均在中央處配置有搭接銲墊28、30者進行說 明。但是,本發明並不僅限於此,亦可爲在偏離中央位置 處配置著搭接銲墊者。在此狀況下亦可將上層半導體晶片 偏離中心地重疊,此外,配合需要亦可在上層半導體晶片 與下層半導體晶片未重疊的部分處,於上層半導體晶片下 方配置者虛設晶片並支撐。 再者,在本實施形態中,雖針對重疊著相同半導體晶片 的情況進行說明,但是本發明並不僅限於相同半導體晶片 的情況,即便重疊著大小不同、或者種類不同的半導體晶 11 312/發明說明書(補件)/92-06/92107374 1222731 片亦可。 再者,在本實施形態中,針對在層合著2層半導體晶片 的情況進行說明。但是,本發明並不僅限於2層,亦可將 半導體晶片重疊爲複數層。此情況下,僅要依不致重疊於 下層所配置半導體晶片之搭接銲墊的方式,使半導體晶片 重疊於偏離中央的方向上便可。 再者,在實施形態1中,參照圖式,針對在左側配置著 下層半導體晶片4,右側配置著虛設晶片8的情況進行說 明。但是,配置位置並不僅限於此,亦可左右顛倒,此外 亦可呈上下配置狀態。另外,雖針對下層半導體晶片4與 虛設晶片8爲隔開間隔而配置的情況進行說明,但是亦可 將下層半導體晶片4與虛設晶片配置呈相接觸的狀態而配 置。雖針對虛設晶片爲Si的情況進行說明,但是在本發明 中,虛設晶片並不僅限於Si。 (實施形態2) 圖3所示係供說明本發明實施形態2中之半導體裝置 2 00用的剖面示意圖;圖4所示係供說明半導體裝置200 之半導體晶片層合狀態用之從上面觀察的透視圖。 半導體裝置200係包含有下述構件而形成:基板2 ;下層 半導體晶片4 ;上層半導體晶片3 2 ;電線1 0、3 4及合成樹 脂14。 圖3所示半導體裝置200中,關於基板2及下層所搭載 的下層半導體晶片4,係如同在實施形態1的半導體裝置 1 〇〇中所說明者。但是,在下層半導體晶片4上方所搭載 12 312/發明說明書(補件)/92-06/92107374 1222731 的上層丰導體晶片32,乃與下層半導體晶片4具不同大小。 再者’如圖4所示,實施形態2亦如同實施形態1,在 下層半導體晶片4中央部位處,一列地排列著搭接銲墊 2 8。又’在上層半導體晶片3 2的中央位置處亦一列地排列 著搭接銲墊3 8。 再者’如圖3、圖4所示,上層半導體晶片3 2係在經下 層半導體晶片4的搭接銲墊28區分之部分的單側上,透過 黏晶材料3 6而黏接著。即,在圖3、圖4所示狀態中,下 層半導體晶片4左側部分與上層半導體晶片3 2右側部分, 係利用黏晶材料3 6而黏接著。 再者’各電線34係在其一端上耦接著上層半導體晶片 3 2的各搭接銲墊3 8,而另一端則耦接於基板2的導線工8。 電線34於上層半導體晶片32之被搭接銲墊38區隔之二個 部份中’係配置成通過與下層半導體晶片4相黏接側部分 的另一側(即,圖3、圖4中上層半導體晶片3 2右側部分) 上方之狀態,並將導線1 8與搭接銲墊3 8予以耦接。 在實施形態2中,上層半導體晶片32係小於下層半導 體晶片4。所以,即便依不致重疊於下層半導體晶片4中 央位置處所配置的搭接焊墊2 8之方式,依錯開狀態配置著 上層半導體晶片32,半導體晶片32背面之未由下層半導 體晶片4所支撐的部分亦較小。因此,在半導體裝置200 中,於半導體晶片32下方未設置虛設晶片。即便如此,半 導體晶片32仍可以足夠強度由下層半導體晶片4支撐著。 其他部分則如同實施形態1,因此省略說明。 13 312/發明說明書(補件)/92-06/92107374 1222731 依照上述,則當上層所搭載的半導體晶片較小之情 時’便不必要設置虛設晶片,可省略虛設晶片之製造 驟。所以,可提升半導體製造之處理速度,且降低半 裝置製造的相關成本。 再者,在實施形態2中,針對下層半導體晶片4大 層半導體晶片3 2的情況進行說明。但是,本發明並不 限於此種情況,上層半導體晶片32只要以足夠強度由 半導體晶片4支撐著,則上層半導體晶片32亦可爲如 層半導體晶片4的大小,或在其以上。 再者,在本發明中,外部電極端子係當作供將外部 與半導體裝置進行電耦接用的端子,譬如相當於實施 1、2中的焊球1 6。此外,在本發明中,第1半導體晶 指在所層合的半導體晶片中,配置於下方的半導體晶 譬如相當於實施形態1、2中的下層半導體晶片4。又 本發明中,第2半導體晶片係指在所層合的半導體晶 中,配置於上方的半導體晶片,譬如相當於實施形態 中的上層半導體晶片6、32。另外,在本發明中,電] 墊係相當於譬如實施形態1、2中的搭接銲墊28、30、 連接線則相當於譬如實施形態1、2中的電線1 〇、1 2、 (發明之效果) 如上述所說明,在本發明中,半導體裝置係將半導 片層合爲二層,且上層的半導體晶片與下層的半導體 片,以分別僅其中一部分呈相對向狀態之方式錯開配 著。所以,無關電極銲墊的配置位置,就連上層亦可 312/發明說明書(補件)/92-06/92107374 況 等步 導體 於上 僅侷 下層 同下 電極 形態 片係 片, ,在 片 1、2 蓮銲 38 ; 3 4° 體晶 晶 置 層合 14 1222731 著較大的半導體晶片,因此較諸於在平面上搭載著半導體 晶片之情況下,可大幅縮小封裝尺寸。 再者,因爲可使上層的半導體晶片與下層的半導體晶片 呈錯開配置狀態,因此即便在中央位置處1列地配置著電 極銲墊的情況時,仍可層合半導體晶片,藉此可獲得高密 度安裝的半導體裝置。 再者,在本發明中,針對於上層的半導體晶片之下方配 置著虛設晶片之情況,即便上層所配置的半導體晶片具某 種程度大小之狀態下,仍可抑制在搭線焊接時對半導體晶 片造成損傷情形發生。 【圖式簡單說明】 圖1爲供說明本發明實施形態1的半導體裝置用之剖視 示意圖。 圖2爲供說明本發明實施形態中之搭載於半導體裝置上 的半導體晶片搭載狀態用之從上面觀察的透視圖。 圖3爲供說明本發明實施形態2的半導體裝置用之剖視 示意圖。 圖4爲供說明本發明實施形態2之搭載於半導體裝置上 的半導體晶片搭載狀態用之從上面觀察的透視圖。 圖5爲供說明習知半導體裝置用的剖視示意圖。 圖6爲供說明習知半導體裝置用之從上面觀察的透視 圖。 圖7爲供說明習知代表性記憶體的DRAM構造用之示意 圖0 15 312/發明說明書(補件)/92-06/92107374 1222731 (元件符號說明) 2 基 4 下 6 上 8 虛 10、 1 2 電 14 合 16 焊 18 導 20 ' 22、2 4 、26 28、 30 32 上 34 電 36 黏 3 8 搭 42 基 44 下 46 上 50 焊 52、 54 搭 56、 5 8 電 60 半 62 搭 100 、200、 300 312/發明說明書(補件)/92-06/92107374 板 層半導體晶片 層半導體晶片 設晶片 線 成樹脂 球 線 黏晶材料 搭接銲墊 層半導體晶片 線 晶材料 接銲墊 板 層半導體晶片 層半導體晶片 球 接銲墊 線 導體晶片 接銲墊 半導體裝置
16
Claims (1)
1222731 拾、申請專利:範圍 1.一種半導體裝置,係具備有: 基板; 配置於上述基板上,並供電耦接於外部電極用的外部電 極端子; 載置於上述基板上方,並在主面上配置著複數電極銲墊 的第1半導體晶片; 載置於上述第1半導體晶片上方,且主面上配置著複數 電極銲墊的第2半導體晶片;以及 將上述電極銲墊與上述外接電極端子進行耦接的連接 線; 依上述第1半導體晶片主面的一部份,與上述第2半導 體晶片主面之相反側面的一部份呈相對向,且上述第1半 導體晶片的電極銲墊上不致重疊著上述第2半導體晶片之 方式,將上述第1、第2半導體晶片錯開而配置。 2·如申請專利範圍第1項之半導體裝置,其中,上述第 1半導體晶片的上述電極銲墊,係在上述第1半導體晶片 相對向之二邊以平行地同一方向配置爲1列; 而上述第2半導體晶片係重疊於上述第1半導體晶片的 上述相對向二邊之其中一邊與上述配置爲1列的電極銲墊 之間。 3 ·如申請專利範圍第1項之半導體裝置,其中,於上述 第2半導體晶片下方之未重疊於上述第丨半導體晶片的部 分,具備有與上述第1半導體晶片相同高度的虛設晶片。 17 312/發明說明書(補件)/92-06/92107374 1222731 4.如申請專利範圍第2項之半導體裝置,其中,在上述 第2半導體晶片下方之未重疊於上述第1半導體晶片的部 分,具備有與上述第1半導體晶片相同高度的虛設晶片。 5 .如申請專利範圍第1至3項中任一項之半導體裝置, 其中,上述第1半導體晶片與上述第2半導體晶片爲相同 大小。 18 312/發明說明書(補件)/92-06/92107374
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002231318A JP2004071947A (ja) | 2002-08-08 | 2002-08-08 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200402856A TW200402856A (en) | 2004-02-16 |
TWI222731B true TWI222731B (en) | 2004-10-21 |
Family
ID=31492368
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092107374A TWI222731B (en) | 2002-08-08 | 2003-04-01 | Semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (1) | US6858938B2 (zh) |
JP (1) | JP2004071947A (zh) |
KR (1) | KR20040014156A (zh) |
TW (1) | TWI222731B (zh) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7242101B2 (en) * | 2004-07-19 | 2007-07-10 | St Assembly Test Services Ltd. | Integrated circuit die with pedestal |
US7915744B2 (en) * | 2005-04-18 | 2011-03-29 | Mediatek Inc. | Bond pad structures and semiconductor devices using the same |
US7518224B2 (en) * | 2005-05-16 | 2009-04-14 | Stats Chippac Ltd. | Offset integrated circuit package-on-package stacking system |
US7746656B2 (en) * | 2005-05-16 | 2010-06-29 | Stats Chippac Ltd. | Offset integrated circuit package-on-package stacking system |
JP4930970B2 (ja) * | 2005-11-28 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | マルチチップモジュール |
US7485953B2 (en) * | 2006-04-05 | 2009-02-03 | United Microelectronics Corp. | Chip package structure |
US8163600B2 (en) * | 2006-12-28 | 2012-04-24 | Stats Chippac Ltd. | Bridge stack integrated circuit package-on-package system |
JP5143451B2 (ja) * | 2007-03-15 | 2013-02-13 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
TWI395273B (zh) * | 2007-07-13 | 2013-05-01 | 矽品精密工業股份有限公司 | 多晶片堆疊結構及其製法 |
JP5529371B2 (ja) * | 2007-10-16 | 2014-06-25 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
JP2010021449A (ja) * | 2008-07-11 | 2010-01-28 | Toshiba Corp | 半導体装置 |
US8476749B2 (en) * | 2009-07-22 | 2013-07-02 | Oracle America, Inc. | High-bandwidth ramp-stack chip package |
US8552546B2 (en) | 2009-10-06 | 2013-10-08 | Samsung Electronics Co., Ltd. | Semiconductor package, semiconductor package structure including the semiconductor package, and mobile phone including the semiconductor package structure |
JP2011249582A (ja) * | 2010-05-27 | 2011-12-08 | Elpida Memory Inc | 半導体装置 |
US8779599B2 (en) * | 2011-11-16 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages including active dies and dummy dies and methods for forming the same |
KR101906269B1 (ko) | 2012-04-17 | 2018-10-10 | 삼성전자 주식회사 | 반도체 패키지 및 그 제조 방법 |
US9082632B2 (en) | 2012-05-10 | 2015-07-14 | Oracle International Corporation | Ramp-stack chip package with variable chip spacing |
US8989367B2 (en) * | 2012-09-12 | 2015-03-24 | Genesys Telecommunications Laboratories, Inc. | System and method for monitoring health of deployment states for a contact center |
KR102021077B1 (ko) * | 2013-01-24 | 2019-09-11 | 삼성전자주식회사 | 적층된 다이 패키지, 이를 포함하는 시스템 및 이의 제조 방법 |
TWI541954B (zh) * | 2013-08-12 | 2016-07-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9406660B2 (en) * | 2014-04-29 | 2016-08-02 | Micron Technology, Inc. | Stacked semiconductor die assemblies with die support members and associated systems and methods |
US9613931B2 (en) | 2015-04-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out stacked system in package (SIP) having dummy dies and methods of making the same |
CN105390482A (zh) * | 2015-11-25 | 2016-03-09 | 北京握奇数据系统有限公司 | 一种堆叠式芯片及其加工方法 |
CN105762122A (zh) * | 2016-04-28 | 2016-07-13 | 珠海市杰理科技有限公司 | 芯片封装结构 |
US9922964B1 (en) * | 2016-09-19 | 2018-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure with dummy die |
US10658258B1 (en) * | 2019-02-21 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip package and method of forming the same |
US11139249B2 (en) * | 2019-04-01 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of forming the same |
US11721657B2 (en) | 2019-06-14 | 2023-08-08 | Stmicroelectronics Pte Ltd | Wafer level chip scale package having varying thicknesses |
DE102020115848A1 (de) | 2020-06-16 | 2021-12-16 | Mann+Hummel Gmbh | Fluidfiltervorrichtung und Dichtvorrichtung mit einem Blech-Dichtungsträger |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5998864A (en) * | 1995-05-26 | 1999-12-07 | Formfactor, Inc. | Stacking semiconductor devices, particularly memory chips |
JP3958522B2 (ja) * | 1998-10-14 | 2007-08-15 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2000315776A (ja) | 1999-05-06 | 2000-11-14 | Hitachi Ltd | 半導体装置 |
JP3765952B2 (ja) * | 1999-10-19 | 2006-04-12 | 富士通株式会社 | 半導体装置 |
US6621155B1 (en) * | 1999-12-23 | 2003-09-16 | Rambus Inc. | Integrated circuit device having stacked dies and impedance balanced transmission lines |
US6252305B1 (en) * | 2000-02-29 | 2001-06-26 | Advanced Semiconductor Engineering, Inc. | Multichip module having a stacked chip arrangement |
JP3813788B2 (ja) * | 2000-04-14 | 2006-08-23 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
JP2002043503A (ja) | 2000-07-25 | 2002-02-08 | Nec Kyushu Ltd | 半導体装置 |
US6476474B1 (en) * | 2000-10-10 | 2002-11-05 | Siliconware Precision Industries Co., Ltd. | Dual-die package structure and method for fabricating the same |
-
2002
- 2002-08-08 JP JP2002231318A patent/JP2004071947A/ja not_active Withdrawn
-
2003
- 2003-02-11 US US10/361,561 patent/US6858938B2/en not_active Expired - Fee Related
- 2003-04-01 TW TW092107374A patent/TWI222731B/zh not_active IP Right Cessation
- 2003-04-10 KR KR1020030022731A patent/KR20040014156A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
JP2004071947A (ja) | 2004-03-04 |
KR20040014156A (ko) | 2004-02-14 |
US6858938B2 (en) | 2005-02-22 |
TW200402856A (en) | 2004-02-16 |
US20040026789A1 (en) | 2004-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI222731B (en) | Semiconductor device | |
TW544902B (en) | Semiconductor device and manufacture the same | |
TW502406B (en) | Ultra-thin package having stacked die | |
US7298032B2 (en) | Semiconductor multi-chip package and fabrication method | |
JP3768761B2 (ja) | 半導体装置およびその製造方法 | |
TWI278947B (en) | A multi-chip package, a semiconductor device used therein and manufacturing method thereof | |
JP5529371B2 (ja) | 半導体装置及びその製造方法 | |
US6462412B2 (en) | Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates | |
TW544901B (en) | Semiconductor device and manufacture thereof | |
US6353263B1 (en) | Semiconductor device and manufacturing method thereof | |
TWI343097B (en) | Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers | |
US20080026506A1 (en) | Semiconductor multi-chip package and fabrication method | |
TWI415201B (zh) | 多晶片堆疊結構及其製法 | |
TWI330872B (en) | Semiconductor device | |
JP2002222889A (ja) | 半導体装置及びその製造方法 | |
KR20070115061A (ko) | 적층 칩과, 그의 제조 방법 및 그를 갖는 반도체 패키지 | |
JP4896010B2 (ja) | 積層型半導体装置及びその製造方法 | |
TW564531B (en) | Low profile stack semiconductor package | |
KR20190099815A (ko) | 반도체 패키지 및 반도체 패키지의 제조 방법 | |
TWI225291B (en) | Multi-chips module and manufacturing method thereof | |
US20050269680A1 (en) | System-in-package (SIP) structure and fabrication thereof | |
KR100621547B1 (ko) | 멀티칩 패키지 | |
US20030015803A1 (en) | High-density multichip module and method for manufacturing the same | |
TWI711131B (zh) | 晶片封裝結構 | |
TWI286783B (en) | Integrated circuit chip and manufacturing process thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |