TW579560B - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
TW579560B
TW579560B TW91112118A TW91112118A TW579560B TW 579560 B TW579560 B TW 579560B TW 91112118 A TW91112118 A TW 91112118A TW 91112118 A TW91112118 A TW 91112118A TW 579560 B TW579560 B TW 579560B
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TW
Taiwan
Prior art keywords
electrodes
main surface
wiring
semiconductor device
semiconductor
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Application number
TW91112118A
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English (en)
Inventor
Tetsuya Hayashida
Original Assignee
Hitachi Ltd
Hitachi Hokkai Semiconductor
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Application filed by Hitachi Ltd, Hitachi Hokkai Semiconductor filed Critical Hitachi Ltd
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Publication of TW579560B publication Critical patent/TW579560B/zh

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    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23H—WORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
    • B23H1/00—Electrical discharge machining, i.e. removing metal with a series of rapidly recurring electrical discharges between an electrode and a workpiece in the presence of a fluid dielectric
    • B23H1/04—Electrodes specially adapted therefor or their manufacture
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23H7/00—Processes or apparatus applicable to both electrical discharge machining and electrochemical machining
    • B23H7/22—Electrodes specially adapted therefor or their manufacture
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23H—WORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
    • B23H7/00—Processes or apparatus applicable to both electrical discharge machining and electrochemical machining
    • B23H7/26—Apparatus for moving or positioning electrode relatively to workpiece; Mounting of electrode
    • B—PERFORMING OPERATIONS; TRANSPORTING
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Description

579560 A7 B7 五、發明説明（d (請先閲讀背面之注意事項再填寫本頁) 本發明是關於半導體裝置及其製造方法，特別是關 於’能夠將表面有線焊接用的電極的半導體晶片，轉換成 具有可以倒裝晶片方式安裝的區域陣列突塊電極的半導體 裝置的技術。 近年來，裝配半導體裝置的電子裝置一直在進行高速 化、高功能化、高密度安裝化，同時在推動薄型化、輕量 化。尤其是，對高速化及薄型化以裝配有LSI等的半導體 晶片（半導體元件）的倒裝晶片方式安裝較有效。 倒裝晶片方式安裝可以粗分成如下述的兩種習知手 法。（1)藉由線焊接法在半導體晶片的周邊電極（例如，鋁） 开《成金突起電極’然後介由ACF(Anisotropic Conductive Film)或NCF(Non Conductive Film)等的熱硬化性樹脂在安裝 基板接合金突起電極，或使用焊錫連接金突起電極與安裝 基板的配線（引線），然後以絕緣性樹脂封裝。 經濟部智慈財產局員工消費合作社印製 (2)在製造半導體晶片的晶圓狀態重複成膜/形成圖案 的製程’形成連接半導體晶片的周邊電極，與配置成格子 狀的焊錫電極用焊接區之間的再配線層，利用在上述焊錫 電極用焊接區上形成焊錫突塊電極的WPP(Wafer Process Package法），分割成各晶片後，經由上述焊錫突塊電極與 基板相連接。 上述的倒裝晶片方式安裝的手法會產生下述的問題。 爲了防止隨配線長度的增大引起的信號延遲，半導體晶片 的周邊電極是沿形成半導體晶片的輸入輸出電路用元件的 領域排列，因此，一般是以很小的間隔（間距）排列在半導體 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -4- 579560 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（2) 晶片的主面上的狹小領域。因此，在半導體晶片的周邊電 極上直接形成突塊電極的上述（1)的方法，形成的突塊電極 的間距很小，而爲了與其配合，安裝基板必須使用較普通 基板爲高價位的組合（build up)型。 而，（2)的方法則因爲形成再配線層，可以在半導體晶 片的主面上的廣大範圍排列成多行/列的格子狀，因此焊 錫突塊電極的間隔也較寬，但是以晶圓狀態包含不良晶片 應用此製程，因此有成本變高，很難形成藉由上述WPP法 緩和安裝基板與半導體晶片間產生的熱應力的機構等的問 題。 安裝半導體裝置的安裝基板一般是使用陶瓷基板、印 刷基板。此等安裝基板之與半導體裝置連接的電極的間距 大致上是130 μπι〜160 μιη，無法將半導體晶片側的周邊電 極的間距80 μιη〜100 μιη直接以倒裝晶片方式進行連接。 因此，一般的印刷基板是使用較傳統的層壓（1 a m i n a t e) 法更容易形成細微的電極的組合（build up)法。 但這種以組合法製造基板，其製造方法較層壓法複 雜.，其成本爲層壓法的1. 7〜2倍。 因此，本發明人便檢討不用WPP法，而使半導體晶片 側的電極成爲，從周邊電極至半導體晶圓的主面上的領 域，排列成由多行/列構成的格子狀的區域陣列突塊電 極，以擴大電極間距，藉此使用廉價的層壓法製成的印刷 基板，而完成本發明。 日本國特開2000 - 5 8594號公報揭示，具有，在有基 (請先閲讀背面之注意事項再填寫本頁) 訂 f. 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 29*7公釐） * 5 - 579560 A7 B7 經濟部智慧財產局R工消費合作社印製 五、發明説明（3) 板安裝用的多數焊錫球的突塊用基板的帶子上，介由接合 材搭機半導體晶片的構造的半導體裝置，其特徵是具有， 從帶子的形成焊錫球的表面設溝，藉此溝分散應力的構 造。 本發明的目的在提供，具有適合倒裝晶片安裝法的區 域陣列突塊電極的半導體裝置及其製造方法。 本發明的其他目的在廉價提供，具有適合倒裝晶片安 裝法的區域陣列突塊電極的半導體裝置。 本發明的其他目的在提供，在配置成格子狀的突塊電 極’與半導體晶片之間，有應力緩和構造的半導體裝置及 其製造方法。 本發明的上述及其他目的以及新穎的特徵，可以從本 說明書的記述及附圖獲得進一步的瞭解。 茲簡單說明本案所揭示的發明中具代表性者的槪要如 下。 (1)具備有： 備有主面、形成在上述主面上的多數半導體元件、及 多數電極的半導體晶片； 形成在上述半導體晶片的各電極上的金突起電極（金線 突塊電極）； '備有，有主面及背面的絕緣基材層（帶狀基材）、形成在 上述絕緣基材層的主面上的多數配線、及形成在上述絕緣 基材層的貫穿孔的配線基板（配線帶基板）； 在上述配線基板的主面上，具有分別連接在各多數配 (請先閲讀背面之注意事項再填寫本頁) A衣. 訂 f 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -6- 579560 經濟部智慧財產局員工消費合作社印製 A7 __B7_五、發明説明（4) 線而形成的多數焊錫突起電極（區域陣列突塊電極）的半導體 裝置，其特徵在於， 上述配線基板是將上述絕緣基材層的背面面對上述半 導體晶片的主面配置， 上述絕緣基材層的背面與上述半導體晶片的主面是介 由接合材（熱硬化性樹脂）接合在一起， 上述金突起電極的各電極是在上述貫穿孔的內部與上 述配線基板的配線連接在一起， 上述多數焊錫突起電極，是以較上述半導體晶片的電 極的最小間距爲大的間距，排列成由多數行、列構成的格 子狀， 上述焊錫突起電極的各電極是介由上述接合材及上述 •絕緣基材層，配置在上半導體晶片的主面上。 上述絕緣基材層的厚度與上述接合材的厚度的和爲50 〜100 μιη，上述絕緣基材層的厚度較上述接合材的厚度（50 μηι以下）爲厚。上述多數配線是由銅膜、形成在上述銅膜表 面的S η電鍍膜或N i - A u電鍍膜所構成。上述半導體晶 片的電極是沿上述半導體晶片主面的周圍排列。上述半導 體晶片的電極是沿形成輸入輸出電路用元件的領域排列。 上述焊錫突起電極是配置在離開配置上述金突起電極的領 域的領域。上述金突起電極的彈性率較上述絕緣基材層的 彈性率及上述接合材的彈性率大。上述絕緣基材層是由可 撓性膜（聚醯亞胺系樹脂）構成。 這種半導體裝置是以下述方法製造。亦即， 本紙張尺度適用中國國家標準（CNS ) A4規格（ 210X297公釐） ' " ' ' (請先閲讀背面之注意事項再填寫本頁) 579560 經濟部智慧財產局員工消費合作社印製 A7 _ B7五、發明説明（5) 包含有： 準備，具有主面、形成在上述主面上的多數半導體元 件及多數電極的半導體晶片的製程； 準備，具有，有主面及背面的絕緣基材層、形成在上 述絕緣基材層的主面上的多數配線、及形成在上述絕緣基 材層的貫穿孔的配線基板的製程； 在上述半導體晶片的各電極上形成金突起電極的製 程； 在上述絕緣基材層的背面與上述半導體晶片的主面之 間，介由接合材（熱硬化性樹脂）將上述配線基板配置在上述 半導體晶片的主面上的製程； 在配置上述配線基板的製程的後，對上述配線基板施 加壓力，令上述金突起電極與上述配線在上述貫穿孔的內 部接觸，且對上述接合材加熱使其硬化的製程；以及， 在上述配線基板的主面上，連接在各多數配線形成多 數焊錫突起電極的製程， 上述多數焊錫突起電極以較上述半導體晶片的電極的 最小間距爲大的間距，排列成由多數行、列構成的格子 狀， 上述焊錫突起電極的各電極是介由上述接合材及上述 絕緣基材層，配置在上半導體晶片的主面上。 依據上述（1)的手段時，（a)因爲可以使用配線基板，使 沿周邊配置線焊接用電極的半導體晶片，成爲較上述電極 的間距大的焊錫突塊電極，因此可以提高電氣特性。亦 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -8- 579560 經濟部智慈財產局員工消費合作社印製 Μ _Β7_五、發明説明（6) 即，尤其是能夠將高速信號處理化所不可或缺的電感，從 線焊接法的1〜1，5 η Η降低至大致0. 1 η H.。 (b) 由於使線焊接用的電極成爲較此電極的間距寬且大 的焊錫突起電極，可以提高安裝半導體裝置時的連接可靠 度。 (c) 配設焊錫突起電極的配線基板與半導體晶片是同一 大小，且與半導體晶片一致重疊，因此可以達成半導體裝 置的小型化。 · (d) 焊錫突起電極配置在配置金突起電極的領域以外的 領域，同時，上述金突起電極的彈性率較上述絕緣基材層 的彈性率及上述接合材的彈性率大。因此，由於介由較金 突起電極的彈性率小的絕緣基材層或硬化後的接合材，將 .焊錫突起電極配置在半導體晶片的主面上，安裝於安裝基 板時，可以藉由絕緣基材層或接合材緩和半導體晶片與安 裝基板的熱膨脹係數差所產生的熱應力。 (e) 由於配置在半導體晶片的主面上的焊錫突起電極與 半導體晶片之間，形成有，由彈性率低的有機樹脂形成的 50〜100 μιη或以上厚度的層，因此可以緩和半導體晶片與 安裝基板間的熱應力。 (f) 如果要形成50μιη以上的由ACF或NCF等的熱硬化 性樹脂形成的接合材，則在熱硬化製程所產生的厚度的部 分性參差不齊，會引起形成在其上的焊錫突起電極的平坦 度降低的問題。但，依據本發明時，因爲可以將接合材的 層厚度抑制在50μηι以下，同時在焊錫突起電極與半導體晶 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) (請先閲讀背面之注意事項再填寫本頁) -9- 579560 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（7) 片的間配置絕緣基材層，藉此確保焊錫突起電極與半導體 晶片間的有機樹脂層的厚度，其結果，可以抑制焊錫突起 電極的平坦度的降低。 (g)因爲此絕緣基材層是由可撓性樹脂膜形成，且其厚 度也是在30〜ΙΟΟμιτι前後，因此可以緩和將半導體裝置安 裝於安裝基板後的應力，可以提高安裝的可靠性。 茲參照附圖詳細說明本發明的實施形態如下。再者， 在說明本發明的實施形態用的所有圖式具有同一功能者， 標示同一記號，省略重複的說明。 (實施形態1) 第1圖至第14圖是本發明一實施形態（實施形態1)的 半導體裝置的圖。第1圖是表示半導體裝設的模式截面 圖，第2圖是半導體裝置的平面圖，第3圖是半導體裝置 的背面圖，第4圖是表示區域陣列突塊電極與半導體晶片 的電極的結線狀態的半導體裝置的模式平面圖。 本實施形態1的半導體裝置1是如第1圖所示，具有 介由接合材4在半導體晶片2的主面（第1圖是上面）重疊接 合配線基板（配線帶基板）3的構造，在露出配線基板3的面 (第1圖是上面）設有焊錫突起電極（區域陣列突塊電極）5。 第1圖爲了使配線基板3的構造明確，放大且以模式 方式表示兩個區域陣列突塊電極5。區域陣列突塊電極5的 排列狀態具體上是如第2圖所示縱橫排列成格子狀。在以 下的說明，製造方法等的一部分，區域陣列突塊電極5有 本紙張尺度適用中.國國家標準（CNS ) Α4規格（210Χ297公釐) ~ -10- (請先閲讀背面之注意事項再填寫本頁) 579560 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（8) 兩個的狀態也進行說明。 半導體晶片2是將完成晶圓處理的直徑很大的半導體 基板（晶圓）縱橫切割而獲得的晶片，如第3圖、第5圖所示 以四方形狀的半導體基板（例如矽基板）2a爲主體形成，上 面形成有未圖示的LSI等的電路。在半導體基板2a的主 面，沿著形成未圖示的輸入輸出電路的領域，成一列排列 有成爲電路的外部端子的電極（焊接墊）6(參照第5圖）。 本實施形態1的上述電極6是例如沿著半導體基板2a (半導體晶片2 )的周緣配置，成爲所謂周邊電極排列。除了 此電極部分的半導體基板2a的主面由絕緣膜7被覆（參照第 1圖）。電極（焊接墊）6是連接導線的端子，由鋁或鋁合金形 成，大小約6 0〜9 0 μ m的四方形’最小間距a (參照第5圖） 在70〜100 μπι前後。同時，半導體晶片2的背面是如第3 圖所示，成爲平坦的矽面。此矽面也成爲半導體裝置1的 外壁面。 配線帶基板3的構造是如第6圖至第8圖所示。第6 圖是配線帶基板的平面圖，第7圖是配線帶基板的模式截 面圖，第8圖是配線帶基板的背面圖。 本實施形態1是如第7圖所示，配線帶基板3與半導 體晶片2成一致重疊，因此是與半導體晶片2同一尺寸的 四方形狀。配線帶基板3是由：與半導體晶片2同樣的四 方形狀的有機樹脂材料構成的絕緣基材層（帶狀基材）1 〇 ;形 成在此帶狀基材10表面的配線11 ;被覆帶狀基材10的表 面，同時選擇性被覆上述配線11的絕緣膜（抗焊錫膜）12 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） (請先閲讀背面之注意事項再填寫本頁) -11 - 579560 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明（9) (在第6圖以斜線表示的部分）所構成。 未設抗焊錫膜12的領域，亦即開口部π成爲，例如 桌6圖所不的圓形領域，成爲露出配線11的一部分的連接 部的領域。在此連接部形成有後述的.焊錫突起電極（區域陣 列突塊電極）5。此開口部13是如第6圖所示縱橫排列配置 成格子狀。此開口部1 3的間距，亦即區域陣列突塊電極5 的間距b較第5圖所示的半導體晶片2的電極6的間距a 大。例如，a爲80〜100 μιη前後，b爲150〜500 μιη前 後。如此，使區域陣列突塊電極5的間距較半導體晶片2 的電極6的間距大，便可以達成安裝性能良好的倒裝晶片 方式的安裝。 又如第8圖所示，在帶狀基材10的背面沿著邊緣設有 貫穿孔（開口溝）14。此開口溝14對應半導體晶片2的各電 極6，將配線帶基板3重疊在半導體晶片2時，各電極6則 位於開口溝14內的對應位置。 設在帶狀基材10的表面的配線11的各外端部分，以 橫越開口溝14狀延伸而形成露出的連接部。此連接部在將 配線帶基板3重疊於半導體晶片2時，露出於開口溝14部 分的配線11的連接部，分別與半導體晶片2的電極6成面 對面。 在第8圖，配線11的外端部分的連接部以矩形狀模式 方式表示之。又如第4圖的模式圖所示，最終，一定的電 極6與一定的區域陣列突塊電極5將由一定的配線11電氣 方式相連接。第4圖是表示半導體晶片2的電極6與區域 本紙張尺度適用中國國家標準（CNS ) Α4規福Γ210Χ 297公釐） ~ " 一 -12- (請先閱讀背面之注意事項再填寫本頁) 579560 經濟部智慧財產局員工消費合作杜印製 A7 _B7__五、發明説明（j 陣列突塊電極5的結線狀態的半導體裝置的模式平面圖。 開口部13的位置是選擇在，可將區域陣列突塊電極5 設在偏離半導體晶片2的電極6上的位置。·這是因爲區域 陣列突塊電極是經由彈性率較金線突塊電極的彈性率小的 帶狀基材10，或硬化後的接合材4，配置在半導體晶片2 的主面上，因此在安裝於安裝基板30時，因半導體晶片2 與安裝基板30的熱膨脹係數差所產生的熱應力，可以藉由 帶狀基材10或接合材4來緩和。再者，如後述，電極6是 經由金線突塊電極連接在配線11的連接部。 又如第7圖所示，露出在開口溝14底部的配線11的 連接部及開口部13底部的配線11的連接部的表面，設有 電鍍膜15、16。 帶狀基材10是由使用環氧樹脂、聚醯亞胺樹脂等可撓 性樹脂膜形成，從緩 和半導體裝置1安裝於安裝基板後的應力的觀點，帶 狀基材10的厚度以30〜100 μπι前後最佳。同時，配線11 是將黏貼在通常用作配線材料的帶狀基材的銅箔蝕刻成一 定圖案而形成。配線11的露出在開口溝14或開口部13的 底部的配線部分用作電極，但爲了降低金屬的接觸電阻、 促進焊錫的反應性，此電極部分被覆鎳、金等較佳，而如 上述設電鍍膜15、16。此等電鍍膜15、16是由例如S η電 鍍膜或N i - A u電鍍膜形成。 帶狀基材10的厚度較抗焊錫膜12的厚度爲厚，不會 因抗焊錫膜1 2的硬化收縮等而發生扭曲。例如，帶狀基材 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) 一 -13- (請先閲讀背面之注意事項再填寫本頁)
、1T f 579560 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明（1) 1〇的厚度是20〜100 μπι前後時，抗焊錫膜12的厚度爲20 〜50 μΐΉ前後。 金線突塊電極20固定在半導體晶片2的電極6上，同 時，此金線突塊電極20的前端是連接在配線11的連接 部。金線突塊電極20的前端是電氣方式連接在連接部的電 鍍膜1 5。同時’配線帶基板3的開口部1 3分別固定有區域 陣列突塊電極5。 其次，再參照第9圖至第13圖，說明本實施形態1的 半導體裝置1的製造。如第9圖所示，在半導體晶片2的 電極6上形成金線突塊電極20。雖未圖示，用放電火炬等 溶化常用的線焊接裝置的焊接工具所保持的金線（例如直徑 20〜30 μιη)的前端，形成金屬球（例如50〜80 μιη)，然後， 用焊接工具將其擠垮在半導體晶片2的電極6上並固定 之。然後，牽拉焊接線，藉此在焊接部分切斷焊接線，形 成第9圖所示的金線突塊電極20。因爲是拉斷，金線突塊 電極20的前端的直徑較金線的直徑小。固定在電極6的球 狀部分的直徑在60〜90 μιη左右，高度爲70 μιη左右。本 實施形態1是如後述將尖端部分（凸部）利用來與配線11的 連接部相連接。 其次，如第10圖所示，在半導體晶片2的配設突塊電 極20的面上重疊與半導體晶片2大致上同大的半固形的接 合材4，及配線帶基板3。第10圖是爲了淸楚表示，將導 體晶片2、接合材4，及配線帶基板3分開來表示。 如第11圖所示，將此等半導體晶片2、接合材4、配 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐) " ' -14- (請先閱讀背面之注意事項再填寫本頁) 579560 經濟部智慧財產局員工消費合作社印製 A7 _ B7五、發明説明（〇 線帶基板3定位夾入加熱·加壓裝置的下模具25與上模具 '26之間，以一定的溫度及壓力加熱、加壓以電氣方式連接 金線突塊電極20與露出在配線帶基板3的開口溝14底部 的配線11的連接部，同時使接合材4硬化，將配線帶基板 3固定在半導體晶片2 (參照第12圖）。 上述接合材4，其一個例子是使用絕緣性的熱硬化性樹 月旨。在接合時，以半導體晶片2的各電極6上的金線突塊 電極20前端的凸部刺穿接合材4，以電氣方式連接金線突 塊電極20與配線帶基板3的配線11的連接部。露出在配 線帶基板3的開口溝14底部的配線11的連接部在其表面 設有鍍S η膜或鍍N i - A u膜，因此，金線突塊電極20與 連接部的接合成爲Au-Sn接合（Au- Sn合金）或Au-A u接合。 而接合材4也可以使用市售的NCF(No n Conductive Film)或 ACF(Anisotropic Conductive Film)。使用 ACF 時’ 可介由ACF內的導電粒子以電氣方式連接金線突塊電極20 與配線帶基板3的配線11的連接部。 接著，如第13圖所示，將區域陣列突塊電極5固定於 露出在配線帶基板3的開口溝14底部的配線11的連接 部。上述連接部的表面設有由鍍S η膜或鍍N i - A u膜構 成的電鍍膜1 6。爲了形成區域陣列突塊電極5 ’向開口部 1 3供應由P b - S η共晶焊錫或無鉛焊錫等形成的焊錫球’ 藉加熱回流形成區域陣列突塊電極5。例如向開口部1 3供 應直徑400 μΐΉ的焊錫球，形成直徑450 μιη高度400 μιη的 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -15- 579560 經濟部智慧財產局員工消費合作社印製 A7 __ B7五、發明説明（d 區域陣列突塊電極5。 從緩和產生在安裝基板與半導體晶片間的熱應力的觀 點，配置在晶片的主面上的區域陣列突塊電極5與半導體 晶片2之間，最好形成有由彈性率低的有機樹脂形成的50 〜100 μιη或以上厚度的膜層。但如果要形成50 μιη以上厚 度的由ACF或NCF等熱硬化性樹脂形成的接合材4層，由 於在熱硬化製程產生的厚度的部分性的參差不齊，會引起 形成在其上的焊錫突起電極5的平坦度降低的問題。 上述平坦度降低的問題是，在採用安裝半導體晶片時 加熱加壓的本實施形態的製造方法的半導體裝置，會更顯 著出現的問題。 爲了解決這種問題，將接合材4的厚度抑制在50 μιη 以下，同時在焊錫突起電極5與半導體晶片2間配置帶狀 基材10，以爭取焊錫突起電極5與半導體晶片2間的有機 樹脂層的厚度較有效。 在焊錫突起電極5與半導體晶片2間配置帶狀基材10 的架構，可以準備在帶狀基材10的兩面有配線的配線帶基 板3，在其表面側的配線上形成焊錫突起電極5，連接其背 面側的配線與半導體晶片2的金線突塊電極20，但，帶狀 基材10的兩面有配線的配線帶基板3較僅在帶狀基材10 的一面有配線的配線帶基板3，其價格高昂。 而如本實施形態，使用僅在帶狀基材10的一面有配線 的廉價配線帶基板3時，令與帶狀基材10的形成有配線的 主面相反側的背面面向半導體晶片，在形成於帶狀基材的 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -16- 579560 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（j 開口溝（貫穿孔）14的內部連接金線突塊電極20與配線，則 可形成在焊錫突起電極5與半導體晶片2之間配置帶狀基 材10的架構。 本實施形態1是在配線帶基板3安裝單一的半導體晶 片2，但也可以藉由變更配線帶基板3的配線圖案，安裝更 多的半導體晶片2使成爲MCM構造。 這種半導體裝置1是如第14圖所示，搭載於一定的電 子裝置的安裝基板。第14圖是表示電子裝置的一部分的模 式截面圖。安裝基板30上搭載有本實施形態1的半導體裝 置1，及其他的組件構造的半導體裝置，亦即，QFP(Quad Flat Package)3 卜 BGA(Ball Grid Array)32、CSP(Chip Size Package)33。雖未圖示，但是，安裝基板30當然可以搭載 電阻器、電容器、連接器等其他電子零件。 依據本實施形態1時，可以有下述效果。 (1) 可以使用配線帶基板3，使能夠作爲裸晶片取得的 沿周緣配置線焊接用電 極6的半導體晶片2，成爲間距較上述電極6大的區域 陣列突塊電極5，因此可以提高電氣特性。例如，本發明可 以將較之使用線焊接法的CSP在高速信號處理化所不可或 缺的電感，從1〜1 · 5 η Η降低到約0，1 η Η。因爲本發明 未使用線焊接法，因此完全不含因線焊接用的焊接線的胃 度造成的電感1〜1，5 η Η。 (2) 由於使線焊接用的電極6成爲較此電極6大，且帛 距寬的區域陣列突塊 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 一 --- -17- (請先閱讀背面之注意事項再填寫本頁) 579560 經濟部智慧財產局員工消費合作社印製 A7 __ _B7 ___五、發明説明（d 電極5，因此在安裝半導體裝置1時可以提高連接的可 靠性。 (3) 設有區域陣列突塊電極5的配線帶基板3的大小與 半導體晶片2 —樣，且與半導體晶片2 —致重疊，因此可 以達成半導體裝置1的小型化。 (4) 區域陣列突塊電極5是設在偏離配置金線突塊電極 20的領域的領域， 上述金線突塊電極20的彈性率較上述帶狀基材10的 彈性率及上述接合材的彈性率大。因此，由於區域陣列突 塊電極5是介由彈性率較金線突塊電極20小的帶狀基材10 或硬化後的接合材4，配置在半導體晶片2的主面上，因此 在安裝於安裝基板30時，可以藉由帶狀基材10或接合材4 來緩和半導體晶片2與安裝基板30的熱膨脹係數差所產生 的熱應力。 (5) 配置在半導體晶片2的主面上的區域陣列突塊電極 5與半導體晶片2之間，形成有由彈性率低的有機樹脂形成 的50〜1 00 μιη或以上厚度的膜層，因此可以緩和半導體晶 片2與安裝基板30的熱膨脹係數差所產生的熱應力。 (6) 如果要形成50 μηι以上厚度的由ACF或NCF等熱 硬化性樹脂形成的接合材4層，由於在熱硬化製程產生的 厚度的部分性參差不齊，會引起形成在其上的區域陣列突 塊電極5的平坦度降低的問題。但是，依據本發明時，可 將接合材4的厚度抑制在50 μπι以下，同時在區域陣列突 塊電極5與半導體晶片2間配置帶狀基材10，藉此可以爭 本紙張尺度適用中國國家標準( CNS ) Α4規格（210X297公釐) ~ -18- (請先閱讀背面之注意事項再填寫本頁) 579560 A7 ___B7 五、發明説明（d (請先閲讀背面之注意事項再填寫本頁) 取焊錫突起電極5與半導體晶片2間的有機樹脂層的厚 度，其結果，可以抑制區域陣列突塊電極5的平坦度的降 低。 (7) 絕緣基材層由可撓性樹脂膜，亦即由帶狀基材1〇形 成，且其厚度爲30〜100 μΐΉ前後，因此可以緩和將半導體 裝置1安裝於安裝基板30後的應力，安裝可靠性提高。 (8) 半導體裝置1的小型化、輕量化、高速度化在通信 領域、攜帶式機器領域是重要的要素。以倒裝晶片方式安 裝半導體晶片2，且使其成爲MCM，便可以進一步高性能 化。此 MCM 是將 DRAM (Dynamic Random Access Memory)、SRAM (Static Random Access Memory)，快閃記憶 器、邏輯IC甚至於高頻IC等安裝在一個基板，達成高密 度 MCM。 (實施形態2) 經濟部智慧財產局員工消費合作社印製 第15圖是表示本發明其他實施形態（實施形態2)的半 導體裝置模式截面圖。在實施形態1，設在半導體晶片2的 主面的電極6，是沿半導體晶片2邊緣排列的周邊電極排列 構造，在本實施形態2是在電極6沿半導體晶片2的中央 附近的配置輸入輸出電路用半導體元件的領域排列的半導 體晶片2，介由接合材4重疊黏貼配線帶基板3，再在配線 帶基板3的一定處所安裝區域陣列突塊電極5的構造。這 種架構也可以收到與實施形態1同樣的效果。 本實施形態2是說明沿半導體晶片2中央排列1列電 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） -19- 579560 經濟部智慧財產局員工消費合作社印製 A7 _B7_五、發明説明（θ 極6者，但也可以適用排列兩列等多列的半導體晶片2的 組合，而收到同樣的效果。 (實施形態3) 第1 6圖是表示本發明其他實施形態（實施形態3)的半 導體裝置的模式截面圖。本實施形態3的配線帶基板3形 成多層的配線，是加大配線的布設寬裕度的例子。 亦即，實施形態1的半導體裝置1，是在形成於帶狀基 材10表面的配線11上形成一定圖案的1層絕緣性的層間 絕緣膜40，在上述層間絕緣膜40上形成配線1 la，再以選 擇性形成的上述抗焊錫膜12被覆上述層間絕緣膜40上的 配線11a，同時，形成電氣方式連接到配線11a的區域陣列 突塊電極5。 而以層間絕緣膜40的上下的配線1 la、11，使電氣方 式連接到形成在半導體晶片2的電極6上的金線突塊電極 20的配線11，與形成在帶狀基材10表面的區域陣列突塊 電極5導通。 本實施形態3可以採層間絕緣膜更多，配線的更多層 化的架構。這時，是在各層間絕緣膜上形成配線，以選擇 性形成的上述抗焊錫膜被覆最上層的層間絕緣膜上的配 線，同時，以層間絕緣膜的上下的配線，使電氣方式連接 到形成在半導體晶片的電極上的金線突塊電極的最下層的 配線，與形成在帶狀基材表面的區域陣列突塊電極導通。 同時，如果在靠近配線帶基板的固定半導體晶片的一 (請先閲讀背面之注意事項再填寫本頁) 訂 -ΦΙ. 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -20- 579560 經濟部智慈財產局員工消費合作社印製 A7 _____B7__五、發明説明（d 側的面，至少配設電源配線及接地配線，便可以使電位穩 定，提高電氣特性。而且，本實施形態3也可以在配線帶 基板固定多數半導體晶片而達成MCM化。 本實施形態3可以藉配設多層配線層，進一步以高密 度排列區域陣列突塊電極5，可以達成半導體裝置的多插腳 化。 另一方面，配線的多層化的手法也可以考慮下述手 法。亦即，在1片帶狀基材的表裏面分別形成配線的構 造。這時，帶狀基材的表裏面的配線是通過設在帶狀基材 的貫穿孔的構造。同時，由設在帶狀基材表面的配線帶基 材的抗焊錫膜選擇性被覆。同時，未被抗焊錫膜被覆的部 分則成爲設區域陣列突塊電極的開口部。 本例也與上述同樣，若採用在配線帶基板的固定半導 體晶片的一側面側至少配設電源配線及接地配線的構造， 便可以使電位穩定，提高電氣特性。而且，由於在配線帶 基板固定多數半導體晶片，也可以達成MCM化。 (實施形態4) 第17圖是表示本發明其他實施形態（實施形態4)的半 導體裝置的模式截面圖。本實施形態4是可以使區域陣列 突塊電極5的間距更寬的例子。 亦即，如第17圖所示，在實施形態1的半導體裝置 1 ’使配線帶基板3較半導體晶片2大（大面積化）的例子。 在本實施形態4，是使配線帶基板3的外周從半導體晶片2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -21 - 579560 經濟部智慧財產局員工消費合作社印製 A7 _B7五、發明説明（^ 的全周緣突出的構造。 本例因爲可以使配線帶基板3較寬，因此可以將區域 陣列突塊電極5的間距放大至較實施形態1爲大。因爲可 以加大安裝此半導體裝置的安裝基板的電極間距，因此可 以降低安裝基板的製造成本。 (實施形態5) 第18圖是表示本發明其他實施形態（實施形態5)的區 域陣列突塊電極與半導體晶片電極的結線狀態的半導體裝 置的模式平面圖。在本實施形態5的半導體裝置1，設在配 線基板（配線帶基板）3的主面的多數焊錫突起電極（區域陣列 突塊電極）5中，至少一個焊錫突起電極5連接在半導體元 件（半導體晶片）2主面的多數電極6中的多數電極6，此焊 錫突起電極5成爲共同電極。 成爲共同電極的焊錫突起電極5在第1 8圖施加有小 點，使其較爲淸楚。成爲共同電極的焊錫突起電極5是如 第1 8圖所示，在中央設有4個。由於焊錫突起電極5的一 部分成爲共同電極，因此可以使焊錫突起電極5的數目較 半導體晶片2的電極6的數目少。經由配線11連接於成爲 共同電極的焊錫突起電極5的電極6也施加有小點。 在實施形態1等的半導體裝置，因爲只在配線基板（配 線帶基板）3的單面形成配線，因此，較之一般使用的在樹 脂基板上有多層配線的構造，配線的自由度變小。因此， 本實施形態5是配設連接半導體晶片2的多數電極6的突 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -22- 579560 經濟部智慧財產局員工消費合作社印製 A7 __B7五、發明説明（ 塊焊接區，使突塊焊接區的數目較晶片上電極6少，藉此 確保在配線帶基板3上有更多的布放配線的有效空間，使 其在單層配線構造時仍可與更多插腳的半導體晶片連接。 共同電極（共同配線）適合作爲供應接地（GND)電位或電源電 位的配線。 第19圖是本實施形態5的變形例子的區域陣列電極與 半導體晶片電極的結線狀態的半導體裝置的模式平面圖。 共同配線適用以供應GND電位或電源電位的配線時較爲有 效，這時是可以如第19圖所示，在經由共同的焊錫突起電 極5與配線11連接的各電極6，如描繪有斜線部分所示加 寬配線11寬度，調節共同配線與信號的輸入輸出用的配線 的間隔，藉此調節配線的阻抗等，以變更配線特性。 (實施形態6) 第20圖至第22圖是表示本發明其他實施形態（實施形 態6)的製造半導體裝置的方法的圖。第20圖是表示使用帶 狀的配線帶基板（多連帶）製造半導體裝置的方法的模式圖。 本實施形態6是以捲軸至捲軸方式製造半’導體裝置的‘ 方法。捲軸至捲軸方式是如第20圖所示，從捲軸45拉出 以一定間隔形成有半導體裝置形成部的帶狀的配線帶基板 3(多連帶），進行對半導體裝置形成部的半導體晶片2的搭 載、形成焊錫突起電極5等的裝配加工，而捲收在捲收用 捲軸46。這時也可以，從被覆帶用捲軸48拉出被覆帶 47，將半導體晶片2夾在配線帶基板3與被覆帶47之間， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -23- 579560 經濟部智慧財產局員工消費合作社印製 A7 ___B7五、發明説明（j 將配線帶基板3捲在捲收用捲軸46。藉此可以保護製品。 多連帶（配線帶基板）的構造與實施形態1的配線基板 (配線帶基板）3相同。同時，在這個時候，捲在捲軸4 5的 配線帶基板3的主面已黏貼有帶狀NCF的接合材4。 在第2 0圖，沿著配線帶基板3 (多連帶）的移動方向， 配置有裝配加工站的晶片焊接（晶片安裝）站A、金屬球裝設 站B、金屬球回流站C。 晶片安裝站A是藉由真空吸引將半導體晶片2保持在 筒夾5 0的下端，將配線帶基板3固定在配線帶基板3的一 定的製品形成部。第21圖是表示將半導體晶片搭載於配線 帶基板的狀態的放大模式圖。令藉由筒夾50運送的半導體 晶片2以金線突塊電極20面向配線帶基板3的狀態下降到 支持在工作台5 1上的配線帶基板3的製品形成部上，而固 定在配線帶基板3。 亦即如第21圖所示，工作台5 1上的配線帶基板3的 上面黏貼有由NCF所成的熱硬化性的接合材4。因爲筒夾 50下降，半導體晶片2下面的金線突塊電極20進入配線帶 基板3的貫穿孔（開口溝）14內。這時，金線突塊電極20的 前端便刺穿接合材4，接觸到位於開口溝14底的電鍍膜 15。由於筒夾50對工作台51的擠壓，及因工作台51等的 加熱，金線突塊電極20將經由電鍍膜1 5連接到配線11。 同時，這時的加熱加壓使接合材4熱硬化，半導體晶 片2便確實接合在配線帶基板3。 露出在配線帶基板3的開口溝14底的配線11的連接 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -24- 579560 經濟部智慧財產局員工消費合作社印製 A7 __B7_五、發明説明（j 部表面設有S η電鍍膜或N i - A u電鍍膜，因此，與金線 突塊電極20的連接部的接合是A u - S η接合（A u _ S η合 金）或Au- Au接觸。再者，與實施形態1同樣，接合材4 也可以使用ACF。 在金屬球裝置站B，在供應金屬球用工具5 5的平坦的 主面矩陣狀保持多個金屬球56。這種保持是藉由真空吸 著，以設在供應金屬球用工具55主面的未圖示的真空吸引 孔爲之。真空吸引孔是對應配線帶基板3的開口部13配設 之。 第22圖是說明真空吸著保持金屬球56的焊錫球，然 後供給配線帶基板3的供應金屬球用工具55的動作狀況的 模式圖。供應金屬球用工具55是如第22圖所示，以供應 金屬球用工具55的主面向下的狀態，如箭頭所示移動至收 容金屬球56的球供應箱57上，且降到一定高度。在此狀 態下進行真空吸引動作，將金屬球56真空吸著保持在真空 吸引孔。 接著，供應金屬球用工具55在上昇後向左橫方向移 動，再度降到一定高度，在收容助焊劑5 9的助焊劑槽5 8 內，在以供應金屬球用工具5 5保持的金屬球5 6塗抹助焊 劑。 接著，供應金屬球用工具55則再度上昇到一定高度 後，向左橫方向移動，停止在停在金屬球裝設站；B的配線 帶基板3 (多連帶）的直下方。然後，供應金屬球工具5 5則 以軸60爲中心反轉180度，使主面朝上。然後，供應金屬 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -25- 579560 A7 ___ B7 五、發明説明（^ (請先閱讀背面之注意事項再填寫本頁) 球用工具55再上昇到一定的高度，將保持在主面的金屬球 56供給配線帶基板3的下面。利用助焊劑液的接合力使金 屬球56附著在配線帶基板3下面的開口部1 3底的電鍍膜 16。附著後停止真空吸引，令供應金屬球用工具55下降一 定的高度。 附著在配線帶基板3下面的金屬球56則在下一站的金 屬球回流站C，以配置在上下的加熱器61暫行加熱（回 流）。藉此回流使金屬球56軟北溶融，在設有電鍍膜16的 配線11的表面形成爲焊錫突起電極（區域突塊陣列電極）5。 安裝半導體晶片2，形成焊錫突起電極5的配線帶基板 3,便連同被覆帶47 —倂被間歇方式捲入捲收用捲軸46。 製品以捲收用捲軸46的狀態出貨，由使用者切斷配線帶基 板3，取出半導體裝置1。 經濟部智慧財產局員工消費合作社印製 如此，以捲軸至捲軸方式電氣方式連接半導體晶片與 配線帶基板，且爲了保護半導體晶片主面而以樹脂封裝 時，最好是使用NCF等，採用介由熱硬化性樹脂使用供應 金屬球用工具將半導體基板搭載於配線帶基板上的手段。 將半導體基板搭載於配線帶基板上的習知手段有，線焊接 後進行傳遞模塑；及焊錫突塊回流安裝後塡底封裝等手 段，但無論那一種手段均會發生，很難與藉由捲軸至捲軸 方式進行的別的製程配合的問題。 與此比較，在使用熱硬化性樹脂進行熱壓接的手段， 則不僅，例如裝設金屬球、金屬球回流製程的製造時間或 裝配加工裝置架構成的配合較容易，也有能夠防止發生接 本紙張尺度適用中，國國家&準（CNS ) A4規格（210X297公釐） ' ~ ' -26- 579560 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（2) 觸不良的優點。 (實施形態7) 第23圖至第25圖是表示本發明其他實施形態（實施形 態7)的半導體模組（多晶片模組）的圖。本實施形態7的半導 體模組70是如第23圖的模式截面圖所示，備有絕緣性的 模組基板7 1。此模組基板7 1在主面有多數連接用電極 72，背面（圖上爲下面）有多數外部電極端子73。雖未圖 示，一定的外部電極端子73與一定的連接用電極72由貫 穿模組基板7 1內部的導體電氣方式相連接。外部電極端子 73由設在模組基板7 1背面的配線73a，與形成在此配線 7 3a上的突塊電極73b構成，成爲BGA型。 在模組基板71主面的連接用電極72是對應半導體裝 置1的焊錫突起電極5的排列配設成矩陣狀（區域陣列狀）， 以便能夠搭載實施形態1所示的半導體裝置1。如此的一群 連接用電極72是視需要配設在模組基板7 1的各處。 同時，在一部分的一群連接用電極72，換言之，在矩 陣狀排列的連接用電極的外側設有框狀的成爲線焊接墊的 連接用電極72a。在第23圖，連接用電極72a是配置在左 側。 在連接用電極72，藉回流固定（面朝下固定）有半導體 裝置1的焊錫突起電極5，半導體裝置1是搭載於模組基板 7 1。同時，在左側的半導體裝置1上介由未圖示的接合材 固定有半導體元件（半導體晶片）75。半導體晶片75是如第 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐Ί " -27- (請先閲讀背面之注意事項再填寫本頁) 579560 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（ 24圖所示，在露出面有電極76。而，各電極76與模組基 板71主面的連接用電極72a是以導電性的導線77連接在一 起。 、 半導體晶片75的固定接合材是導電性或非導電性均可 以。這時，若使用導電性的接合材，構成半導體晶片75的 基板是矽或化合物半導體時，便與構成半導體裝置1的半 導體晶片2的由矽構成的基板成爲等電位。因此，依據半 導體晶片2或半導體晶片75的電路架構時，兩者有時也可 以例如作爲GND電位而共同化。 如第24圖所示，連接模組基板71的導線77的多數連 接用電極72a的間距（d)，較設在半導體晶片75主面的多數 電極76的最小間距（a)爲大，成爲再配線構造。 同時，如實施形態1所示，多數焊錫突起電極5是以 較半導體晶片2的電極6的最小間距爲大的間距排列成由 多數行、業構成的格子狀，這也成爲再配線構造。此等再 配線構造可以促進半導體晶片的搭載的容易化。 同時’以下的構造特徵在實施形態1有說明，半導體 裝置1的絕緣基材層（帶狀基材）1〇的厚度與接合材4的厚 度的和爲50〜1〇〇 μπι，半導體裝置丨的絕緣基材層10的厚 度較接合材4的厚度爲厚，半導體裝置1的接合材4的厚 度爲50 μιη以下。而在半導體裝置丨的絕緣基材層的主面 上形成有覆蓋配線11的一部分的絕緣膜（抗焊錫膜）1 2，絕 緣基材層1 0的厚度較絕緣膜1 2的厚度爲厚。而且，半導 體裝置1的金突起電極（金線突塊電極）2〇的彈性率，較絕 本紙張尺度適用中關家標準（CNS ) A4規格（21GX；Z97公釐) 一 -28- (請先閱讀背面之注意事項再填寫本頁) 579560 經濟部智慧財產局員工消費合作社印製 A7 ___B7 _五、發明説明（^ 緣基材層1 0的彈性率及接合材4的彈性率爲大。而此等構 造特徵在半導體模組70也可以發揮與半導體裝置1同樣的 效果。 同時，在模組基板7 1的主面側，藉由傳遞模塑的單面 模塑形成有絕緣性樹脂構成的封裝體79。藉由此封裝體79 可以完全覆蓋半導體裝置1、半導體晶片75、連接用電極 72、72a及導線77等。 本實施形態7的半導體模組70，是依第24圖所示的流 程圖製造。雖未圖示，但如流程圖所示，準備半導體晶片2 後（S 101)，在半導體晶片的電極部分形成金線突塊電極 20 (S 102)，將半導體晶片2接合在配線帶基板3 (S 103)。 接著，在配線帶基板3的一定處所裝置金屬球（焊錫 球）（S 104)，然後，進行半導體裝置的單體的測試（半導體 單體測試：S 105)。 接著，準備模組基板71後，在此MCM基板搭載半導 體裝置1或半導體晶片75，且以導線77連接半導體晶片 75的電極76與連接用電極72a，同時，藉由單面模塑形成 封裝體79，覆蓋半導體裝置1、半導體晶片75、連接用電 極72、72a及導線77，結束模組的安裝（S 106)。而且，進 行如此製成的半導體模組70的測試（S 107)，去除不良 品，將良品出貨。 要形成MCM (MCP :多晶片組件）時，堆疊安裝半導體 晶片對MCP的小型化有效。堆疊半導體晶片時，下層的晶 片採用介由突起電極連接的面朝下的形態較之，將下層晶 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -29- 579560 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（2) 片面朝上搭載而線焊接時，對形成在半導體晶片主面上的 電極布置的限制較少，可以成爲自由度高的組件形態。 而關於以面朝下方式安裝的半導體晶片，依據本發明 的組件形態形成突起電極較有效。 亦即，以面朝下方式安裝的半導體晶片.，採用在半導 體晶片主面上的電極（焊接墊）上直接形成突起電極，而藉由 該突起電極連接在模組基板上的裸露晶片安裝法時，突起 電極的間隔受到半導體晶片上的電極的間隔的限制，其間 隔總是會變狹窄，因此，模組基板必須準備能夠形成細微 配線的尺寸準確度高的基板，會產生零件單價的上昇使模 組價格高昂的問題。 同時，如果以面朝下方式安裝的半導體晶片採用晶圓 級組裝品（WPP : Wafer Process Package )時，對不良晶片施 加的組裝製程的單價，會加在良品晶片的單價上，因此， 同樣會發生零件單價的上昇，有模組價格高昂的問題。 與這一些比較，本發明的半導體模組，其價格可以抑 制得較低，同時，尤其是將半導體晶片積層於組件內安裝 時，也可以有同時能滿足對各個半導體晶片要求的薄型化 要求的優點。 以i： ’依據實施形態具體說明由本發明人完成的發 明’但本發明並不限定於上述實施形態，當然可以在不脫 離其主旨的範圍內作各種變更。 簡單說明，可從本案所揭示的發明中具代表性者獲得 的效果如下。 (請先閱讀背面之注意事項再填寫本頁} 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -30- 579560 經濟部智慧財產局員工消費合作社印製 A7 ____B7_五、發明説明（^ 因爲可以用配線帶基板，使沿周緣配置線焊接用電極 的半導體晶片，成 爲間距較上述電極大的區域陣列突塊電極，因此，可 以提高電氣特性。亦即，特別是可以將高速信號處理化所 不可或缺的電感，從線焊接法的1〜1. 5 η Η降低至 0，1 η Η。 由於使線焊接用的電極成爲間距較此電極寬的區域陣 列突塊電極，因 此，可以提高安裝半導體裝置時的連接可靠性。 設有區域陣列突塊電極的配線帶基板具有，大小與半 導體晶片相同，且 * 與半導體晶片一致重疊的構造，因此可以達成半導體 • 裝置的小型化。 (4) 可以將多數不同種類的半導體晶片裝設在同一配 線帶基板，可以達成半導體裝置的MCM化。 (5) 同時，由於使外部連接電極成爲區域陣列，可以 使半導體裝置的電極間距加大，可以使用傳統的層壓法形 成的廉價的絕緣性基板（有機基板）。 (6) 而且是真實晶片尺寸的半導體裝置，可以達成小 型、輕量且可以倒裝晶片，可以傳送高速信號，因此’可 以期待在攜帶式機器、通信機器廣被利用。 (7) 可以提供能夠達成高速信號處理化、高功能化、 高密度安裝化、薄型化及輕量化的半導體模組（多晶片模 組）。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 -31 - 579560 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（ 如以上所述，本發明的半導體裝置對電子機器的控制 用或記憶用的半導體裝置有用，特別是適合於能夠達成高 速信號處理化、高功能化、高密度安裝化、薄型化及輕量 化的半導體裝置。 圖式之簡單說明 第1圖是表示本發明一實施形態（實施形態1)的半導體 裝置的模式截面圖。 第2圖是本實施形態1的半導體裝置的平面圖。 第3圖是本實施形態1的半導體裝置的背面圖。 第4圖是表示本實施形態1的區域陣列電極與半導體 晶片的電極的結線狀態的半導體裝置的模式平面圖。 第5圖是本實施形態1的半導體裝置的半導體晶片的 模式平面圖。 第6圖是本實施形態1的半導體裝置的配線帶基板的 平面圖。 第7圖是上述配線帶基板的模式截面圖。 第8圖是上述配線帶基板的背面圖。 第9圖是表示製造本實施形態1的半導體裝置時在電 極上形成金導線突塊電極的半導體晶片的模式截面圖。 第10圖是表示製造本實施形態1的半導體裝置時重疊 在半導體晶片上的接合材及配線帶基板的模式截面圖。 第11圖是表示製造本實施形態1的半導體裝置時介由 接合材在半導體晶片上接合配線帶基板的狀態的模式截面 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐) " 一 ' -32- (請先閱讀背面之注意事項再填寫本頁) 579560 經濟部智慧財產局員工消費合作社印製 A7 __________B7__五、發明説明（3(J 圖。 第12圖是表示製造本實施形態丨的半導體裝置時介由 接合材重疊接合在半導體晶片上的配線帶基板的模式截面 圖。 第1 3圖是表示製造本實施形態1的半導體裝置時將區 域陣列電極固定在配線帶基板的狀態的截面圖。 第14圖是表示搭載本實施形態1的半導體裝置的電子 裝置的部分模式截面圖。 第15圖是表示本發明的其他實施形態（實施形態2)的 半導體裝置的模式截面圖。 第16圖是表示本發明的其他實施形態（實施形態3)的 半導體裝置的模式截面圖。 第17圖是表示本發明的其他實施形態（實施形態4)的 半導體裝置的模式截面圖。 第18圖是表示本發明的其他實施形態（實施形態5)的 區域陣列電極與半導體晶片的電極的結線狀態的半導體裝 置的模式平面圖。 第1 9圖是表示本實施形態5的變形例子的區域陣列電 極與半導體晶片的電極的結線狀態的半導體裝置的模式平 面圖。 第20圖是表示本發明的其他實施形態（實施形態6)的 使用多連帶製造半導體裝置的方法的模式圖。 第21圖是表示製造本實施形態6的半導體裝置時將半 導體晶片搭載於配線帶基板的狀態的放大模式圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公釐） " 一 -33- (請先閱讀背面之注意事項再填寫本頁) 訂 579560 A7 __ B7_____五、發明説明（3) 第22圖是表示製造本實施形態6的半導體裝置時供應 焊錫球形成焊錫突起電極的方法的模式圖。 第23圖是表示本發明的其他實施形態（實施形態7)的 多晶片模組的模式截面圖。 第24圖是表示本實施形態7的多晶片模組的半導體晶 片的電極排列與多晶片模組基板的線焊接墊的排列模式 圖。 第25圖是表示本實施形態6的多晶片模組的製造方法 的流程圖。 主要元件對照表 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1 ..........半導體裝置 2 ..........半導體晶片 3 ..........配線帶基板 4 ..........接合材 5 ..........區域陣列突塊電極 6 ..........電極 7 ..........絕緣膜 10 ........一帶狀基材 11 ..........配線 12 ..........抗焊錫膜 13 ..........開口部 ……開口溝 15、16..........電鍍膜 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -34- 579560 A7 B7 五、發明説明（ 經濟部智慧財產局員工消費合作社印製 20--........金突塊電極 25-.........下模具 26 — —......上模具 30..........安裝基板 45---.......捲軸 46 ..........捲收用捲軸 47 ..........被覆帶 48 ......-一-被覆帶用捲軸 50——……筒夾 51..........工作台 55..........供應金屬球用工具 5 6----------金屬球 5 7----------球供應箱 58--........助焊劑槽 59----------助焊劑液 60——……軸 70 ----------半導體模組 71 ..........模組基板 72 ..........連接用電極 73 ..........外部電極端子 75 ..........半導體晶片 77..........導線 76 ..........電極 79……--一封裝體。 (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 本紙張尺度適用中.國國家標率（CNS ) A4規格（210X297公釐） -35-

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  1. 579560
    曰修正:Zi^5fcr/·補·^ 六、申請專利範圍 第9111211 8號專利申請案 中文申請專利範圍修正本 (請先閲讀背面之注意事項再填寫本頁) 民國92年7月4 日修正 1.一種半導體裝置，具備有： 有一主面、形成在上述主面上的多數半導體元件及多 數電極的半導體晶片； 形成在上述半導體晶片的各電極上的金突起電極； 備有’有一主面及一背面的絕緣基材層、形成在上述 絕緣基材層的主面上的多數配線、及形成在上述絕緣基材 層的貫穿孔的配線基板； 在上述配線基板的主面上，具有分別連接在各多數配 線而形成的多數焊錫突起電極的半導體裝置，其特徵在 於， 上述配線基板是將上述絕緣基材層的背面面向上述半 導體晶片的主面配置， 上述絕緣基材層的背面與上述半導體晶片的主面是介 由接合材接合在一起， 經濟部智慧財產局員工消費合作社印製 上述金突起電極的各電極是在上述貫穿孔的內部與上 述配線基板的配線連接， 上述多數焊錫突起電極以較上·述半導體晶片的電極的 最小間距爲大的間距，排列成由多數行、列構成的格子 狀， 上述焊錫突起電極的各電極是介由上述接合材及上述 絕緣基材層，配置在上半導體晶片的主面上。 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） 579560 A8 B8 C8 D8 六、申請專利範圍 2·如申請專利範圍第1項的半導體裝置，其中，上述絕 緣基材層的厚度與上述接合材的厚度的和爲50〜丨〇〇 μηι。 (請先閱讀背面之注意事項再填寫本頁) 3·如申請專利範圍第1項的半導體裝置，其中，上述絕 緣基材層的厚度較上述接合材的厚度爲厚。 4.如申請專利範圍第2項的半導體裝置，其中，上述接 合材的厚度爲50 μιη以下。. 5·如申請專利範圍第1項的半導體裝置，其中，上述絕 緣基材層的主面上形成有覆蓋上述配線的一部分的絕緣 膜’上述絕緣基材層的厚度較上述絕緣膜的厚度爲厚。 6·如申請專利範圍第1項的半導體裝置，其中，上述多 數配線是由銅膜、形成在上述銅膜表面的S η電鍍膜或 N i - A u電鍍膜所構成。 7.如申請專利範圍第1項的半導體裝置，其中，上述接 合材是熱硬化性樹脂。 8·如申請專利範圍第1項的半導體裝置，其中，上述半 導體晶片的電極是沿上述半導體晶片主面的周圍排列。 經濟部智慧財產局員工消費合作社印製 9·如申請專利範圍第1項的半導體裝置，其中，上述半 導體晶片的電極是沿形成輸入輸出電路用元件的領域排 列。 I 〇·如申請專利範圍第1項的半導體裝置，其中，上述 焊錫突起電極是配置在離開配置上述金突起電極的領域的 領域。 II ·如申請專利範圍第1項的半導體裝置，其中，上述 金突起電極的彈性率較上述絕緣基材層的彈性率及上述接 本紙張尺度通用宁國國冢揉準（CNS ) A4規格（210X297公釐） -2 - 579560 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 夂、申請專利範圍 合材的彈性率大。 12·如申請專利範圍第1項的半導體裝置，其中，上述 絕緣基材層是由可撓性膜構成。 13·如申請專利範圍第1項的半導體裝置，其中，上述 可撓性膜是由聚醯亞胺（polyimide)系樹脂構成。 14· 一種半導體裝置的製造方法，包含有： 準備，具有一主面、形成在上述主面上的多數半導體 元件及多數電極的半導體晶片的製程； 準備，具有，有一主面及一背面的可撓性薄膜狀的絕 緣基材層、形成在上述絕緣基材層的主面上的多數配線、 及形成在上述絕緣基材層的貫穿孔的配線基板的製程； 在上述半導體晶片的各電極上形成金突起電極的製 程； 在上述絕緣基材層的背面與上述半導體晶片的主面之 間，介由接合材將上述配線基板配置在上述半導體晶片的 主面上的製程； 在配置上述配線基板的製程之後，對上述配線基板施 加壓力，令上述金突起電極與上述配線在上述貫穿孔的內 部接觸，且對上述接合材加熱使其硬化的製程；以及， 在上述配線基板的主面上，將多數焊錫突.起電極連接 在各多數配線而形成多數電極的製程， 上述多數焊錫突起電極以較上述半導體晶片的電極的 最小間距爲大的間距，排列成由多數行、列構成的格子 狀， 本紙張尺度逋用中國國家梂準（CNS ) A4規格（210x297公釐） ---------------訂------ (請先閱讀背面之注意事項再填寫本頁) 579560 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 上述焊錫突起電極的各電極是介由上述接合材及上述 絕緣基材層，配置在上半導體晶片的主面上。 15·如申請專利範圍第項的半導體裝置的製造方法， 其中，上述接合材是熱硬化性樹脂。 16·如申請專利範圍第i4項的半導體裝置的製造方法， 其中’上述金突起電極的彈性率較上述絕緣基材層的彈性 率及上述接合材的彈性率大。 1 7 ·如申請專利範圍第1項的半導體裝置，其中，上述 配線基板的至少一個焊錫突起電極與上述半導體元件的多 數上述電極成電氣方式連接，而成爲共同電極。 18·如申請專利範圍第17項的半導體裝置，其中，上述 焊錫突起電極的數目較上半導體元件的上述電極的數目 少。 19·一種半導體裝置的製造方法，其特徵在於，準備多 數具有半導體裝置形成部的配線帶基板，在其一部分的半 導體裝置形成部的一面，介由熱硬化性接合材加壓加熱搭 載半導體晶片。 20 ·如申請專利範圍第1 9項的半導體裝置的製造方法， 在上述配線帶基板的一部分的半導體裝置形成部的一面搭 載上述半導體晶片後，在上述半導體裝置形成.部的其他一 面的配線裝設金屬球而形成球電極。 21.如申請專利範圍第19項的半導體裝置的製造方法， 其中，上述配線帶基板的上述半導體裝置形成部的架構 是，具有：有一主面及一背面的絕緣基材層；形成在上述 本紙張尺度逋用中國國家梂準（CNS ) A4規格（210X297公釐） ---------------訂------ (請先閱讀背面之注意事項再填寫本頁) -4- 579560 A8 B8 C8 D8 六、申請專利範圍 絕緣基材層的主面上的多數配線；及形成在上述絕緣基材 層，上述配線位於其底部的貫穿孔， (請先閲讀背面之注意事項再填寫本頁) 上述半導體晶片的架構是，具有：一主面、形成在上 述主面上的多數半導體元件及多數電極，上述各電極上有 金突起電極， 在加壓加熱搭載上述·半導體晶片時，令上述金突起電 極的前端刺穿上述熱硬化性接合材，壓接固定在上述配線 帶基板的貫穿孔底的配線。 22.如申請專利範圍第19項的半導體裝置的製造方法， 其中，上述配線帶基板的上述半導體裝置形成部的架構 是，具有：有一主面及一背面的絕緣基材層；形成在上述 絕緣基材層的主面上的多數配線；及形成在上述絕緣基材 層，上述配線位於其底部的貫穿孔， 上述半導體晶片的架構是，具有：一主面、形成在上 述主面上的多數半導體元件及多數電極，上述各電極上有 金突起電極， 經濟部智慧財產局員工消費合作社印製 形成上述球電極時，將上述金屬球連接到上述配線帶 基板的主面的配線。 23·如申請專利範圍第19項的半導體裝置的製造方法， 是從捲軸拉出上述配線帶基板，進行上述半導體裝置形成 部的裝配加工後，捲收在捲收用捲軸。 24.—種半導體模組，其特徵在於，具備有： 主面有多數連接用電極，背面有多數外部電極端子， 上述一定的外部電極端子與上述一定的連接用電極以貫通 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） -5- 579560 A8 B8 C8 ____ D8 六、申請專利範圍 內部的導體電氣方式連接在一起的絕緣性的模組基板； (請先閲讀背面之注意事項再填寫本頁) 搭載於上述模組基板的主面的一個以上的半導體裝 置；以及 至少搭載於一個上述半導體裝置上，露出的主面有多 數電極的半導體元件， 上述半導體元件的一.定的電極與上述模組基板的主面 的一定的連接用電極，用導電性的導線連接在一起， 連接上述模組基板的主面的上述導線的多數上述連接 用電極，其間距較上述半導體元件的主面的多數電極的最 小間距大， 上述半導體裝置備有·· 具有一主面、形成在上述主面上的多數半導體元件及 多數電極的半導體晶片； 形成在上述半導體晶片的各電極上的金突起電極； 具有，有一主面及一背面的絕緣基材層、形成在上述 絕緣基材層的主面上的多數配線、及形成在上述絕緣基材 層的貫穿孔的配線基板；以及， 經濟部智慧財產局員工消費合作社印t 分別連接在各多數配線，形成在上述配線基板的主面 上的多數焊錫突起電極， 上述配線基板是配置成，上述絕緣基材層的背面面對 上述半導體晶片的主面， 上述絕緣基材層的背面與上述半導體晶片的主面是介 由接合材接合在一*起’ 上述金突起電極之各電極是在上述貫穿孔之內部與上 ^紙張尺度逋用中國國家揉準( CNS ) A4規格（210X297公釐） " -6 - 579560 Α8 Β8 C8 D8 六、申請專利範圍 述配線基板之配線連接在一起， 上述多數金突起電極以較上述半導體晶片的電極的最 小間距爲大的間距，排列成由多行、列構成的格子狀， 上述焊錫突起電極的各電極是介由上述接合材及上述 絕緣基材層配置在上述半導體晶片的主面上， 上述焊錫突起電極是.連接在上述模組基板的主面的連 接用電極。 25·如申請專利範圍第24項的半導體模組，其中，上述 半導體裝置的絕緣基材層的厚度與上述接合材的厚度的和 爲 50 〜100 μιη。 26·如申請專利範圍第24項的半導體模組，其中，上述 半導體裝置的上述絕緣基材層的厚度較上述接合材的厚度 爲厚。 27.如申請專利範圍第24項的半導體模組，其中，上述 半導體裝置的上述接合材的厚度爲50 μιη以下。 28·如申請專利範圍第24項的半導體模組，其中，上述 半導體裝置的上述絕緣基材層的主面上形成有覆蓋上述.配 線的一部分的絕緣膜，上述絕緣基材層的厚度較上述絕緣 膜的厚度爲厚。 29·如申請專利範圍第24項的半導體模組.，其中，上述 半導體裝置的上述金突起電極的彈性率較上述絕緣基材層 的彈性率及上述接合材的彈性率大。 30· —種半導體裝置的製造方法，包含有：· 準備，具有一主面、形成在上述主面上的多數半導體 本紙張尺度適用中國國家揉準（CNS ) Α4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) ，1Τ. 經濟部智慧財產局員工消費合作社印製 579560 A8 B8 C8 D8 六、申請專利範圍 元件及多數電極的半導體晶片的製程； (請先閲讀背面之注意事項再填寫本頁) 準備，具有，有一主面及一背面的可撓性薄膜狀的絕 緣基材層、形成在上述絕緣基材層的主面上的多數配線、 及形成在上述絕緣基材層的貫穿孔的配線基板的製程； 在上述半導體晶片的各電極上形成金突起電極的製 程； 在上述絕緣基材層的背面與上述半導體晶片的主面之 間’將上述配線基板配置在上述半導體晶片的主面上的製 程； 在配置上述配線基板的製程之後，對上述配線基板施 加壓力，令上述金突起電極與上述配線在上述貫穿孔的內 部接觸，且接合上述配線基板與上述半導體晶片的製程； 以及， 在上述配線基板的主面上，將多數焊錫突起電極連接 在各多數配線而形成多數電極的製程， 經濟部智慧財產局員工消費合作社印製 上述多數焊錫突起電極以較上述半導體晶片的電極的 最小間距爲大的間距，排列成由多數行、列構成的格.子 狀， 上述焊錫突起電極的各電極是介由上述接合材及上述 絕緣基材層，配置在上半導體晶片的主面上。. 3 1 ·如申請專利範圍第30項的半導體裝置的製造方法， 其中，上述金突起電極的彈性率較上述絕緣基材層的彈性 率大。 . 32.如申請專利範圍第30項的半導體裝置的製造方法， 本紙張尺度逋用中國國家揲率（CNS ) A4规格（210X297公釐） -8- 579560 A8 B8 C8 D8 六、申請專利範圍 其中，上述多數配線是由銅膜、形成在上述銅膜表面的S η 電鍍膜或N i - A u電鑛膜所構成。 (請先閲讀背面之注f項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度逍用中國國家橾準（CNS ) A4规格（210X297公釐） -9-
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