TW567599B - Wafer level package with air pads and manufacturing method thereof - Google Patents

Wafer level package with air pads and manufacturing method thereof Download PDF

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Publication number
TW567599B
TW567599B TW091134312A TW91134312A TW567599B TW 567599 B TW567599 B TW 567599B TW 091134312 A TW091134312 A TW 091134312A TW 91134312 A TW91134312 A TW 91134312A TW 567599 B TW567599 B TW 567599B
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Taiwan
Prior art keywords
metal
pad
patent application
metal connection
layer
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TW091134312A
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English (en)
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TW200303078A (en
Inventor
Gu-Sung Kim
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Samsung Electronics Co Ltd
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Publication of TW200303078A publication Critical patent/TW200303078A/zh
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Publication of TW567599B publication Critical patent/TW567599B/zh

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    • HELECTRICITY
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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567599 ⑴ 狄、發明說明 u月况鳩敘明.發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 發明背景 術領娀 、,、^月大致有關半導體製造,更特別地是,有關一具有 增進連接可靠度的晶圓層級封裝(WLp)和—製造方法。 2^_先前拮術 為了符口幸又新一代電子產品的封裝需求,必須花費心血 =創k可Λ、具成本效益、微小、和高性能的封裝。上述 而求例如疋電子訊號傳遞延遲的降低、整體零件區的減少 、和在輸入/輸出(1/〇)端點位置有更廣的自由。 為了符合這些要求,一 WLp已被開發,其中一陣列的外 部I/O端點分布在半導體晶片表面上,而不是只是位於在一 個或更多晶片邊緣的周圍如傳統的導線架封S。典型地, 一陣列的錫球提供表面分布1/0端點給WLP。上述端點位置 的分布降低埋置訊號線的需要,其連接積體電路IC的電路 區塊到位於邊緣的傳統1/0端點。消除上述訊號線增進裝置 的電性,因為這樣的線典型地有一高電容。而且,當鎮上 時此區域被WLP佔領’並且藉由錫球和一印刷電路板或其 他基板連接,、是曰曰片大小’而不是封裝的導線架大小。因 此,WLP的尺寸可做得非常小。 圖1表示一傳統錫球連接結構的剖面視圖。晶片1〇有一連 接墊20藉由錫球4G黏著到基板或印刷電路板(pCB)5〇。然而 如此連接衣置的一重大缺點是金屬錫球4〇是最無彈性 的。在連接塾20和锡球40間的接合處以陰影區3〇表示。此 陰影區30和錫球40是相同的材料並以不同的元件顯示只是 (2) (2)567599
為了解釋的目白勺’為了顯示後續裂縫的作用和導致於晶片 10和PCB 50間分歧移動的無彈性應力。 囷1 b_ 1 c表示圖1 &所示傳統錫球結構在不同熱循環階段 』間的d面視圖’ #即分別是加熱和冷卻,顯示垂直移動 和作用在連接結構的力量導致膨脹和縮收。 參照圖lb,在一般和電子裝置典型操作有關的熱變化下 :在石夕晶片U)和環氧道璃pcB5〇間一顯著不一致的熱膨服 係數(CTE)會導致機械應力作用在錫球連接的接合處。換 言之,當晶片跡熱時,晶片1〇和PCB 50都以不同比率膨 脹,其會產生如圖lb的扭曲。當熱去除時,晶片i〇*pcB5〇 :以不同比率縮收如圖lc所示。這相對的膨脹和縮收對固 貫的連接亦即錫球40產生應力。如此膨脹/縮收差異對於 較大的晶片尺寸變得更明顯,晶片的周圍區域比晶片的中 間部分呈現更大顯著的膨脹。 可=易看出’當一側或另一相對側的銲錫連接移動,例 如在前述熱膨脹和縮收期間,可看到—扭力作用在錫球4〇 和接合處30。典型地,以低於錫球熔點溫度的重覆膨脹和 縮收,對固實接合處30可被充足的加壓來從墊20引起分裂 或裂縫如圖le區域標示32所示,因此傷害銲錫連接的可靠 度。 因此,對於WLP具有改善連接可靠度有一展示的需要, 特別是在晶片和PCB之間,以及製造的方法。 發明内容 本發明的-特徵是提供—半導體裝置封裝產品,例如基 (3) (3)567599 圓,級封裝(WLP)具有絕佳的可靠度並降低生 根據本發明—較佳呈 — 成本 I/O端點的特色為”::母一個表面分布多數的 規則形凹洞在一其板内A。虱塾的結構包㈣刻-不 支擇声到凹ί内積一由可溶解材料做成的暫時 s ” 儿積一金屬連接墊到暫時支撐層上、以 便至少部分的全屬;鱼姑 曰上 w 部分相心。 伸超過不規則相洞並覆蓋一 二:ir=然後溶解支撐層來產生空氣緩衝在金屬 玉屬連接墊被前述覆蓋的基板部支撐 此氣墊的特色_為一支撐結構,其中一 超過全眉i皇垃轨— ’、 ;;豆工間侧向延伸 孟屬連接墊。在金屬連接㈣·附近有充分的 支撐=金!:妾墊的沉積/形成時需要移除暫時的可溶解 ;:科、和2)-般熱的自由度與振動的移動沒有和基板 具體實施例中,在晶圓層級封裝中提 :…連接的、4包括一金屬連接塾其覆蓋一氣穴 至>-。P分的氣穴側向延伸超過金屬連接墊,: 連接塾覆蓋並接觸到多數的周圍支撐結構。而/、中金屬. 多數的周圍支撐結構也支撐配線圖案 =至少一 連接塾到其他晶片上的電路。 地連接金屬 -較佳氣穴是定義在介電層,其中介電層 提供支撐給金屬連接墊。至少一突出 f用來 案有電地連接到金屬連接墊。此外,此結:能支撑配線圖 一第二介電層穿過它一部分的金屬連接墊晨1 =步包含 -保護金屬層形成在金屬連接墊暴露的部::。來,並且 (4) 567599
—~· 一 =^發明’在晶®層級封裝中提供彈性連接結構的製 二=包括較佳的步驟為:形成—氣穴在半導體基板上; 圖㈣材料填入氣穴;形成一金屬層在可移除材料上; 氣;側:屬層來形成一金屬連接墊,其藉由至少-部分的 除材=Γ:Γ墊來完成;從氣穴中移除可移 “屬層…將可移除材料平坦化,且此平坦化 單程或一CMP製程來執行。此可移除材料可選自由 早體材料、多體材料、和彈性體材料組成之群,例如— 解rrbie材料。此可移除材料可藉由濕钱刻化學劑來溶 ^最好藉由沉積-介電層和使用一微影製程來圖宰化 ^"電層而形成。此外,在形成金屬連接墊之後, 可沉積在金屬連㈣上以致—部分的 穿過:介電層暴露出來。再者,藉由使用無電解電鑛二 沉積在金屬連接塾上。此保護層可使用選 和鎳組成之群的金屬構成。 ” 使用-低介電材料如空氣在連接墊之下 =增加相關電子訊號傳遞的速度。藉由構成只有在^ U以圍墊具有支撐墊的結構’一完成的鲜锡連接可吸 +導體晶片和印刷電路板間分歧移動相關的機械應 本發明的這些和其他特徵對普通熟悉此 下詳述後將报快地明白。 β 在看凡以 (5) (5)567599
實施方式 。康本毛月’ 一彈性氣墊連接結構在積體電路(1C)的晶 圓層、.及封哀(WLP)中提供_低介電電容’其分隔一輸入/輸 出(I/O)金屬連接墊和其下具有電路的—基板。傳統無彈性 耽塾連接結構被典型㈣封住且被緊鄰層所有邊緣支撐著 。使用此結構只是降低-節點的電容,其藉由以具有低介 電常數的空氣㈣-有機切基的介電材料在電容的電極 板=間(亦即連接塾和基板)。然而’本發明的氣塾結構提供 最v數里的支撐點/導電接觸在連接墊的周圍,來允許連 接塾有-最大量的垂直和側向熱和/或機械移動,同時仍提 供空氣介質所有的低電容。此最少組接觸提供彈性給連接 、’、CT 5處,其可降低破壞性的機械應力在一銲錫連接上。 製造上述的氣墊可使用以下步驟::^在…基板内產生一 不規則形凹洞具有少數周圍墊支撐且大於所要的連接墊; 2)以可溶基材料如單體材料、多體材料、和彈性體材料填 入凹洞;3)在固化可溶基材料之後,沉積一金屬墊層到可 溶基層上並覆蓋住周圍墊支撐;以及4)溶解與移除可溶基 層,在金屬墊層下留下一氣縫,金屬墊層由周圍墊支撐^ 所支持並與周圍墊支撐部形成電性的接觸。 圖2a和2b表示在沉積一覆蓋金屬連接墊13〇之前和之後 氣墊凹洞120的上平面視圖。 圖2a表示氣墊凹洞120形成在介電層11〇内的上平面視圖 。凹洞120有充分的深度以便在所有環境和機械條件下,後續 覆蓋金屬塾(圖2b的130)的屈曲不會碰到凹洞12〇的底部。凹 (6) (6)567599
洞120的形狀是使得介電層突出對U2可較佳地提供 支撐給以下步驟沉積的金屬連接墊(圖孔的13〇)。需要注意 的是一最少需要二個這樣相對的支撐112,雖然大部分的運 用最好有3或4個此類支撐112。針對在焊接期間需要最大垂 直移動彈性的運用,只有運用到二個支撐,因此允許金屬 連接塾在外部連接裝置,亦即錫球,在焊接期間有“搖晃” 的性能。另一具體實施例可運用導線當作外部連接裝置, 俾提供額外的連接彈性和可#度,同時仍然具有wLp技術 之尺寸和空間的優勢。 圖2 b表示在沉積或置放金屬連接墊丨3 〇到圖2 &中氣墊凹 洞120上後的一氣墊結構1〇〇。從圖以和礼的上平面視圖可 看得出,氣墊凹洞120最好大於金屬連接墊13〇,除了在支 撐/連接點對112外,以便部分的金屬連接墊13〇沒有接觸到 支撐/連接點112懸浮在空中,並具有一限制自由度的垂直 矛夕動到其下的氣縫中。過大的凹洞^^^也在凹洞Η。邊緣和 墊130邊緣之間提供一暴露區,其中可運用溶解劑且暫時可 溶基材料可被移除。對於金屬連接墊13〇其提供電訊連接, 電路圖案140形成在介電層上並連接到金屬連接墊 130的一個或更多的支撐/連接點n2。因此,導線圖案14〇 在金屬連接墊13〇和晶片積體電路之間作直接的電氣連接 。在導線圖案140和墊130之間的金屬連接之總接觸面積必 屑等於導線圖案140斷面的載電流。這顯示在點142有加寬 的V線圖案140。墊1 30的較佳形狀通常是橢圓形或矩形具 有一長軸其最好朝向WLP的中心。 -10- 567599
圖3a表示沿著圖2a和圖2b的線A-A,所取的剖面視圖,且 3 b疋/σ耆圖2 a和圖2 b的線B - B ’所取的剖面視圖。一起參照 圖3a和3b,為了保護晶片的積體電路免於在以氧化矽、氮 化矽、氧氮化矽等覆蓋晶片的保護層12和使用在導線和連 接圖案如銀(Ag)或銅(Cu)的金屬間的熱膨脹係數差異,並 免於機械傷害,因第一介電層11〇插入其中。第一介電層ιι〇 作為一應力緩衝區並增進電訊反應特性。第一介電層丨1〇最 好u括令亞胺材料(介電常數·· 2.8)具有一約2微米到5〇 微米的厚度。_ 在第一介電層110上形成金屬連接墊13〇和導線圖案(圖 2_4〇)最好包括一金屬例如銀(Ag)或銅(cu)。金屬連接墊 130可使用傳統的賤鑛、蒸錄、電錢、無電解電鍵法、或這 些方法的組合來形成。一種子金屬層132在形成金屬連接墊 13〇前可預先形成。導線圖案的厚度最好厚過傳統 金屬的厚度,亦即將進15_到5〇_。 復蓋^線圖案’-第:介電層16()最好由具有約2㈣到約 ΓμΐΏ的聚亞胺材料構成。第二介電層⑽提供側向機械保 4給錫球40 ’因此保護錫球4〇免於接合破壞與降低對晶片 的:在機械傷害而不是改善電氣特性。第二介電層160的材 料取好V用上等的機械和化學特性以保護晶片免於 境應力。 • Ρ刀的連接墊130穿過第二介電層6〇暴露出來被以如 錄(N i)或金(a u)的金屬雷都p —、 羁4鍍或無電解電鍍,因此形成一防腐 蚀保護金屬層134。錫球40放在金屬連接塾13〇上。 -11- 567599
圖4a到4k表示根據本發明用以製造氣墊結構模範製程步 驟的剖面視圖。視圖的看法是從圖2&和沘所示的線b_b,。 雖然這些視圖沒有顯示在凹洞12〇邊緣和金屬連接墊13〇邊 緣之間的暴露區,透過它暫時支撐層被移除,如此一暴露 區被整合到本發明。 圖4a表示保護層12形成在包含很多IC晶片的晶圓上。保 護層12是以傳統的晶圓製造技術來製造。圖仆中,藉由冷 佈聚亞胺材料在保護層12上來形成第一介電層11〇,然後軟 烤、曝光和顯影。蝕刻之後形成氣墊凹洞12〇和支撐點(圖 2a中的112),最後硬烤第一介電層丨1〇。 如圖4c所示,一 B-stage-able高分子122最好藉由旋轉塗 佈法來形成。然後’如圖牝所示,使用回蝕法或化學機: 研磨法來平坦化B-stage-able高分子122以提供一均勻的表 面。然後賤鍍一種子金屬層132以產生如圖4e所示的平台: 在印上一光阻150到種子金屬層132上以後,光阻15〇被圖案 化如圖4f所示。 如圖4f所示,金屬被電鍍在種子金屬層132的暴露區上 且光阻150被移除,從而形成金屬連接墊13〇如圖&所示 。如圖4h所示,在連接墊13〇周圍外的一部份種子金屬層 132被蝕刻移除來產生只有連接墊13〇在平坦表面上如^ 4h所示。 參照圖4i ’最好以濕蝕刻化學劑將高分子^ 22 溶解透過前述在凹洞12〇邊緣和金屬連接墊i3〇邊緣之間的 暴露區將其從氣墊凹洞120中移除。然後,如圖例示,為 -12- (9) (9)567599
了側向的支撐金屬連接塾130’形成第二介電層i6〇。然後 電鍍上抗腐㈣護金屬層在金屬連㈣nG的暴露區上,例 如鎖(Ni)或金(Au)19,最好使用無電解電鑛法。最後,如圖 4k所示’形成或放上錫球4〇並保持_附著裝置在金屬連接 墊130上。 雖然本發明最好使用B_stage_aMe高分子作為可分解材 料在連接墊130之下’其他材料如矽甲完等可取代 B-stage-able南分子。 ,本發明提供,具有氣塾結構的WLP,其令有圖案的氣缝 形成在金屬連接墊130之下,從而增進WLp的可靠度和電氣 特性。 圖h表示根據本發明第二具體實施例的一氣塾結構2〇〇 。在此具體實施例中,-大體橢圓形的連接塾230有二個金 屬突出236延伸到第—介電層11〇的二個介電支撑上。圖^ 表示根據本發明第三具體實施例的一氣墊結構3〇〇,其中金 屬連接塾330有一大體圓形而不是圖2b中所示的矩形連接. 〇矛圖5a中的230。連接墊230或330的金屬突出236提供 支撐給連接塾23G或33G浮在氣墊凹洞12〇上,但是沒有直接 支樓著錫球。 么月的車又佳具體實施例已揭露於此,雖有運用特殊 員人,他們只是用在一般和描述性觀念而不是為了限制的 目=ο此藝一般技術者因此將了解在不脫離本發明如以下 申。月專利轨圍的精神和範圍下可進行不同型式和細節的變 -13- ^07599
(ίο) =貫穿全文同樣的參照符號代表同樣的結構元件。 表不—傳統銲錫連接結構的剖面視圖’· ::表示圖la所示傳統錫球結構在不同熱循環階段 和作用在、表桩沾 刀別疋加熱和冷卻,顯示垂直移動 連接、、、口構的力量導致膨脹和縮收;
面=表不根據本發明一較佳具體實施例氣墊凹洞的上平 塾=:連接塾—上之後的氣 圖3a表不著圖2a和圖2b的線A),所取的剖面視圖; 圖3b表示沿著圖2a和圖以的線b_b,所取的剖面視圖; 圖4a到4k表tf根據本發明—較佳具體實施 構之代表性步驟的剖面視圖; 乳蟄… 圖5a表示根據本發明之第二具體實施例氣墊結構的上平 面視圖;及
圖5b表示根據本發明之第三具體實施例氣墊結構的上平 面視圖; 圖式代表符號說明 10 晶片 12 保護層 20 連接墊 30 接合處 32 裂縫 -14- 567599 ⑼ 40 錫球 50 印刷電路板 100, 200, 300 氣墊結構 110 第一介電層 112 突出對 120 氣墊凹洞 122 B-stage-able聚合物 130 金屬連接墊 132 - 種子金屬層 134 保護金屬層 140 導線圖案 142 較寬的導線圖案 150 光阻 160 第二介電層 230 橢圓形金屬連接墊 236 金屬突出 330 圓形金屬連接墊
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Claims (1)

  1. 、申請專利範圍 —種用來在晶®層級封裝巾提供彈性連接的結構,其勺 ^-金屬連接塾覆蓋-氣穴,其中該氣穴至少__部分2 向延伸超過金屬連接墊。 如申請專利範圍第W之結構,其中氣穴包括—具有供人 屬連接墊用之多數個周圍支撐結構的幾何結構。盃 如申請專利範圍第2項之結構,其中至少— 也支撐-電性連接到金屬連接塾之配線圖案。“構 ,申請專利範圍第旧之結構,更包括—介電層來界定此 氣穴。 … 如申請專利範圍第4項之結構’其中介電層包括突出對, 以針對金屬連接墊來提供支撐部。 如申請專利範圍第5項之結構,其中至少一突出對亦支撐 一電性連接到金屬連接墊之配線圖案。 如申請專利範圍第4項之結構,更包括一第二介電層,藉 以使金屬連接墊之—部分可穿過此第二介電層而暴露出 來。 一、 如申請專利範圍第7項之結構,更包括-保護金屬層形成 在金屬連接墊暴露的部位上。 曰 一種在晶圓層級封裝中提供彈性連接之結構的製造方法 ,包括以下的步驟: …彳 A.在半導體基板上形成一氣穴; B •以可移除材料填入氣穴; C ·在可移除材料上形成一金屬層; 567599
    ------ , a水取成一金屬連接墊,藉此使氣穴的 至少一部分側向延伸超過金屬連接墊; Ε·從氣穴中移除可移除材料;以及 F.在金屬連接墊上形成一互連材料。 1〇.t申請專利範圍第9項之方法,其中在形成金屬層前將可 移除材料平坦化。 11.如申請專利範圍第丨〇項 # 鈾制立々 貝之方法,其中平坦化是藉由一回 蝕衣釭或一 CMP製程來執行。 !2·如申請專利範圍第9項 單俨姑、之方法,其中可移除材料是選自由 早體材枓、多體材料、和 13 φ ^ ^ 5早11體材枓組成之群的材料。 如申凊專利範圍第9項 “We材料。之方法,其中可移除材料是-Μ·如申請專利範圍第9項之 雷届4姑Μ 古其中乳穴是藉由沉積一介 電層和然後圖案化這個介電層而形成。 積" •如申請專利範圍第丨4項之 濕姓刻化學劑來溶解移除。…中可移除材料可藉由 1 6·如申請專利範圍第9項之方、 後,沉積一介電層在金屬連_ 形成金屬連接塾之 -部分穿過此介電層而暴露出來f ’以使金屬連接墊的 17·如申請專利範圍第9項之方 18後二積一保護層在金屬連接塾上中在形成金屬連接塾之 •如申凊專利範圍第17項之方 ^ 來進行保護層的沉積。 /、藉由無電解電鍍法 19·如申請專利範圍第18項之方法,其中使用八 甲使用一金屬來形成 567599
    保護層。 2 0.如申請專利範圍第1 9項之方法,其中金屬選自由金和鎳 組成之群。
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100726946B1 (ko) * 2004-12-24 2007-06-14 위니아만도 주식회사 다중 송풍구조를 갖는 에어컨 실내기
KR100596452B1 (ko) 2005-03-22 2006-07-04 삼성전자주식회사 볼 랜드와 솔더 볼 사이에 에어 갭을 갖는 웨이퍼 레벨 칩스케일 패키지와 그 제조 방법
KR100640659B1 (ko) * 2005-08-01 2006-11-01 삼성전자주식회사 가요성 인쇄회로 및 이의 제조방법
KR100699891B1 (ko) * 2006-01-14 2007-03-28 삼성전자주식회사 재배선을 갖는 웨이퍼 레벨 칩 사이즈 패키지 및 그제조방법
KR100712548B1 (ko) * 2006-01-27 2007-05-02 삼성전자주식회사 부양된 메탈라인을 갖는 웨이퍼 레벨 패키지 및 그 제조방법
JP2008159948A (ja) * 2006-12-25 2008-07-10 Rohm Co Ltd 半導体装置
KR100806350B1 (ko) * 2007-01-25 2008-03-06 삼성전자주식회사 반도체 소자 패키지 및 그 제조 방법
US8278748B2 (en) 2010-02-17 2012-10-02 Maxim Integrated Products, Inc. Wafer-level packaged device having self-assembled resilient leads
US8420950B2 (en) * 2010-03-02 2013-04-16 Stats Chippac Ltd. Circuit system with leads and method of manufacture thereof
US8686560B2 (en) 2010-04-07 2014-04-01 Maxim Integrated Products, Inc. Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stress
US8754338B2 (en) * 2011-05-28 2014-06-17 Banpil Photonics, Inc. On-chip interconnects with reduced capacitance and method of afbrication
US9093364B2 (en) 2011-06-22 2015-07-28 Stats Chippac Ltd. Integrated circuit packaging system with exposed vertical interconnects and method of manufacture thereof
US8815650B2 (en) 2011-09-23 2014-08-26 Stats Chippac Ltd. Integrated circuit packaging system with formed under-fill and method of manufacture thereof
KR102012935B1 (ko) 2012-06-13 2019-08-21 삼성전자주식회사 전기적 연결 구조 및 그의 제조방법
US9177931B2 (en) * 2014-02-27 2015-11-03 Globalfoundries U.S. 2 Llc Reducing thermal energy transfer during chip-join processing
JP6210922B2 (ja) 2014-04-04 2017-10-11 アルプス電気株式会社 電子部品
JP2015201495A (ja) 2014-04-04 2015-11-12 アルプス電気株式会社 電子部品
US10325860B2 (en) 2016-04-26 2019-06-18 Intel Corporation Microelectronic bond pads having integrated spring structures
KR20180069629A (ko) 2016-12-15 2018-06-25 삼성전자주식회사 반도체 장치
US10090271B1 (en) * 2017-06-28 2018-10-02 International Business Machines Corporation Metal pad modification

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52146558A (en) 1976-05-31 1977-12-06 Nec Corp Production of beam lead type semiconductor device
EP0529503A1 (en) 1991-08-22 1993-03-03 Hewlett-Packard Company Flexible attachment flip-chip assembly
US5592025A (en) * 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
JP2638557B2 (ja) * 1995-03-30 1997-08-06 日本電気株式会社 半導体装置
JP2674567B2 (ja) 1995-05-31 1997-11-12 日本電気株式会社 半導体装置
JPH09298252A (ja) * 1996-05-01 1997-11-18 Shinko Electric Ind Co Ltd 半導体パッケージ及びこれを用いた半導体装置
JP3719806B2 (ja) * 1997-01-20 2005-11-24 日本特殊陶業株式会社 配線基板
DE69820232T2 (de) * 1997-01-21 2004-09-16 Georgia Tech Research Corp. Verfahren zur herstellung einer halbleitervorrichtung mit luftspalten für verbindungen mit ultraniedriger kapazität
JP3371759B2 (ja) * 1997-06-16 2003-01-27 松下電器産業株式会社 導電性ボールの搭載方法
US6335222B1 (en) * 1997-09-18 2002-01-01 Tessera, Inc. Microelectronic packages with solder interconnections
US6333565B1 (en) * 1998-03-23 2001-12-25 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
JP2000091382A (ja) * 1998-09-14 2000-03-31 Shinko Electric Ind Co Ltd 多層配線基板への半導体チップの実装方法
JP2000133920A (ja) * 1998-10-23 2000-05-12 Toshiba Corp プリント配線板及び印刷ユニット構造
US6341071B1 (en) * 1999-03-19 2002-01-22 International Business Machines Corporation Stress relieved ball grid array package
JP3360723B2 (ja) * 1999-06-08 2002-12-24 日本電気株式会社 半導体素子のチップサイズパッケージ
US6221727B1 (en) * 1999-08-30 2001-04-24 Chartered Semiconductor Manufacturing Ltd. Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology

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DE10301432A1 (de) 2003-08-28
US20030153171A1 (en) 2003-08-14
JP4703938B2 (ja) 2011-06-15
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DE10301432B4 (de) 2007-10-18

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