TW559951B - A semiconductor device barrier layer - Google Patents

A semiconductor device barrier layer Download PDF

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Publication number
TW559951B
TW559951B TW091118815A TW91118815A TW559951B TW 559951 B TW559951 B TW 559951B TW 091118815 A TW091118815 A TW 091118815A TW 91118815 A TW91118815 A TW 91118815A TW 559951 B TW559951 B TW 559951B
Authority
TW
Taiwan
Prior art keywords
dielectric material
silicon nitride
semiconductor device
layer
notch
Prior art date
Application number
TW091118815A
Other languages
English (en)
Chinese (zh)
Inventor
Sailesh Mansinh Merchant
Isaiah O Oladeji
Seong-Jin Koh
Original Assignee
Agere Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Inc filed Critical Agere Systems Inc
Application granted granted Critical
Publication of TW559951B publication Critical patent/TW559951B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW091118815A 2002-05-21 2002-08-20 A semiconductor device barrier layer TW559951B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/153,231 US6686662B2 (en) 2002-05-21 2002-05-21 Semiconductor device barrier layer

Publications (1)

Publication Number Publication Date
TW559951B true TW559951B (en) 2003-11-01

Family

ID=22546315

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091118815A TW559951B (en) 2002-05-21 2002-08-20 A semiconductor device barrier layer

Country Status (5)

Country Link
US (1) US6686662B2 (https=)
JP (2) JP2004031937A (https=)
KR (1) KR100977947B1 (https=)
GB (1) GB2388959A (https=)
TW (1) TW559951B (https=)

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US7282802B2 (en) * 2004-10-14 2007-10-16 International Business Machines Corporation Modified via bottom structure for reliability enhancement
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US8415799B2 (en) * 2005-06-30 2013-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene interconnect in hybrid dielectric
US8134196B2 (en) * 2005-09-02 2012-03-13 Stats Chippac Ltd. Integrated circuit system with metal-insulator-metal circuit element
US20070052107A1 (en) * 2005-09-05 2007-03-08 Cheng-Ming Weng Multi-layered structure and fabricating method thereof and dual damascene structure, interconnect structure and capacitor
US20070126120A1 (en) * 2005-12-06 2007-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
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DE102007046851B4 (de) * 2007-09-29 2019-01-10 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterstruktur mit einem elektrisch leitfähigen Strukturelement und Verfahren zum Ausbilden einer Halbleiterstruktur
JP5331443B2 (ja) * 2008-10-29 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
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JP5173863B2 (ja) * 2009-01-20 2013-04-03 パナソニック株式会社 半導体装置およびその製造方法
US8138605B2 (en) * 2009-10-26 2012-03-20 Alpha & Omega Semiconductor, Inc. Multiple layer barrier metal for device component formed in contact trench
US10269706B2 (en) * 2016-07-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9905459B1 (en) * 2016-09-01 2018-02-27 International Business Machines Corporation Neutral atom beam nitridation for copper interconnect
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US10964636B2 (en) * 2018-09-19 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure with low resistivity and method for forming the same
WO2020131897A1 (en) * 2018-12-17 2020-06-25 Averatek Corporation Three dimensional circuit formation
US12156331B2 (en) * 2021-03-25 2024-11-26 Intel Corporation Technologies for power tunnels on circuit boards
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Also Published As

Publication number Publication date
GB2388959A (en) 2003-11-26
US20030218256A1 (en) 2003-11-27
GB0220209D0 (en) 2002-10-09
KR100977947B1 (ko) 2010-08-24
JP2004031937A (ja) 2004-01-29
KR20030091700A (ko) 2003-12-03
US6686662B2 (en) 2004-02-03
JP2011205155A (ja) 2011-10-13

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