KR100977947B1 - 반도체 장치 및 반도체 장치 제조 공정 - Google Patents

반도체 장치 및 반도체 장치 제조 공정 Download PDF

Info

Publication number
KR100977947B1
KR100977947B1 KR1020030031929A KR20030031929A KR100977947B1 KR 100977947 B1 KR100977947 B1 KR 100977947B1 KR 1020030031929 A KR1020030031929 A KR 1020030031929A KR 20030031929 A KR20030031929 A KR 20030031929A KR 100977947 B1 KR100977947 B1 KR 100977947B1
Authority
KR
South Korea
Prior art keywords
dielectric layer
layer
etch stop
opening
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1020030031929A
Other languages
English (en)
Korean (ko)
Other versions
KR20030091700A (ko
Inventor
세일러쉬 만신 머찬트
이사이아 오 올라드지
성 진 고
Original Assignee
에이저 시스템즈 인크
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에이저 시스템즈 인크 filed Critical 에이저 시스템즈 인크
Publication of KR20030091700A publication Critical patent/KR20030091700A/ko
Application granted granted Critical
Publication of KR100977947B1 publication Critical patent/KR100977947B1/ko
Assigned to 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 reassignment 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 권리의 전부이전등록 Assignors: 에이저 시스템즈 엘엘시
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020030031929A 2002-05-21 2003-05-20 반도체 장치 및 반도체 장치 제조 공정 Expired - Lifetime KR100977947B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/153,231 US6686662B2 (en) 2002-05-21 2002-05-21 Semiconductor device barrier layer
US10/153,231 2002-05-21

Publications (2)

Publication Number Publication Date
KR20030091700A KR20030091700A (ko) 2003-12-03
KR100977947B1 true KR100977947B1 (ko) 2010-08-24

Family

ID=22546315

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030031929A Expired - Lifetime KR100977947B1 (ko) 2002-05-21 2003-05-20 반도체 장치 및 반도체 장치 제조 공정

Country Status (5)

Country Link
US (1) US6686662B2 (https=)
JP (2) JP2004031937A (https=)
KR (1) KR100977947B1 (https=)
GB (1) GB2388959A (https=)
TW (1) TW559951B (https=)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100462884B1 (ko) * 2002-08-21 2004-12-17 삼성전자주식회사 희생충진물질을 이용한 반도체 장치의 듀얼다마신배선형성방법
KR100523618B1 (ko) * 2002-12-30 2005-10-24 동부아남반도체 주식회사 반도체 장치의 콘택트 홀 형성 방법
US20040222527A1 (en) * 2003-05-06 2004-11-11 Dostalik William W. Dual damascene pattern liner
KR101048002B1 (ko) * 2003-12-26 2011-07-13 매그나칩 반도체 유한회사 반도체 소자의 장벽 금속층 형성방법
JP2005217162A (ja) * 2004-01-29 2005-08-11 Semiconductor Leading Edge Technologies Inc 半導体装置及びその製造方法
KR100642633B1 (ko) * 2004-06-11 2006-11-10 삼성전자주식회사 엠아이엠 캐패시터들 및 그의 제조 방법
US7282802B2 (en) * 2004-10-14 2007-10-16 International Business Machines Corporation Modified via bottom structure for reliability enhancement
KR100715267B1 (ko) * 2005-06-09 2007-05-08 삼성전자주식회사 스택형 반도체 장치 및 그 제조 방법
US8415799B2 (en) * 2005-06-30 2013-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene interconnect in hybrid dielectric
US8134196B2 (en) * 2005-09-02 2012-03-13 Stats Chippac Ltd. Integrated circuit system with metal-insulator-metal circuit element
US20070052107A1 (en) * 2005-09-05 2007-03-08 Cheng-Ming Weng Multi-layered structure and fabricating method thereof and dual damascene structure, interconnect structure and capacitor
US20070126120A1 (en) * 2005-12-06 2007-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
US7417321B2 (en) * 2005-12-30 2008-08-26 Taiwan Semiconductor Manufacturing Co., Ltd Via structure and process for forming the same
US7435674B2 (en) * 2006-03-27 2008-10-14 International Business Machines Corporation Dielectric interconnect structures and methods for forming the same
US9385034B2 (en) * 2007-04-11 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Carbonization of metal caps
KR100924546B1 (ko) * 2007-07-27 2009-11-02 주식회사 하이닉스반도체 반도체 소자의 금속배선 및 그의 형성방법
DE102007046851B4 (de) * 2007-09-29 2019-01-10 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterstruktur mit einem elektrisch leitfähigen Strukturelement und Verfahren zum Ausbilden einer Halbleiterstruktur
JP5331443B2 (ja) * 2008-10-29 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US8283250B2 (en) 2008-12-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming a conductive via-in-via structure
JP5173863B2 (ja) * 2009-01-20 2013-04-03 パナソニック株式会社 半導体装置およびその製造方法
US8138605B2 (en) * 2009-10-26 2012-03-20 Alpha & Omega Semiconductor, Inc. Multiple layer barrier metal for device component formed in contact trench
US10269706B2 (en) * 2016-07-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9905459B1 (en) * 2016-09-01 2018-02-27 International Business Machines Corporation Neutral atom beam nitridation for copper interconnect
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US10964636B2 (en) * 2018-09-19 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure with low resistivity and method for forming the same
WO2020131897A1 (en) * 2018-12-17 2020-06-25 Averatek Corporation Three dimensional circuit formation
US12156331B2 (en) * 2021-03-25 2024-11-26 Intel Corporation Technologies for power tunnels on circuit boards
US12105163B2 (en) 2021-09-21 2024-10-01 Tdk Corporation Magnetic sensor
CN114267634A (zh) * 2021-12-21 2022-04-01 华虹半导体(无锡)有限公司 低通孔双大马士革结构的制备方法
US20240313079A1 (en) * 2023-03-16 2024-09-19 Applied Materials, Inc. Semiconductor devices containing bi-metallic silicide with reduced contact resistivity
US20250132193A1 (en) * 2023-10-19 2025-04-24 Nanya Technology Corporation Semiconductor device structure with liner layer having tapered sidewall and method for preparing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059542A (ko) * 1999-12-30 2001-07-06 박종섭 반도체 소자의 금속배선 형성방법
KR20020002911A (ko) * 2000-06-30 2002-01-10 박종섭 반도체소자의 금속배선 형성방법

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2946978B2 (ja) * 1991-11-29 1999-09-13 ソニー株式会社 配線形成方法
JP3297220B2 (ja) * 1993-10-29 2002-07-02 株式会社東芝 半導体装置の製造方法および半導体装置
JP2728025B2 (ja) * 1995-04-13 1998-03-18 日本電気株式会社 半導体装置の製造方法
US6268291B1 (en) * 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
US5668054A (en) 1996-01-11 1997-09-16 United Microelectronics Corporation Process for fabricating tantalum nitride diffusion barrier for copper matallization
US6037246A (en) * 1996-09-17 2000-03-14 Motorola Inc. Method of making a contact structure
JPH10125783A (ja) * 1996-10-15 1998-05-15 Sony Corp 半導体装置の製造方法
JPH10335458A (ja) * 1997-05-30 1998-12-18 Nec Corp 半導体装置及びその製造方法
US5821168A (en) * 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
US5940698A (en) 1997-12-01 1999-08-17 Advanced Micro Devices Method of making a semiconductor device having high performance gate electrode structure
US6294836B1 (en) 1998-12-22 2001-09-25 Cvc Products Inc. Semiconductor chip interconnect barrier material and fabrication method
US6417094B1 (en) 1998-12-31 2002-07-09 Newport Fab, Llc Dual-damascene interconnect structures and methods of fabricating same
US6140231A (en) 1999-02-12 2000-10-31 Taiwan Semiconductor Manufacturing Company Robust diffusion barrier for Cu metallization
US6339258B1 (en) * 1999-07-02 2002-01-15 International Business Machines Corporation Low resistivity tantalum
US6140220A (en) * 1999-07-08 2000-10-31 Industrial Technology Institute Reseach Dual damascene process and structure with dielectric barrier layer
JP2001035917A (ja) * 1999-07-19 2001-02-09 Hitachi Ltd 半導体装置およびその製造方法
US6284657B1 (en) * 2000-02-25 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Non-metallic barrier formation for copper damascene type interconnects
US6372636B1 (en) * 2000-06-05 2002-04-16 Chartered Semiconductor Manufacturing Ltd. Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
US6531780B1 (en) * 2001-06-27 2003-03-11 Advanced Micro Devices, Inc. Via formation in integrated circuit interconnects
US6525428B1 (en) * 2002-06-28 2003-02-25 Advance Micro Devices, Inc. Graded low-k middle-etch stop layer for dual-inlaid patterning

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059542A (ko) * 1999-12-30 2001-07-06 박종섭 반도체 소자의 금속배선 형성방법
KR20020002911A (ko) * 2000-06-30 2002-01-10 박종섭 반도체소자의 금속배선 형성방법

Also Published As

Publication number Publication date
GB2388959A (en) 2003-11-26
US20030218256A1 (en) 2003-11-27
GB0220209D0 (en) 2002-10-09
JP2004031937A (ja) 2004-01-29
TW559951B (en) 2003-11-01
KR20030091700A (ko) 2003-12-03
US6686662B2 (en) 2004-02-03
JP2011205155A (ja) 2011-10-13

Similar Documents

Publication Publication Date Title
KR100977947B1 (ko) 반도체 장치 및 반도체 장치 제조 공정
US6245663B1 (en) IC interconnect structures and methods for making same
US7051934B2 (en) Methods of forming metal layers in integrated circuit devices using selective deposition on edges of recesses
US7094705B2 (en) Multi-step plasma treatment method to improve CU interconnect electrical performance
US6169024B1 (en) Process to manufacture continuous metal interconnects
CN101443894B (zh) 在双镶嵌中集成多孔密封衬垫的方法和器件
US6472231B1 (en) Dielectric layer with treated top surface forming an etch stop layer and method of making the same
US20050110147A1 (en) Method for forming a multi-layer seed layer for improved Cu ECP
US20030008490A1 (en) Dual hardmask process for the formation of copper/low-k interconnects
US20050054202A1 (en) Method for simultaneous degas and baking in copper damascene process
US8368220B2 (en) Anchored damascene structures
US7074721B2 (en) Method for forming thick copper self-aligned dual damascene
KR20030027817A (ko) 마스크 층 및 집적 회로 장치의 듀얼 대머신 상호 연결구조물 형성 방법과 집적 회로 장치 상에서 상호 연결구조물을 형성하는 방법
JP2004505447A (ja) 界面および接着性が改良された銅配線キャップ層を形成する方法
US9653403B1 (en) Structure and process for W contacts
US7176141B2 (en) Plasma treatment to improve barrier layer performance over porous low-K insulating dielectrics
US7223692B2 (en) Multi-level semiconductor device with capping layer for improved adhesion
US7670946B2 (en) Methods to eliminate contact plug sidewall slit
US7138333B2 (en) Process for sealing plasma-damaged, porous low-k materials
JP2004289155A (ja) 選択性エッチング化学薬品及びｃｄ制御のための高重合性ガスを含むｂａｒｃエッチング
US20030207558A1 (en) Method forming copper containing semiconductor features to prevent thermally induced defects
US6599838B1 (en) Method for forming metal filled semiconductor features to improve a subsequent metal CMP process
JP2008147675A (ja) 不均一窒化金属膜を用いる電気的接続構造物の形成方法およびこの方法によって製造された接続構造物
US7309651B2 (en) Method for improving reliability of copper interconnects
US20020173079A1 (en) Dual damascene integration scheme using a bilayer interlevel dielectric

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

R15-X000 Change to inventor requested

St.27 status event code: A-3-3-R10-R15-oth-X000

R16-X000 Change to inventor recorded

St.27 status event code: A-3-3-R10-R16-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
AMND Amendment
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

AMND Amendment
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E601 Decision to refuse application
PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

J201 Request for trial against refusal decision
PJ0201 Trial against decision of rejection

St.27 status event code: A-3-3-V10-V11-apl-PJ0201

AMND Amendment
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PB0901 Examination by re-examination before a trial

St.27 status event code: A-6-3-E10-E12-rex-PB0901

B701 Decision to grant
PB0701 Decision of registration after re-examination before a trial

St.27 status event code: A-3-4-F10-F13-rex-PB0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20130723

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20140722

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

FPAY Annual fee payment

Payment date: 20160801

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20170811

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20180801

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20190801

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

PC1801 Expiration of term

St.27 status event code: N-4-6-H10-H14-oth-PC1801

Not in force date: 20230521

Ip right cessation event data comment text: Termination Category : EXPIRATION_OF_DURATION

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000