JP2004289155A - 選択性エッチング化学薬品及びcd制御のための高重合性ガスを含むbarcエッチング - Google Patents
選択性エッチング化学薬品及びcd制御のための高重合性ガスを含むbarcエッチング Download PDFInfo
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- JP2004289155A JP2004289155A JP2004079355A JP2004079355A JP2004289155A JP 2004289155 A JP2004289155 A JP 2004289155A JP 2004079355 A JP2004079355 A JP 2004079355A JP 2004079355 A JP2004079355 A JP 2004079355A JP 2004289155 A JP2004289155 A JP 2004289155A
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- 238000005530 etching Methods 0.000 title claims abstract description 53
- 239000000126 substance Substances 0.000 title abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 230000007261 regionalization Effects 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000009977 dual effect Effects 0.000 description 20
- 230000008569 process Effects 0.000 description 20
- 239000007789 gas Substances 0.000 description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 238000000059 patterning Methods 0.000 description 9
- 229910052731 fluorine Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 238000012876 topography Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 3
- 230000000379 polymerizing effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- -1 transition metal nitride Chemical class 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
【解決手段】BARCエッチングは、CD制御のための高重合性ガスと一緒に選択性エッチング化学薬品を含む。BARCエッチングをビア先行デュアルダマシン法に用いることができる。ビア116のパターン形成及びエッチングの後、厚いBARC層120を堆積してビア116を充填し、IMD110を被覆する。トレンチレジストパターン125をBARC層120の上に形成する。次いで、IMD110上のBARC120の露出部分を、選択性エッチング化学薬品に加えた高重合性ガスを用いてエッチングする。より多くの重合性ガスはトレンチレジスト125の側壁を不動態化してトレンチのCDを維持し、又は改善する。主要なトレンチエッチングの間、BARC120の一部がビア内に残って、ビア116の底部のエッチング停止材104を保護する。
【選択図】図2C
Description
圧力: 15mトル
電力: 200ワット
CH2F2流量: 20sccm
N2流量: 80sccm
O2流量: 20sccm
チャック温度: 20℃
圧力: 15mトル
電力: 200ワット
CH2F2流量: 20sccm
N2流量: 80sccm
O2流量: 20sccm
チャック温度: 20℃
(1)パターン形成可能な層を有する半導体本体を提供するステップと、
前記パターン形成可能な層の上にBARC層を堆積するステップと、
前記BARC層の上にレジストマスクを形成するステップであって、前記レジストマスクが前記BARC層の一部を露出させるステップと、
選択性エッチング化学薬品を前記レジストマスクの側壁を不動態化するための高重合性ガスと一緒に用いて、前記パターン形成可能な層の上に前記BARC層の露出部分をエッチングするステップとを含む集積回路を製造する方法。
(2)前記パターン形成可能な層が誘電体を含み、前記BARC層の露出部分をエッチングする前記ステップの後に、前記レジストマスクを使用して前記誘電体中にトレンチをエッチングするステップをさらに含む第1項記載の方法。
(3)前記パターン形成可能な層が誘電体を含み、前記BARC層の露出部分をエッチングする前記ステップの後に、前記レジストマスクを使用して前記誘電体中にビアホールをエッチングするステップをさらに含む第1項記載の方法。
(4)前記パターン形成可能な層が誘電体を含み、前記BARC層の露出部分をエッチングする前記ステップの後に、前記レジストマスクを使用して前記誘電体中にコンタクトホールをエッチングするステップをさらに含む第1項記載の方法。
(5)前記高重合性ガスが、CH2F2、CH3F、C4F6、C4F8、C5F8からなる群から選択される第1項記載の方法。
(6)誘電体層が半導体本体上に形成された半導体本体を提供するステップと、
前記誘電体層の上にBARC層を堆積するステップと、
前記BARC層上のレジストマスクをパターン形成するステップであって、前記レジストマスクが前記BARC層の一部を露出するステップと、
前記BARC層の露出部分を、選択性エッチング化学薬品と高重合性ガスを用いて、レジストマスクのパターンのCDを増大させずにエッチングするステップと、
前記誘電体層中に空洞をエッチングするステップとを含む集積回路を製造する方法。
(7)前記誘電体がOSGを含む第6項記載の方法。
(8)前記選択性エッチング化学薬品がN2とO2を含む第7項記載の方法。
(9)前記より多くの重合性ガスが、CH2F2、CH3F、C4F6、C4F8、C5F8からなる群から選択される第6項記載の方法。
12 ILD
16 バリア層
18 相互接続配線
20、116 ビア
100 半導体本体
102 第1相互接続レベル
104 エッチング停止層
106 ILD層
120 BARC層
124 トレンチ
125 トレンチパターン
126 第2相互接続層
Claims (1)
- パターン形成可能な層を有する半導体本体を提供するステップと、
前記パターン形成可能な層の上にBARC層を堆積するステップと、
前記BARC層の上にレジストマスクを形成するステップであって、前記レジストマスクが前記BARC層の一部を露出させるステップと、
選択性エッチング化学薬品を前記レジストマスクの側壁を不動態化するための高重合性ガスと一緒に用いて、前記パターン形成可能な層の上に前記BARC層の露出部分をエッチングするステップとを含む集積回路を製造する方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/393,317 US6900123B2 (en) | 2003-03-20 | 2003-03-20 | BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control |
Publications (1)
Publication Number | Publication Date |
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JP2004289155A true JP2004289155A (ja) | 2004-10-14 |
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JP2004079355A Pending JP2004289155A (ja) | 2003-03-20 | 2004-03-19 | 選択性エッチング化学薬品及びcd制御のための高重合性ガスを含むbarcエッチング |
Country Status (3)
Country | Link |
---|---|
US (1) | US6900123B2 (ja) |
EP (1) | EP1460677A3 (ja) |
JP (1) | JP2004289155A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009530863A (ja) * | 2006-03-20 | 2009-08-27 | アプライド マテリアルズ インコーポレイテッド | 低kデュアルダマシン集積回路の形成に用いることのできる有機barcエッチングプロセス |
Families Citing this family (11)
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US7192877B2 (en) * | 2004-05-21 | 2007-03-20 | Texas Instruments Incorporated | Low-K dielectric etch process for dual-damascene structures |
US7361588B2 (en) | 2005-04-04 | 2008-04-22 | Advanced Micro Devices, Inc. | Etch process for CD reduction of arc material |
KR100673196B1 (ko) | 2005-07-14 | 2007-01-22 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 금속배선 및 콘택플러그 형성방법 |
US20090301996A1 (en) * | 2005-11-08 | 2009-12-10 | Advanced Technology Materials, Inc. | Formulations for removing cooper-containing post-etch residue from microelectronic devices |
US7435676B2 (en) * | 2006-01-10 | 2008-10-14 | International Business Machines Corporation | Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity |
US7553758B2 (en) * | 2006-09-18 | 2009-06-30 | Samsung Electronics Co., Ltd. | Method of fabricating interconnections of microelectronic device using dual damascene process |
US7807064B2 (en) * | 2007-03-21 | 2010-10-05 | Applied Materials, Inc. | Halogen-free amorphous carbon mask etch having high selectivity to photoresist |
US8097402B2 (en) * | 2009-03-31 | 2012-01-17 | Tokyo Electron Limited | Using electric-field directed post-exposure bake for double-patterning (D-P) |
US8383510B2 (en) * | 2011-03-04 | 2013-02-26 | Globalfoundries Inc. | Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials |
US10957850B2 (en) | 2018-10-04 | 2021-03-23 | International Business Machines Corporation | Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabrication |
US10692755B2 (en) | 2018-10-24 | 2020-06-23 | International Business Machines Corporation | Selective deposition of dielectrics on ultra-low k dielectrics |
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JP2000208488A (ja) * | 1999-01-12 | 2000-07-28 | Kawasaki Steel Corp | エッチング方法 |
JP2001250862A (ja) * | 2000-03-07 | 2001-09-14 | Matsushita Electric Ind Co Ltd | コンタクトホール形成方法 |
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2003
- 2003-03-20 US US10/393,317 patent/US6900123B2/en not_active Expired - Lifetime
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2004
- 2004-03-18 EP EP04101122A patent/EP1460677A3/en not_active Withdrawn
- 2004-03-19 JP JP2004079355A patent/JP2004289155A/ja active Pending
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JP2009530863A (ja) * | 2006-03-20 | 2009-08-27 | アプライド マテリアルズ インコーポレイテッド | 低kデュアルダマシン集積回路の形成に用いることのできる有機barcエッチングプロセス |
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EP1460677A2 (en) | 2004-09-22 |
EP1460677A3 (en) | 2005-04-06 |
US20040185655A1 (en) | 2004-09-23 |
US6900123B2 (en) | 2005-05-31 |
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