TW557553B - Alternate bump metallurgy bars for power and ground routing - Google Patents
Alternate bump metallurgy bars for power and ground routing Download PDFInfo
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- TW557553B TW557553B TW091106311A TW91106311A TW557553B TW 557553 B TW557553 B TW 557553B TW 091106311 A TW091106311 A TW 091106311A TW 91106311 A TW91106311 A TW 91106311A TW 557553 B TW557553 B TW 557553B
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Description
557553 A7
liUP 景 領域 尤其與微晶片和封裝基板間 本發明與微晶片領域有關, 之排程電力及接地連結有關。 LilAI技藝探討 使用高電力位準之積體電路需要電力與接地線之密集圖 樣,俾傳遞所需電流並實現所期性能。隨著電路所需電力 <增加,需要較多之正規連接層(例如P86〇上之]^5與1^6)以 ^排程電力與接地,其會使可用之排程信號減少。對排程 電力與接地之需求須附加更多連接層而定址。圖丨A係具C4 凸塊圖樣之晶粒表面闡釋圖,其包含對信號、電力與接地 之I/O。在晶粒與晶粒封裝間提供較精細間距凸塊之挑戰, 會增加在晶粒表面之排程與排程之複雜度。圖1B所示係一 日口粒表面,其具連結至晶片上之接地(Vss)與電力(Vdd)線之 ABM凸塊。按此設計,凸塊間最低間距趨近乃微米,凸塊 直徑趨近75微米,並具有效排程信號線之15〇微米最低間距 發明概要 一種裝置,其包括一晶粒,其表面包括電氣傳導凸塊之 一陣列;以及位於電氣傳導凸塊之該陣列内之複數個電氣 傳導棒。 圖式之簡述 圖1A係具C 4凸塊圖樣之晶粒表面闡釋圖,其包含對信號 、電力與接地之I/O。 -4-
O:\76\76467-920707 D0Q4VLAN 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 557553 . • « A7 B7 五、發明説明(2 ) 圖1B所示係一晶粒表面,其具連結至晶片上之接地(Vss) 與電力(Vdd)線之ABM凸塊。 圖2A係利用交替凸塊冶金而具電力與接地棒之晶粒之闡 釋圖。 圖2B係具電力與接地棒以及邊緣環之晶粒之闡釋圖。 圖3係置放於接地與電力線(既存於金屬層内並與刻劃鈍 態開孔連接)之ABM棒闡釋圖。 圖4 A係連結至M7銅層之ABM棒闡釋圖。 圖4B係自圖4A轉90度角所見連結至M7銅層之ABM棒闡 釋圖。 圖5A-5H係在晶粒上產生ABM棒之方法闡釋圖。 圖5 A係包含在一金屬層内含電力與接地線之晶粒闡釋圖 〇 圖5B係具沉積於金屬層上具有一介電層之晶粒闡釋圖。 圖5C係具沉積於介電層上具有一鈍態層之晶粒闡釋圖。 圖5D係具蝕刻穿透介電層與鈍態層之鈍態開孔之晶粒闡 釋圖。 圖5E係具刻劃鈍態開孔之晶粒闡釋圖。 圖5F係具圖樣化光阻層之晶粒闡釋圖。 圖5G係具以銅填充之圖樣之晶粒闡釋圖。 圖5H係晶粒闡釋圖,其具電力棒、接地棒以及具交替凸 塊冶金之凸塊。 圖6A係在一封裝組成中之一晶粒-基板組成闡釋圖。 圖6B係晶粒與基板間之電力與接地連結闡釋圖。 O:\76\76467-920707 DOC\4\LAN - 5 ~ 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 557553
主發明之細#尨祕 揭示一種提供電力與接地棒之結構與方法,其位於一晶 粒表面上之I/O信號凸塊陣列中央。在一具體實施例中,ι/〇 信號凸塊及電力與接地棒可為銅凸塊型式。此結構與方法 可獒供連結微晶片(晶粒)與基板間之電力與接地之有效工具 。此結構與方法可利用與銲錫相異之凸塊冶金(亦即交替凸 塊冶金或ABM)。結果電力與接地結構可位於晶粒上,並具 I/O環繞於有序陣列上之信號凸塊(信號凸塊)。進一步結果 在於可自與信號凸塊相同之金屬層製造電力與接地結構。 由於可適用更緊密之間距,故此結構與方法使得連接金屬 層範圍内可置放更多的電力與接地線。 在一具體實施例之組合中,在晶粒上之信號凸塊可搭配 在基板(諸如晶粒封裝)上之各銲錫台。晶粒封裝可具數個銲 錫口 ’其與曰曰粒上之電力與接地棒及信號凸塊相接。或者 銲錫台覆盍之面積大到足以接觸一或多個電力棒及/或接地 棒之整體表面。電力棒與接地棒以及搭配之銲錫台可為自 正方形至數個線性細帶之任意外型。 在下列敘述中描述多種特殊細節,諸如特殊材料、裝備 與處理,俾對本發明完全瞭解。在其它實例中,已知之電 腦組成技術及機械並未詳述,以避免模糊本發明。 圖2A與2B係具有以交替之凸塊冶金(abm)做為電力與接 地棒204之晶粒202闡釋圖。在圖2A之一具體實施例中,作 號凸塊206係位於一陣列圖樣中,其具位於其間之電力與接 地棒204。在如圖2B之另一具體實施例中,附加系列棒於信 O:\76\76467-920707 DOC\4\LAN - 6 _ I紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) ' ----- 557553 * A7 五、發( 4 ) ' - 號凸塊週邊,亦即晶圓邊緣。邊緣棒之目的在於當晶粒固 接於諸如塑膠封裝之基板時,可提供改善密封狀況。在一 具體實施例中,所形成之電力與接地棒2〇4外型可為矩形, 並以介電與鈍態塗覆和上方金屬隔離。電力與接地棒可依 序覆以低溫銲錫薄層,俾改善與搭配基板上之搭配銲鍚台 或棒之電氣接觸。 圖3所示係一晶粒302區,其具電力304與304,以及置於既 存於晶粒302之金屬層内之接地312與312,和電力314與314, 上’並與刻劃鈍態開孔(在鈍態與介電層中)31〇與31〇,電氣 連接之接地303 ABM棒。ABM棒304、304,與303宽度約為 75微米,在晶粒3〇2上之間距約為75微米。刻劃鈍態開孔 310與310'可藉由每邊大約5微米長度之約略矩形之一地區所 形成。ABM棒304、304'與303間之刻劃鈍態開孔31〇與31〇, 以及金屬表面可形成ABM棒304、304,與303對各電力線3 14 與314'和接地312與312,線之連接。 圖3更闡釋採用ABM棒(棒)3〇4、3〇4,時較採用凸塊時(圖 ic上方)可獲得之精細間距308,其連結電力與接地至晶粒 3 02外侧之電路系統。八3?4棒3〇4、3〇4,供電力排程較佳, 此係因其可在晶粒302上較均勻分配電力。對ABM凸塊(圖 1B上方)而言,在最終金屬層中之下方電力現可僅存在於凸 塊下方,而凸塊間距因製程限制而限於約15〇微米。電力與 接地線可僅各相間75微米。回到圖3,其具八;6]^1棒3〇4、 304',鈍態開孔310可存在於棒3〇4與3〇4,中任何位置,因此 幾乎可如所欲置放電力與接地線(Vdd/Vss)312、312'、314 O:\76\76467-920707 DOQ4\LAN j 本紙張尺度適用中國國家標準(CN& A4規格(210x 297公董)-"~ --- 557553 A7 _ B7 五、發明説明(5 ) : 與3 14',諸如每30微米。相間更緊密而具更多的電力和接地 線312、312'、314與314',可藉由電阻壓降降低並具較低電 感而可改善電力傳遞。結果可改善其性能。 圖4A&4B闡釋ABM接地棒402側視圖,其具至]^7層4〇6之 連接(刻劃鈍態開孔)404。在一具體實施例中,該連接穿透 ShlSU介電層408以及聚硫亞胺純態層410。圖4A&4B所示 ABM接地棒402連結至自M7 406層製造之銅接地線410,同 時一相鄰之ABM電力棒412以ShN4 408及聚硫亞胺41〇層與 接地線410隔離。 圖5A-5H闡釋在晶粒上產生ABM棒之方法。圖5A闡釋在 晶粒500上之最終金屬連接層501,諸如M7(沉積於圖樣化介 電層内)’其可包含電力線502、502'與接地線504、504,之 組合。如圖5B所示,沉積一層介電材料506(諸如矽氮化物 (Si#4)或礙化碎SiC)於晶粒500表面,其包含經姓刻之M7層 501。圖5C闡釋鈍態層508之沉積。在一具體實施例中,鈍 態層可為諸如聚硫亞胺或二氧化矽材料,經以濺鍍、旋鍍 、CVD或滾動而整體沉積覆蓋介電塗覆5〇6。在施加鈍態層 之後,可以光阻將表面圖樣化(未圖示)。圖5D闡釋在鈍態 層508與介電層506中之鈍態開孔510與510,、金屬電力502與 502’之暴露區、在M7 501内之接地線504與504,。可先以光 阻(未圖示)圖樣化產生開孔510與510,,接著蚀刻穿透鈍態 506與介電504層,露出在M7 501之線502、502,、504與504, 。圖5E係與傳導金屬或金屬合金刻劃之刻劃鈍態開孔5 η與 512'。在一具體實施例中,鈍態開孔512與5 12,具有以鈦而
O:\76\76467-920707 DOC\4\LAN _ Q 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 557553 A7 B7 五、發明説明(6 ) 後銅濺鍍之雙層(未圖示)。圖5F闡釋施於鈍態塗覆506上之 圖樣化光阻514。圖5G闡釋以銅516電鍍填充在光阻圖樣5 14 中之開孔處理結果。圖5H闡釋晶粒500橫剖圖,其中已以溶 劑剝除光阻,而ABM棒518與518'以及銅信號凸塊520則維 持連接至M7 501内之線502、502f、504與504'。 圖6A&6B闡釋一晶粒-基板組成600。一種組成處理,諸 如以上圖5A-5H所述具體實施例,可將晶粒602固接於基板 604。基板604可為任意搭配部件,連結晶粒602至外側電路 系統,諸如封裝或印刷電路板,其中基板604可包含接觸銲 錫609與60V之接地606與606'及電力608棒區,俾搭配在晶 粒602上之接地610與61(Τ及電力612棒區。銲錫609與60W可 為低溫銲錫,諸如鉛錫或銀錫,塗覆於下方之銅表面(未圖 示)。在基板604上具等效搭配銲錫區609與609'可與晶粒602 上之銅接地610與61 (Τ及電力612棒搭配之益處在於可增加自 晶粒602之熱轉換率,同時可以電腦施行晶粒操作。 接著藉由在一回流爐中置放晶粒-基板組成,施行加熱週 期將銲錫加熱直到其成為流體。在回流操作後,銅凸塊經 電氣與機械連結至銲錫台,以及晶粒之電力/接地棒經電氣 與機械連結至基板上搭配之電力/接地細帶或台。 在製造期間,稍後與晶粒搭配之基板,諸如塑膠封裝或 印刷電路板,穿經一銲錫裝置,其中一側經銲錫操作而在 各基板上銲住數百個端子。為此目的採用之波浪銲錫機係 為已知。這些機械包含運輸裝置,其可載運板於銲錫溶浴 中,其攪動使得波浪倚於板之下側上升。在波浪銲鍚前, O:\76\76467-920707 DOC\4\LAN _ 9 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 557553 A7 B7 五、發明説明(7 ) 需以銲錫罩操作保護部份封裝基板,使其免於與熱熔銲錫 接觸。銲錫罩係以已知技術施加為一或多層塗覆,諸如濺 鍍、喷灑,或絲幕,諸如藉由鋼幕網為之。當以幕網施加 銲錫罩時,網中圖樣可提供銲錫罩中,稍後為銲錫操作填 充之開孔。在銲錫罩完成後,施行波浪銲錫填充罩中區域 開孔。在最終基板上完成之銲錫罩對欲防護之電路線具良 好介電遮蓋。 元件符號說明 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 202 晶粒 500 晶粒 204, 204’ 電力與接地棒 501 最終金屬連接層 206 信號凸塊 502, 502丨 電力線 302 晶粒 504, 504’ 接地線 303 接地棒 506 介電材料層 304 電力棒 508 鈍態層 308 精細間距 510, 510 丨 鈍態開孔 310,310’ 刻劃鈍態開孔 512 刻劃鈍態開孔 312, 312, 電力線 514 圖樣化光阻 314,314’ 接地線 516 銅 402 接地棒 518, 518, 棒 404 連接(刻劃鈍態開孔) 520 銅信號棒 406 M7層 600 晶粒-基板組成 408 Si3N4介電層 602 晶粒 410 聚硫亞胺鈍態層 604 基板 412 電力棒 606, 606, 接觸接地 O:\76\76467-920707 DOQ4VLAN -10- 557553 A7 B7 五、發明説明(8 ) 608 電力棒 609, 609’ 銲錫 610,6101 接地 612 電力棒 -11 -
O:\76\76467-920707 DOC\5\LAN 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)
Claims (1)
- 8 8 AB 園範利專 請中 CD 種供電力及接地排程之裝 一晶粒,其表面包括: 電氣傳導凸塊陣列;以及 位於電氣傳導凸塊陣助之複數個電氣傳導棒。 :申請t利範圍第1項之裝置,其中至少複數個電氣傳$ 棒又一連結至電力。 寸 如申請專利範圍第1項之裝置 棒之一連結接地。 如申請專利範圍第丨項之裝置 構成電氣傳導凸塊陣列週邊。 如申請專利範圍第4項之裝置 如申請專利範圍第4項之裝置 位於電氣傳導凸塊中央。 如申請專利範圍第1項之裝置 如申請專利範圍第6項之裝置 一種電子裝置組成,其包括 一晶粒,其具複數個電氣傳導棒; 一基板,其具複數個電氣傳導台;此類組成使得在 粒上之複數個電氣傳導棒與在基板上之複數個電氣傳 台相接。 ' 10·如申請專利範圍第9項之組成,其中至少複數個電氣傳 棒之一連結至電力。 11·如申請專利範圍第9項之組成,其中至少複數個電氣傳 棒之一連結接地。 2. 4. 6. 9. 其中至少複數個電氣傳名 其中複數個棒之一或更^ 其中週邊之棒連結接地。 其中複數個電氣傳導棒$ 其中電氣傳導棒為銅。 其中電氣傳導棒為銅。 O:\76\76467-920707 DOC\6\LAN 557553 , A8 B8 C8 D8 六、申請專利範圍 12. 如申請專利範圍第9項之組成,其中一或多個電氣傳導棒 位於電氣傳導凸塊陣列中央。 13. 如申請專利範圍第9項之組成,其中至少複數個金屬棒位 於電氣傳導凸塊週邊。 14. 一種供電力及接地排程之方法,其包括: 沉積一介電層於晶粒之上金屬層上; 在鈍態層之上表面與上金屬層間產生鈍態開孔; 以傳導材料於鈍態開孔刻劃;以及 沉積複數個電氣傳導棒於鈍態層上表面,與經劃線之 鈍態開孔相接。 15. 如申請專利範圍第14項之方法,更包括: 沉積鈍態層於介電層上。 16. 如申請專利範圍第14項之方法,更包括: 連結至少複數個電氣傳導棒之一接地。 17. 如申請專利範圍第14項之方法,更包括: 連結至少複數個電氣傳導棒之一至電力。 18. 如申請專利範圍第14項之方法,更包括: 置放銲錫台陣列於基板上;以及 連結晶粒至基板使得銲錫台陣列搭配在晶粒上之複數 個電氣傳導棒。 19. 一種供電力及接地排程之裝置,其包括: 供電力自晶粒連結至基板之工具; O:\76\76467-920707 D0C\6\LAN ~ 2 _ 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 557553 A8 B8 C8 D8 六、申請專利範圍 供接地自晶粒連結至基板之工具;使得大致信號接頭 陣列位於連結電力工具與連結接地工具週邊。 20. 如申請專利範圍第19項之裝置,其中連結電力工具使用 一或多個電氣傳導棒。 21. 如申請專利範圍第19項之裝置,其中連結接地工具使用 一或多個電氣傳導棒。 22. 如申請專利範圍第19項之裝置,其中連結接地工具沿晶 粒邊緣週邊置放一或多個電氣傳導棒。 O:\76\76467-920707 DOC\6\LAN 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 公告本 申請日期 案 號 09110631Γ 類 別 (以上各攔由本局填註) A4 C4 中文說明書替換本(92年7月) 557553
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US09/823,427 US6653563B2 (en) | 2001-03-30 | 2001-03-30 | Alternate bump metallurgy bars for power and ground routing |
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TW557553B true TW557553B (en) | 2003-10-11 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW091106311A TW557553B (en) | 2001-03-30 | 2002-03-29 | Alternate bump metallurgy bars for power and ground routing |
Country Status (8)
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US (1) | US6653563B2 (zh) |
EP (1) | EP1374306B1 (zh) |
CN (1) | CN100440504C (zh) |
AT (1) | ATE347176T1 (zh) |
AU (1) | AU2002252469A1 (zh) |
DE (1) | DE60216433T2 (zh) |
TW (1) | TW557553B (zh) |
WO (1) | WO2002080273A2 (zh) |
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-
2001
- 2001-03-30 US US09/823,427 patent/US6653563B2/en not_active Expired - Lifetime
-
2002
- 2002-03-22 AU AU2002252469A patent/AU2002252469A1/en not_active Abandoned
- 2002-03-22 WO PCT/US2002/008905 patent/WO2002080273A2/en active IP Right Grant
- 2002-03-22 CN CNB028076249A patent/CN100440504C/zh not_active Expired - Lifetime
- 2002-03-22 AT AT02721543T patent/ATE347176T1/de not_active IP Right Cessation
- 2002-03-22 EP EP02721543A patent/EP1374306B1/en not_active Expired - Lifetime
- 2002-03-22 DE DE60216433T patent/DE60216433T2/de not_active Expired - Lifetime
- 2002-03-29 TW TW091106311A patent/TW557553B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1374306A2 (en) | 2004-01-02 |
AU2002252469A1 (en) | 2002-10-15 |
EP1374306B1 (en) | 2006-11-29 |
CN1579019A (zh) | 2005-02-09 |
ATE347176T1 (de) | 2006-12-15 |
WO2002080273A2 (en) | 2002-10-10 |
DE60216433D1 (de) | 2007-01-11 |
US20020141171A1 (en) | 2002-10-03 |
CN100440504C (zh) | 2008-12-03 |
WO2002080273A3 (en) | 2003-07-03 |
DE60216433T2 (de) | 2007-09-20 |
US6653563B2 (en) | 2003-11-25 |
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