TW557540B - Aggregate dielectric layer to reduce nitride consumption - Google Patents

Aggregate dielectric layer to reduce nitride consumption Download PDF

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Publication number
TW557540B
TW557540B TW091102128A TW91102128A TW557540B TW 557540 B TW557540 B TW 557540B TW 091102128 A TW091102128 A TW 091102128A TW 91102128 A TW91102128 A TW 91102128A TW 557540 B TW557540 B TW 557540B
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layer
substrate
patent application
dielectric
introducing
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TW091102128A
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Kevin Mukai
Shankar Chandran
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Applied Materials Inc
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    • H01L21/3143Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
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Description

557540 A7
本發明是有關於用在例如是電路結構中之保護層或 介電層。 發明背景J_ 介電層或薄膜係用於n瑕離電路結構中的各個元 件以及用於電性隔離多重内連線系統例如可在許多積體 電路、,構中找到的各!^導體。舉例來說,微處理器可具有 51¾或更多階的内連線結構位於基材上例如半導體基材。 在多重内連線系統或結構中之各個不同介電層或薄 膜間會有一個明顯的差異。舉例來說,預金屬介電材料 (PMD)層或薄膜一般係用於基材與元件基部間(例如,基材 含有主動原於其中/其上),或其他區域内連線階層物質 間’以及第一内連線階層(例如,Metal 1)間。PMD層或薄 膜通常可在比内金屬介電層可能的較高溫度中進行沉積 (以及在有需要的情形下進行硬化)。此外,pMD膜可在超 過7 00°C的溫度中進行熱流及再熱流,以促使溝填。若内 連線結構被導入到一基材上,由於幸屬内連線在超過4〇〇 °C的溫度中易於融化(例如,在銘或銅融化溫度中),故要 降低導入介電層或薄膜之最大溫度。 PMD層或薄膜有兩種方式來隔離積體電路結構中的 元件。其可使元件電性隔離内連線層,且其可使元件實質 隔離污染源例如移動性離子(例如,來自往後過程或處 理)。移動性離子例如鈉及鉀,其易於降低基本元件特性 第4頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 裝丨I (請先閲讀背面之注意事項再場寫本頁} 訂· 經濟部智慧財產局員工消費合作社印製 557540 A7 B7 五、發明説明() 例如電晶體元件之臨界電壓。 若電路結構或基材上之元件密度增加,則PMD層或 薄膜用以達到無空隙溝填的能力會變的格外重要。舉例來 說,在次0.25微米(/zm)元件中,用於在PMD製程中填充 溝槽的基準為具有5比1縱橫比之〇·1微米(vm)。 硼磷矽玻璃(BPSG)-二氧化矽(Si〇2)是一種用於PMD 層或薄膜的習知物質。BPS G —般含有大約2至6重量百 分比的硼和磷。BPSG —般係使用熱化學氣相沉積法(CVD) 並於400至700°C中進行沉積,然後在7〇〇至l〇〇〇°C中進 行回火(再熱流)。一般來說,B P S G中的辦係用作為可能 朝向元件(例如電晶體)擴散之各種移動性離子之吸取)劑, 而由於硼在再熱流回火後易於軟化層,故爛用以提供良好 的溝填能力。 在習知積體電路結構狀態之傳統製造過程中,氮化梦 (ShN4)之薄層會被導入到基材上以作為起始介電層或薄 膜,隨後,例如導入B P S G層或薄膜。除了其之保護層特 性之外,氮化矽也可在平坦化後續導入的PMD層或薄膜 中用作為蝕刻中止層,例如B P S G層或薄膜。 如上所述,若元件密度增加,則PMD層或薄膜之溝 填能力格外重要。B P S G層或薄膜之溝填特性可經由在大 於8 00 °C的溫度中進行回火而充分運用。高溫回火將可以 增加BPSG的再熱流能力。然而,高溫回火及再熱流過程 的一個缺點是,BPS G物質會消耗下層氮化矽層或薄膜中 的氮。氮化物消耗將會導致氮化矽物質之隔離特性變差。 第5頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 裝. -訂. 經濟部智慧財產局員工消費合作社印製 D7540
發明説明( :此:在含有亞磷之熱處理過程中,如何能夠控制含氛之 、或薄膜之氮化物消耗的一種方法是有需要的^ -一 ijgjl的及概沭: 在一實施例中,一種方法包括形成聚合層;於電路基材 上,聚合層包括阻障層並介於含有氮之第一介電層與含有 磷之第二介電層之間。在此實施例中,本方法也包括,在 形成聚合層之後,熱處理此電路基材。用以實行此處描述 又本方法的適當導入位置是在PMD層或薄膜中,其中電 路基材包括一元件基部及至少一金屬層,而聚合層係被導 入於元件基部與至少一金屬層間。適當的阻障層包括介電 材料’特別是矽酸鹽例如硼矽玻璃(BSG)或未摻雜的矽玻 璃(USG)。例如,介於氮化矽薄膜與BPSG材料間之BSG 或USG薄膜可降低在再熱流(熱回火)BPSG期間之消耗。 在另一實施例中,本發明是有關於一種裝置。在一觀 點中,此裝置包括電路基材與聚合層,而聚合層包括阻障 層並介於含有氮之第一介電層與含有磷之第二介電層之 間。一個範例為聚合層作為PMD層或薄膜,其包括介電 材料之阻障層,例如BSG或USG,並被配置在氮化矽層 與BPSG層之間,而作為PMD薄膜之聚合層。 參照此處之所附圖式及詳細說明,將可明瞭附加特 徵、實施例及優點。 圖式簡單說明: 第6頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) (請先閲讀背面之注意事項再填寫本頁) 裝. 經濟部智慧財產局員工消費>作社印製 557540 、發明說明( 本發明的完整插述,將於往後之說 圖形做#裎‘ μ 3曰 予τ補以下列 細的關⑧’然並不限制於此,而相同 所揭露出之實施二 並不限制 #出〈實施例中,其代表至少有一個實施例。 :1圖為依照本發明一實施例之包括有元件形成於 、之部77積體電路基材的剖面側視圖; ,弟2圖為在第}圖之結構之後,依照本發明一實施 (導入包括氮之介電層及p且障層之—部分聚合 薄膜的剖面圖; ’口 第3圖為在第2圖之結構之後,依照 >道λ π 明一實施 矛入及平坦化包括有磷之介電膜的剖面 ’以及 抑“圖為在導入内連線結構於平坦化介電嗅上之後 弟3圖之結構的剖面圖。 於 上 例 或 例 f請先閲讀背面之注意事項再填寫本頁) 裝· 、可· 經濟部智慧財產局員工消費合作社印製 圖號對照說明: 100 結構 102 基材 10 5,115 電晶體元件 108 表面 1 1 0,1 2 0 閘極電極 1 30,1 40 擴散區 150 淺溝渠隔離結構 160 構槽 170 含氮層或薄膜 180 阻障層或薄 190 含亞磷層或薄膜 195 PMD層表面 210 内連線結構 發明詳細說明: 第7頁 557540 A7 B7 五、發明説明( 如上所述,聚合層適用作為積體電路結構之介電層或 保護層,而其為實現聚合層之方法及含有聚合層之裝置的 一種實施例。 在一實施例中,提供一種方法包括形成一聚合層於電 路基材上,聚合層包括阻障層並介於含有氮之第一介電層 與含有磷之第二介電層之間;以及,在形成聚合層之後’ 熱處理此電路基材。依照PMD層來說,聚合層的一個範 例是阻障層或薄膜,其為介電材料例如硼矽玻璃(B s G)或 未摻雜的矽玻璃(USG),用以從硼磷矽玻璃(BPSG)層或薄 膜隔開氮化矽層或薄膜。在這種情況下,阻障層或薄膜可 降低或減少BPSG層或薄膜與氮化矽層或薄膜間的氮消 耗,特別是在熱再熱流期間。 在以下的說明中,將描述出一種聚合層。可得知的 是,聚合層包括被導入或形成於電路基材上之多層或薄 膜。意思就是,此處所述之聚合層包括或可作為”層”,例 如PMD層或内金屬層。 請參照圖式,第1圖為具有元件形成於上及其中之一 部分積體電路基材的剖面側視圖。特別的是,結構1 00包 括基材102,基材102例如是半導體基材且包括N型電晶 體元件1 0 5和P型電晶體元件11 5。電晶體元件1 〇 5和11 5 彼此分離,且係形成於由淺溝渠隔離(STI)結構150定義之 主動元件區中。N型電晶體元件1〇5包括形成於基材1〇2 表面上之閘極電極11〇(—般是在閘極介電層上)以及形成 於基材102中之接面或擴散區13〇。電晶體元件115包括 第8頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚) (請先閲讀背面之注意事項再填寫本頁) 裝· 訂. 經 濟 部 智 慧 財 產 局 員 X 消 費 合 •作 社 印 製 557540 、發明説明() 形成於基材102表面上之閘極電極12〇 以及形成於基材 經濟部智慧財產局員工消費>作社印製 102中之接面或擴散區14〇。 若積體電路結構之元件密度增加,則介於電晶體元件 7之設置通常會減少,導致無法在基材(例如晶片)上之特 定區放入較多㈣#»因A,元件之電子隔離變得更為困 難。所以,-旦元件係形成於一結構上,例如第i圖所示 芡結構,PMD層或薄膜會被導入至結構表面上,以隔離個 別電晶體元鍵與内連線結構,而形成元件之電子連接。在 其他特質中,PMD層具有足夠的溝填能力來填充溝槽,例 如介於電晶體元件間之構槽丨6〇。 第2圖為在第1圖之結構之後,導入含氮介電材料例 如氮化碎(ShN4)之薄膜於基材1〇2表面1〇8上的剖面圖。 在這方面,含氮層或薄膜170會一致地被導入到基材1〇2 表面108上,且會分別覆蓋在閘極電極丨1〇與12〇上。含 氮層或薄膜170係作為介電層或保護層及蝕刻中止層,用 以形成開口透過後續導入到的介電材料,其將於往後段落 中詳細說明而清楚明瞭。氮化矽通常被認為具有一個很高 的介電常數,故其可用作為一個完整的PMD層》因此, 在選擇氮化矽作為含氮層或薄膜1 7 0的實施洳中,例如使 用化學氣相沉積法(CVD),導入例如大約20至200埃之氮 化矽而形成一薄膜,以作為蝕刻中止層。 第2圖也顯示出在第1圖之結構之後,均勻導入阻障 層或薄膜180於含氮層或薄膜170上的示意圖。在一實施 例中,阻障層或薄膜1 8 0係選擇在後續熱處理或回火期 第9頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再塡寫本頁) •裝· 訂· 557540 A7
五、發明説明() 間,將不易消耗含氮層或薄膜170中之氮的材料。在另一 觀點中,阻障層或薄膜180係選擇能夠在習知元件密度狀 態中,達成適當溝填標準(例如再熱流特性)之特性的材 料。 用於阻障層或薄膜180之適當材料包括但不限制在不 含有磷的介電材料β可以相信的是,在再熱流或熱處理期 間,磷會消耗氮。經由加入不含亞磷的阻障層或薄膜,則 在後續熱處理期間的亂消耗可獲得控制。用於阻障層或薄 膜180之典型材料包括但不限制在棚梦玻璃(Bsg)及未摻 雜的碎玻璃(USG) β在一範例中,可導入小於1〇〇〇 # m(BPSG中之後續供應層或薄膜)之BSG或USG作為薄 膜。一種方法是,使用CVD製程和快速加熱處理(rtp), 導入此種BSG或USG之薄膜並進行約30秒。 第3圖為在第2圖之結構之後,導入含亞鱗層或薄膜 1 9 0於結構上的剖面圖。在一實施例中,含亞磷層或薄膜 190是一種選擇用於其之溝填特性的介電材料,特別的 是,此處之材料用以形成PMD層的一部分。亞磷之吸氣 特性也是希望的。用於含亞磷層或薄膜190的一種適當材 料是硼磷矽玻璃(BPSG)。在一實施例中,在習知積體電路 結構狀態中,均勻沉積例如大於20〇〇埃厚度的含亞磷層 或薄膜190。傳統的導入技術是CVD。
為了改善PMD層之溝填特性(如第3圖所示,包括含 氮層或薄膜170、阻障層或薄膜180及含亞磷層或薄膜 190),結構100可進行熱處理或回火製程,然後導入PMD 第10頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公楚) (請先閲讀背面之注意事項再填寫本頁) .裝· 、τ 經濟部智慧財產局員工消費合作社印製 557540
(請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)~' *----------- .装·
,1T 五、發明説明() (請先閲讀背面之注意事項再填寫本頁) 在PMD層中形成開口或介層窗之後,可使用一導電 材料來填充此開口或介層窗。一種普通的方法是’沿著開 口或介層窗的側壁導入一飲黏著層,隨後也是沿著此側壁 導入氮化鈦阻障層。接著,纟剩餘的開口或介層窗中填充 鎢。接著,導入及圖案化位於導電介層窗或開口上之 層表面195上之例如鋁或銅·材料(包括鋁或銅之合金)的内 連線結構210。内連線結構21〇之導入及圖案化過程,可 使用習知方法來完成。 在上述中’已說明了適用作為PMD層之聚合層。關 於PMD層之聚合層,含亞磷介電材料(例如BpSG)通常被 用於連接含氮材料(例如ShN4)。在熱處理期間,阻障層或 薄膜的存在,可降低直接佈置之含亞磷和含氮材料間的氮 消耗。然而,可以得知的是,例如所述之聚合層可用在各 種情況中,而在含有亞磷之氮消耗是需注意的。此種其他 的應用包括但不限制在内金屬介電層或薄膜。 經濟部智慧財產局員工消費合.作社印製 在:L述說明文字中,已揭露出與其之特定實施例有關 之一種方法及裝置。然而,顯然的是,在不脫離本發明之 精神和範圍内,當可作各種之更動與潤飾,因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。舉 例來說,在上述說明文字中,已揭露出與積體電路結構有 關之方法及裝置。此種結構包括但不限制在電子及光學結 構。可在其上形成聚合層之基材,可因此包括但不限制在 半導體、陶瓷、玻璃基材,或半導體、陶瓷及/或玻璃基材 之結合者。因此,本發明並不限制在所描述出之說明文字 第12頁 本紙張尺度適用中國國家標準(CNS)A4規格(2i〇x297公釐) 557540 A7 B7 五、發明説明() 及圖式中。 (請先閲讀背面之注意事項再填寫本頁) 裝. 、可· 經濟部智慧財產局員工消費合作社印製 第1頂 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)

Claims (1)

  1. A8
    一種基材處理方法,至少包括 Γ Μ步驟: 形成一聚合層於一基材上, « μ邊合層至少包括一阻 障層並介於含有氮之一第—介泰 一 包層與含有亞磷之一第 一介電層之間;以及 在形成該玫合層之後,熱處理 該基材 經濟部智慧財產局員工消费合作社印製 2.如申請專利範圍第!項所述之方法,其中該基材至少 括-元件基部及至少-金屬層,而導入該聚合層至少 括導入該聚合層於該元件基部與該至少一金屬層間。 3·如申請專利範圍第!項所述之方法,其中該基材至少 括一非平坦表面,而導入該聚合層至少包括直接導入 聚合層於該非平坦表面上。 4·如申請專利範圍第i項所述之方法,其中該基材至少 括至少一溝渠,而導入該聚合層包括導入該聚合層於 至少一溝渠中。 5·如申請專利範圍第1項所述之方法,其中該第一介電 至少包括氮化♦。 包 包 包 該 包 該 層 6 ·如申凊專利範圍第5項所述之方法,其中該阻障層至少 包括一介電材料。 第14頁 本紙張尺度適用中國國豕標準(CNS)A4規格(210 X 297公餐) (請先閱讀背面之注意事項再填寫本頁) 557540 A8 B8 C8 D8 六、申請專利範圍 7·如申請專利範圍第6項所述之方法,其中該阻障層至少 包括硼。 8. —種基材處理方法,其至少包括下列步驟: 在一基材上,直接導入一阻障層於含有氮之一第一 介電層上; 直接導入含有亞磷之一第二介電層於該阻障層上; 以及 熱處理該基材。 9. 如申請專利範圍第8項所述之方法,其中該基材至少包 括一元件基部及至少一金屬層,而導入該第一介電層包 括導入該第一介電層於該元件基部與該至少一金屬層 間。 10·如申請專利範圍第8項所述之方法,其中該基材少包括 一非平坦表面,而導入該聚合層包括直接導入該聚合層 於該非平坦表面上。 1 1 ·如申請專利範圍第8項所述之方法,其中該基材至少包 括至少一溝渠,而導入該聚合層包括導入該聚合層於該 至少一溝渠中。 1 2 ·如申請專利範圍第4項所述之方法,其中該阻障層至少 第15頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---- I-----丨訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣 557540 A8B8C8D8 六、申請專利範圍 包括一介電材料 •如申叫專利範圍帛5項所述之方法,其中該阻障層至少 包括刪。 14· 一種基材處理裝置|,其至少包括; 一基材;以及 -聚合層’至少包括_阻障材料並介於含有氣之— 第-介電材料與含有亞狀_第二介電材料之間。 15.如申請專利範圍第14项所述之裝置,其中該基材至少 包括-元件基部及至少一金屬材料,而該聚合層係被配 置於孩元件基部與該至少一金屬材料之間。 ^ n ϋ n I ϋ n n ϋ n n I n 0 ϋ I (請先閱讀背面之注意事項再填寫本頁} ·1 訂· 16.如申請專利範圍第15項所述之裝置,其中該第一 材料至少包括氮化矽。 介電 -線· 經濟部智慧財產局員工消費合作社印制衣 如申請專利範圍’第16項所述之裝置,其中該阻障材料 至少包括一介電材料。 該阻障材料 1 8 ·如申請專利範圍第1 7項所述之装置,其中 至少包括硼。 第16頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
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US6967143B2 (en) * 2003-04-30 2005-11-22 Freescale Semiconductor, Inc. Semiconductor fabrication process with asymmetrical conductive spacers
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US7884030B1 (en) 2006-04-21 2011-02-08 Advanced Micro Devices, Inc. and Spansion LLC Gap-filling with uniform properties
US8435898B2 (en) * 2007-04-05 2013-05-07 Freescale Semiconductor, Inc. First inter-layer dielectric stack for non-volatile memory
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US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
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US5166088A (en) 1990-07-03 1992-11-24 Sharp Kabushiki Kaisha Method of manufacturing semiconductor device contact vias in layers comprising silicon nitride and glass
JPH07183250A (ja) 1993-12-24 1995-07-21 Sharp Corp コンタクト形成方法
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US6063656A (en) 1997-04-18 2000-05-16 Micron Technology, Inc. Cell capacitors, memory cells, memory arrays, and method of fabrication
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