TW541622B - Method of post treatment for a metal line of semiconductor device - Google Patents

Method of post treatment for a metal line of semiconductor device Download PDF

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Publication number
TW541622B
TW541622B TW091114234A TW91114234A TW541622B TW 541622 B TW541622 B TW 541622B TW 091114234 A TW091114234 A TW 091114234A TW 91114234 A TW91114234 A TW 91114234A TW 541622 B TW541622 B TW 541622B
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Taiwan
Prior art keywords
metal wiring
layer
post
aluminum
barrier layer
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TW091114234A
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English (en)
Inventor
Jae-Suk Lee
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Dongbu Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31616—Deposition of Al2O3
    • H01L21/3162—Deposition of Al2O3 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

541622 A7 B7 五、發明説明（） 【發明所屬技術領域】 (請先閲讀背面之注意事項再填寫本頁) 本發明係有關利用將氧化鋁膜當成金屬配線之保護 層來使用，可以增進金屬配線可靠度的半導體元件用金屬 配線之後處理方法。 【技術背景】 習知在一般的製造半導體元件上，為了形成多樣型態 之金屬配線（例如鋁合金等）圖案化步驟是必要的，不過， 將鋁合金採用任意圖案進行蝕刻而形成金屬配線的典型蝕 刻步驟，有如利用電漿的乾式蝕刻步驟等。 此外，基板上形成的金屬配線為了可以補償時間常數 等，透過後處理步驟，藉由内金屬介電層（IMD)來埋藏，不 過像這樣的金屬介電層主要利用誘電率較低的氟摻雜矽玻 ^ (Fluorine doped Silicon Glass : FSG)° 再者，氟摻雜矽玻璃（FSG)的主成分氟素（F)係被當成 腐蝕性氣體，在接觸金屬的情況下將引發金屬蝕刻（Metal Etching)。故，若為了減低誘電率而增加氟素成分的話， 經濟部智慧財產局員工消費合作社印製 則會產生嚴重的金屬腐蝕現象，故衍生半導體元件信賴度 降低之問題。 因此，舉例來看習知於金屬配線塗上氟摻雜矽玻璃 前，所使用之保護膜（氟摻雜矽玻璃的下部層）則如由第1 A 圖至第1C圖所示那樣地使用四乙氧基矽烷氧化層（TE0S氧 化層）或是高密度電漿二氧化矽玻璃（HighDensityPlasma
Undoped Silicon Glass : HDP USG) ° 第5頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 541622 A7 -;--- B7 五、發明説明（） 由第1 A圖至第1 c圖係依據習知方法，施行金屬配線 之後處理方法步驟的步驟順序圖。 > 第1 A圖’形成在基板1 〇 2上已具有任意圖案的 金屬配線1 〇 4的丄工 ^ 的治’為了減少時間常數而以内金屬介電層 )材料於形成氟摻雜石夕玻璃（f s G )前，舉例說明，則 如第1 β圖圖式形成既定厚度之保護層1 0 6。此時，保護層 1 06係使用四乙氧基矽烷氧化層或是HDP USG。 接著’利用施行蒸鍍步驟，舉例說明，則如第1C圖 所不’藉由於保護層丨〇 6上部整面形成氟摻雜矽玻璃 (FSG)l〇8’而完成對形成於基板ι〇2上之金屬配線1〇4的 後處理’透過如此形成之氟摻雜矽玻璃即可補償延遲時間 常數。 【發明欲解決之課題】 然’上述之習知方法係被當成保護層來使用的四乙氧 基石夕院氧化層或是高密度電漿二氧化矽玻璃’將產生絕緣 性多少有較低的問題，且因為無法確實阻隔FSG内所含氟 素（F)的擴散，故導致金屬配線被腐蝕，進而產生金屬配線 可靠度降低的問題’並引起因不同性質的物質（四乙氧基 矽烷氧化層或是HDP USG和金屬物質）間所引發應力而造 成使配線可靠度降低的問題。 【解決課題之手段】 本發明係為了要解決上述習知技術之問題點，並為了 達成上述目的，依照本發明之其一型態係提供一種對基板 第6頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂· 線- 經濟部智慧財產局員工消費合作社印製 541622 A7 B7 五、發明説明（） 上已形成任意圖案的金屬配線，施行後處理之方法，乃包 含有：施行蒸鍍步驟而在已形成上述金屬配線的基板整面 上，形成既定厚度鋁的步驟；利用在既定步驟條件下施行 電漿處理，將上述鋁變化成構成下部阻障層之氧化鋁膜的 步驟；以及施行蒸鍍步驟，於上述下部阻障層上面整面上 形成層間絕緣層的步驟。 本發明為達成上述目的之其他型態係提供一種在基 板上已形成任意圖案之金屬配線，施行後處理的方法；包 含有：施行蒸鍍步驟，而於上述已形成金屬配線之基板整面 上，形成由既定厚度氧化鋁膜所構成下部阻障層的步驟； 以及施行蒸鍍步驟而於上述下部阻障層上面整面，形成層 間絕緣層的步驟。 本發明含有上述及其他目的等許多優點，希望能藉由 熟悉此技術分野者，參照附圖並藉由下述之本發明實施例 開始使其更明確。 【發明實施形態】 以下，參照附圖，對本發明之較佳實施例進行詳細說 明。 首先，本發明之核心技術要旨係不同於上述之習知技 術，即並非使用四乙氧基矽烷氧化層或是高密度電漿二氧 化矽玻璃來當作金屬配線之保護層，而係使用具優越絕緣 性且可確實抑制氟素擴散，且具有和金屬配線相類似性質 的氧化鋁膜（A 12〇3 )，透過這樣的技術手段可以容易地達成 第7頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) (請先閲讀背面之注意事項再填寫本頁) 羲. 經濟部智慧財產局員工消費合作社印製 2 2 6 五 經濟部智慧財產局員工消費合作社印製 A7 — _B7^ 發明説明（） 本發明目的。 第2A圖至第2c圖係依據本發明，為金屬配線之後處 王里 , y 而於幵> 成金屬配線之晶圓上進行後續步驟過程予以圖 式化之步驟順序圖。 參照第2 A圖，於基板2 0 2上形成任意圖案的金屬配 2 0 4 ,則為了減少時間常數，在當作形成内金屬介電層 才料之氟摻雜矽玻璃前，舉例說明則如第2 b圖所示，使用 匕干氣相沉積法（C V D )或是物理氣相沉積法（p v D )，在金屬 配線2 04上面整面，蒸鍍上當作下部阻障物質用的既定厚 度（例如80A至150A之程度，最理想則為1〇〇A)。 接著，依照既定步驟條件下’用〇2或是N2〇進行電漿 處理，使下部阻障物質（A 1 )變化為由氧化鋁膜（A丨2〇3)所構 成的下部阻障層2 0 6。 此時’於金屬配線2 0 4上形成之氧化鋁膜（A 12〇3 )，係 和使用四乙氧基矽烷氧化層或是高密度電聚二氧化矽破璃 比較，則更具優越絕緣性，並可確實抑制透過後續步驟而 於下部阻障層2 0 6上所形成之層間絕緣層2〇8内所含氟素 (F )之擴散，並且不會誘發和金屬配線2 〇 *間的應力。 接著，藉由進行蒸鍍步驟，舉例如第2C圖所示，依 據遍及於下部阻障層2 0 6之上部整面所形成之氟摻雜發破 璃（FSG)2〇8’完成對在基板2 02上所形成金屬配線2〇4之 後處理，並且透過如此形成說換雜發破壤，則可以補償 延遲。 第8頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ......----(裝.........訂.........線· (請先閲讀背面之注意事項再填寫本頁) 541622 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 另，於本實施例說明雖為將鋁（A 1 )蒸鍍後，透過電漿 處理於金屬配線上部形成具有下部阻障層機能之氧化鋁膜 (A 12〇3 )，但本發明絕非僅限於此，更可以透過化學氣相沉 積法於金屬配線上直接形成氧化鋁膜（A 12〇3 )，透過此法可 以實質地得到同一結果。 【發明效果】 以上，同上述說明本發明有別於習知技術之使用四乙 氧基矽烷氧化層或是高密度電漿二氧化矽玻璃來當金屬配 線之保護層，而係使用具有優越秀絕緣性質之可以確實抑 制氟擴散，且為和金屬配線屬於類似系列物質之氧化鋁膜 (A 12〇3 )來當成為保護金屬配線之下部阻障層，藉此除了可 確保絕緣性，亦確實地抑制氟之擴散，又因可減少其和金 屬配線間之應力，故可有效地增進金屬配線之可靠度。 以上為將本發明藉由實施例之詳細說明，然，本發明 並不為實施例所侷限，且於屬於本發明之技術領域中，在 具有一般知識下，將不會背離本發明之思想及精神，而可 修正或變更本發明。 經濟部智慧財產局員工消費合作社印製 【圖式簡單說明】 第1 A圖至第1 C圖係利用習知方法，進行金屬配線之 後處理步驟過程之步驟順序圖。 第2 A圖至第2 C圖係本發明之金屬配線之後處理，於 金屬配線形成於晶圓上所進行後續步驟過程之步驟順序 圖。 第9頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） 541622 A7 B7 五、發明説明（） 【圖示符號說明】 202 基板 204 金屬配線 206 保護層 208 層間絕緣層 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 第10頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)

Claims (1)

  1. A B CD 541622 々、申請專利範圍 1. 一種半體體元件之金屬配線之後處理方法，係對已在基 板上形成任意圖案的金屬配線施行後處理的方法，包含 有： 施行蒸鍍步驟而在已形成上述金屬配線的基板整面上，形 成既定厚度之鋁的步驟； 在既定步驟條件下施行電漿處理，而將上述鋁形成構成下 部阻障層的氧化鋁膜之步驟；以及 施行蒸鍍步驟而在上述下部阻障層上面整面上，形成層間 絕緣層的步驟。 2. 如申請專利範圍第1項之半體體元件之金屬配線之後處 理方法，其中上述鋁的厚度為80A至1 50A的範圍。 3 .如申請專利範圍第1項之半體體元件之金屬配線之後處 理方法，其中上述電漿處理係使用02或是N2〇。 4. 一種半體體元件之金屬配線之後處理方法，係係對已在 基板上形成任意圖案的金屬配線施行後處理的方法，包 ------k............裝.........訂.........線^ (請先閲讀背面之注意事項再填寫本頁) 形 上 面 整 板 基 的 線 配 金 述 上 成 形 已 在 而 驟 步 : 鍍 有蒸 含行 施 經濟部智慧財產局員工消費合作社印製 間 •, 層 驟成 步形 的 ， 層 上 障 面 阻 整 部面 下上 成 層 構 障 所阻 膜部 鋁下 化述 氧 上 之在 度而 厚理 定 處 既 漿 由 電 成行 施 步 勺 白 層 緣 邑 么''· 頃 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)
TW091114234A 2001-06-27 2002-06-27 Method of post treatment for a metal line of semiconductor device TW541622B (en)

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