TW580750B - Forming method of barrier layer for protecting metal conduction wire - Google Patents

Abstract

A kind of method for forming the barrier layer to protect metal conduction wire is provided in the present invention. The invention includes the followings: at first, providing a deposition processing room; providing a semiconductor substrate on which a metal conduction wire is formed; then, forming the first barrier layer on the surface of the metal conduction wire in the deposition processing room and under 0W bias power; increasing bias power to the first bias power to form the second barrier layer on the first barrier in the deposition processing room; and increasing bias power to the second bias power to form a dielectric layer on the semiconductor substrate and the metal conduction wire in the deposition processing room.

Description

580750 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to an abundance riding system. KA 八 M # M t- neodymium body work, 4 inches is related to a method of forming a line Therefore, the A EX people from G and D will maintain the distance-to-width ratio between the metal wires and avoid filling in the metal wires; a gap will be created when the electrical layer is formed. The previous technology has been used in ICs for ICs, ΑΛ. LL, and ^^ 7. Applications of conductors, semiconductors, and insulating layer materials have been widely used, and thin film deposition (thin fUm deP0Sltlon) ), Lithography process (ph0tothography), and etching (etching) are the main semiconductor technologies. Among them, the thin film deposition is to deposit the above-mentioned material layers on the surface of the wafer to be processed, and the lithography process is to copy the desired element or circuit patterns to be formed, and then transfer these patterns to the surface of the wafer to be processed through the etching step. Each layer forms a semiconductor element such as a transistor or a capacitor. After the component fabrication is completed, a metal wire needs to be manufactured next to connect the components, that is, a metallization (m e t a 1 1 i z a t i ON) process. In the metallization process, 'in order to avoid short circuits between components or metal wires due to direct contact, an insulating layer must be formed between the metal wires or between the components for isolation, and the insulating layer used for isolation is generally called the inner layer dielectric. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) can be used to isolate semiconductor elements such as transistors and capacitors from metal layers, and as a dielectric to isolate the interconnections of various metals. Floor. In a general semiconductor manufacturing process, an aluminum-copper alloy layer made of an aluminum-copper alloy can be used as an interconnecting wire. Because the resistivity of aluminum metal itself

0503-8659TO (Nl); TSMC2002-0520; Claire.ptd Page 6 580750 V. Description of the invention (2) (R esistivity) is quite low, and the adhesion to the silicon dioxide layer is good, it has been used by Jinbian As the main conductive material of the component, it can reduce the RC Time Delay and increase the switching frequency of the component. Please refer to Figures 1a-1g. Figures 1a-1g are schematic diagrams showing the conventional formation of an insulating layer between metal wires.

Please refer to FIG. 1a. First, a semiconductor substrate 101 is provided, and a metal layer 102, an anti-reflection layer 103, and a patterned masking layer 104 are sequentially formed on the semiconductor substrate 101 to a thickness of about 4000 to 8000 A. The metal layer 10 covered by the patterned mask layer 104 is the position where the metal wires are subsequently formed. The metal layer 102 is, for example, an aluminum-copper metal layer; the anti-reflection layer 103 is, for example, a titanium (Ti) layer or a titanium nitride (TiN) layer or a composite layer thereof, to prevent light reflection on the metal surface. Effect on the accuracy of photoresist exposure. Referring to FIG. 1b, the patterned mask layer 10 is used as a mask, and the anti-reflection layer 103 and the metal layer 10 are sequentially etched until the surface of the semiconductor substrate 101 is exposed to form a metal wire 102a. And the anti-reflection layer 1 0 3 a ′ remaining on the metal wire 1 0 2 a, and at the same time, a groove 1 0 5 is formed between the metal wire 1 2 a and the groove 1 0 5 will expose the semiconductor substrate 1 0 1 Part of the surface; wherein the width of the trench 105 is about 1000 to 3500A.

Next, “the semiconductor substrate 1 〇1 is put into a chemical deposition processing chamber, and the semiconductor substrate 1 〇1 is subjected to a silicon dioxide (Si H4) as a reaction gas under the condition of a bias power (bias RF) of 0W for about 5 seconds. 5 to 5 seconds of plasma enhanced chemical vapor deposition (PE CVD) treatment, in order to

580750 V. Description of the invention (3) A barrier layer 1 0 6 having a thickness of about 250 to 500 people is formed on the exposed surface of the line 102 a and the anti-reflection layer 103 a. The barrier layer 1 0 6 is formed in the trench 1 0 5 A vertex 1 0 6 a will occur at the top corner of the substrate, as shown in FIG. 1 c; wherein the barrier layer 10 6 is, for example, an oxide layer (p E-ο X ide) or rich Shi Xi oxide layer (PE-si1 icon rich oxide 5 PE-SRO) o Please refer to the figure Id, and then, under the condition that the bias power (bias rf) is 0 W, use silane (S i H4) The semiconductor substrate 100 is subjected to a high density plasma chemical vapor deposition (HDP CVD) treatment for about 3 to 5 seconds to open on the surface of the barrier layer 106 to a thickness of about iQ. 〇 to 3qqa barrier layer ίο ?, the barrier layer 107 at the top corner of the trench 105 will have overhang (〇verhang) 107a or 107b occurs, as shown in Figures I-I and Figures le-2 As shown in the figure, wherein the barrier layer 107 is, for example, undoped silica glass (us). Please refer to Figure 1e_1. When the high-density plasma chemical vapor deposition is performed for a long time, the barrier layer on the side wall of the trench 105 has a thickness sufficient to prevent subsequent trenches. 〇5 The fluorine contained in the filled fluoro-silica glass enters the metal wire 10 2a, but the overhang at the top corner of the groove 105 is 107 °. The situation will be quite serious. Fluoro-silicon glass is filled in the trench 105. Jiao Bei ',,, and Fa Jiang 3 Please refer to the figure le_2. When the time of Gao Poi and Emperor Fragment is short, the top of the mountain located at the trench i05 is not obvious, but the side wall of the trench m is not obvious. In the case of the sudden miG? Ba, it cannot prevent the subsequent thickness of the trench layer 107 from being too thin and entering the metal wire 102a, which causes the gas contained in the stone evening glass to enter. Contained in fluorosilicone glass

580750 V. Description of the invention (4) Gas enters the metal wire 10 2a. If the fluorine enters the metal wire 102a, the water vapor generated by the subsequent thermal oxidation treatment will cause the fluorine to form fluoric acid (HF). The fluoric acid will invade the metal and generate metal 1 corrosion. The phenomenon. Please refer to the If figure, and then, under the condition that the bias power (bias RF) is 2500 W, the semiconductor substrate 100 is subjected to high-density plasma chemistry for about 1000 to 250 seconds with fluorine (F). A high density plasma chemical vapor deposition (HDP CVD) process is performed to fill the trench 105 with a fluoro silicate silicate g 1 ass (FSG) layer 108 and continue to deposit to a desired thickness To facilitate the subsequent contact window process, as shown in Figure 1g. The above processes are all performed in the same machine, and only the settings of the machine need to be adjusted to proceed to the next step; also because the bias power required for each of the above steps is not the same, the inventor of this case found that when the bias power is changed from When the 〇W is changed to 2 500W, the sudden high energy will make the metal wire 102a and the anti-reflection layer 10 3a unable to be tightly bonded, resulting in the anti-reflection layer 1 0 3 a There will be a phenomenon similar to ARC pee 1 ing 1 09. A method of improving the cvd-FSG layer as a metal barrier layer or a diffusion barrier layer is mentioned in U.S. Patent No. 6,035,518.

A method of improving a thin layer of h_p_fsG as a barrier layer is also mentioned in US Pat. No. 6,410,457. In addition, U.S. Patent No. 6,121,161 also mentions a method and apparatus for reducing the flow of ions and contamination of metal layers in an HDP-CVD deposition processing chamber.

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580750 V. Description of the invention (6) A first barrier layer is formed on the exposed surface of the metal wire and the anti-reflection layer; in the deposition processing chamber, a semiconductor substrate is firstly subjected to a bias power of 0 W. A high-density electro-chemical chemical vapor deposition process is performed to form a second barrier layer on the surface of the first barrier layer; in the deposition processing chamber, the bias power is increased to a first bias power to the semiconductor The substrate is subjected to a second high-density plasma chemical vapor deposition process to form a bias barrier layer on the first barrier layer, and the first barrier layer, the second barrier layer, and the bias barrier layer together form a A composite barrier layer; and a third high-density plasma chemical vapor deposition process on the semiconductor substrate to increase the bias power to a second bias power in the deposition processing chamber to cover the semiconductor covered by the composite layer A dielectric layer is formed on the substrate and the metal wires. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Implementation: Please refer to Section 2a-2 Figure i, Figures 2a-2i are schematic views showing the formation of an insulating layer between metal wires according to the present invention. Please refer to FIG. 2a. First, a semiconductor substrate 201 is provided, and a metal layer with a thickness of about 4000 to 8000 A is sequentially formed on the semiconductor substrate 201. An anti-reflection layer 203 and a patterned mask are sequentially formed. The layer 2 0 4 is a metal layer 2 0 2 covered by the patterned mask layer 2 0 4, which is a position for forming a metal wire subsequently. Among them, the metal layer 202 is, for example, a copper metal layer; the anti-reflection layer 203 is, for example, a titanium (T i) layer or a titanium nitride (T i N) layer or a composite layer thereof to prevent gold

0503-8659TWF (Nl); TSMC2002-0520; Claire.ptd Page 11 580750 V. Description of the invention (7) The influence of the reflection of the metal surface on the accuracy of the photoresist exposure. Please refer to FIG. 2b, with the patterned mask layer 204 as a mask, and sequentially etch the anti-reflection layer 203 and the metal layer 202 until the surface of the semiconductor substrate 201 is exposed to form a metal wire 2 0 2a and remain on the metal wire 2 The anti-reflection layer 2 0 3 a on 02a, and at the same time, a groove 205 is formed between the metal wires 2 0 2 a, and the groove 205 will expose a part of the surface of the semiconductor substrate 201; The width is approximately 1 0 0 0 to 3 5 0 0 A. Next, the semiconductor substrate 2 01 is put into a chemical deposition reaction chamber, and the semiconductor substrate 2 01 is subjected to silicon dioxide (SiH4) as a reaction gas for about 5 to 1 under the condition that the bias power (bias RF) is 0W. 5 seconds of plasma enhanced chemical vapor deposition (PECVD) treatment to form a thickness of about 2 50 to 3 on the exposed surface of the semiconductor substrate 201, the metal wire 202a, and the antireflection layer 2 0 3a The barrier layer 2 0 6 of 50 A, the barrier layer 2 0 6 at the top corner of the trench 2 0 5 will have an overhang 2 0 6a, as shown in Figure 2c; The barrier layer 206 is, for example, an oxide layer (PE-o Xide) or a PE-silicon rich oxide (PE-SR0). Please refer to FIG. 2d, and then, under the condition that the bias power (bias RF) is 0W, the silicon substrate (Si H4) is used to perform a shorter reaction time of about 2 to 1 0 耖The first high-density plasma chemical vapor deposition (HDP CVD) process of time to form a barrier with a thickness of about 100 to 300 people on the surface of the barrier layer 206 The layer 2 0 7 and the barrier layer 2 0 7 may have overhang (0 verhang) 2 0 7 a at the top corner of the trench 2 0 5.

0503-8659TWF (Nl); TSMC2002-0520 > Claire.ptd Page 12 580750 5. Description of the invention (8) --- as shown in Figure 2e; where the barrier layer 2 7 is, for example, undoped silicon glass (USG). Referring to Figure 2e, after performing the high-density plasma chemical vapor phase for a short time = and the step, the situation of the overhang 207ba located at the top corner of the groove 205 will be less obvious, in order to facilitate the follow-up During the manufacturing process, fluorosilicon glass is filled in the trenches. However, when the thickness of the barrier layer 207 on the side wall of the trench 205 is too thin, it will prevent the fluorine contained in the fluorine-containing silicate glass that is subsequently filled from entering the metal wire 20 2a. If fluorine enters the metal wire 202 and the water vapor generated by the subsequent thermal oxidation treatment will cause the fluorine to form fluoric acid (HF), the fluoric acid will know the metal and produce metal corrosion. The phenomenon. Therefore, the characteristic steps of the present invention are performed next. Please refer to FIG. 2 f and FIG. 2 g 'under the condition that the bias power (b 丨 as rf) is the first bias power', the semiconductor substrate 201 is treated with lithoxane (Si M) for about 2 to 10 seconds First high-density plasma chemical vapor deposition (HDP CVD) process to form a bias liner on the surface of the barrier layer 207 with a thickness of about 100-300a 2 0; Among them, the first bias power is about ii OOw to 13 MW, more preferably 1200 W. Because the deposition processing chamber 21 has a bias power of 1200 W Plasma using silicon sulfide (Si Η) as the reaction gas will have a higher speed. Therefore, when the deposition step is performed to form the bias liner 2 08, there will also be a portion of the bias liner 2 0. 8 was dissociated by the plasma. Especially the biased layer 2 0 8 a 'at the top corner position of the trench 20 5' because the overhang of the gaseous $ hit caused the overhanging part to splash again. Hit the sidewall of the metal, so when the trench 20 side wall is composed of a barrier layer 2 06, 2 07 and 2 0 8 a composite barrier layer

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After the side wall barrier layer 209b has been deposited to a sufficient thickness, the top corner barrier layer 209a at the top corner position of the trench 205 will not have the overhang phenomenon. . Please consider Figure 2h. Then, under the condition that the bias power (bias rF) is the second bias power, the semiconductor substrate 201 is subjected to a third high density of about 100 to 25 seconds with fluorine (F). High-density plasma chemical vapor deposition (HDP CVD) treatment to fill the trenches 205 with a layer of fluorine-containing silicate glass (Π nor osilicate silicate glass, FSG) 2 10, the second partial The pressure power is about 2400w to 2600 (^, preferably M00W), and is continuously deposited to a desired thickness to facilitate the subsequent contact window process, as shown in FIG. 2i. Fluorine according to the present invention Silica glass can protect the metal layer from fluorine on the side of the metal layer. When adjusting the bias work set by the machine, the energy will not project from the reflective layer 2 0 3 a to 2 0 3 a. The present invention limits the present invention. Within the scope and scope, when the fluorine wall provided by the attached application can be seen to form a thick invasion; the setting rate of the integration is gradually improved, and the shaving will be completed upon completion. How to familiarize yourself with this change and use it to protect the metal layer from being used as a dielectric The formation method of the known barrier layer is because the barrier layer is sufficient, so it can effectively ensure that the above processes are carried out in the same machine, and then the next step can be performed. Therefore, when the hair is raised from 0W to 1200W, it will be improved. To 2500W = too high, so after the metal wire 202a and the anti-fluorine-containing glass layer, the anti-reflection layer is peeled. Only the example is disclosed above, but it is not intended to be a technical person, without departing from the present invention. The spirit of decoration, so the scope of protection of the present invention shall prevail.

580750 Brief Description of Drawings Figures 1 a-1 g show the conventional intention of forming an insulating layer between metal wires. Brother 2a-2i is a schematic diagram showing the insufficiency of the formation of an insulating layer between metal wires. Explanation of symbols: 1 0 1, 2 0 1 ~ semiconductor substrate; 1 0 2, 2 0 2 ~ metal layer; 102a, 202a ~ metal wire; 1 0 3, 1 0 3 a, 2 0 3, 2 0 3 a ~ Anti-reflection layer; 104, 20-4 ~ patterned mask layer; 105, 20 ~ 5 trench; 106, 206 ~ barrier layer; 106a, 107a, 107b, 2 0 6a, 2 0 7 a ~ protrusion; 108, 2100 ~ dielectric layer; 109 ~ chipped; 209a ~ apex barrier layer; 209b ~ sidewall barrier layer.

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Claims (1)

580750 VI. Application patent scope 1. A method for forming a barrier layer for protecting a metal wire, including the following steps: providing a deposition processing chamber; providing a semiconductor substrate on which a metal wire is formed; and in the deposition processing chamber Forming a first barrier layer on the surface of the metal wire under a bias power of 0 W; and in the deposition processing chamber, increasing the bias power to a first bias power at the first A second barrier layer is formed on the barrier layer. 2. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of the patent application, wherein after forming the second barrier layer, the method further includes the following steps: In the deposition processing chamber, increasing the bias voltage A dielectric layer is formed on the semiconductor substrate and the metal wire under a second bias power. 3. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of the patent application, wherein the metal wire is an aluminum copper metal layer. 4. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of the patent application, wherein the thickness of the first barrier layer is 250 to 500 A. 5. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of the patent application, wherein the method for forming the first barrier layer is a plasma-assisted chemical vapor deposition method. 6. The method for forming a barrier layer for protecting a metal wire according to item 5 of the scope of patent application, wherein the plasma-assisted chemical vapor deposition method is performed for 5 to 15 seconds. 0503-8659TO (Nl); TSMC2002-0520; Claire.ptd page 16 580750 6. Application for patent scope 7. The method for forming a barrier layer for protecting a metal wire as described in item 1 of the scope of patent application, wherein the first The reactive gas of a barrier layer is silicon methane. 8. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of the patent application, wherein the first barrier layer is a composite layer of a silicon-rich oxide layer and an undoped silicon glass. 9. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of the patent application, wherein the first bias power is 1 100 W to 1 300 W. I 0. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of the patent application, wherein the second bias power is from 24 0W to 26 0W. II. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of patent application, wherein the thickness of the second barrier layer is 100 to 300 A. 1 2. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of patent application, wherein the method for forming the second barrier layer is a high-density plasma chemical vapor deposition method. 13. The method for forming a barrier layer for protecting a metal wire according to item 12 of the scope of the patent application, wherein the high-density plasma chemical vapor deposition method is performed for 2 to 10 seconds. 14. The method for forming a barrier layer for protecting a metal wire according to item 13 of the scope of the patent application, wherein the high-density plasma chemical vapor deposition method is performed for 1 to 10 seconds. 15. The method for forming a barrier layer for protecting a metal wire as described in item 1 of the scope of the patent application, wherein the reaction gas used to form the second barrier layer is siloxane. 0503-8659TWF (N1); TSMC2002-0520; Claire.ptd Page 17 580750 6. Application for patent scope 1 6. The method for forming a barrier layer for protecting a metal wire as described in item 1 of the scope of patent application, wherein the intermediary The electrical layer is a layer of a low dielectric constant material. 1 7. The method for forming a barrier layer for protecting a metal wire according to item 16 of the scope of the patent application, wherein the low-dielectric-constant material layer is a fluorine-containing silicon glass layer. 1 8. The method for forming a barrier layer for protecting a metal wire according to item 1 of the scope of the patent application, wherein the method for forming the dielectric layer is a high-density plasma chemical vapor deposition method. 19. The method for forming a barrier layer for protecting a metal wire according to item 18 of the scope of the patent application, wherein the high-density plasma chemical vapor deposition method is performed for 100 to 250 seconds. 20. A method for forming a barrier layer for protecting a metal wire includes the following steps: providing a deposition processing chamber; providing a semiconductor substrate; a metal wire is formed on the semiconductor substrate, and the metal wire is covered with an anti-reflection layer; In the deposition processing chamber, under a bias power of 0 W, a plasma-assisted chemical vapor deposition process is performed on the semiconductor substrate to form a first barrier on the exposed surface of the metal wire and the anti-reflection layer. A first high-density plasma chemical vapor deposition process on the semiconductor substrate at a bias power of 0 W in the deposition processing chamber to form a first on the surface of the first barrier layer Two barrier layers; in the deposition processing chamber, increasing the bias power to a first bias power5 performing a second-density electropolymerization chemical vapor deposition on the semiconductor substrate 0503-8659B, F (Nl); TSMC2002-0520; Claire.ptd page 18 580750 6. Apply for a patent range process to form a bias liner on the first barrier layer, and the first barrier layer , The second barrier layer and the bias liner layer together form a composite barrier layer; and in the deposition processing chamber, increasing the bias power to a second bias power, performing a third high on the semiconductor substrate A density plasma chemical vapor deposition process is performed to form a dielectric layer on the semiconductor substrate and the metal wire covered by the composite layer. 2 1. The method for forming a barrier layer for protecting a metal wire as described in item 20 of the scope of patent application, wherein the metal wire is an aluminum copper metal layer. 2 2. The method for forming a barrier layer for protecting a metal wire as described in item 20 of the patent application scope, wherein the anti-reflection layer is a titanium (Ti) layer or a titanium nitride (TiN) layer or a composite layer thereof. 2 3. The method for forming a barrier layer for protecting a metal wire according to item 20 of the scope of the patent application, wherein the first barrier layer is a silicon-rich oxide layer. 24. The method for forming a barrier layer for protecting a metal wire according to item 20 of the scope of the patent application, wherein the thickness of the first barrier layer is 250 to 350 A. 25. The method for forming a barrier layer for protecting a metal wire according to item 20 of the scope of the patent application, wherein the plasma-assisted chemical vapor deposition is performed for 1 to 3 seconds. 26. The method for forming a barrier layer for protecting a metal wire according to item 20 of the scope of the patent application, wherein the second barrier layer is an undoped silica glass layer. 27. The method for forming a barrier layer for protecting a metal wire according to item 20 of the scope of the patent application, wherein the thickness of the second barrier layer is 100 to 300. 0503-8659TWF (Nl); TSMC2002-0520; Claire.ptd page 19 580750 6. Scope of patent application. 28. The method for forming a barrier layer for protecting a metal wire as described in Item 20 of the scope of the patent application, wherein the first bias power is 1 1 0 0 W to 1 3 0 0 W. 29. The method for forming a barrier layer for protecting a metal wire as described in item 20 of the scope of patent application, wherein the time for performing the / high-density plasma chemical vapor deposition method is 1 to 3 seconds. 30. The method for forming a barrier layer for protecting a metal wire as described in Item 20 of the scope of the patent application, wherein the thickness of the bias liner is 50 to 150 A. 3 1 · The method of forming a barrier layer for protecting a metal wire as described in item 2 q of the patent scope, wherein the second bias power is 2400W to 2600W. 32. The method for forming a barrier layer for protecting a metal wire as described in Item 20 of the scope of patent application, wherein the time for performing the second high-density plasma chemical vapor deposition method is 1 to 50 seconds. 3 3. The method for forming a barrier layer for protecting a metal wire as described in item 20 of the scope of patent application, wherein the dielectric layer is a low-dielectric-constant material layer. 34. The method for forming a barrier layer for protecting a metal wire according to item 32 of the scope of the patent application, wherein the low-dielectric-constant material layer is a fluorine-containing silicon glass layer. 35. The method for forming a barrier layer for protecting a metal wire as described in item 20 of the scope of the patent application, wherein the method for forming the dielectric layer is a high-density plasma chemical vapor deposition method. 3 6 · The method for forming a barrier layer for protecting a metal wire as described in item 20 of the scope of the patent application, wherein the time for performing the > branch-off plasma chemical vapor deposition method is 100 to 2 5 0 seconds. .. ________________________________ " .......-