Λ ?J· B 5 3 A7 ______ _ B7 ~ 1 — - 五、發明說明（/ ) 發明領域： 本發明係關於S種積體電路之金屬阻障層的製作方法’ 特別是關於一種於習知之化學氣相沉積氮化鈦層上形成一超 薄之物理氣相沉積氮化鈦層的複層阻障層結構。 發明背景： —般而言’半導體元件隨著積體電路密度的增加及體積 的縮小’可明顯改善電性動作的速度，並減少電子產品的生 產成本’是以元件尺寸極小化與高積集度，一直是積體電路 製作上極爲重要的發展方向之一。然而，元件尺寸極小化使 得晶片的表面無法提供足夠面積來製作所需的導線結構，多 層導線結構的需求也就越來越重要，此外，發展優於傳統製 程之新方法或新材料，亦是當今迫切需解決的課題。 經濟部智慧財產局員工消费合作社印製 ιιιιιι — — — — — _^-------—訂· (請先閱讀背面之注意事項再填寫本頁) 在目前之積體電路製程中，無論是在傳統的鋁金屬製程 或新發展之銅金屬製程都同時面臨了^個問題，即爲金屬與 矽接面間產生的尖峰（spike)現象，所述尖峰現象之成因 係爲：當金屬（鋁或銅）沉積在砂表面，而溫度高於兩者之 互溶溫度時，矽對金屬有一固態溶解度，矽將藉擴散效應而 進入金屬層中’金屬也會回塡因擴散所遺留下來之空隙，使 得矽與金屬之接面形成尖峰，如果這些尖峰的長度太長，則 可能會造成迴路短路（short)，解決此問題的一種方法即在 金屬與砂之間加入一稱爲阻障金屬（barrier metal)的材料， 而在現行積體電路之金屬溝塡製程中，通常在沉積插塞 (plug)金屬鎢（W)之前，依序於矽基板上形成一物理氣 相沉積（Physical Vapor Deposition; PVD )之鈦（Ti)金屬層 2 尺度適用中國國ϋ举（CNS)A4規格（210 X 297公β 4 2185 3 部 五 貝 工 消 費 B7 發明說明（>) 與一化學氣相沉積（Chemical Vapor Deposition; CVD )之氮 化鈦（TiN)層，其中利用CVD形成之氮化鈦層將具有較佳 之階梯覆蓋能力，而所述鈦金屬層則Μ高與矽之間的接觸 電阻，然而，當選擇利用有機的含鈦反應氣體（例如:TDMAT (Tetrakis-Dimethylamino-Titanium; Ti-(N(CH3)2)4))來形成 所述CVD-氮化鈦層時，經由熱裂解方式形成的氮化鈦薄膜 具有多孔性且常含有大量的碳（C )及氧（0 )雜質則明顯 影響其電阻値，雖後續利用N2電漿進行處理，可提昇所述 CVD-氮化鈦層之性質，降低C、Ο含量及其過高的電阻値’ 但所述\電漿處理仍無法完全消弭所述CVD-氮化鈦層在大 氣下吸收水氣及氧化的現象，是以隨著暴露在大氣中的時間 增加，所述CVD-氮化鈦層的阻値將隨之增加，而此現象稱 之爲氮化欽薄膜的老化效應（aging effect)。所述氮化鈦薄 膜易吸水氣及易氧化的現象會使得後續製作金屬成核層時’ 無法形成一均勻覆蓋於所述CVD-氮化鈦層上的金屬成核層 (nucleation layer) ’跟著便影響接下來的金屬溝塡製程及插 塞金屬的性質，故本發明提供一新金屬阻障層之製作方法來 降低所述CVD-氮化鈦層的老化效應。 發明之槪述： 本發明之主要目的是提供一種積體電路之金屬阻障層的 製作方法，形成具較低且均勻分佈之電阻値的金屬阻障層。 本發明係使用下列步驟來達到上述之各項目的：首先’ 提供一表面已形成有一介電層的基板；接著，於所述基板中 開啓數個溝槽（trench);再接著，依序沉積一 PVD-鈦金 -----------I — — — — — — I— (請先閱讀背面之注意事項再填寫本真) 製 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 42185 3 A7 B7 部 智 慧 財 員 工 消 費 20-介電層 40-鈦金屬層 60-PVD氮化鈦層 五、發明說明（〉） 屬層及一 CYD-氮化鈦層；接下來爲本發明之重要特徵，係 於所述CVD-氮化鈦層上形成一 PVD-超薄氮化鈦層，而形 成一堆疊式複層阻障層結構；最後，依序形成銅金屬成核層 (nudeation layer)及插塞（plug)金屬層，移除所述介電 層上之所述插塞金屬層、所述銅金屬成核層及所述複層阻障 層，完成了具有PVD-超薄氮化鈦層之金屬溝塡製作。 圖式簡要說明： 圖一爲本發明實施例中於一具有溝槽之基板上依序形成 —PVD-鈦金屬層、一 CVD-氮化鈦層及一 PVD-超 薄氮化欽層之剖面示意圖。 圖二爲本發明實施例中有、無製作PVD-超薄氮化鈦層 之晶片其暴露於大氣中之時間與片電阻變化量之 相對關係圖。 圖號說明： 10-基板 30-溝槽 50-CVD氮化鈦層 A-僅具CVD氮化鈦層時之片電阻變化量 B- CVD氮化鈦層覆蓋有PVD氮化鈦層時之片電阻變化量 發明詳細說明： 本發明係有關於積體電路之金屬阻障層的製作方法，其 主要特徵乃於習知之CVD-氮化鈦層上覆蓋一超薄之PVD-氮 化鈦層，其詳細的製程實施步驟詳述如下，並請同時參閱圖 -------------- ^--------訂---------線‘ (請先閱讀背面之注意事項再填寫本頁) _ 製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 4 2^85 3 五、發明說明（拳） -----—--—-- I · 1---- 訂. (諳先閱讀背面之注意Ϋ項再填寫本頁> 首先，提供一半導體基板10，所述基板10上已形成有一 介電層20，並利用微影及非均向之乾式蝕刻技術於所述基板 10中開啓一個或數個溝槽（trench) 30，其中所述介電層20 係利用化學氣相沉積法（Chem i ca 1 Vapor Depos i t i on; CTD) 形成之氧化矽結構或其他低介電係數（lowk)材質。〇 接著，依序利用物理氣相沉積法（PVD)及化學氣相沉 積法（CVD) ’於所述基板10上及所述_30中沉積一PVD-鈦金屬層40及一CVD-氮化鈦層50，其中選擇利用CVD形成 之所述氮化鈦層50係因CVD沉積法形成之薄膜具有較佳之 階梯覆蓋能力，而形成所述鈦金屬層40則可提高與砍之間的 接觸電阻。所述PVD-鈦金屬層40之厚度係介於30A至500A 之間。所述CVD-氮化鈦層50之厚度係介於20A至200人之間。 經濟部智慧財產局員工湞費合作社印製 接下來爲本發明之重要特徵，係利用物理氣相沉積法形 成一超薄之氮化鈦層60覆蓋於所述CVD-氮化鈦層50上，藉 由所述PVD-氮化鈦層60保護所述CVD-氮化鈦層50，尤其是 保護接觸洞孔肩部之所述CVD-氮化鈦層50，減少所述CVD-氮化鈦層50與大氣接觸的面積，降低所述CVD-氮化鈦層50 的老化效應。其中所述PVD-氮化鈦層60之厚度係介於30A至 300A之間。 最後，利用習知之金屬溝塡製作方法，依序利用化學氣 相t几積法沉積一金屬成核層（nucleation layer)於所述PVD-氮化鈦層上，並沉積一插塞（plug)金屬層塡滿所述溝槽30， 其中所述金屬成核層及所述插塞金屬層之材質係皆爲鎢 (W )金屬；然後，利用化學機械硏磨法（chemical Mechanical I____：_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 經濟部智慧財產局員工消費合作社印製 4 2185 3 A7 ___B7____________ 五、發明說明（丨） *Λ? J · B 5 3 A7 ______ _ B7 ~ 1 —-V. Description of the invention (/) Field of the invention: The present invention relates to a method for manufacturing a metal barrier layer of S-type integrated circuits', especially to a method known in the art. A chemical vapor deposition titanium nitride layer forms an ultra-thin physical vapor deposition titanium nitride layer with a multilayer barrier layer structure. Background of the invention:-In general, 'Semiconductor components with integrated circuit density increase and volume reduction' can significantly improve the speed of electrical operation and reduce the production cost of electronic products' is based on minimizing component size and high accumulation Degree has always been one of the most important development directions in the manufacture of integrated circuits. However, the miniaturization of the component size has prevented the surface of the wafer from providing enough area to make the required wire structure, and the demand for multilayer wire structures has become increasingly important. In addition, the development of new methods or new materials that are superior to traditional processes is also Issues that urgently need to be addressed today. Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs — — — — — _ ^ -------— Order · (Please read the notes on the back before filling this page) In the current integrated circuit manufacturing process, Both the traditional aluminum metal process and the newly developed copper metal process are facing ^ problem at the same time, which is the spike phenomenon generated between the metal and the silicon interface. The cause of the spike phenomenon is: when the metal When (aluminum or copper) is deposited on the sand surface, and the temperature is higher than the mutual solubility temperature of the two, silicon has a solid solubility for the metal, and the silicon will enter the metal layer by the diffusion effect. The metal will also return to the legacy left by the diffusion. The gap makes the interface between silicon and metal form spikes. If the length of these spikes is too long, it may cause a short circuit. One way to solve this problem is to add a barrier metal between the metal and the sand. (Barrier metal) material, and in the current metal trench manufacturing process of integrated circuits, usually a physical vapor deposition (Ph) is sequentially formed on a silicon substrate before the plug metal tungsten (W) is deposited. ysical Vapor Deposition; PVD) of titanium (Ti) metal layer 2 scales are applicable to China National Examination (CNS) A4 specifications (210 X 297 male β 4 2185 3 Department of five shellfish consumer B7 invention description >) and a chemical gas Phase deposited (Chemical Vapor Deposition; CVD) titanium nitride (TiN) layer, wherein the titanium nitride layer formed by CVD will have better step coverage, and the titanium metal layer has a high contact with silicon Resistance, however, when an organic titanium-containing reaction gas (such as: TDMAT (Tetrakis-Dimethylamino-Titanium; Ti- (N (CH3) 2) 4)) is selected to form the CVD-titanium nitride layer, The titanium nitride film formed by the cracking method is porous and often contains a large amount of carbon (C) and oxygen (0) impurities, which significantly affects its resistance. Although the subsequent treatment with N2 plasma can improve the CVD-nitriding The nature of the titanium layer reduces the content of C and O and its excessively high resistance. However, the plasma treatment still cannot completely eliminate the phenomenon that the CVD-titanium nitride layer absorbs moisture and oxidation in the atmosphere. As the time of exposure to the atmosphere increases, the Thallium will increase accordingly, and this phenomenon is called the aging effect of the nitride film. The phenomenon that the titanium nitride film is easy to absorb moisture and easy to oxidize will make it impossible to form a metal nucleation layer in the subsequent fabrication. A metal nucleation layer uniformly covering the CVD-titanium nitride layer will affect the subsequent metal trench process and the properties of the plug metal, so the invention provides a new metal barrier layer The manufacturing method is used to reduce the aging effect of the CVD-titanium nitride layer. Description of the invention: The main object of the present invention is to provide a method for manufacturing a metal barrier layer of an integrated circuit, so as to form a metal barrier layer having a relatively low and uniformly distributed resistance 値. The present invention uses the following steps to achieve the above-mentioned objects: first, a substrate having a dielectric layer formed on its surface is provided; then, a plurality of trenches are opened in the substrate; and then, sequentially deposited One PVD-titanium gold ----------- I — — — — — — I— (Please read the notes on the back before filling in the true) System 3 This paper size applies to Chinese National Standards (CNS) A4 specification (210 X 297 mm) 42185 3 A7 B7 Ministry of Smart Finance employees consume 20-dielectric layer 40-titanium metal layer 60-PVD titanium nitride layer V. Description of invention (>) Metal layer and a CYD-nitride Titanium layer; next is an important feature of the present invention. A PVD-ultra-thin titanium nitride layer is formed on the CVD-titanium nitride layer to form a stacked multi-layer barrier layer structure. Finally, sequentially Forming a copper metal nucleation layer and a plug metal layer, removing the plug metal layer, the copper metal nucleation layer, and the multi-layer barrier layer on the dielectric layer , Completed the production of metal trenches with PVD-ultra-thin titanium nitride layer. Brief description of the drawings: FIG. 1 is a cross-section of a PVD-titanium metal layer, a CVD-titanium nitride layer, and a PVD-ultra-thin nitride layer formed sequentially on a substrate with a trench in an embodiment of the present invention. schematic diagram. Fig. 2 is a graph showing the relative relationship between the exposure time of the wafer with and without the PVD-ultra-thin titanium nitride layer and the change in sheet resistance in the embodiment of the present invention. Description of drawing number: 10-substrate 30-trench 50-CVD titanium nitride layer A-sheet resistance change when only CVD titanium nitride layer is present B-sheet when CVD titanium nitride layer is covered with PVD titanium nitride layer Detailed description of the resistance change invention: The present invention relates to a method for manufacturing a metal barrier layer of an integrated circuit. Its main feature is to cover a conventional CVD-titanium nitride layer with an ultra-thin PVD-titanium nitride layer. The detailed process implementation steps are detailed below, and please also refer to the figure at the same time -------------- ^ -------- order --------- line ' (Please read the notes on the back before filling this page) _ The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) A7 4 2 ^ 85 3 V. Description of the invention (boxing) ---- -——---- I · 1 ---- Order. (谙 Please read the note on the back before filling in this page> First, a semiconductor substrate 10 is provided, and a dielectric layer has been formed on the substrate 10 20, and one or more trenches 30 are opened in the substrate 10 by lithography and non-uniform dry etching techniques, wherein the dielectric layer 20 is formed by chemical vapor deposition (Chem i ca 1 Vapor Depos it i on; CTD) formed silicon oxide structure or other low dielectric constant (lowk) materials. 〇 Next, physical vapor deposition (PVD) and chemical vapor deposition (CVD) are sequentially used on the substrate 10 A PVD-titanium metal layer 40 and a CVD-titanium nitride layer 50 are deposited in the above-mentioned _30. Among them, the titanium nitride layer 50 selected by CVD is a thin film formed by a CVD deposition method and has a better step. Covering capability, and forming the titanium metal layer 40 can increase the contact resistance between the metal layer and the chip. The thickness of the PVD-titanium metal layer 40 is between 30A and 500A. The CVD-titanium nitride layer 50 The thickness is between 20A and 200 people. Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by a cooperative, which is an important feature of the present invention. It uses physical vapor deposition to form an ultra-thin titanium nitride layer 60. On the CVD-titanium nitride layer 50, the PVD-titanium nitride layer 60 is used to protect the CVD-titanium nitride layer 50, especially the CVD-titanium nitride that protects the shoulders of the contact holes. The layer 50 reduces the area of the CVD-titanium nitride layer 50 in contact with the atmosphere, and reduces the aging effect of the CVD-titanium nitride layer 50. Wherein, the thickness of the PVD-titanium nitride layer 60 is between 30A and 300A. Finally, a metal nucleation layer is sequentially deposited by using a conventional method for manufacturing metal trenches and sequentially using a chemical vapor phase t-product method. layer) on the PVD-titanium nitride layer, and a plug metal layer is deposited to fill the trench 30, wherein the material of the metal nucleation layer and the plug metal layer is both Tungsten (W) metal; then, chemical mechanical honing method (chemical mechanical I ____: _ This paper size applies to China National Standard (CNS) A4 specification (210 x 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2185 3 A7 ___B7____________ 5. Description of the invention (丨) *
Polish; CMP)硏磨移除所述介電層20上之所述插塞金屬層、 所述金屬成核層、所述PVD-氮化鈦層60、所述CVD-氮化鈦 層50及所述鈦金屬層40，完成一具有PVD-TiN/CVD-TiN之 複層金屬阻障層的溝塡製作。 上述之製程步驟係利用一超薄之PVD-氮化鈦層60覆蓋 於所述CVD-氮化鈦阻障層50上，其用意在於：當利用有機 的含鈦反應氣體爲CVD沉積方法的前驅物時，經由熱裂解 方式形成的所述CVD-氮化鈦層50具有多孔性且常含有大量 會明顯影響電阻値的碳（C)及氧（Ο)雜質，雖然後續經 過％電漿進行處理，可降低所述CVD-氮化鈦層50中C、0含 量及其過高的電阻値，但所述\電漿處理仍無法完全消弭所 述CVD-氮化鈦層50在大氣下吸收水氣及氧化的現象，所述 反應將使得所述CVD-氮化鈦層50的電阻値隨著暴露在大氣 中的時間增加而隨之增加，即爲一般所說的老化效應（aging effect)。此外，所述CVD-氮化鈦阻障層中C、0的存在及過 高的電阻値，將使得後續金屬成核層的薄膜均勻性不佳，並 導致插塞金屬層充塡度差，造成金屬層導電性及抗電子遷移 能力不佳，而且所述插塞金屬層亦容易因後續之CMP回蝕 亥[1處理或化學之濕式處理而被侵鈾破壞產生凹陷、孔洞或斷 裂等問題，影響到元件可靠度及產品的良率，是以本發明於 所述CVD-氮化鈦層50上覆蓋一超薄之PVD-氮化鈦層60，目 的在於因爲PVD沉積法形成之薄膜沒有如CVD沉積法形成 之薄膜易吸濕及易氧化的現象，故利用本發明所述之PVD-超薄氮化鈦層60來覆蓋所述CVD-氮化鈦層50，主要在保護 6 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) (請先Μ讀背面之注意事項再填寫本頁) 裝--------訂---------^! 經濟部智慧財產局員工消费合作社印製 4 2 18 5 3 A7 ____B7__ 五、發明說明（t ) 住接觸洞孔肩部之所述CVD-氮化鈦層50，減少此位置與大 氣接觸之面積，降低晶片於大氣中阻値隨時間增加而增加之 老化效應，並提昇插塞金屬層之充塡度與均勻性，避免上述 凹陷、孔洞或斷裂等問題。所述PVD-超薄氮化鈦層60抑制 電阻値增高的效果可參考圖二所示，圖二係爲金屬溝塡製作 時有、無沉積所述PVD-超薄氮化鈦層60之晶片其暴露於大 氣中之時間與片電阻（sheet resistance; Rs)變化量之相對關 係圖，其中橫軸表示暴露於大氣中之時間，縱軸表示片電阻 之變化量（Rs(t)/ Rs(0))，即在時間⑴時之片電阻値（Rs(t)) 相較起始（t=0)之片電阻値（Rs⑼）的比値。圖二中之曲 線A即爲僅具CVD-氮化鈦阻障層50時片電阻隨時間增加之 變化量，曲線B則爲覆蓋有一超薄之PVD-氮化鈦層60時片電 阻隨時間增加之變化量，由此圖可看出所述PVD-氮化鈦層60 的存在可有效抑制所述CVD-氮化鈦層50至少60%以上的老 化速度’可避免導電性、抗電子遷移能力不佳及界面氧化、 吸濕等問題，提局產品的良率與兀件的電性及可靠度。 利用本發明製作積體電路之金屬阻障層的方法具有下列 的優點： 1.本發明係在積體電路中金屬溝塡製作時提供一具較 低且均勻分佈的電阻値之CVD_金屬阻障層。 Z本發明係在積體電路中之金屬溝塡製作時提供金屬 成核層一較佳的成長環境。 3·本發明係在積體電路中之金屬溝塡製作時提供一結 構較佳之插塞金屬層。 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <請先閲讀背面之注意事項再填寫本頁) 裝--------訂---------峻 4 2 ^ δ5 3 五、發明說明（/ ) 4.本發明可避免插塞金屬因侵蝕破壞而產生四陷 '孔 洞或斷裂等的問題，而影響到元件的可靠度'電1性 及產品良率。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，因此熟知此技藝的人士應能明瞭，適當而作 些微的改變與調整，仍將不失本發明之要義所在，亦不脫離 本發明之精神和範圍，故都應視爲本發明的進一步實施狀 況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Polish; CMP) honing to remove the plug metal layer, the metal nucleation layer, the PVD-titanium nitride layer 60, the CVD-titanium nitride layer 50, and the dielectric layer 20 The titanium metal layer 40 completes the trench fabrication of a multi-layer metal barrier layer with PVD-TiN / CVD-TiN. The above process steps are covered with an ultra-thin PVD-titanium nitride layer 60 on the CVD-titanium nitride barrier layer 50. The purpose is to use an organic titanium-containing reaction gas as a precursor of the CVD deposition method. The CVD-titanium nitride layer 50 formed by thermal cracking has porosity and often contains a large amount of carbon (C) and oxygen (0) impurities that significantly affect the resistance 値, although it is subsequently processed by% plasma. Can reduce the content of C and 0 in the CVD-titanium nitride layer 50 and its excessively high resistance, but the plasma treatment still cannot completely eliminate the CVD-titanium nitride layer 50 absorbing water in the atmosphere Gas and oxidation phenomena, the reaction will make the resistance of the CVD-titanium nitride layer 50 increase with the increase of time exposed to the atmosphere, which is generally known as the aging effect. In addition, the presence of C and 0 in the CVD-titanium nitride barrier layer and an excessively high resistance 値 will make the film uniformity of the subsequent metal nucleation layer poor, and lead to poor filling of the plug metal layer. Causes poor conductivity of the metal layer and the ability to resist electron migration, and the plug metal layer is also easily damaged by uranium invasion due to subsequent CMP etchback [1 treatment or chemical wet treatment, resulting in depressions, holes or fractures, etc. The problem affects the reliability of the device and the yield of the product. The CVD-titanium nitride layer 50 is covered with an ultra-thin PVD-titanium nitride layer 60 according to the present invention. The purpose is to form a thin film formed by the PVD deposition method. There is no phenomenon that the thin film formed by the CVD deposition method is easy to absorb moisture and oxidize. Therefore, the PVD-ultra-thin titanium nitride layer 60 described in the present invention is used to cover the CVD-titanium nitride layer 50, which is mainly used for protection. Paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Loading -------- Order -------- -^! Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2 18 5 3 A7 ____B7__ V. Description of the Invention (t) Living in a contact hole The CVD-titanium nitride layer 50 on the shoulder reduces the area in contact with the atmosphere at this position, reduces the aging effect of the chip's resistance in the atmosphere and increases with time, and improves the filling and uniformity of the plug metal layer. To avoid the above-mentioned problems such as depressions, holes or fractures. The effect of the PVD-ultra-thin titanium nitride layer 60 on suppressing the increase in resistance can be referred to FIG. 2. FIG. 2 is a wafer with or without deposition of the PVD-ultra-thin titanium nitride layer 60 during metal trench production. The graph of the relative relationship between the time of exposure to the atmosphere and the change in sheet resistance (Rs), where the horizontal axis represents the time of exposure to the atmosphere, and the vertical axis represents the change in sheet resistance (Rs (t) / Rs ( 0)), which is the ratio 片 of the sheet resistance 値 (Rs (t)) to the initial sheet resistance 値 (Rs⑼) at time ⑼. The curve A in Figure 2 is the change of the sheet resistance with time when only the CVD-titanium nitride barrier layer 50 is provided, and the curve B is the sheet resistance with time when it is covered with an ultra-thin PVD-titanium nitride layer 60. The amount of change is increased. From this figure, it can be seen that the presence of the PVD-titanium nitride layer 60 can effectively inhibit the aging speed of the CVD-titanium nitride layer 50 by at least 60% or more. Poor capacity and interfacial oxidation, moisture absorption and other issues, improve the yield of the product and the electrical and reliability of the components. The method for manufacturing the metal barrier layer of the integrated circuit by using the present invention has the following advantages: 1. The present invention provides a CVD_metal resistance with a lower and uniform distribution of resistance when the metal trench in the integrated circuit is manufactured. Barrier. Z The present invention provides a better growth environment for the metal nucleation layer when manufacturing metal trenches in integrated circuits. 3. The present invention provides a plug metal layer having a better structure when a metal trench in an integrated circuit is manufactured. 7 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) < Please read the notes on the back before filling this page) --- Jun 4 2 ^ δ5 3 V. Description of the invention (/) 4. The invention can avoid the problem of plugging holes or fractures caused by the plug metal due to erosion and damage, and affect the reliability of the component. And product yield. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should be able to understand that making appropriate changes and adjustments will still not lose the essence of the present invention. Without departing from the spirit and scope of the present invention, it should be regarded as a further implementation status of the present invention. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm)