TW521315B - Method for fabricating a semiconductor epitaxial wafer having doped carbon - Google Patents

Method for fabricating a semiconductor epitaxial wafer having doped carbon Download PDF

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TW521315B
TW521315B TW090133289A TW90133289A TW521315B TW 521315 B TW521315 B TW 521315B TW 090133289 A TW090133289 A TW 090133289A TW 90133289 A TW90133289 A TW 90133289A TW 521315 B TW521315 B TW 521315B
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silicon
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Seung-Ho Pyi
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B13/00—Single-crystal growth by zone-melting; Refining by zone-melting
    • C30B13/08—Single-crystal growth by zone-melting; Refining by zone-melting adding crystallising materials or reactants forming it in situ to the molten zone
    • C30B13/10—Single-crystal growth by zone-melting; Refining by zone-melting adding crystallising materials or reactants forming it in situ to the molten zone with addition of doping materials
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/02—Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt
    • C30B15/04—Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n-p-junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Description

521315 修正 _案號 90133289 五、發明說明（1) <發明之範圍> 、 本發明以一般而言係關於一種半導體磊晶圓之製備方 法。尤其是本發明係關於一種製備半導體磊晶圓的方法，其 中矽基板係藉一起熔解聚矽與碳短塊來滲雜碳，因此有效控 制有細縫的矽並影響元件的主動區而因此可製成很大規模的 積體半導體元件。 ' <發明 通常 注入離子 的矽在後 在矽空隙 短通道電 成元件特 這些 法，其中 近收集方 散，但不 力口0 晶圓的 時無論 續的熱 内形成 晶體内 性的變 問題如 注入碳 法可有 幸，碳 > 製備過程 如何會產 處理步驟 深陷阱。 的反向短 差，如節 要解決， 於通道範 效的利用 原子會形 必須經 生大量 中引起 加之硼 通道效 點茂漏 傳統技 圍内來 注入的 成另一 過離子注入步驟，矽結晶内 的有細縫的矽。這種有細縫 過渡性增強的硼擴散，同時 的過渡性增強擴散往往造成 應，另一方面深陷阱水準造 電流。 術中曾經採用鄰近收集方 吸收有細縫的石夕。雖然此鄰 碳來抑制硼的過渡性增強擴 種陷阱造成節點漏電流的增 <發明之總論> 本發明之目 法，其能抑制由 電流。 的之一在提供一種半導體磊晶圓的製備方 於滲入之碳形成的陷阱水準引起的節點洩 漏 本發日月> q 法，其能雜V Λ、一目的在提供一種半導體磊晶圓的製備戈 曰 > 成更多的本態性收集區域而改善本態性收負
第4頁 521315 五、發明說明（2) 效應。 這些本發明的目的可藉滲雜碳的半導體磊晶圓的製備 方法來達成，該方法包括的步驟有：提供含碳的矽，從含 碳的矽成長一鑄錠，將鑄錠切成細片來形成含碳的矽晶 圓，及成長一磊矽層於含碳之矽晶圓表面上。 依照本發明之另一形態，其滲雜碳的半導體磊晶圓的 製備方法包括的步驟有：混合一個碳塊與一個矽塊然後一 同熔解，從熔解的含有碳的矽成長一鑄錠，研磨含有碳的 鑄錠以便生成一平坦表面與一凹痕，將含有碳的鑄錠切成 石夕晶圓的細片’研磨含有石炭的石夕晶圓片’及成長一蠢晶石夕 層於已研磨的含碳矽晶圓的表面上。 依照本發明之另一形態，其提供的半導體磊晶圓包括 含有一個碳塊的一個矽塊；從含有碳的矽形成的一鑄錠； 藉將鑄錠切成細片所得複數的粗晶圓所成含碳的矽晶圓； 及一形成於各含碳矽晶圓表面上的磊矽層。 <較佳具體實施例之詳細描述> 下文中參照附圖詳細描述本發明之内容，其中說明本 發明實施例之各步驟。本發明可以有很多不同的實施方 式，所以不能只限定以下文說明之實施例而已，無寧說這 些實施例之提供可有助於對本發明之澈底而完全之瞭解， 可對熟習與此方面技術之人士傳達本發明之精神。 如第1圖所示，坩堝1 0中含有一矽晶塊準備形成一矽 晶圓。另外，一個碳塊3混入於坩堝1 0中與矽晶塊一起。 此混合的矽塊1與碳塊3然後經加熱至混合物達於熔融液狀
第5頁 叫315 五、發明說明（3) 矽4的狀態，如第2圖。碳的熔融液狀矽4中的滲 好約為1 X 1 014至5 X 1 017原子/cm3 〇 “又取 此後’參照第3圖’以所須觸動用的種晶5 九石夕4的上部纟面然後緩慢提高，—方面種晶5與掛禍1〇 =
相反方向回轉。其中的滲有碳的矽鑄錠7於H 結構。如此的晶體成長法乃眾所知乘纟 '疋上马早晶 〜，而稱為
Czochralski法。另外的晶體成長法，如浮動區域法 (Floating Zone Method) ’亦可以使用。鑄錠7中的氧濃 度最好控制在8至1 3 p p m a間的水準（p a r + / · Ί Ί . ^ cirts/mi 1 1 ion atoms ) 〇 接著，滲有碳而以特定的方向成長的矽錠7施以研磨 3產i「平㈣表面與一一凹痕，然後用環氧樹脂繫固於 石^ ^次:如第4圖業已不意者，將石夕錠7切成複數的細 隹，；：包ΐ有滲雜碳的原始晶圓11。然後原始晶圓11更 進一步接受邊緣研磨過程。 2後I妝第5圖’滲碳的矽晶圓片1 1用研磨裝置3 0 磨過程。此外，陶統過程如粗磨、邊緣研 驗溶液中餘刻、加熱施體扼殺、a更細的研磨等 均可在表面研磨過程前後施行。 u晉ΐϊ合=磨的晶圓，如第6圖所示之一片滲碳晶圓 m ^ =田6、至内（未圖示）以便成長矽磊晶。參照第e :♦ 至1^ ‘观矽層13在經研磨晶圓11上成長至一既定 let疋獲侍了一滲有碳的半導體磊晶圓15。半導體磊 晶圓15的厚度最好控制在〇·5至5微米之間。
521315 五、發明說明（4) 如前文中業已充分說明，本發明的製備方法有如下述 之優點。由於滲碳矽晶圓上的磊矽層形成一元件在下一製 備步驟的主動區（不再在此進一步描述），某一深度的有細 縫矽與碳結合。由是，侵入於元件主動區的矽濃度可能相 當程度的減少。亦即本發明提供了依據使用磊矽晶圓的現 有優點外尚有依照滲雜碳的效果。特別是由於滲碳矽晶圓 具有較其他未滲碳矽晶圓很多的本態收集區，是以其本態 收集效應亦有改善。 在附圖與說明書中，曾揭示了本發明的較佳實施例， 雖然採用了特定項目，但係用以一般說明之目的而已，並 非做為限定性之目的，本發明的精神範圍，在所附申請專 利範圍中予以界定。
第7頁 521315 圖式簡單說明 第1圖為本發明的半導體磊晶圓的製備方法一實施例 步驟中將某些量的聚矽與碳一起放入坩堝中的示意圖。 第2圖為本發明的半導體磊晶圓的製備方法一實施例 中聚矽與碳熔解於坩堝中的示意圖。 第3圖為本發明的半導體磊晶圓的製備方法一實施例 中利用C ζ 〇 c h r a 1 s k i法生長滲雜碳的石夕鑄錠步驟的示意 圖。 第4圖為本發明的半導體磊晶圓的製備方法一實施例 中已經切成細片的原始滲有碳的晶圓的示意圖。 第5圖為本發明的半導體磊晶圓的製備方法一實施例 中表示研磨滲有碳的晶圓細片步驟的示意圖。 第6圖為本發明的半導體磊晶圓的製備方法一實施例 中表示生長一磊晶層於經研磨的滲有碳的晶圓上步驟的示 意圖。 <圖式中元件名稱與符號對照表> 矽晶塊 液狀矽 矽錠 3 :碳塊 10 :坩堝 5 ·種晶 11 :原始晶圓 15 ·蠢晶圓 3 0 :研磨裝置 13 :磊矽層
第8頁

Claims (1)

  1. 修正 曰 六 案號 90133289 申請專利範圍 將含有碳的該鑄錠切成矽晶圓的細片； 研磨含有碳的該矽晶圓片，及 、 成長一屋晶石夕層於該已研磨山 8·如申請專利範圍第7項法'奴石曰曰 ' 的表面上 的碳濃度係在1摩至5 原子/c/之中間3。於溶融石夕内 9 ·如申請專利範圍第7瑁 晶圓中的氧濃度係在8至13ppma之間。’、中β 3有叙的石夕 其中該晶圓的蠢石夕 其中該磊矽層係做 ，其中所述成長含碳 1〇·如申請專利範圍第7項之方 層厚度係在0· 5至5微米之間。 、11 ·如申請專利範圍第γ項之方沐 為元件主動區之用。 1上如申請專利範圍第7項之方法，纟中所述幻 二的，。chralski法或浮動區法完成之。 石夕晶圓包0入的明一專，5'圍f7項之方法，其中研磨該含碳的 研磨、萨=妗、、々w程係選自包含表面研磨、粗研磨、邊緣 諸過程中^ /谷液中蝕刻、加熱施體抑殺法、及細研磨等
    _
    第10頁
TW090133289A 2001-10-30 2001-12-31 Method for fabricating a semiconductor epitaxial wafer having doped carbon TW521315B (en)

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