TW518700B - Chip structure with bumps and the manufacturing method thereof - Google Patents
Chip structure with bumps and the manufacturing method thereof Download PDFInfo
- Publication number
- TW518700B TW518700B TW091100094A TW91100094A TW518700B TW 518700 B TW518700 B TW 518700B TW 091100094 A TW091100094 A TW 091100094A TW 91100094 A TW91100094 A TW 91100094A TW 518700 B TW518700 B TW 518700B
- Authority
- TW
- Taiwan
- Prior art keywords
- bump
- scope
- patent application
- wafer
- manufacturing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Chemically Coating (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
經濟部中央標準局負工消費合作社印裝 518700 8012twf.doc/009 五、發明説明(/ ) 本發明是有關於一種晶片上凸塊及其製造方法,且 特別是有關於一種改變凸塊之材質’使得可以簡化凸塊的 製作方法,進而降低成本。 在現今資訊爆炸的社會,電子產品遍佈於日常生活 中,無論在食衣住行育樂方面,都會用到積體電路元件所 組成的產品。隨著電子科技不斷地演進,功能性更複雜、 更人性化的產品推陳出新,就電子產品外觀而言,也朝向 輕、薄、短、小的趨勢設計,因此在半導體構裝技術上, 開發出許多高密度半導體封裝的形式。在一些封裝的製作 中,會在晶片上長出凸塊(bumP),以進行覆晶封裝(FliP chiP Package)或是貼帶載座封裝(Tape Carrier Package,TCP)。 就凸塊的形式而言’一般分爲兩種’ 一種係由錫鉛合金所 製成的凸塊,而另一種係由金所製成的凸塊,其製作方式 亦有所不同。接下來將敘述習知以金所製成的凸塊之製 程。 第1圖至第5圖繪示習知以金所製成的凸塊之製程 對應於凸塊部份之剖面放大示意圖。請先參照第1圖’首 先提供一晶片110,晶片110具有一主動表面112(active surface),而晶片110具有一保護層114(passivation)及多 個焊墊116(bonding pad)(僅繪示出其中的一個),位在主動 表面112上,並且保護層114暴露出焊墊116,晶片11G 可以透過焊墊116與外界電路(未繪示)電性連接。接下來 進行一製作球底金屬層(Under Bump Metal,UBM)之製程’ 先以濺鍍的方式將一阻障層120(barner layer)形成於晶片 3 -----—-- 本紙張尺度適用中國國家榡準(CNS ) A4規格(210X297公釐) ----------------tr------MW (請先閲讀背面之注意事項存填寫本頁) 經濟部中央標準局貝工消費合作社印装 518700 五、發明説明(^ ) 110之主動表面112上,而阻障層120會覆蓋焊墊116及 保護層114,阻障層的材質可以是鎢化鈦(TlW)等,其厚度 約爲數千埃;然後以電鑛或濺鍍的方式將一種子層130(seed layer)形成於阻障層12〇上,而種子層13〇的材質可以是 i ’而其厚度約爲一千埃左右,如此球底金屬層140便製 作完成,其中球底金屬層140係由阻障層120及種子層130 所組成。 請參照第2圖,接下來進行一微影(photolilthography) 製程’首先將一光阻150(photo resist)形成於種子層13〇 上’然後透過曝光、顯影等步驟,將一圖案(未繪示)轉移 至光阻15〇,使得光阻150形成多個開口 152(opening)(僅 繪示出其中的一個),而開口 152暴露出焊墊116。 請參照第3圖,接下來進行一製作凸塊(bump)製程, 以電鍍的方式塡入多個凸塊160(僅繪示出其中的一個)於 光阻150之開口 152中,其中凸塊160的材質係爲金。 請參照第3圖、第4圖,然後進行一除去光阻製程, 將光阻150從種子層130的表面去除。 請參照第4圖、第5圖,然後進行一蝕刻(etching) 製程,以蝕刻的方式將暴露於外的球底金屬層140去除。 然後進行回火(annealmg)之製程,可以讓凸塊160內含有 缺陷的金屬離子,進行分佈的重整以達到較穩定的狀態。 如上所述,其凸塊製程甚爲繁雜’相對地成本也較 高,就製程上而言甚不具效率性。 因此本發明的目的就是在提供一種凸塊及其製造方 4 ---------ΜΨ-------、tr------ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 518700 8012twf.doc/009 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明(々) 法,藉由改變凸塊的材質,大幅地縮減凸塊的製作過程, 相對地成本也較低。 爲達成本發明之上述和其他目的,提出一種具有凸 塊之晶片結構’其包括一晶片及至少一凸塊。而晶片具有 一主動表面及至少一焊墊,焊墊係位在主動表面上。而凸 塊係配置在焊墊上,且凸塊包括一過渡層、一凸塊主體及 一凸塊主體保護層。其中,過渡層位在焊墊上,而過渡層 之材質係爲鋅。凸塊主體係位在過渡層上,而凸塊主體的 材質係爲鎳。凸塊主體保護層係覆在凸塊主體上未與過渡 層接合之處,而凸塊主體保護層之材質係爲金。 爲達成本發明之上述和其他目的,提出一種具有凸 塊之晶片結構製造方法,其係先提供一晶片,而晶片具有 一主動表面及至少一焊墊,焊墊暴露出主動表面。然後進 行一活化製程,沉積一過渡層鋅在焊墊上。接下來,進行 一製作凸塊主體製程,以無電電鍍鎳的方式製作至少一凸 塊主體在過渡層上。最後,進行一製作凸塊主體保護層製 程,以無電電鍍金的方式製作一凸塊主體保護層覆在凸塊 主體上未與過渡層接合之處。 依照本發明的一較佳實施例,其中凸塊主體的材質 係爲鎳,而凸塊主體保護層的材質係爲金。另外,凸塊的 高度係介於5微米到10微米之間,而凸塊主體保護層的 厚度係介於1微米到3微米之間。此外,凸塊主體及凸塊 主體保護層均以無電電鍍的方式製作而成。 綜上所述,本發明的特徵係在於改變凸塊的材質’ 5 訂 I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家榡準(CNS ) A4規格(210Χ297公釐) 518700 經濟部中央標準局貝工消費合作社印裝 五、發明説明(今) 使得凸塊可以以較簡易的製程形成在晶片的焊墊上。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂,下文特舉一較佳實施例’並配合所附圖式,作 詳細說明如下: 圖式之簡單說明: 第1圖至第5圖繪示習知以金所製成的凸塊之製程 對應於凸塊部份之剖面放大示意圖。 第6圖、第7圖繪示依照本發明一較佳實施例的一 種凸塊製造方法對應於凸塊部份之剖面放大示意圖。 第8圖至第10圖繪示依照本發明另一較佳實施例 的一種凸塊製造方法對應於凸塊部份之剖面放大示意圖。 圖式之標示說明: 110、210、310 :晶片 112、212 :主動表面 114、214 :保護層 116、216、316 ·•焊墊 228、328 :過渡層 120 ··阻障層 130 :種子層 140 :球底金屬層 150、350 :光阻 152、352 ··開口 220 ' 320 :凸塊主體 6 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210Χ297公釐) 518700 A7 B7 8012twf.d〇c/°09 五、發明説明(G ) 230 :凸塊主體保護層 j6〇、240 :凸塊 (請先閲讀背面之注意事項再填寫本頁) %ΜΆ. 請參照第6圖、弟7圖,其繪示依照本發明一較佳 實施例的一種凸塊製造方法對應於凸塊部份之剖面放大示 意圖。請先參照第6圖,首先提供一晶片210,晶片210 具有一主動表面212,而晶片210還具有一保護層214及 多個焊墊216(僅繪示出其中的一個),其均位在晶片210 之主動表面212上’並且保護層214暴露出焊墊晶 片210可以透過焊墊216與外界電路(未繪示)電性連接。 經濟部中央標準局貝工消費合作社印製 接下來進行一製作凸塊製程,其包括先進行一製作 凸塊主體製程,然後再進行一製作凸塊主體保護層製程。 其中就製作凸塊主體製程而言,係以無電電鍍(electroless plating)的方式製作至少—凸塊主體220而與晶片210之焊 墊216電性接合。其係先進行一活化製程,而在進行活化 製程時,係將晶片210置放到具有鋅離子之溶液中,此時 鋅會沉積到晶片21〇之焊墊216上,而形成一過渡層228, 過渡層228的材質係爲鋅,由於鋅只是在無電電鍍鎳之前 作爲活化劑之用’因此鋅的沉積厚度不需太厚。接下來, 再進行一無電電鍍製程,將晶片210浸在具有鎳離子的溶 液中,而以無電電鍍的方式鍍上鎳,並且藉由活化劑鋅的 作用,鎳會沉積在鋅上,而形成凸塊主體220。而其可以 依照凸塊主體220所需的大小,來控制晶片浸在鎳離子溶 液中的時間。因此,凸塊主體220可以透過過渡層228而 7 本紙張尺度適用中國國家標隼(CNS ) A4現格(210 X 297公釐) 518700 經濟部中央標準局貝工消費合作社印裝 五、發明説明(u ) 與焊墊216接合,其中凸塊主體220材質係爲鎳。 請參照第7圖,然後進行一製作凸塊主體保護層製 程,以無電電鍍金的方式製作一凸塊主體保護層230覆在 凸塊主體220上未與過渡層228接合之處,其中凸塊主體 保護層230之材質係爲金,因此可以防止凸塊主體220(鎳) 的氧化,如此凸塊240便製作完成,其中凸塊240包括凸 塊主體220及凸塊主體保護層230,由於凸塊主體220的 材質係爲鎳,其硬度甚高,因此凸塊240的高度僅需5微 米〜微米便足夠用於貼帶載座封裝(TCP)的製程,而凸塊 主體保護層230的厚度係約介於1微米到3微米之間。 相較於習知技藝,如上所述之凸塊製程可以省去球 底金屬層的製作,亦無須微影製程及蝕刻表面製程,並且 不需以電鍍的方式製作凸塊,因此本發明之凸塊製程甚爲 簡便,且製作成本可以大幅降低。 請參照第8圖至第10圖,其繪示依照本發明另一 較佳實施例的一種凸塊製造方法對應於凸塊部份之剖面放 大示意圖。在前述的實施例中,晶片係直接以無電電鍍的 方式在焊墊上製作出凸塊主體,然而製作凸塊的製程還可 以加入一微影製程,使得可以控制凸塊的形狀。 請參照第8圖,在晶片310提供之後,便接著進行 微影製程,首先將一光阻350形成於晶片310上,然後透 過曝光、顯影等步驟,將一圖案(未繪示)轉移至光阻350, 使得光阻350形成多個開口 352(〇penmg)(僅繪示出其中的 一個),而開口 3 52暴露出焊墊3 16。接下來,進行活化製 8 ---------ii (請先閲讀背面之注意事項再填寫本頁) 訂· 本紙張尺度適用中國國家榡準(CNS ) A4規格(21〇><297公釐) 518700 經濟部中央標準局貝工消費合作社印裝 8〇l2twf. doc / 009 _____B7五、發明説明(V^ ) 程,使得一過渡層328鋅可以覆蓋在晶片310之焊墊316 上。然後再進行無電電鍍的方式,使得凸塊主體320鎳會 形成在開口 352內之過渡層328上。 請參照第8圖、第9圖,然後進行一除去光阻製程, 將光阻350從晶片310的表面去除。 請參照第10圖,最後,再進行一製作凸塊主體保 護層製程,以無電電鍍金的方式製作一凸塊主體保護層330 金,而覆蓋在凸塊主體320上未與過渡層32S接合之處。 請參照第8圖,在上述的製程中,由於凸塊主體32〇 係形成在開口 352內,因此可以藉由控制開口 352的形狀 來控制凸塊主體320形成的形狀,並且藉由上述的製程’ 凸塊主體320可以做得較高。 綜上所述,本發明之凸塊及其製程’係藉由改變凸 塊的材質,可以大幅地縮減凸塊的製作過程’相對地成本 也較低。 雖然本發明已以一較佳實施例揭露如上’然其並非 用以限定本發明,任何熟習此技藝者,在不脫離本發明之 精神和範圍內,當可作些許之更動與潤飾’因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) 訂 9 本紙張尺度適用中國國家榡準(CNS ) A4说格(210X297公釐)
Claims (1)
- 經濟部中央標準局員工消費合作社印製 518700 六、申請專利範圍 1. 一種具有凸塊之晶片結構,包括: 一晶片,具有一主動表面,而該晶片還具有至少一 焊墊,位在該主動表面上;以及 至少一凸塊,該凸塊係配置在該焊墊上,該凸塊包 括: 一過渡層,該過渡層位在該焊墊上,而該過渡層之 材質包括鋅, 一凸塊主體,位在該過渡層,而該凸塊主體的材質 包括鎳,以及 一凸塊主體保護層,覆在該凸塊主體上未與該過渡 層接合之處,而該凸塊主體保護層之材質包括金。 2. 如申請專利範圍第1項所述之具有凸塊之晶片結 構,其中該凸塊的高度係介於5微米到1Q微米之間。 3. 如申請專利範圍第1項所述之具有凸塊之晶片結 構,其中該凸塊主體保護層的厚度係介於1微米到3微米 之間。 4. 一種凸塊,適於配置在一晶片上,該晶片具有一 主動表面及至少一焊墊,該焊墊暴露出該主動表面,而該 凸塊至少包括: 一過渡層,該過渡層位在該焊墊上;以及 一凸塊主體,位在該過渡層上,其中該凸塊主體的 材質包括鎳。 5. 如申請專利範圍第4項所述之凸塊,其中該凸塊 還包括一凸塊主體保護層,覆在該凸塊主體上未與該過渡 10 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐〉 (請先閲讀背面之注意事項再填寫本頁)518700 A8 8012twf.doc/009 C8 D8 六、申請專利範圍 層接合之處。 6.如申請專利範圍第5項所述之凸塊,其中該凸塊 主體保護層之材質包括金。 (請先閲讀背面之注意事項再填寫本頁) 如申請專利範圍第5項所述之凸塊,其中該凸塊 主體保護層的厚度係介於1微米到3微米之間。 8. 如申請專利範圍第4項所述之凸塊,其中該凸塊 的高度係介於5微米到10微米之間。 9. 如申請專利範圍第4項所述之凸塊,其中該過渡 層之材質包括鋅。 10. —種凸塊,適於配置在一晶片上,該晶片具有一 主動表面及至少一焊墊,該焊墊暴露出該主動表面,而該 凸塊至少包括: 一過渡層,該過渡層位在該焊墊上,其中該過渡層 之材質包括鋅;以及 一凸塊主體,位在該過渡層上。 11. 如申請專利範圍第10項所述之凸塊,其中該凸 塊還包括一凸塊主體保護層,覆在該凸塊主體上未與該過 渡層接合之處。 經濟部中央標準局員工消費合作社印製 12. 如申請專利範圍第11項所述之凸塊,其中該凸 塊主體保護層之材質包括金。 13. 如申請專利範圍第11項所述之凸塊,其中該凸 塊主體保護層的厚度係介於1微米到3微米之間。 14. 如申請專利範圍第10項所述之凸塊,其中該凸 塊的高度係介於5微米到10微米之間。 11 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X :297公釐) 518700 六、申請專利範圍 15. 如申請專利範圍第10項所述之凸塊,其中該凸 塊主體之材質包括鎳。 16. —種具有凸塊之晶片結構製造方法,包括: 提供一晶片,該晶片具有一主動表面,而該晶片還 具有至少一焊墊,該焊墊暴露出該主動表面; 進行一活化製程,沉積一過渡層在該焊墊上; 進行一製作凸塊主體製程,以無電電鍍的方式製作 至少一凸塊主體在該過渡層上;以及 進行一製作凸塊主體保護層製程,以無電電鍍的方 式製作一凸塊主體保護層覆在該凸塊主體上未與該過渡層 接合之處。 17. 如申請專利範圍第16項所述之具有凸塊之晶片 結構製造方法,其中該凸塊主體的材質係爲鎳。 18. 如申請專利範圍第16項所述之具有凸塊之晶片 結構製造方法,其中該凸塊主體保護層的材質係爲金。 19. 如申請專利範圍第16項所述之具有凸塊之晶片 結構製造方法,其中該過渡層的材質係爲鋅。 20. —種具有凸塊之晶片結構製造方法,包括: 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 提供一晶片,該晶片具有一主動表面,而該晶片還 具有至少一焊墊,該焊墊暴露出該主動表面; 進行一微影製程,形成一光阻在該晶片上,該光阻 具有至少一開口,該開口暴露出該焊墊; 進行一活化製程,沉積一過渡層在該焊墊上; 進行一製作凸塊主體製程,以無電電鍍的方式製作 12 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 經濟部中央標準局員工消費合作社印製 518700 々、申請專利範圍 至少一凸塊主體於該過渡層上,且該凸塊主體位在該開口 中; 進行一去除光阻製程,將該光阻從該晶片上去除; 以及 進行一製作凸塊主體保護層製程,以無電電鍍的方 式製作一凸塊主體保護層覆在該凸塊主體上未與該過渡層 接合之處。 21. 如申請專利範圍第20項所述之具有凸塊之晶片 結構製造方法,其中該凸塊主體的材質係爲鎳。 22. 如申請專利範圍第20項所述之具有凸塊之晶片 結構製造方法,其中該凸塊主體保護層的材質係爲金。 23. 如申請專利範圍第20項所述之具有凸塊之晶片 結構製造方法,其中該過渡層的材質係爲鋅。 24. —種凸塊製造方法,該凸塊係配置在一晶片上, 而該晶片具有一主動表面及至少一焊墊,該焊墊暴露出該 主動表面,該凸塊之製造方法包括: 進行一活化製程,沉積一過渡層在該焊墊上;以及 進行一製作凸塊主體製程,以無電電鍍的方式製作 至少一凸塊主體在該過渡層上。 25. 如申請專利範圍第24項所述之凸塊製造方法, 其中該凸塊主體的材質係爲鎳。 26. 如申請專利範圍第24項所述之凸塊製造方法, 其中該過渡層的材質係爲鋅。 27. 如申請專利範圍第24項所述之凸塊製造方法, 13 (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 518700 8012twf.doc/00 A8 B8 C8 D8 六、申請專利範圍 其中在進行該製作凸塊主體製程之後,還包括進行一製作 凸塊主體保護層製程,其係以無電電鍍的方式製作一凸塊 主體保護層覆在該凸塊主體上未與該過渡層接合之處。 28·如申請專利範圍第27項所述之凸塊製造方法, 其中該凸塊主體保護層的材質係爲金。 29. —種凸塊製造方法,該凸塊係配置在一晶片上, 而該晶片具有一主動表面及至少一焊墊,該焊墊暴露出該 主動表面,該凸塊之製造方法包括: 進行一微影製程,形成一光阻在該晶片上,該光阻 具有至少一開口,該開口暴露出該焊墊; 進行一活化製程,沉積一過渡層在該焊墊上; 進行一製作凸塊主體製程,以無電電鍍的方式製作 至少一凸塊主體於該過渡層上,且該凸塊主體位在該開口 中;以及 進行一去除光阻製程,將該光阻從該晶片上去除。 30. 如申請專利範圍第29項所述之凸塊製造方法, 其中該凸塊主體的材質係爲鎳。 31. 如申請專利範圍第29項所述之凸塊製造方法, 其中該過渡層的材質係爲鋅。 經濟部中央標準局員工消費合作社印裝 (請先閲讀背面之注意事項再填寫本頁) 訂 32·如申請專利範圍第29項所述之凸塊製造方法, 其中在進行該去除光阻製程之後,還包括進行一製作凸塊 主體保護層製程,其係以無電電鍍的方式製作一凸塊主體 保護層覆在該凸塊主體上未與該過渡層接合之處。 33.如申請專利範圍第32項所述之凸塊製造方法, 其中該凸塊主體保護層的材質係爲金。 14 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公嫠)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW091100094A TW518700B (en) | 2002-01-07 | 2002-01-07 | Chip structure with bumps and the manufacturing method thereof |
US10/065,632 US6812124B2 (en) | 2002-01-07 | 2002-11-05 | Chip structure with bumps and a process for fabricating the same |
US10/711,444 US20050023678A1 (en) | 2002-01-07 | 2004-09-20 | Chip structure with bumps and a process for fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW091100094A TW518700B (en) | 2002-01-07 | 2002-01-07 | Chip structure with bumps and the manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
TW518700B true TW518700B (en) | 2003-01-21 |
Family
ID=21688168
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091100094A TW518700B (en) | 2002-01-07 | 2002-01-07 | Chip structure with bumps and the manufacturing method thereof |
Country Status (2)
Country | Link |
---|---|
US (2) | US6812124B2 (zh) |
TW (1) | TW518700B (zh) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7960269B2 (en) | 2005-07-22 | 2011-06-14 | Megica Corporation | Method for forming a double embossing structure |
US7964973B2 (en) | 2004-08-12 | 2011-06-21 | Megica Corporation | Chip structure |
US8022544B2 (en) | 2004-07-09 | 2011-09-20 | Megica Corporation | Chip structure |
US8198729B2 (en) | 2004-07-16 | 2012-06-12 | Megica Corporation | Connection between a semiconductor chip and a circuit component with a large contact area |
CN103107156A (zh) * | 2011-11-11 | 2013-05-15 | 讯忆科技股份有限公司 | 晶圆焊垫的凸块结构及其制造方法 |
US8581404B2 (en) | 2004-07-09 | 2013-11-12 | Megit Acquistion Corp. | Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures |
TWI469288B (zh) * | 2009-06-11 | 2015-01-11 | Chipbond Technology Corp | 凸塊化晶片結構及其應用之半導體覆晶裝置 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003203940A (ja) * | 2001-10-25 | 2003-07-18 | Seiko Epson Corp | 半導体チップ及び配線基板並びにこれらの製造方法、半導体ウエハ、半導体装置、回路基板並びに電子機器 |
JP2005191541A (ja) * | 2003-12-05 | 2005-07-14 | Seiko Epson Corp | 半導体装置、半導体チップ、半導体装置の製造方法及び電子機器 |
US20070267745A1 (en) * | 2006-05-22 | 2007-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including electrically conductive bump and method of manufacturing the same |
TWI447870B (zh) * | 2008-02-20 | 2014-08-01 | Chipmos Technologies Inc | 用於一半導體積體電路之導電結構 |
DE102008042107A1 (de) * | 2008-09-15 | 2010-03-18 | Robert Bosch Gmbh | Elektronisches Bauteil sowie Verfahren zu seiner Herstellung |
TWM397591U (en) * | 2010-04-22 | 2011-02-01 | Mao Bang Electronic Co Ltd | Bumping structure |
CN103515341B (zh) * | 2012-06-20 | 2016-12-21 | 讯忆科技股份有限公司 | 晶圆焊垫的化镀镍凸块结构及其制造方法 |
CN103531571B (zh) * | 2012-07-05 | 2016-09-28 | 讯忆科技股份有限公司 | 晶圆焊垫的化镀镍凸块结构及其制造方法 |
US20150235978A1 (en) * | 2012-07-05 | 2015-08-20 | Aflash Technology Co., Ltd. | Electroless nickel bump of die pad and manufacturing method thereof |
US9646951B2 (en) * | 2013-12-10 | 2017-05-09 | Semiconductor Components Industries, Llc | Method of forming a semiconductor device and structure therefor |
US9865565B2 (en) | 2015-12-08 | 2018-01-09 | Amkor Technology, Inc. | Transient interface gradient bonding for metal bonds |
US10037957B2 (en) | 2016-11-14 | 2018-07-31 | Amkor Technology, Inc. | Semiconductor device and method of manufacturing thereof |
US11121076B2 (en) * | 2019-06-27 | 2021-09-14 | Texas Instruments Incorporated | Semiconductor die with conversion coating |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
KR100298828B1 (ko) * | 1999-07-12 | 2001-11-01 | 윤종용 | 재배선 필름과 솔더 접합을 이용한 웨이퍼 레벨 칩 스케일 패키지 제조방법 |
US6570251B1 (en) * | 1999-09-02 | 2003-05-27 | Micron Technology, Inc. | Under bump metalization pad and solder bump connections |
JP4656275B2 (ja) * | 2001-01-15 | 2011-03-23 | 日本電気株式会社 | 半導体装置の製造方法 |
TW498510B (en) * | 2001-06-05 | 2002-08-11 | Chipbond Technology Corp | Metallized surface wafer level package structure |
US6413851B1 (en) * | 2001-06-12 | 2002-07-02 | Advanced Interconnect Technology, Ltd. | Method of fabrication of barrier cap for under bump metal |
US6737353B2 (en) * | 2001-06-19 | 2004-05-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having bump electrodes |
-
2002
- 2002-01-07 TW TW091100094A patent/TW518700B/zh not_active IP Right Cessation
- 2002-11-05 US US10/065,632 patent/US6812124B2/en not_active Expired - Lifetime
-
2004
- 2004-09-20 US US10/711,444 patent/US20050023678A1/en not_active Abandoned
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8022544B2 (en) | 2004-07-09 | 2011-09-20 | Megica Corporation | Chip structure |
US8519552B2 (en) | 2004-07-09 | 2013-08-27 | Megica Corporation | Chip structure |
US8581404B2 (en) | 2004-07-09 | 2013-11-12 | Megit Acquistion Corp. | Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures |
US8198729B2 (en) | 2004-07-16 | 2012-06-12 | Megica Corporation | Connection between a semiconductor chip and a circuit component with a large contact area |
US7964973B2 (en) | 2004-08-12 | 2011-06-21 | Megica Corporation | Chip structure |
US7960269B2 (en) | 2005-07-22 | 2011-06-14 | Megica Corporation | Method for forming a double embossing structure |
TWI469288B (zh) * | 2009-06-11 | 2015-01-11 | Chipbond Technology Corp | 凸塊化晶片結構及其應用之半導體覆晶裝置 |
CN103107156A (zh) * | 2011-11-11 | 2013-05-15 | 讯忆科技股份有限公司 | 晶圆焊垫的凸块结构及其制造方法 |
CN103107156B (zh) * | 2011-11-11 | 2016-02-10 | 讯忆科技股份有限公司 | 晶圆焊垫的凸块结构及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20030127730A1 (en) | 2003-07-10 |
US6812124B2 (en) | 2004-11-02 |
US20050023678A1 (en) | 2005-02-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW518700B (en) | Chip structure with bumps and the manufacturing method thereof | |
TW508766B (en) | Semiconductor device | |
TWI252546B (en) | Bumping process and structure thereof | |
JP3050812B2 (ja) | 多層プリント配線板 | |
TW200303604A (en) | Semiconductor device and method of manufacturing the same | |
JPH07506217A (ja) | 製造された半導体ダイ上に電極の接続を形成する方法 | |
TW456013B (en) | Heat spreader substrate structure and the process thereof | |
TW465063B (en) | Semiconductor device and fabricating method therefor | |
TW200400591A (en) | High density raised stud microjoining system and methods of fabricating the same | |
TW488052B (en) | Manufacture process of bumps of double layers or more | |
TW441062B (en) | Carrier substrate for producing semiconductor device | |
JPH06132474A (ja) | 半導体装置 | |
JPH01226160A (ja) | 電子部品接続用の端子装置および端子の製造方法 | |
TW471146B (en) | Bump fabrication method | |
TW455965B (en) | Method for forming solder bumpers on IC package substrate and structure formed by the same | |
JPS636850A (ja) | 電子部品の製造方法 | |
TW515016B (en) | Flip chip and its manufacturing process | |
JP2007048887A (ja) | 半導体装置およびその製造方法 | |
TW498471B (en) | Manufacturing method for solder bump | |
TW495938B (en) | A mater-level package structure and a process for producing the same | |
JPS62282449A (ja) | はんだバンプの製造方法 | |
JPH03283378A (ja) | 電気的接続部材 | |
JPS6031245A (ja) | 半導体装置 | |
JPH03132036A (ja) | 半導体装置の製造方法 | |
TW510012B (en) | Wafer transportation process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MK4A | Expiration of patent term of an invention patent |