495938 A7 B7 五、發明說明（（） 發明領域 本發明係關於半導體封裝結構與製程，尤其係關於晶 圓級半導體的封裝結構與製程。 背景說明 在現今半導體裝置的製程中，由於裝置的積集度的上 升以及裝置體積的縮小，對於半導體封裝技術的要求也與 日倶增。傳統上，有許多種方法被用以降低封裝後的晶圓 尺寸。其中，覆晶（flip chip)技術是最常使用者。不採 用習知銲線（wire bond )接合1C上銲墊與導線線架（lead frame)的引腳，覆晶技術直接形成金屬凸塊陣列於晶粒的 表面上。金屬凸塊通常係以金、銅、鉛與錫等金屬材料或 其合金所構成。 爲了更有效利用晶粒表面的所有面積，這類的晶圓級 半導體封裝通常也牽涉到重佈層的使用。重佈層可以重新 分佈金屬凸塊的位置，而不限定其一定要在銲墊的正上 方。甚至可以使金屬凸塊排列成整齊的矩形陣列。 請參考圖1，爲先前技術的晶圓級半導體封裝結構示 意圖，其係在美國專利案案號6，197,613號中被提出，發 明人爲Ling-Chen Kung等人。晶圓101上具有一銲墊1〇2, 銲墊102爲晶圓101上晶粒的輸入/輸出端。銲墊1〇2上沉 積了一絕緣層103。絕緣層1〇3可以保護晶圓ι〇1不會受 到污染。絕緣層103並不完全遮蔽銲墊1〇2，而暴露出銲 4CHIPBOND200101TW, CBP-01-001 ι 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--- <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製495938 A7 B7 V. Description of the Invention (() Field of the Invention The present invention relates to semiconductor packaging structures and processes, especially to wafer-level semiconductor packaging structures and processes. Background In today's semiconductor device manufacturing processes, due to the accumulation of devices, The increase in the degree and shrinking of the device volume has increased the requirements for semiconductor packaging technology. Traditionally, there are many methods used to reduce the size of the wafer after packaging. Among them, flip chip technology is the most popular Common users. Instead of using conventional wire bonds to bond the pads on the 1C and the leads of the lead frame, the flip-chip technology directly forms an array of metal bumps on the surface of the die. Metal bumps Usually made of metal materials such as gold, copper, lead, and tin, or alloys thereof. In order to more effectively use the entire area of the die surface, such wafer-level semiconductor packages often involve the use of redistribution layers. Redistribution The layer can redistribute the positions of the metal bumps without limiting it to be directly above the pads. It can even arrange the metal bumps into a neat rectangular array. Referring to FIG. 1, a schematic diagram of a wafer-level semiconductor package structure of the prior art is proposed in US Patent No. 6,197,613, and the inventor is Ling-Chen Kung et al. The wafer 101 has a pad 10, the bonding pad 102 is an input / output terminal of the die on the wafer 101. An insulating layer 103 is deposited on the bonding pad 102. The insulating layer 103 can protect the wafer 010 from contamination. The insulation layer 103 does not completely shield the solder pad 102, but exposes the solder 4CHIPBOND200101TW, CBP-01-001 ι This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------ ----- Equipment --- < Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
495938 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（> ) 墊接觸面104。銲墊接觸面104上方具有一介層洞插塞 105，介層洞插塞1〇5係以導電物質如銅或鋁所形成。於形 成一介層洞插塞105之後，塗佈一層彈性材料並再進行回 蝕’以形成如圖1所示之彈性材料層106。完成彈性材料 層106後’再沉積一金屬導線層1〇7以作爲重佈層。金屬 導線層107完成後，沉積一介電層ι〇8於金屬導線層107 上’以作爲絕緣之用。於欲形成凸塊處對介電層108進行 蝕刻’以暴露出金屬導線層107，之後形成一凸塊下金屬 109。最後，於凸塊下金屬109上，形成金屬凸塊uo。其 中’凸塊下金屬109可作爲與金屬凸塊的結合層以及金屬 防滲漏層。 先前技術之晶圓級封裝的特徵在於其使用了一彈性材 料層，如圖1中之彈性材料層106。此彈性材料層1〇6除 了可以作爲封裝製程中機械應力的緩衝層，對於熱膨脹也 有一定的吸收作用。 然而’先前技術中，與銲墊接觸的金屬係爲導電度高 的金屬所構成’這些金屬包含銅、鋁、銅合金、鋁合金與 銀。然而這些金屬或合金抗電磁干擾的能力都不佳。此外， 沉積方式產生的重佈層、凸塊下金屬的厚度無法有效提 高，導致結構脆弱，可靠度不足。 基於此，本發明提供一種改良的晶圓級半導體封裝結 構以及其製程，以解決前述現今晶圓級半導體封裝結構的 缺點。 4CHIPBOND200101TW, CBP-01-001 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 495938 A7 B7 五、發明說明（3 ) 摘要說明 於考慮沒有重佈層的情況時，本發明提供晶圓級半導 體封裝結構與製程。此晶圓級半導體封裝結構包括一晶 圓，晶圓上具有一銲墊。銲墊上具有一絕緣層，遮蔽此銲 墊之第一部份，銲墊的第二部分外露。此絕緣層上具有一 軟性高分子層。銲墊的第二部分上具有一第一金屬層，第 一金屬層與銲墊電氣接合。第一金屬層上具有一第二金屬 層，第二金屬層與第一金屬層電氣接合。第二金屬層上具 有一第三金屬層，第三金屬層該第二金屬層電氣接合。第 三金屬層上具有一金屬凸塊，此金屬凸塊與第三金屬層電 氣接合。 上述半導體封裝結構之製程如下。首先，提供一晶圓。 晶圓上之半導體裝置係已完成，且具有複數個輸入/輸出用 之銲墊。銲墊具有被絕緣層遮蔽之第一部份與未被遮蔽之 第二部分。沉積一絕緣層，並且於第二部分上方蝕刻一介 層洞，以暴露出第二部分。接著，本發明首先沉積一第一 金屬層，再沉積一第二金屬層，最後再以電鍍方式形成一 第三金屬層於沉積的第二金屬層上方，以形成一凸塊下金 屬。然後，以迴銲方式形成一金屬凸塊於凸塊下金屬上。 另一方面，於有重佈層存在時，本發明提供晶圓級封 裝結構與製程。此晶圓級半導體封裝結構包括一晶圓，晶 圓上具有一銲墊。銲墊上具有一絕緣層，此絕緣層遮蔽銲 墊之第一部份，銲墊的第二部分外露。此絕緣層上具有一 軟性高分子層。此晶圓級半導體封裝結構亦包括一重佈 4CHIPBOND200101TW, CBP-01-001 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 零-裝--------訂---------線* 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 495938 A7 B7 五、發明說明（今） 層。重佈層進一步包含一第一金屬連線層，其位於銲墊的 第二部分上，與銲墊電氣接合；一第二金屬連線層，其位 於第一金屬連線層上，與第一金屬連線層電氣接合；以及 一第三金屬連線層，其位於第二金屬連線層上，與第二金 屬連線層電氣接合。重佈層於遠離該銲墊的一端上，具有 一第一金屬層，此第一金屬層與第三金屬連線層電氣接 合。第一金屬層上具有一第二金屬層，第二金屬層與第一 金屬層電氣接合。第二金屬層上具有一第三金屬層，第三 金屬層與第二金屬層電氣接合。第三金屬層上具有一金屬 凸塊，此金屬凸塊與第三金屬層電氣接合。 上述晶圓級半導體封裝結構之製程如下。首先，提供 一晶圓。晶圓上之半導體裝置係已完成，且具有複數個輸 入/輸出用之銲墊。銲墊具有被絕緣層遮蔽之第一部份與未 被遮蔽之第二部分。沉積一第一絕緣層，並且於第二部分 上方蝕刻一第一介層洞，以暴露出第二部分。接著，本發 明首先沉積一第一金屬連線層，再沉積一第二金屬連線 層，最後再以電鍍方式形成一第三金屬連線層於沉積的第 二金屬連線層上方，以形成一重佈層。於重佈層再塗佈一 第二絕緣層，並在重佈層上方，遠離銲墊的一端之預定位 置上，以蝕刻方式形成一第二介層洞，以暴露出重佈層（第 三金屬連線層）。然後，沉積一第一金屬層，沉積一第二金 屬層，最後再以電鍍方式形成一第三金屬層於沉積的第二 金屬層上方，以形成與重佈層電器連接之凸塊下金屬。之 後，以迴銲方式形成一金屬凸塊於凸塊下金屬上。 4CHIPBOND200101TW, CBP-01-001 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 495938 A7 B7 五、發明說明（^ ) 其中第一金屬層與第一金屬連線層較佳係爲以濺鍍方 式沉積的Ml層。第二金屬層與第二金屬連線層較佳係爲 以濺鍍方式沉積的M2層。而第三金屬層與第三金屬連線 層較佳係爲以電鍍方式形成的M3層。其中Ml係爲選自 鈦、鎳、鉻、鉬、鈦鎢合金以及鉅鎢合金的金屬，M2係 爲選自銅、鉻銅合金、鎳銅合金以及鈦銅合金的金屬，而 M3係爲選自銅、鎳與金的金屬。 圖式之簡單說明 圖1揭露先前技術之晶圓級半導體封裝結構； 圖2揭露依照本發明晶圓級半導體封裝結構之第一實 施例； 圖3揭露依照本發明之晶圓級半導體封裝結構之第二 實施例； 圖4a揭露依據本發明第一實施例之具有複數個銲墊 之晶圓的剖面圖； 圖4b揭露圖4a中的晶圓塗佈軟性局分子層並進彳了第 一次光罩製程後之示意圖； 圖4c揭露圖4b中的晶圓經過軟性高分子材料顯影與 固化後的示意圖； 圖4d揭露圖4c中的晶圓先後經過Ml與M2沉積後 的示意圖； 圖4e揭露圖4d中的晶圓經過光阻層塗佈並進行第二 次光罩製程後之示意圖； 4CHIPBOND200101TW, CBP-01-001 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 ----訂--------- A7 B7 五、發明說明（b ) 圖4f揭露圖4e中的晶圓經過顯影後之示意圖； 圖4g揭露圖4f中之晶圓經過M3與銲錫電鍍後之示 意圖； 圖4h揭露圖4g中之晶圓上之光阻層移除後之示意 圖； 圖41揭露圖4h中之晶圓經過Ml以及M2的蝕刻後之 示意圖； 圖4j揭露圖4i中之晶圓經過迴銲後之示意圖； 圖5a揭露依據本發明第二實施例之具有複數個銲墊 之晶圓的剖面圖； 圖5b揭露圖5a中的晶圓塗佈軟性高分子層並進行第 一次光罩製程後之示意圖； 圖5c揭露圖5b中的晶圓經過軟性高分子層顯影與固 化後的示意圖； 圖5d揭露圖5c中的晶圓先後經過Ml與M2沉積後 的示意圖； 圖5e揭露圖5d中的晶圓經過光阻層塗佈並進行第二 次光罩製程後之示意圖； 圖5f揭露圖5e中之晶圓經過M3電鍍後之示意圖； 圖5g揭露圖5f中之晶圓上光阻層被移除並進行Ml 與M2的蝕刻後之示意圖； 圖5h揭露圖5g中的晶圓塗佈軟性高分子層並進行第 三次光罩製程後之示意圖； 圖5i揭露圖5h中的晶圓經過軟性高分子層顯影與固 4CHIPBOND200101TW, CBP-01-001 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注咅2事項再填寫本頁) 产裝--------訂---------線泰 經濟部智慧財產局員工消費合作社印製 495938 A7 _B7五、發明說明Ο ) 化後的示意圖； 圖5j揭露圖5i中的晶圓先後經過Ml與M2沉積後的 示意圖； 圖5k揭露圖5j中的晶圓經過光阻層塗佈並進行第四 次光罩製程後之示意圖； 圖51揭露圖5k中的晶圓經過光阻層顯影後的示意 圖； 圖5m揭露圖51中之晶圓經過M3與銲錫電鍍後之示 意圖； 圖5n揭露圖5m中之晶圓上光阻層移除後之示意圖； 圖5〇揭露圖5n之晶圓經過Ml與M2的蝕刻後之示 意圖；以及 圖5P揭露圖5〇中之晶圓經過迴銲後之示意圖。 (請先閱讀背面之注意事項再填寫本頁) 零-裝 經濟部智慧財產局員工消費合作社印制衣 圖式之元件符號說明 101晶圓 102銲墊 103絕緣層 104銲墊接觸面 105介層洞插塞 106彈性材料層 107金屬導線層 108介電層 109凸塊下金屬 110金屬凸塊 201晶圓 202銲墊 203絕緣層 204第一部份 205第二部分 206軟性高分子層 207第一金屬層 208第二金屬層 4CHIPBOND200101TW, CBP-01-001 ϋ ϋ n ϋ 一 0， n ϋ emmt Βϋ ΛΜ§ I · 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 495938 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2 ) 209第三金屬層 301晶圓 303絕緣層 305第二部分 307重佈層 309第二金屬連線層 311第二軟性高分子層 313第二金屬層 315金屬凸塊 402銲墊 404第一部份 406軟性高分子層 408第一金屬層 410光阻層 412金屬凸塊 502銲墊 504第一部份 506第一軟性高分子層 508第一金屬連線層 510第一光阻層 512第二軟性高分子層 514第一金屬層 516第二光阻層 518金屬凸塊 4CHIPBOND200101TW, CBP-01-001 210金屬凸塊 302銲墊 304第一部份 306第一軟性高分子層 308第一金屬連線層 310第三金屬連線層 312第一金屬層 314第三金屬層 401晶圓 403絕緣層 405第二部分 407介層洞 409第二金屬層 411第三金屬層 501晶圓 503絕緣層 505第二部分 507第一介層洞 509第二金屬連線層 511第三金屬連線層 5 13第二介層洞 515第二金屬層 517第三金屬層 (請先閱讀背面之注意事項再填寫本頁) 裝---- 訂---- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 495938 經濟部智慧財產局員工消費合作社印制衣 A7 五、發明說明（（| ) 發明之詳細說明 Η 2所不爲本發明晶圓級半導體封裝結構之第〜寶 例的示意圖。此晶圓級半導體封裝結構包括一晶圓細 晶圓201上具有一銲墊2〇2。銲墊2〇2 一般而言係舄=或 銅等材質。銲墊202上具有一絕緣層203，遮蔽此銲執^ 第一部份2〇4，銲墊的第二部分2〇5外露。此絕緣層2之 有一軟性高分子層206。此軟性高分子層2〇6較佳爲苯^ 環丁烯（Benzocyclobutene，BCB)、聚亞醯胺（p〇lyi如. PI)等材料所構成。使用此兩種材料的主要原因在於 以由光罩、顯影的方式改變圖形形狀並鑽挖介層滴 : 1|」，而不 用另闢新製程單元即可加以實施。 銲墊2〇2的第二部分2〇5上具有一第一金屬靥2〇7 第一金屬層207與銲墊202電氣接合。第一金屬層2〇7 、 佳係爲以濺鍍方式沉積的Ml金屬層。Ml代表選自餘X 鎳、絡、钽、欽鎢合金以及鉅鎢合金的金屬。其中尤# _ 組、欽鶴合金以及組鶴合金爲良好之阻障層^具有 抗腐蝕之特性，當直接沉積於銲墊上時，具有防止 干擾（electromagnetic，EMI)以及抗金屬凸塊材料，々口以 與錫，侵蝕之功能。第一金屬層207上具有一第：；：金屬層 208，第二金屬層208與第一金屬層207電氣接合。第二金 屬層208較佳係爲以濺鍍方式沉積的M2金屬層。Μ2代表 選自銅、鉻銅合金、鎳銅合金、以及鈦銅合金的金屬。此 濺鍍M2層，可以作爲電鍍M3層與濺鍍Ml層之中介層， 使兩者之間的結合力更強。M3代表選自銅、鎳與金的金 4CHIPBOND200101TW, CBP-01-001 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------·ΐ!訂---------$ (請先閱讀背面之注意事項再填寫本頁) 495938 A7 B7 五、發明說明（ι〇) 屬。第二金屬層208上具有一第三金屬層209，第三金屬 層209與第二金屬層208電氣接合。在本發明中，第三金 屬層209較佳係爲以電鍍方式形成的M3金屬層。以電鍍 方式產生之M3金屬層，其厚度比以濺鍍方式沉積的金屬 層來的厚，因此可以提高機械強度與可靠度。第三金屬層 209上具有一金屬凸塊210,此金屬凸塊210與第三金屬層 209電氣接合。金屬凸塊210通常係爲鉛錫合金。 軟性高分子層206可以作爲金屬凸塊210與晶圓201 之間之應力緩衝層。降低裝設金屬凸塊210於晶圓201時， 對晶圓201造成破壞之機會。 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 3! 請參照圖3,其爲依照本發明晶圓級半導體封裝結構 之第二實施例的示意圖。此晶圓級半導體封裝結構包括一 晶圓301，晶圓301上具有一銲墊302。銲墊302上具有一 絕緣層303，此絕緣層303遮蔽銲墊302之第一部份304， 銲墊302的第二部分305外露。此絕緣層303上具有一第 一軟性高分子層306。此晶圓級半導體封裝結構亦包括一 重佈層307。重佈層307進一步包含一第一金屬連線層 308,其位於銲墊的第二部分305上，與銲墊302電氣接合； 一第二金屬連線層309，其位於第一金屬連線層308上， 與第一金屬連線層308電氣接合；以及一第三金屬連線層 310，其位於第二金屬連線層309上，與第二金屬連線層 309電氣接合。重佈層307上較佳係具有一第二軟性高分 子層311，以鞏固凸塊下金屬之結構。重佈層307遠離該 銲墊302的一端上具有一第一金屬層312，其與第三金屬 4CHIPBOND200101TW, CBP-01-001 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 495938 A7 B7__ 五、發明說明（丨！） 連線層310電氣接合。第一金屬層312上具有一第二金屬 層313，第二金屬層313與第一金屬層312電氣接合。第 二金屬層313上具有一第三金屬層314，第三金屬層314 與第二金屬層313電氣接合。第三金屬層314上具有一金 屬凸塊315,此金屬凸塊315與第三金屬層3 14電氣接合。 第一軟性高分子層306可以作爲金屬凸塊315與晶圓 301之間之應力緩衝層。降低裝設金屬凸塊315於晶圓301 上時，對晶圓301造成破壞之機會。 如圖2中所示之晶圓級半導體封裝結構之製程如下所 述並對照圖4a到4j。請參考圖4a，一晶圓401上之半導 體裝置已經完成，其具有複數個輸入/輸出用的銲墊402。 銲墊402通常爲鋁質或銅質。銲墊402上方具有被絕緣層 403遮蔽之第一部份404與未被遮蔽之第二部分405。沉積 一軟性高分子層406，如圖4b所示，並且進行第一次光罩 製程以於第二部分405上方蝕刻一介層洞407,如圖4c所 示，以暴露出第二部分405。接著，本發明首先沉積一第 一金屬層408，再沉積一第二金屬層409，如圖4d所示。 毯覆式塗佈一光阻層410於第二金屬層409上，進行第二 次光罩製程，如圖4e所示。顯影此光阻層410以將介層洞 407表面的第二金屬層409暴露出來，如圖4f所示。形成 一第三金屬層411於沉積的第二金屬層409上方，並電鍍 銲錫於沉積的第二金屬層409上方，以形成一金屬凸塊 412，如圖4g所示。其中，由第一金屬層408、第二金屬 層409與第三金屬層411所形成的三層結構，即爲凸塊下 4CHIPBOND200101TW, CBP-01-001 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 零-裝 — 訂---------I. 經濟部智慧財產局員工消費合作社印製 495938 A7 B7 _ 五、發明說明（〗>) 金屬。 接著，在圖4h中，光阻層410被移除。在圖4i中， 將之前以濺鍍方式沉積的第一金屬層408與第二金屬層 409,以蝕刻移除，只留下金屬凸塊412下方的部分。最後， 在圖4j中，進行迴銲，以使金屬凸塊412成形。其中第一 金屬層408係爲Ml所構成。Ml代表選自鈦、鎳、鉻、鉅、 鈦鎢合金以及钽鎢合金的金屬。其中尤其鈦、鉅、鈦鎢合 金以及鉅鎢合金爲良好之阻障層，具有耐酸鹼、抗腐蝕之 特性，當直接沉積於銲墊上時，具有防止電磁波干擾（EMI) 以及抗金屬凸塊材料，如鉛與錫，侵蝕之功能。第二金屬 層409爲M2所構成。M2代表選自銅、鉻銅合金、鎳銅合 金、以及鈦銅合金的金屬。第三金屬層411爲M3所構成。 M3代表選自銅、鎳與金的金屬。第二金屬層409係以濺 鍍方式沉積，第三金屬層411係以電鍍方式形成。 第二金屬層409可以作爲第一金屬層408與第三金屬 層411之間的中介層，以加強第三金屬層411與第一金屬 層408之間的結合力。此外，以電鍍方式形成的第三金屬 層411厚度較厚’機械強度與可靠度皆較高。在製程中， 爲了縮短触刻時間’弟二金屬層411只電鑛於由光阻層410 所限制的範圍，如圖4g所示，而不是毯覆式的電鍍，以避 免在後續進行同蝕刻時，如圖4i所示，蝕刻時程過長。由 於一般餓刻皆無法達到非等向性飩刻（anisotropic etching)，蝕刻時程過長，很容易造成局部過度蝕刻或底 切（undercut)，良率降低。 4CHIPBOND200101TW, CBP-01-001 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝--------訂--------- 經濟部智慧財產局員工消費合作社印製 495938 A7 B7 五、發明說明（13) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 如圖3中所示之晶圓級半導體封裝結構之製程如下所 述並參考圖5a至5p。請參考圖5a，一晶圓501上之半導 體裝置已經完成，其具有複數個輸入/輸出用的銲墊502。 銲墊502通常爲鋁質或銅質。銲墊502上方具有被絕緣層 503遮蔽之第一部份504與未被遮蔽之第二部分505。沉積 一第一軟性高分子層506，如圖5b所示，並且進行第一次 光罩製程以於第二部分505上方鈾刻一第一介層洞507， 如圖5c所示，以暴露出第二部分505。接著，如圖5d所 示，本發明首先沉積一第一金屬連線層508，再沉積一第 二金屬連線層509。毯覆式塗佈一第一光阻層510於第二 金屬連線層509上，進行第二次光罩製程，如圖5e所示。 顯影此第一光阻層510以將第一介層洞507表面的第二金 屬連線層509暴露出來。如圖5f所示。形成一第三金屬連 線層511於沉積的第二金屬連線層509上方。移除前述第 一光阻層510，並進行蝕刻，以將第一金屬連線層508與 第二金屬連線層509的中間不需電氣連接之部分蝕斷分 開，如圖5g所示。第一金屬連線層508、第二金屬連線層 509以及第三金屬連線層511構成具有三層結構的一重佈 層，其可以幫助變換金屬凸塊所在的位置，而不一定要在 銲墊的正上方。 接著，毯覆式塗佈一第二軟性局分子層512，並進行 第三次光罩製程，在第三金屬連線層511上方，遠離銲墊 502的一端形成一第二介層洞513，如圖5h所示。圖5i 所示爲完成第二軟性高分子層512的顯影與固化後之示意 4CHIPBOND200101TW, CBP-01-001 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 495938 A7 B7 五、發明說明（丨今） 圖，可以看到完成的介層洞513。然後，沉積一第一金屬 層514與一第二金屬層515於顯影固化後之第二軟性高分 子層512上，如圖5j所示。毯覆式塗佈一第二光阻層516, 並進行第四次光罩製程，以暴露出第二金屬層515位於第 二介層洞5 13上方的部分，如圖5k所示。顯影第二光阻層 516，如圖51所示。形成一第三金屬層517於第二金屬層 515暴露出來的部分上，並且電鍍銲錫以形成金屬凸塊518 到第三金屬層517上，如圖5m所示。其中，由第一金屬 層514、第二金屬層515與第三金屬層517所形成的三層 結構，即爲凸塊下金屬。 接著，在圖5n中，第二光阻層516被移除。在圖5〇 中，將之前以沉積的第一金屬層514與第二金屬層515以 蝕刻移除，只留下金屬凸塊下方的部分。最後，在圖5p 中，進行迴銲，以使金屬凸塊518達到預定形狀。其中第 一金屬連線層508與第一金屬層514係爲Ml。Ml代表選 自鈦、鎳、鉻、鉬、鈦鎢合金以及鉅鎢合金的金屬。其中 尤其鈦、鉅、鈦鎢合金以及鉬鎢合金爲良好之阻障層，具 有耐酸鹼、抗腐蝕之特性，當直接沉積於銲墊上時，具有 防止電磁波干擾（EMI )以及抗金屬凸塊材料，如與錫， 侵蝕之功能。第二金屬連線層509與第二金屬層515皆爲 M2所構成，皆以濺鍍的方式沉積而成。M2代表選自銅、 鉻銅合金、鎳銅合金、以及鈦銅合金的金屬。然而第三金 屬連線層511與第三金屬層517係以電鍍方式，由M3所 構成者。M3代表選自銅、鎳與金的金屬。 4CHIPBOND200101TW, CBP-01-001 14 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） - (請先閱讀背面之注意事項再填寫本頁) 零，裝 ----訂---------_ 495938 A7 B7 五、發明說明（丨5) 第二金屬連線層5〇9或第二金屬層515可以作爲中介 層，以加強第三金屬連線層511與第一金屬連線層508之 間，第三金屬層517與第一金屬層514之間的結合力。此 外，以電鍍方式形成的第三金屬連線層511與第三金屬層 517厚度較厚，機械強度與可靠度皆較高。此外，在製程 中，爲了縮短飩刻時間，第三金屬連線層511與第三金屬 層517只電鍍於由第一光阻層510與第二光阻層516所限 制的範圍，如圖5f與5m所示，而不是毯覆式的電鍍，以 避免在後續進行同蝕刻時，如圖5g與5〇所示，蝕刻時程 過長。由於一般蝕刻皆無法達到非等向性飩刻（anisotropic etching)，當蝕刻時程拉長時，很容易造成局部過度飩刻 或底切（undercut) ’良率降低。 於本發明的第一較佳實施例中，提出了一種三層結構 的凸塊下金屬。此凸塊下金屬主要包含以濺鍍方式形成的 Ml層、以濺鍍方式形成的M2層、以及以電鍍方式形成的 M3層。此濺鍍Ml層可以較一般金屬提供銲墊與晶圓更完 善的保護，其可以抗電磁干擾、抗酸鹼腐鈾。濺鍍M2層 主要是提供濺鍍Ml層與電鍍M3層之間更好的接合力。 電鍍M3層的厚度遠較濺鍍M2層爲厚，其機械強強度與 可靠度都將大大提昇。 相同的技術與原則亦應用於本發明第二較佳實施例中 的重佈層上。在本發明之第二較佳實施例中，重佈層同樣 是由一濺鍍Ml層、一濺鍍M2層以及一電鍍M3層所形 成。如此所得之晶圓級半導體封裝結構，在良率、可靠度 4CHIPBOND200101TW, CBP-01-001 ic 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------. 經濟部智慧財產局員工消費合作社印製 495938 A7 B7 五、發明說明（A) 與機械強度上，都優於先前技術所得之半導體封裝結構。 另一方面，本發明亦提供完成第一與第二較佳實施例所需 之製程。一般半導體製程的實施者，可以在少量更動，甚 至不更動原有半導體製程器具的前提下，同時完成半導體 裝置與依照本發明較佳實施例之晶圓級半導體封裝結構。 採用本發明晶圓級半導體封裝結構的晶片或晶片組， 可以裝設在電路板上或電子計算裝置上，尤其係體積小巧 之電路板與電子計算裝置，以執行所需要之計算。 熟悉本項技術者應該淸楚了解，本發明可以在不脫離 本發明的精神與範圍下’以許多其他特定形式加以實施。 因此，現在提供的實施例應該被當作說明性的，而不是限 制性的，此發明不受文中所給細節的侷限，而可以於隨附 申請專利範圍的範圍內作均等的變化與修改。 (請先閱讀背面之注音？事項再填寫本頁) 裝 ----訂---------^^1. 經濟部智慧財產局員工消費合作社印製 4CHIPBOND200101TW, CBP-01-001 16 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）495938 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (>) Pad contact surface 104. Above the pad contact surface 104, there is a via hole plug 105, and the via hole plug 105 is formed of a conductive material such as copper or aluminum. After forming a via hole plug 105, a layer of elastic material is coated and etched back to form an elastic material layer 106 as shown in FIG. After the elastic material layer 106 is completed, a metal wire layer 107 is further deposited as a redistribution layer. After the metal wiring layer 107 is completed, a dielectric layer 108 is deposited on the metal wiring layer 107 'for insulation. The dielectric layer 108 is etched 'at the place where the bump is to be formed to expose the metal wire layer 107, and then a metal under bump 109 is formed. Finally, a metal bump uo is formed on the metal 109 under the bump. The 'under bump metal 109 can be used as a bonding layer with a metal bump and a metal leakage preventing layer. The wafer-level package of the prior art is characterized in that it uses an elastic material layer, such as the elastic material layer 106 in FIG. 1. This elastic material layer 106 is not only used as a buffer layer for mechanical stress in the packaging process, but also has a certain absorption effect on thermal expansion. However, "in the prior art, the metal in contact with the pad is made of a highly conductive metal" These metals include copper, aluminum, copper alloy, aluminum alloy, and silver. However, these metals or alloys are not good at resisting electromagnetic interference. In addition, the thickness of the redistribution layer and the metal under the bump produced by the deposition method cannot be effectively increased, resulting in a fragile structure and insufficient reliability. Based on this, the present invention provides an improved wafer-level semiconductor package structure and its manufacturing process to solve the aforementioned disadvantages of the current wafer-level semiconductor package structure. 4CHIPBOND200101TW, CBP-01-001 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- installation -------- order --- ------ Line (Please read the precautions on the back before filling this page) 495938 A7 B7 V. Description of the Invention (3) Abstract When considering the case where there is no redistribution layer, the present invention provides a wafer-level semiconductor package Structure and process. The wafer-level semiconductor package structure includes a wafer and a solder pad on the wafer. The pad has an insulating layer that shields the first part of the pad, and the second part of the pad is exposed. The insulating layer has a soft polymer layer. The second portion of the solder pad has a first metal layer, and the first metal layer is electrically connected to the solder pad. The first metal layer has a second metal layer thereon, and the second metal layer is electrically connected to the first metal layer. The second metal layer is provided with a third metal layer, and the third metal layer is electrically connected to the second metal layer. The third metal layer has a metal bump, and the metal bump is electrically connected to the third metal layer. The manufacturing process of the above semiconductor package structure is as follows. First, a wafer is provided. The semiconductor device on the wafer is completed and has a plurality of pads for input / output. The pad has a first portion that is shielded by the insulating layer and a second portion that is not shielded. An insulating layer is deposited, and a via is etched over the second portion to expose the second portion. Next, the present invention first deposits a first metal layer, then deposits a second metal layer, and finally forms a third metal layer over the deposited second metal layer by electroplating to form a metal under bump. Then, a metal bump is formed on the metal under the bump by reflow. On the other hand, the present invention provides a wafer-level packaging structure and process in the presence of a redistribution layer. The wafer-level semiconductor package structure includes a wafer with a pad on the wafer. The pad has an insulating layer which shields the first part of the pad and the second part of the pad is exposed. The insulating layer has a soft polymer layer. This wafer-level semiconductor package structure also includes a double cloth 4CHIPBOND200101TW, CBP-01-001 3 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page ) Zero-fitting -------- Order --------- Line * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Cooperatives of the Ministry of Economic Affairs Intellectual Property Bureau 495938 A7 B7 V. Invention Explanation (today) layers. The redistribution layer further includes a first metal connection layer, which is located on the second portion of the bonding pad, and is electrically connected to the pad; a second metal connection layer, which is located on the first metal connection layer, and is connected to the first The metal connection layer is electrically connected; and a third metal connection layer is located on the second metal connection layer and is electrically connected to the second metal connection layer. The redistribution layer has a first metal layer on an end remote from the bonding pad, and the first metal layer is electrically connected to the third metal connection layer. The first metal layer has a second metal layer thereon, and the second metal layer is electrically connected to the first metal layer. The second metal layer has a third metal layer thereon, and the third metal layer is electrically connected to the second metal layer. The third metal layer has a metal bump, and the metal bump is electrically connected to the third metal layer. The manufacturing process of the above-mentioned wafer-level semiconductor package structure is as follows. First, a wafer is provided. The semiconductor device on the wafer is completed and has a plurality of pads for input / output. The pad has a first portion that is shielded by the insulating layer and a second portion that is not shielded. A first insulating layer is deposited, and a first via hole is etched over the second portion to expose the second portion. Next, the present invention first deposits a first metal wiring layer, then deposits a second metal wiring layer, and finally forms a third metal wiring layer over the deposited second metal wiring layer by electroplating to form One heavy layer. A second insulating layer is coated on the redistribution layer, and a second via hole is formed by etching above the redistribution layer at a predetermined position away from the pad to expose the redistribution layer (third Metal wiring layer). Then, a first metal layer is deposited, a second metal layer is deposited, and finally a third metal layer is formed over the deposited second metal layer by electroplating to form a metal under the bump that is electrically connected to the redistribution layer. After that, a metal bump is formed on the metal under the bump by reflow. 4CHIPBOND200101TW, CBP-01-001 4 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ----------- installation -------- order-- ------- line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 495938 A7 B7 V. Description of the Invention (^) The first metal layer and the first metal The wiring layer is preferably an M1 layer deposited by sputtering. The second metal layer and the second metal connection layer are preferably M2 layers deposited by sputtering. The third metal layer and the third metal connection layer are preferably M3 layers formed by electroplating. Where Ml is a metal selected from titanium, nickel, chromium, molybdenum, titanium tungsten alloy and giant tungsten alloy, M2 is a metal selected from copper, chrome copper alloy, nickel copper alloy and titanium copper alloy, and M3 series is selected Metals from copper, nickel and gold. Brief description of the drawings FIG. 1 discloses a wafer-level semiconductor package structure of the prior art; FIG. 2 discloses a first embodiment of a wafer-level semiconductor package structure according to the present invention; FIG. 3 discloses a wafer-level semiconductor package structure according to the present invention Second embodiment; FIG. 4a discloses a cross-sectional view of a wafer having a plurality of bonding pads according to the first embodiment of the present invention; FIG. 4b discloses the wafer in FIG. Figure 4c shows the schematic diagram of the wafer in Figure 4b after development and curing of the soft polymer material; Figure 4d shows the schematic diagram of the wafer in Figure 4c after M1 and M2 deposition; Figure 4e Schematic diagram of the wafer in 4d after photoresist coating and the second photomask process; 4CHIPBOND200101TW, CBP-01-001 5 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling in this page) Binding ---- Order --------- A7 B7 V. Description of the invention (b) Figure 4f reveals the wafer in Figure 4e after development. Schematic; Figure 4g reveals the wafer warp in Figure 4f Schematic diagram after M3 and solder plating; Figure 4h exposes the schematic diagram of the photoresist layer on the wafer in Figure 4g after removal; Figure 41 discloses the schematic diagram of the wafer in Figure 4h after etching of M1 and M2; Figure 4j exposes Figure 4i is a schematic view of the wafer after reflow; Figure 5a is a cross-sectional view of a wafer having a plurality of bonding pads according to a second embodiment of the present invention; Figure 5b is a wafer coated with a soft polymer in Figure 5a Figure 5c shows the schematic diagram after the first photomask process; Figure 5c exposes the wafer in Figure 5b after the soft polymer layer is developed and cured; Figure 5d reveals the wafer in Figure 5c after M1 and M2 deposition FIG. 5e is a schematic view of the wafer in FIG. 5d after being coated with a photoresist layer and subjected to a second photomask process; FIG. 5f is a schematic view of the wafer in FIG. 5e after being subjected to M3 plating; The schematic diagram after the photoresist layer on the wafer in 5f is removed and etched with Ml and M2; Figure 5h discloses the schematic diagram after the wafer in Figure 5g is coated with a soft polymer layer and the third photomask process is performed; Figure 5i reveals that the wafer in Figure 5h passes through a soft polymer Develop and solid 4CHIPBOND200101TW, CBP-01-001 6 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read Note 2 on the back before filling out this page) Production --- ----- Order --------- Printed by the Consumer Property Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 495938 A7 _B7 V. Description of invention 0) Schematic diagram after the transformation; Figure 5j reveals the wafer in Figure 5i Schematic diagram after M1 and M2 deposition successively; Figure 5k reveals the schematic diagram of the wafer in Figure 5j after photoresist layer coating and the fourth photomask process; Figure 51 discloses the wafer in Figure 5k through the photoresist layer Schematic diagram after development; Figure 5m reveals the schematic diagram of the wafer in Figure 51 after M3 and solder plating; Figure 5n reveals the schematic diagram after the photoresist layer on the wafer in Figure 5m is removed; Figure 50 exposes the crystal of Figure 5n The schematic diagram of the circle after the M1 and M2 etching; and FIG. 5P exposes the schematic diagram of the wafer in FIG. 50 after reflow. (Please read the precautions on the back before filling out this page) Component Symbols for Printed Garment Schematic Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs 101 Hole plug 106 Elastic material layer 107 Metal wire layer 108 Dielectric layer 109 Metal under bump 110 Metal bump 201 Wafer 202 Welding pad 203 Insulation layer 204 First part 205 Second part 206 Soft polymer layer 207 First Metal layer 208, second metal layer 4CHIPBOND200101TW, CBP-01-001 ϋ ϋ n ϋ 0 0, n ϋ emmt Βϋ ΛΜ§ I B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (2) 209 Third metal layer 301 Wafer 303 Insulation layer 305 Second part 307 Redistribution layer 309 Second metal connection layer 311 Second soft polymer Layer 313 second metal layer 315 metal bump 402 solder pad 404 first part 406 soft polymer layer 408 first metal layer 410 photoresist layer 412 metal bump 502 solder pad 504 first part 506 first soft polymer Layer 508 first gold Connection layer 510 first photoresist layer 512 second flexible polymer layer 514 first metal layer 516 second photoresist layer 518 metal bump 4CHIPBOND200101TW, CBP-01-001 210 metal bump 302 pad 304 first part 306 first flexible polymer layer 308 first metal connection layer 310 third metal connection layer 312 first metal layer 314 third metal layer 401 wafer 403 insulation layer 405 second portion 407 interlayer hole 409 second metal layer 411 third metal layer 501 wafer 503 insulation layer 505 second part 507 first via hole 509 second metal link layer 511 third metal link layer 5 13 second via hole 515 second metal layer 517 third Metal layer (please read the precautions on the back before filling this page) Loading-Ordering-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 495938 Intellectual Property Bureau, Ministry of Economic Affairs Printed clothing A7 for employee consumer cooperatives V. Description of the invention ((|) Detailed description of the invention Η 2 is not a schematic diagram of the first ~ treasure example of the wafer-level semiconductor package structure of the present invention. This wafer-level semiconductor package structure includes a crystal A circular wafer 201 has a solder pad 202. The solder pad 2 02 Generally speaking, it is made of 舄 = or copper. There is an insulating layer 203 on the pad 202 to shield the welding pad ^ The first part 204 is exposed, and the second part 200 is exposed. The insulating layer 2 has a flexible polymer layer 206. The soft polymer layer 206 is preferably made of a material such as Benzenecyclobutene (BCB), polyimide (Polyi such as PI), and the like. The main reason for using these two materials is to change the shape of the pattern and drill the interlayer drops: 1 | "by means of photomask, development, and can be implemented without creating a new process unit. The second portion 205 of the solder pad 202 has a first metal 靥 207. The first metal layer 207 is electrically connected to the solder pad 202. The first metal layer 207 is preferably an M1 metal layer deposited by sputtering. Ml represents a metal selected from the group consisting of nickel, nickel, copper, tantalum, tungsten tungsten alloy, and giant tungsten alloy. Among them, ## group, Qinhe alloy, and group crane alloy are good barrier layers. ^ It has anti-corrosion properties. When directly deposited on the pad, it has anti-interference (EMI) and anti-metal bump materials. 々 The function of erosion with tin. The first metal layer 207 has a first metal layer 208, and the second metal layer 208 is electrically connected to the first metal layer 207. The second metal layer 208 is preferably an M2 metal layer deposited by sputtering. M2 represents a metal selected from copper, chrome copper alloy, nickel copper alloy, and titanium copper alloy. The sputtered M2 layer can be used as an interposer for the electroplated M3 layer and the sputtered M1 layer, so that the bonding force between the two is stronger. M3 stands for gold selected from copper, nickel and gold. 4CHIPBOND200101TW, CBP-01-001 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----------- · ΐ ! Order --------- $ (Please read the notes on the back before filling out this page) 495938 A7 B7 V. Description of the invention (ι〇) There is a third metal layer 209 on the second metal layer 208, and the third metal layer 209 is electrically connected to the second metal layer 208. In the present invention, the third metal layer 209 is preferably an M3 metal layer formed by electroplating. The M3 metal layer produced by electroplating is thicker than the metal layer deposited by sputtering, so it can improve mechanical strength and reliability. The third metal layer 209 has a metal bump 210 thereon, and the metal bump 210 is electrically connected to the third metal layer 209. The metal bump 210 is usually a lead-tin alloy. The soft polymer layer 206 can serve as a stress buffer layer between the metal bump 210 and the wafer 201. When mounting the metal bump 210 on the wafer 201, the chance of damaging the wafer 201 is reduced. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page) 3! Please refer to FIG. 3, which is a schematic diagram of a second embodiment of a wafer-level semiconductor package structure according to the present invention. The wafer-level semiconductor package structure includes a wafer 301 having a bonding pad 302 thereon. The solder pad 302 has an insulating layer 303 on it, which shields the first portion 304 of the solder pad 302 and the second portion 305 of the solder pad 302 is exposed. The insulating layer 303 has a first flexible polymer layer 306 thereon. The wafer-level semiconductor package structure also includes a redistribution layer 307. The redistribution layer 307 further includes a first metal wiring layer 308 which is located on the second portion 305 of the bonding pad and is electrically connected to the bonding pad 302; a second metal wiring layer 309 which is located on the first metal wiring layer 308 is electrically connected to the first metal connection layer 308; and a third metal connection layer 310 is located on the second metal connection layer 309 and is electrically connected to the second metal connection layer 309. The redistribution layer 307 preferably has a second soft high molecular layer 311 to strengthen the structure of the metal under the bump. The redistribution layer 307 has a first metal layer 312 on an end remote from the bonding pad 302, and the third metal layer 4CHIPBOND200101TW, CBP-01-001 10 This paper size applies to China National Standard (CNS) A4 (210 X 297) (Centi) 495938 A7 B7__ 5. Description of the invention (丨!) The wiring layer 310 is electrically connected. The first metal layer 312 has a second metal layer 313 thereon, and the second metal layer 313 is electrically connected to the first metal layer 312. A third metal layer 314 is disposed on the second metal layer 313, and the third metal layer 314 is electrically connected to the second metal layer 313. The third metal layer 314 has a metal bump 315 thereon, and the metal bump 315 is electrically connected to the third metal layer 314. The first flexible polymer layer 306 can be used as a stress buffer layer between the metal bump 315 and the wafer 301. When the metal bump 315 is mounted on the wafer 301, the chance of damaging the wafer 301 is reduced. The process of manufacturing a wafer-level semiconductor package structure as shown in FIG. 2 is described below and compared with FIGS. 4a to 4j. Please refer to FIG. 4a, a semiconductor device on a wafer 401 has been completed, and has a plurality of pads 402 for input / output. The solder pad 402 is usually aluminum or copper. Above the pad 402, there is a first portion 404 that is shielded by the insulating layer 403 and a second portion 405 that is not shielded. A soft polymer layer 406 is deposited, as shown in FIG. 4b, and a first photomask process is performed to etch a via hole 407 over the second portion 405, as shown in FIG. 4c, to expose the second portion 405. Next, the present invention first deposits a first metal layer 408 and then deposits a second metal layer 409, as shown in FIG. 4d. A blanket coating a photoresist layer 410 on the second metal layer 409 is performed for a second photomask process, as shown in FIG. 4e. The photoresist layer 410 is developed to expose the second metal layer 409 on the surface of the via 407, as shown in FIG. 4f. A third metal layer 411 is formed over the deposited second metal layer 409, and a solder is plated over the deposited second metal layer 409 to form a metal bump 412, as shown in FIG. 4g. Among them, the three-layer structure formed by the first metal layer 408, the second metal layer 409, and the third metal layer 411 is the under bump 4CHIPBOND200101TW, CBP-01-001 11 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) Zero-Pack — Order --------- I. Printed by the Employee Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 495938 A7 B7 _ 5. Description of the invention (〗 >) Metal. Then, in FIG. 4h, the photoresist layer 410 is removed. In FIG. 4i, the first metal layer 408 and the second metal layer 409 that were previously deposited by sputtering are removed by etching, leaving only a portion below the metal bump 412. Finally, in FIG. 4j, reflow is performed to form the metal bump 412. The first metal layer 408 is composed of M1. Ml represents a metal selected from titanium, nickel, chromium, giant, titanium tungsten alloys, and tantalum tungsten alloys. Among them, titanium, giant, titanium tungsten alloy and giant tungsten alloy are good barrier layers, which have the characteristics of acid and alkali resistance and corrosion resistance. When directly deposited on the solder pad, they have the ability to prevent electromagnetic interference (EMI) and resist metal bumps Materials, such as lead and tin, erode the function. The second metal layer 409 is made of M2. M2 represents a metal selected from the group consisting of copper, chrome copper alloy, nickel copper alloy, and titanium copper alloy. The third metal layer 411 is made of M3. M3 represents a metal selected from copper, nickel and gold. The second metal layer 409 is deposited by sputtering, and the third metal layer 411 is formed by plating. The second metal layer 409 can be used as an interposer between the first metal layer 408 and the third metal layer 411 to strengthen the bonding force between the third metal layer 411 and the first metal layer 408. In addition, the thickness of the third metal layer 411 formed by electroplating is thicker, and its mechanical strength and reliability are higher. In the manufacturing process, in order to shorten the etching time, 411 second metal layer 411 electric ore is limited to the range limited by the photoresist layer 410, as shown in FIG. 4g, instead of blanket plating, to avoid subsequent etching at the same time. As shown in FIG. 4i, the etching duration is too long. Since anisotropic etching cannot be achieved in general, the etching time is too long, it is easy to cause local over-etching or undercut, and the yield is reduced. 4CHIPBOND200101TW, CBP-01-001 12 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) -Installation -------- Order --------- Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs' Consumer Cooperatives 495938 A7 B7 V. Description of the Invention (13) (Please read the precautions on the back before filling this page) The cooperative process for printing a wafer-level semiconductor package structure as shown in FIG. 3 is described below with reference to FIGS. 5a to 5p. Referring to FIG. 5a, the semiconductor device on a wafer 501 has been completed, and has a plurality of pads 502 for input / output. The bonding pad 502 is usually aluminum or copper. Above the pad 502, there is a first portion 504 that is shielded by the insulating layer 503 and a second portion 505 that is not shielded. A first soft polymer layer 506 is deposited, as shown in FIG. 5b, and a first photomask process is performed to etch a first interlayer hole 507 on the uranium above the second portion 505, as shown in FIG. 5c, to expose The second part 505. Next, as shown in FIG. 5d, the present invention first deposits a first metal wiring layer 508, and then deposits a second metal wiring layer 509. A blanket coating a first photoresist layer 510 on the second metal connection layer 509 to perform a second photomask process, as shown in FIG. 5e. This first photoresist layer 510 is developed to expose the second metal wiring layer 509 on the surface of the first via hole 507. As shown in Figure 5f. A third metal wiring layer 511 is formed over the deposited second metal wiring layer 509. The aforementioned first photoresist layer 510 is removed and etched to separate the portion of the first metal wiring layer 508 and the second metal wiring layer 509 that do not require electrical connection, as shown in FIG. 5g. The first metal connection layer 508, the second metal connection layer 509, and the third metal connection layer 511 constitute a double-layered layer having a three-layer structure, which can help to change the position of the metal bumps, and does not have to be soldered. Right above the pad. Next, a blanket is applied to coat a second soft local molecular layer 512, and a third photomask process is performed. A second via hole 513 is formed on the third metal connection layer 511 at an end away from the pad 502. As shown in Figure 5h. Figure 5i shows the schematic diagram after the development and curing of the second flexible polymer layer 512 is completed. 4CHIPBOND200101TW, CBP-01-001 13 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Wisdom of the Ministry of Economic Affairs The 495938 A7 B7 printed by the employee's consumer cooperative of the property bureau 5. Description of the invention (丨 present) Figure, you can see the completed mezzanine hole 513. Then, a first metal layer 514 and a second metal layer 515 are deposited on the second soft polymer layer 512 after development and curing, as shown in FIG. 5j. A blanket photo-coating a second photoresist layer 516, and a fourth photomask process is performed to expose a portion of the second metal layer 515 above the second via 5313, as shown in FIG. 5k. The second photoresist layer 516 is developed, as shown in FIG. 51. A third metal layer 517 is formed on the exposed portion of the second metal layer 515, and solder is plated to form a metal bump 518 onto the third metal layer 517, as shown in FIG. 5m. The three-layer structure formed by the first metal layer 514, the second metal layer 515, and the third metal layer 517 is a metal under bump. Next, in FIG. 5n, the second photoresist layer 516 is removed. In FIG. 50, the first metal layer 514 and the second metal layer 515 that were previously deposited are removed by etching, leaving only a portion below the metal bump. Finally, in Fig. 5p, reflow is performed to bring the metal bumps 518 to a predetermined shape. The first metal wiring layer 508 and the first metal layer 514 are M1. Ml represents a metal selected from titanium, nickel, chromium, molybdenum, titanium tungsten alloy, and giant tungsten alloy. Among them, titanium, giant, titanium-tungsten alloys and molybdenum-tungsten alloys are good barrier layers, which have the characteristics of resistance to acid and alkali and corrosion. When directly deposited on the pads, they have the ability to prevent electromagnetic interference (EMI) and resist metal bumps Materials, such as with tin, erode the function. Both the second metal connection layer 509 and the second metal layer 515 are made of M2, and both are deposited by sputtering. M2 represents a metal selected from copper, chrome copper alloy, nickel copper alloy, and titanium copper alloy. However, the third metal connection layer 511 and the third metal layer 517 are made of M3 by electroplating. M3 represents a metal selected from copper, nickel and gold. 4CHIPBOND200101TW, CBP-01-001 14 ^ Paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)-(Please read the precautions on the back before filling this page) Zero, Packing ---- Order- --------_ 495938 A7 B7 V. Description of the invention (丨 5) The second metal connection layer 509 or the second metal layer 515 can be used as an interposer to strengthen the third metal connection layer 511 and The bonding force between the first metal wiring layer 508, the third metal layer 517 and the first metal layer 514. In addition, the third metal wiring layer 511 and the third metal layer 517 formed by electroplating are thicker, and have higher mechanical strength and reliability. In addition, in order to shorten the engraving time, the third metal wiring layer 511 and the third metal layer 517 are electroplated only in the range restricted by the first photoresist layer 510 and the second photoresist layer 516, as shown in FIG. 5f. As shown in FIG. 5g, instead of blanket plating, to avoid the same etching in the subsequent, as shown in FIGS. 5g and 50, the etching time is too long. As general etching cannot achieve anisotropic etching, when the etching duration is prolonged, it is easy to cause local over-etching or undercut ′ yield reduction. In a first preferred embodiment of the present invention, a three-layer structure under bump metal is proposed. The metal under the bump mainly includes an M1 layer formed by sputtering, an M2 layer formed by sputtering, and an M3 layer formed by plating. This sputtered Ml layer can provide better protection of solder pads and wafers than ordinary metals, and it can resist electromagnetic interference and resist acid and alkali corrosion of uranium. Sputtering the M2 layer is mainly to provide better adhesion between the sputtered M1 layer and the electroplated M3 layer. The thickness of the electroplated M3 layer is much thicker than that of the sputtered M2 layer, and its mechanical strength and reliability will be greatly improved. The same technique and principle are also applied to the redistribution layer in the second preferred embodiment of the present invention. In the second preferred embodiment of the present invention, the redistribution layer is also formed of a sputtered M1 layer, a sputtered M2 layer, and a plated M3 layer. The wafer-level semiconductor package structure obtained in this way has a yield and reliability of 4CHIPBOND200101TW, CBP-01-001 ic This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back first (Please fill in this page for matters) Packing -------- Order ---------. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 495938 A7 B7 V. Description of the invention (A) and mechanical strength , Are better than the semiconductor package structure obtained in the prior art. On the other hand, the present invention also provides the processes required to complete the first and second preferred embodiments. Implementers of a general semiconductor process can complete a semiconductor device and a wafer-level semiconductor package structure in accordance with a preferred embodiment of the present invention at the same time with little or no change to the original semiconductor process equipment. The wafer or chip set using the wafer-level semiconductor package structure of the present invention can be mounted on a circuit board or an electronic computing device, especially a small-sized circuit board and an electronic computing device to perform required calculations. Those skilled in the art should understand that the present invention can be implemented in many other specific forms without departing from the spirit and scope of the invention. Therefore, the embodiments provided now should be regarded as illustrative rather than restrictive. This invention is not limited by the details given in the text, but can be changed and modified equally within the scope of the accompanying patent application. (Please read the phonetic on the back? Matters before filling out this page) Binding ---- Order --------- ^^ 1. Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs 16 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)