515016 7824twf.doc/〇〇6 五、發明說明(I ) 本發明是有關於一種覆晶晶片及其製程,且特別是 有關於一種改變凸塊形式之具有重配置線路結構體的覆晶 晶片,就其製程而言,可以大幅縮減其製造步驟。 在現今資訊爆炸的社會,電子產品遍佈於日常生活 中’無論在食衣住fr育樂方面’都會用到積體電路元件所 組成的產品。隨著電子科技不斷地演進,功能性更複雜、 更人性化的產品推陳出新’就電子產品外觀而言,也朝向 輕、薄、短、小的趨勢設計,因此在半導體構裝技術上, 開發出許多局密度半導體封裝的形式。而透過覆晶封裝 (Flip Chip)技術可以達到上述的目的,由於覆晶晶片的 封裝係形成多個凸塊於晶片的焊墊上,而透過凸塊直接與 基板(Substrate)電性連接,相較於打線(wi re bonding) 及軟片自動貼合(TAB)方式,覆晶的電路路徑較短,具有 甚佳的電性品質;而覆晶晶片亦可以設計成晶背裸露的形 式’而提高晶片散熱性。基於上述原因,覆晶晶片封裝普 遍地應用於半導體封裝產業中。一般而言,會在晶片之主 動表面上製作一重配置線路結構體,使得晶片之對外接點 的相對位置可以調整,以符合覆晶晶片在與基板接合時的 條件。 第2A圖至第2N圖繪示習知晶片上重配置線路結構 體及凸塊之製程剖面放大示意圖,爲詳盡敘述習知技藝的 技術內容,僅繪示出晶片之焊墊區域的剖面放大圖。首先, g靑參照第2 A圖,先提供一晶片11 〇,晶片110具有一主動 表面11 2 ( a c t i v e s u r f a c e ),並且晶片11 〇還具有一保護 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公髮) (請先閱讀背面之注意事項3寫本頁) 訂· ;線: 經濟部智慧財產局員工消費合作社印製 515016 五、發明說明(1) 層 114(passivation)及至少一焊墊 116(bonding pad) ’ 保護層114及焊墊116均位在主動表面112上,保護層114 具有至少一保護層開口 118,以暴露出焊墊116,其中保 護層114的材質可以是二氧化矽或氮化矽。接下來,以旋 塗固化的方式在主動面上形成一絕緣層120,其材質可以 是聚亞醯胺(Polyimide)。然後在絕緣層120上,再以旋 塗固化的方式形一光阻130(photo resist)。 請參照第2B圖,然後進行曝光顯影的製程,使得 光阻130在焊墊116之上方處形成一光阻開口 132,暴露 出絕緣層120。 請參照第2C圖,接下來進行濕蝕刻或乾蝕刻製程, 將未受光阻130覆蓋的絕緣層120蝕刻去掉,以形成至少 一絕緣層開口 122,暴露出焊墊116。 請參照第2C圖、第2D圖,接下來進行去除光阻製 程,可以利用乾式去光阻法或濕式去光阻法,將光阻13 0 去除,使得絕緣層120暴露於外。 請參照第2E圖,接下來進行製作種子層製程,可 以利用濺鍍的方式,形成一種子層140(seed layer)於絕 緣層120上、絕緣層開口 122之側壁上及焊墊116上,其 中種子層14 0的材質可以是駄、鎢化欽、銘及銅。接下來, 進行塗佈光阻之製程,利用旋塗的方式,形成-一光阻150 於種子層140上。 請參照第2F圖,然後進行曝光顯影的製程,使得 光阻.150在欲形成金屬線路之處形成一光阻開口 152,以 4 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------------裝— (請先閱讀背面之注意事項Hi寫本頁) 訂: 線· 經濟部智慧財產局員工消費合作社印製515016 7824twf.doc / 〇〇6 5. Description of the invention (I) The present invention relates to a flip-chip wafer and its process, and in particular to a flip-chip wafer with a reconfigured circuit structure that changes the form of a bump. As far as its manufacturing process is concerned, its manufacturing steps can be greatly reduced. In today's information exploding society, electronic products are used in daily life. No matter in terms of food, clothing, and leisure education, products made of integrated circuit components are used. With the continuous evolution of electronic technology, more complex and more human-friendly products are being introduced. As far as the appearance of electronic products is concerned, they are also designed to be light, thin, short, and small. Therefore, in the field of semiconductor assembly technology, Many forms of local density semiconductor packages. The above-mentioned purpose can be achieved through flip-chip packaging (Flip Chip) technology. Since the flip-chip packaging system forms a plurality of bumps on the bonding pads of the wafer, the bumps are directly and electrically connected to the substrate (substrate). In Wi re bonding and TAB methods, the flip-chip circuit path is short and has excellent electrical quality; and the flip-chip wafer can also be designed in the form of bare wafer back to improve the chip Heat dissipation. For these reasons, flip chip packages are commonly used in the semiconductor packaging industry. Generally speaking, a reconfiguration circuit structure is made on the active surface of the wafer, so that the relative position of the wafer to the external point can be adjusted to meet the conditions of the flip-chip wafer when it is bonded to the substrate. Figures 2A to 2N show enlarged schematic cross-sectional views of the process of reconfiguring circuit structures and bumps on a conventional wafer. In order to describe the technical content of the conventional technique in detail, only the enlarged cross-sectional views of the pad area of the wafer are shown. . First, referring to Figure 2A, g 靑 first provides a wafer 11 〇, the wafer 110 has an active surface 11 2 (active surface), and the wafer 11 〇 also has a protection of this paper size applicable to China National Standard (CNS) A4 specifications ( (Issued 210 X 297) (please read the note on the back 3 to write this page) Order:; Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 515016 5. Description of the invention (1) Layer 114 (passivation) and at least one Bonding pad 116 'The protective layer 114 and the bonding pad 116 are both located on the active surface 112. The protective layer 114 has at least one protective layer opening 118 to expose the bonding pad 116. The material of the protective layer 114 may be two. Silicon oxide or silicon nitride. Next, an insulating layer 120 is formed on the active surface by spin coating and curing, and the material may be polyimide. Then, a photo resist 130 is formed on the insulating layer 120 by spin coating and curing. Referring to FIG. 2B, a process of exposure and development is performed, so that the photoresist 130 forms a photoresist opening 132 above the bonding pad 116 to expose the insulating layer 120. Referring to FIG. 2C, a wet etching or dry etching process is performed next to remove the insulating layer 120 not covered by the photoresist 130 to form at least one insulating layer opening 122 and expose the solder pad 116. Referring to FIG. 2C and FIG. 2D, a photoresist removal process is performed next. The photoresist 13 0 can be removed by using a dry photoresist method or a wet photoresist method, so that the insulating layer 120 is exposed to the outside. Please refer to FIG. 2E. Next, a seed layer manufacturing process is performed. A seed layer 140 (seed layer) can be formed on the insulation layer 120, the sidewall of the insulation layer opening 122, and the pad 116 by sputtering. The material of the seed layer 140 may be rhenium, tungsten, copper, and copper. Next, a photoresist coating process is performed, and a photoresist 150 is formed on the seed layer 140 by spin coating. Please refer to Figure 2F, and then perform the exposure and development process to make the photoresistor. 150 form a photoresistive opening 152 at the place where the metal circuit is to be formed, and apply the Chinese National Standard (CNS) A4 specification (210 X 297) on 4 paper sizes (Mm) ------------ Packing— (Please read the note on the back Hi to write this page) Order: Printed by the line · Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs
五、發明說明( 暴露出種子層140。接下來,進行塡入金屬製程,可以利 用電鍍的方式’塡入一金屬於絕緣層開口 122中及光阻開 Q 1 5 2中,以形成一金屬線路16 4於絕緣層開口 12 2中及 光阻開口 152中。 請參照第2F圖、第2G圖,接下來進行去除光阻製 程,可以利用乾式去光阻法或濕式去光阻法,將光阻15〇 去除,使得種子層14Q暴露於外。然後進行濕蝕刻或乾蝕 刻製程,將未受金屬線路164覆蓋的種子層140蝕刻去掉, 以暴露出絕緣層120。 請參照桌2Η圖,接下來進行製作焊罩層製程,可 以利用旋塗的方式,形成一焊罩層l70(s〇lder mask)於絕 緣層120上及金屬線路164上。然後進行塗佈光阻製程, 利用旋塗的方式,形成一光阻180於焊罩層170上。 請參照第21圖,然後進行曝光顯影的製程,使得 光阻180在金屬線路164上方欲形成凸塊(bump)之處形 成一光阻開口 182,以暴露出焊罩層17〇。接下來進行濕 蝕刻或乾蝕刻製程,將未受光阻18〇覆蓋的焊罩層17〇蝕 刻去掉’以形成至少一焊罩層開口 172,暴露出金屬線路 164。以暴露出絕緣層120。 請篸照第21圖、第2]圖,接下來進行去除光阻製 程,可以利用乾式去光阻法或濕式去光阻法,將光阻18〇 去除’使得焊罩層170暴露於外。如此便完成重配置線路 結構體220的步驟。 §舍爹照第2K圖,接下來進行製作種子層製程,可 本纸張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐) (請先閱讀背面之注意事項寫本頁) ----- S 訂·丨丨丨! . 經濟部智慧財產局員工消費合作社印製 515016 五、發明說明(Zf) 以利用濺鍍的方式,形成一種子層190於焊罩層170上、 焊罩層開口 172之側壁上及金屬線路164上,其中種子層 190的材質可以是銅。接下來,進行塗佈光阻之製程,利 用旋塗的方式,形成一光阻200於種子層190上。 請參照第2L圖,然後進行曝光顯影的製程,使得 光阻200在欲形成凸塊之處形成一光阻開口 202,以暴露 出種子層190。接下來,進行塡入金屬製程,可以利用電 鍍的方式,塡入一金屬於光阻開口 202中,以形成一凸塊 210於光阻開口 202中。 請參照第2L圖、第2M圖,接下來進行去除光阻製 程,可以利用乾式去光阻法或濕式去光阻法,將光阻2〇〇 去除,使得種子層190暴露於外。然後進行濕蝕刻或乾倉虫 刻製程,將未受凸塊210覆蓋的種子層190蝕刻去掉,以 暴露出焊罩層170。 請參照第2N圖,接下來進行迴焊製程,使得凸塊21〇 形變成球狀的樣式,如此一覆晶晶片100製作過程乍 完成。 經濟部智慧財產局員工消費合作社印製 --------------裝— (請先閱讀背面之注音?事項寫本頁) --線; 另外,就覆晶晶片結構而言,如第14圖所示,一 覆晶晶片100包括一晶片110、一^絕緣層120、二種子層 140、190、至少一金屬線路164、至少一凸塊21〇。晶片11〇 具有一主動表面112,並且晶片110還具有-一保護層π 4 及至少--焊墊116,保護層114及焊墊116均位在主動表 面112上,保護層114具有至少一保護層開口 118,以暴 露出焊墊116。絕緣層120係位在晶片11〇之主動表面112 本紙張尺度適用中國國家標準(CNS)/\4規格(210 X 297公釐) ^5〇i6 經濟部智慧財產局員工消費合作社印製 7824twf.doc/006 _B7 五、發明說明(^) 上,絕緣層120具有一絕緣層開口 122,暴露出晶片no 之焊墊116。種子層140係配置在絕緣層120上、絕緣層 開口 122之側壁上及晶片110之焊墊116上。金屬線路164 係位在種子層140上,並塡入於絕緣層開口 122中。焊罩 層170係位在金屬線路164及絕緣層120上,並且焊罩層 170具有一焊罩層開口 172,暴露出金屬線路164。種子層 190係位在金屬連線164上、焊罩層開口 170之側壁上及 焊罩層170上。凸塊210係位在種子層190上。 在上述的製程中,會分別進行兩次以濺鍍的方式製 作種子層140、190,一次是在絕緣層開口 122製作完成之 後,另一次是在焊罩層開口 Π2製作完成之後,如此在製 程上甚不具效率性。另外,由於在習知的技術中,還必須 製作焊罩層170,以防止焊球210在進行迴焊時,隨意地 流動,然而就製程上而言,還必須增加製作焊罩層170的 步驟,如此製程甚爲複雜。此外,由於凸塊210與晶片110 的距離甚近,並且凸塊210係由錫鉛合金製成,然而錫鉛 合金內的α粒子會對晶片110造成軟錯記(soft error)的 問題,使得記憶體存取間發生錯誤。若是要以低粒子的 錫鉛合金來作凸塊210,則製造成本大幅提高,此乃由於 低α粒子的錫鉛合金價格約爲一般錫鉛合金的十倍。另 外,當晶片110與基板(未繪示)覆晶接合之後,由於晶片 110與基板間的距離相鄰甚短,係利用毛細現象的原理’ 緩慢地塡入一塡充材料(u n d e r f i 11 )(未繪示)於晶片11 〇 與基板間,如此製程甚爲浪費時間,並且不易塡滿於晶片 7 本紙張尺度適用中國國家標準(CNS)A4規格mo X 297公釐) (請先閱讀背面之注音?事項 姒裝—— 寫本頁) 訂---------線 « 24twf.d〇c/〇 A7 '發明說明(<) i10與基板間。再者,由於晶片110與基板間的距離甚短, 使得曰皆 1】n 與基板迴焊焊合後,淸洗液難以從晶片110 輿基板間的繙_ Υ --------------裝--- (請先閱讀背面之注意事項m寫本頁) 流入,將助焊劑(flux)洗淨,使得助焊劑 殘口刀曰^ $ :曰110之主動表面112、基板及凸塊150上, ^此右疋在進行下一個製程時,會造成可靠度不高的問 /ξ§,fch ίπ ~ι ^ 填充材料(underfill)時,由於助焊液殘 留 曰 tir 1 1 ^ 〇及基板上,故主動表面112及基板表面並不 夺=、,、医1此塡充材料會難以順利地進行毛細塡入;並且塡 容易料^助焊齊U間的接合性不高,經過多次熱循環之後’ ^易使塡充材料與助焊劑間產生剝離(del aminat ion)的現 象,使得可靠度降低。 明的目的之一就是在提供一種覆晶晶片及 其製程,可以省去焊罩層的製作。 ^ 明的目的之二就是在提供一種覆晶晶片及其製 •線· 僅需進行一次以濺鍍的方式製作種子層,並且僅進行 〜次移除部份種子層之製程。 ㈡ 本發明的目的之三就是在提供一種覆晶晶片及其製 & ’可以增加晶片與基板間的距離,而提高晶片與基板接 經濟部智慧財產局員工消費合作社印製 合的可靠度。 ㈡ 本發明的目的之四就是在提供一種覆晶晶片及其製 & ’可以減少錫鉛合金之α粒子對晶片所造成的影響。 ^ 本發明的目的之五就是在提供一種覆晶晶片及其製 平壬’可以利用普通錫鉛合金來取代低α粒子錫鉛合金,即 可達到高效能的晶片運作,而普通錫鉛合金之材料成本甚 本紙張尺度1¾用中_家標準(CNS)A4規格⑵Qx 297公餐) 515016 7824twf.doc/0〇6 五、發明說明(q ) 低,如此可大幅降低覆晶晶片製作成本。 ' θ勺目的之六就是在提供一種覆晶晶片及其製 程’可以使^充材料較容易塡充於晶片與基板之間。 本發明的目的之七就是在提供一種覆晶晶片及其製 ^ ’可以,麟製程後職留的麟賺容易洗去。 爲Μ成本_之上述和其他目的,提出—種覆晶晶 片至夕巳括 晶片,具有一主動表面,並且晶片還具 有至少-焊墊’配窻在主動表面上;一絕緣層,配置在晶 片之主動表面上,絕緣層具有至少一絕緣層開口,絕緣層 開口暴露出焊塾;至少一金屬線路,配置在絕緣層上的空 間,而金屬線路還填充於絕緣層開口中,使金屬線路與焊 墊電性連接,至少〜金屬柱,金屬柱配置在金屬線路上; 至少一過渡體,過渡體配置在金屬柱上,其中過渡體之截 面積大於金屬柱的截面積;以及至少一焊塊,焊塊配置在 過渡體上。力外,依照本發明的一較佳實施例,其中金屬 柱的材質包括銅;過渡體的材質包括鎳,且過渡體暴露出 的下表面具有一氧化鎳層。再者,覆晶晶片還包括一種子 層,種子層位在垂屬線路與絕緣層、焊塾之間,而種子層 的材貞包括鈦、鎢化鈦、鉻或銅。金屬柱的高度介於丄〇 微米至100微米之間,而過渡體的厚度介於1微米至 微米之間-,過渡體邊緣至金屬柱邊緣的最短距離大於0.5 铽米。此外,過渡體具有一上表面及對應之一下表面,上 表面與焊塊接觸,下表面與金屬柱接觸,而在過渡體內, 位於上表面的金屬材質要能夠與焊塊互溶,位於該下表面 9 (請先閱讀背面之注意事項寫本頁) 項 I · I I I I--I ^ ·111111!,. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適$>國國家標準(CNS)Ai規格"(210 X 297公爱) 515016 7824twf.doc/006 A7 _B7___ 五、發明說明($ ) 的金屬材質係不易與焊塊產生互溶。 爲達成本發明之上述和其他目的,提出一種覆晶晶 片製程,其至少包括:提供一晶片,晶片具有一主動表面, 並且晶片還具有至少一焊墊,配置在主動表面上;進行一 形成絕緣層製程,使一絕緣層形成在晶片之主動表面上; 進行一製作絕緣層開口製程,以微影蝕刻的方式在絕緣層 中製作出至少一絕緣層開口,絕緣層開口暴露出焊墊;進 行一製作種子層製程,形成一種子層於絕緣層上、絕緣層 開口之側壁上及焊墊上;進行一第一微影製程,形成一第 一光阻在種子層上,並且曝光顯影使第一光阻製作出至少 一第一光阻開口,暴露出種子層及絕緣層開口;進行一塡 入金屬製程,塡入一金屬於絕緣層開口中及第一光阻開口 中,以形成一金屬線路於絕緣層開口中及第一光阻開口 中;進行一第一除去光阻製程,將第一光阻從種子層上除 去;進行一第二微影製程,形成一第二光阻在種子層上及 金屬線路上,並且曝光顯影使第二光阻製作出至少一第二 光阻開口,暴露出金屬線路;進行一製作金屬柱製程,形 成至少一金屬柱於第二光阻開口內,且位在金屬線路上; 進行一製作過渡體製程,製作至少一過渡體於該第二光阻 開口內,且位在該金屬柱上;進行一製作焊塊之製程,製 作至少一焊塊於第二光阻開口內,且位在過渡體上;進行 一第二除去光阻製程,將第二光阻從絕緣層上及金屬線路 上除去;進行一去除部份種子層製程,將暴露於外之種子 層去除;以及進行一去除部份金屬柱製程,去除金屬柱之 (請先閱讀背面之注意事項一^寫本頁) η 線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)Al規格(2〗0 X 297公釐) 515016 7824twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(q) 部份,使金屬柱的截面積小於過渡體的截面積。另外’依 照本發明的一較佳實施例,其中在進行去除部份金屬柱製 程後,還包括進行一熱氧化製程,使過渡體及金屬柱暴露 於外的區域氧化,或者亦可以將金屬柱及過渡體浸於氧化 劑中,以達到氧化的目的,其中氧化劑可以是雙氧水。另 外,依照本發明的一較佳實施例,其中金屬柱的材質包括 銅,過渡體的材質包括鎳,而種子層的材質包括欽、鎢化 鈦、鉻及銅。此外,過渡體的厚度介於1微米至10微米 之間,金屬柱的高度介於10微米至100微米之間’而過 渡體邊緣至該金屬柱邊緣的最短距離大於0.5微米。再者, 過渡體具有一上表面及對應之一下表面,上表面與焊塊接 觸,下表面與金屬柱接觸,而在過渡體內,位於上表面的 金屬材質要能夠與焊塊互溶,位於下表面的金屬材質不易 與焊塊發生互溶。另外,去除部份種子層製程及去除部份 金屬柱製程亦可以同時進行。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂,下文特舉一較佳實施例,並配合所附圖式,作 詳細說明如下: 圖式之簡單說明: 第1A圖至第1]圖繪示依照本發明一較佳實施例之 晶片上重配置線路結構體及凸塊之製程剖面放大示意圖。 第1K圖至第1M圖,其繪示依照本發明第二較佳實 施例的一種覆晶晶片製程對應於凸塊部份之剖面放大示意 圖。 (請先閱讀背面之注音?- 事項寫 本頁) Ρ1裝 ------訂--------線 « 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 515016 7824twf.doc/〇〇6 五、發明說明((〇 ) 第1N圖繪示依照本發明第三較佳實施例之一種半 導體晶片構裝。 --------------裝— (請先閱讀背面之注意事項HI寫本頁) 第10圖繪不依照本發明第四較佳實施例之一種半 導體晶片構裝。 第1P圖繪示依照本發明第五較佳實施例之一種半 導體晶片構裝。 第1Q圖繪示依照本發明第六較佳實施例之一種半 導體晶片構裝。 第2A圖至第2N圖繪示習知晶片上重配置線路結構 體及凸塊之製程剖面放大示意圖。 圖式之標示說明: 100、300 :覆晶晶片 110、310、700、900 :晶片 112、312 :主動表面 114、314 :保護層 116、316 :焊墊 118、318 :保護層開口 經濟部智慧財產局員工消費合作社印製 120、320 :絕緣層 122、322 :絕緣層開口 130、150、180、200、350、370 ··光阻 132、152、182、202、352、372 ··光阻開口 140、19〇、340、540 :種子層 164、364、564 :金屬線路 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 515016 7824twf.doc/006 ___Β7 五、發明說明(丨() 170 :焊罩層 172 :焊罩層開口 220、420、730、830、930、1030 :重配置線路結 構體 210、410、610、710、810、1010:凸塊 380、580 :金屬柱 382 :周圍表面 390、590 ··過渡體 392、592 :下表面 394 :上表面 396 :側邊 400、600、712 :焊塊 750、850、950 :基板 760、770 ··接點 790 :錫球 780、980 :封裝材料 882、982、1082 :塡充材料 1050 :印刷電路板 d =距離 實施例 第1A圖至第26圖繪示依照本發明一較佳實施例之 晶片上重配置線路結構體及凸塊之製程剖面放大示意圖, 爲詳盡敘述本發明的技術內容,僅繪示出晶片之焊墊區域 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項寫本頁) > I · n ϋ 1· 1 ·_1 n ϋ 一 I ϋ ϋ ϋ >ϋ ϋ ϋ I » ^16 ^16 A7 B7 ^24twf.d〇c/006 、發明說明((z) 的剖面放大圖。首先,請參照第1A圖,先提供一晶片310, 晶片310具有一主動表面312,並且晶片310還具有一保 護層314及至少一焊墊316,保護層314及焊墊316均位 在主動表面312上,保護層314具有至少一保護層開口 318,以暴露出焊墊316,其中保護層314的材質可以是二 氧化矽或氮化矽。接下來,以旋塗固化的方式在主動面上 形成一感光性的絕緣層320’其材質可以是感光性的聚亞 酿胺(Polyimide)。 請參照第1B圖,然後進行曝光顯影的製程,使得 絕緣層320在對應於焊墊316之上方處形成一絕緣層開口 322,以暴露出焊墊316。 請參照第1 c圖,接下來進行製作種子層製程,可 以利用濺鍍的方式,形成一種子層340於絕緣層320上、 絕緣層T开 1 口 322之側壁上及焊墊316上,其中種子層340 的材質可以是駄、鶴化欽、絡及銅。接下來,進行塗佈光 阻之製程,利用旋塗的方式,形成一光阻350於種子層340 上。 請參照第1D圖,然後進行曝光顯影的製程,使得 光阻350在欲形成金屬線路之處形成一光阻開口 352,以 暴露出種子層340。接下來,進行塡入金屬製程,可以利 用電鍍的方式,塡入一金屬於絕緣層開口 322中及光阻開 口 352中’以形成一金屬線路364於絕緣層開口 322中及 光阻開口 352中。接下來進行去除光阻製程,可以利用乾 式去光阻法或濕式去光阻法,將光阻350去除,使得種子 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) (請先閱讀背面之注意事項寫本頁) ^ --線. 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 515016 7824twf.doc/006 A7 _B7 _ 五、發明說明(丨>) 層340暴露於外。 請參照第1E圖,接下來,進行塗佈光阻之製程, 利用旋塗的方式,形成一光阻370於種子層340及金屬線 路364上。 請參照第1F圖,然後進行曝光顯影的製程,使得 光阻370在欲形成金屬柱、過渡金屬及焊塊之處形成至 少一光阻開口 372,以暴露出金屬線路364。接下來,進 行製作金屬柱製程,可藉由電鍍的方式,製作至少一金屬 柱380於光阻開口 372內,使金屬柱380配置在金屬線路 364上。金屬柱380的高度約介於10微米至100微米之間, 而其材質可以是銅。然後進行製作過渡體製程,可透過電 鍍的方式製作至少一過渡體390於金屬柱380上,而過渡 體390的高度約介於1微米至10微米之間,其材質可以 是鎳。然後進行一製作焊塊之製程,可以藉由電鍍的方式, 製作多個焊塊400於過渡體390上,而焊塊400的材質可 以是錫錯合金。 請參照第1G圖、第1H圖,接下來進行去除光阻製 程,可以利用乾式去光阻法或濕式去光阻法,將光阻370 去除,使得種子層340及金屬線路364暴露於外。 請參照第1H圖,然後進行去除部份金屬柱製程, 透過濕蝕刻的方式,從金屬柱380之側邊進行蝕刻,使金 屬柱380的截面積小於過渡體390的截面積,也使得過渡 體390的下表面392邊緣暴露於外。而距離d係爲過渡體 390邊緣至金屬柱380邊緣的最短距離,此距離最好大於 ·ϋ n I n ϋ n ϋ^_tfJI I ϋ an ϋ I ϋ n - (請先閱讀背面之注音?事項寫本頁) _#裝 寫夫V. Description of the invention (The seed layer 140 is exposed. Next, a metal-injection process is performed. Electroplating can be used to inject a metal into the insulating layer opening 122 and the photoresist opening Q 1 5 2 to form a metal. The circuit 16 4 is in the insulating layer opening 12 2 and the photoresist opening 152. Please refer to FIG. 2F and FIG. 2G, and then perform the photoresist removal process. The dry photoresist method or the wet photoresist method can be used. The photoresist 15 is removed to expose the seed layer 14Q. Then, a wet or dry etching process is performed to remove the seed layer 140 that is not covered by the metal circuit 164 to expose the insulating layer 120. Please refer to the figure in Table 2 Next, a process of manufacturing a solder mask layer may be performed, and a solder mask layer 70 (solder mask) may be formed on the insulating layer 120 and the metal circuit 164 by a spin coating method. Then, a photoresist coating process is performed by using a spin coating method. In the coating method, a photoresist 180 is formed on the solder mask layer 170. Please refer to FIG. 21, and then perform the exposure and development process, so that the photoresist 180 forms a light on the metal line 164 where a bump is to be formed. Stop opening 182 The solder mask layer 17 is exposed. Next, a wet etching or dry etching process is performed, and the solder mask layer 170 which is not covered by the photoresist 18 is etched away to form at least one solder mask layer opening 172, and the metal circuit 164 is exposed. The insulating layer 120 is exposed. Please follow the steps in Figure 21 and Figure 2], and then perform the photoresist removal process. The dry photoresist method or wet photoresist method can be used to remove the photoresist 18 °. The cover layer 170 is exposed to the outside. In this way, the steps of reconfiguring the circuit structure 220 are completed. § According to Figure 2K, the next step is to make a seed layer process. This paper size can be applied to the Chinese National Standard (CNS) A4 specification ( 21〇X 297 mm) (Please read the notes on the back to write this page first) ----- Order S 丨 丨 丨 丨!. Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 515016 5. Inventory (Zf) A sputtering method is used to form a sub-layer 190 on the solder mask layer 170, the sidewalls of the solder mask layer opening 172, and the metal circuit 164, wherein the material of the seed layer 190 may be copper. Next, coating light is applied. The process of resistance is formed by spin coating. A photoresist 200 is on the seed layer 190. Please refer to FIG. 2L, and then perform the exposure and development process, so that the photoresist 200 forms a photoresist opening 202 at the place where a bump is to be formed to expose the seed layer 190. Next In order to perform the metal intrusion process, a metal can be inserted into the photoresist opening 202 by electroplating to form a bump 210 in the photoresist opening 202. Please refer to FIG. 2L and FIG. 2M, and then proceed In the photoresist removal process, a dry photoresist method or a wet photoresist method can be used to remove the photoresist 200 to expose the seed layer 190 to the outside. Then, a wet etching or dry engraving process is performed, and the seed layer 190 not covered by the bump 210 is etched away to expose the solder mask layer 170. Referring to FIG. 2N, the reflow process is performed next, so that the bumps 21 are shaped into a spherical shape, so that the fabrication process of the flip-chip wafer 100 is completed. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -------------- Installation-(Please read the phonetic on the back? Matters write this page)-line; In addition, the flip chip structure In other words, as shown in FIG. 14, a flip-chip wafer 100 includes a wafer 110, an insulating layer 120, two seed layers 140, 190, at least one metal line 164, and at least one bump 21. The wafer 110 has an active surface 112, and the wafer 110 also has a protective layer π4 and at least--the pad 116. The protective layer 114 and the pad 116 are both located on the active surface 112, and the protective layer 114 has at least one protection. Layer openings 118 to expose the pads 116. The insulating layer 120 is located on the active surface 112 of the wafer 110. The paper size is applicable to the Chinese National Standard (CNS) / \ 4 specification (210 X 297 mm) ^ 50i6 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7824twf. doc / 006 _B7 5. In the description of the invention (^), the insulating layer 120 has an insulating layer opening 122, and the pad 116 of the wafer no is exposed. The seed layer 140 is disposed on the insulating layer 120, the sidewall of the opening 122 of the insulating layer, and the pad 116 of the wafer 110. The metal circuit 164 is positioned on the seed layer 140 and is inserted into the insulating layer opening 122. The solder mask layer 170 is located on the metal circuit 164 and the insulating layer 120, and the solder mask layer 170 has a solder mask layer opening 172 to expose the metal circuit 164. The seed layer 190 is located on the metal wiring 164, on the sidewall of the solder mask layer opening 170, and on the solder mask layer 170. The bump 210 is located on the seed layer 190. In the above process, the seed layers 140 and 190 are sputter-made twice, once after the insulation layer opening 122 is completed, and once after the solder mask layer opening Π2 is completed. Not even efficient. In addition, in the conventional technology, the solder mask layer 170 must also be fabricated to prevent the solder balls 210 from flowing freely during reflow, but in terms of manufacturing process, it is necessary to increase the steps of fabricating the solder mask layer 170. This process is very complicated. In addition, since the bump 210 is very close to the wafer 110, and the bump 210 is made of a tin-lead alloy, the alpha particles in the tin-lead alloy cause a soft error to the wafer 110, making An error occurred during memory access. If a low-particle tin-lead alloy is to be used as the bump 210, the manufacturing cost is greatly increased, because the price of a low-alpha tin-lead alloy is about ten times that of a general tin-lead alloy. In addition, after the wafer 110 is bonded to the substrate (not shown), since the distance between the wafer 110 and the substrate is very short, the principle of capillary phenomenon is used to slowly inject a filling material (underfi 11) ( (Not shown) between the wafer 11 〇 and the substrate, so the process is a waste of time, and it is not easy to be full of the wafer 7 This paper size applies the Chinese National Standard (CNS) A4 specification mo X 297 mm) (Please read the back Phonetic notation? Outfitting-write this page) Order --------- line «24twf.d〇c / 〇A7 'Invention (&); between i10 and substrate. In addition, because the distance between the wafer 110 and the substrate is very short, it is said that 1] n is re-soldered with the substrate, and the cleaning solution is difficult to flip from the wafer 110 to the substrate _ Υ -------- ------ Install --- (Please read the precautions on the back of this page to write this page) Inflow, wash the flux (flux), so that the flux residue knife ^ $: 110 of the active surface 112 On the substrate, and the bump 150, ^ this right will cause a low reliability problem when carrying out the next process / ξ§, fch ίπ ~ ι ^ At the time of underfill, due to the flux residue, tir 1 1 ^ 〇 and the substrate, so the active surface 112 and the surface of the substrate do not capture = ,,, and 1. The filling material will be difficult to smoothly penetrate into the capillary; and it is easy to predict the bonding between U and the solder. It is not high. After multiple thermal cycles, it is easy to cause del aminat ion between the filling material and the flux, which reduces the reliability. One of the goals of Ming is to provide a flip-chip wafer and its manufacturing process, which can eliminate the production of a solder mask layer. ^ The second purpose of Ming is to provide a flip-chip wafer and its fabrication. • The wire only needs to make the seed layer by sputtering once, and only ~ to remove part of the seed layer.三 The third object of the present invention is to provide a flip-chip wafer and its fabrication & ' that can increase the distance between the wafer and the substrate, and improve the reliability of the wafer-substrate connection with the printing and bonding of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs.四 The fourth object of the present invention is to provide a flip-chip wafer and its fabrication & ', which can reduce the effect of the alpha particles of tin-lead alloy on the wafer. ^ The fifth objective of the present invention is to provide a flip-chip wafer and a flat wafer made therefrom. Ordinary tin-lead alloys can be used instead of low-alpha particle tin-lead alloys to achieve high-efficiency wafer operation. The cost of materials is even lower than the standard paper size of the paper. The standard is CNS A4 (Qx 297). 515016 7824twf.doc / 0〇 5. The invention description (q) is low, which can greatly reduce the production cost of flip-chip wafers. 'The sixth purpose of θ spoon is to provide a flip-chip wafer and its process', which can make filling materials between the wafer and the substrate easier. The seventh object of the present invention is to provide a flip-chip wafer and a manufacturing method thereof. For the above and other purposes of the M cost, it is proposed that-a flip-chip wafer to a wafer including an active surface, and the wafer also has at least-pads on the active surface; an insulating layer, disposed on the wafer On the active surface, the insulating layer has at least one opening of the insulating layer, and the opening of the insulating layer exposes the welding pad; at least one metal circuit is arranged in the space on the insulating layer, and the metal circuit is also filled in the opening of the insulating layer, so that the metal circuit and the The pads are electrically connected, at least ~ metal pillars, and the metal pillars are arranged on the metal line; at least one transition body, the transition body is arranged on the metal pillar, wherein the cross-sectional area of the transition body is greater than the cross-sectional area of the metal pillar; and at least one solder block The solder bumps are arranged on the transition body. In addition, according to a preferred embodiment of the present invention, the material of the metal pillars includes copper; the material of the transition body includes nickel, and the exposed lower surface of the transition body has a nickel oxide layer. In addition, the flip-chip wafer also includes a sub-layer, the seed layer is located between the vertical line and the insulation layer, the solder pad, and the material of the seed layer includes titanium, titanium tungsten, chromium or copper. The height of the metal pillar is between 100 micrometers and 100 micrometers, and the thickness of the transition body is between 1 micrometer and micrometer-. The shortest distance from the edge of the transition body to the edge of the metal pillar is greater than 0.5 mm. In addition, the transition body has an upper surface and a corresponding lower surface. The upper surface is in contact with the solder bump and the lower surface is in contact with the metal pillar. In the transition body, the metal material on the upper surface must be compatible with the solder bump and be located on the lower surface. 9 (Please read the notes on the back first to write this page) Item I · III I--I ^ · 111111!,. Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economy Paper size is suitable for National Standards (CNS) Ai specifications " (210 X 297 public love) 515016 7824twf.doc / 006 A7 _B7___ 5. The metal material of the invention description ($) is not easy to be miscible with the solder bump. In order to achieve the above and other objectives of the present invention, a flip-chip wafer manufacturing process is provided, which at least includes: providing a wafer, the wafer having an active surface, and the wafer also having at least one solder pad disposed on the active surface; and performing an insulation formation Layer process, so that an insulating layer is formed on the active surface of the wafer; an insulating layer opening process is performed, at least one insulating layer opening is made in the insulating layer by means of lithographic etching, and the insulating layer opening exposes a solder pad; A process of making a seed layer, forming a sub-layer on the insulating layer, the sidewall of the opening of the insulating layer, and the pad; performing a first lithography process to form a first photoresist on the seed layer, and exposing and developing the first layer The photoresist produces at least one first photoresist opening, exposing the seed layer and the insulating layer opening; performing a metal intrusion process, injecting a metal into the insulating layer opening and the first photoresist opening to form a metal circuit In the opening of the insulating layer and in the first photoresist opening; performing a first photoresist removal process to remove the first photoresist from the seed layer; and performing a second Lithography process, forming a second photoresist on the seed layer and the metal circuit, and exposing and developing the second photoresist to make at least one second photoresist opening, exposing the metal circuit; performing a metal pillar process to form At least one metal pillar is located in the second photoresistive opening and is located on the metal circuit; a transition process is performed to produce at least one transition body in the second photoresistive opening and is located on the metal pillar; A process of making a solder bump, making at least one solder bump in a second photoresist opening and located on a transition body; performing a second photoresist removal process to remove the second photoresist from the insulating layer and the metal circuit; Perform a process of removing part of the seed layer to remove the exposed seed layer; and perform a process of removing part of the metal pillar to remove the metal pillar (please read the precautions on the back first ^ write this page) η Line · Economy Printed by the Ministry of Intellectual Property Bureau ’s Consumer Cooperatives The paper size applies to the Chinese National Standard (CNS) Al Specification (2〗 0 X 297 mm) 515016 7824twf.doc / 006 A7 B7 Employees ’Intellectual Property Bureau Ministry of Economic Affairs ’s consumer cooperation Printed V. Description of the Invention (q) partial, cross-sectional area of the metal post is less than the cross-sectional area of the transition body. In addition, according to a preferred embodiment of the present invention, after performing a process of removing a part of the metal pillars, a thermal oxidation process is further performed to oxidize the transition body and the exposed regions of the metal pillars, or the metal pillars may be oxidized. And the transition body is immersed in an oxidant to achieve the purpose of oxidation, wherein the oxidant may be hydrogen peroxide. In addition, according to a preferred embodiment of the present invention, the material of the metal pillars includes copper, the material of the transition body includes nickel, and the material of the seed layer includes copper, titanium tungsten, chromium, and copper. In addition, the thickness of the transition body is between 1 micrometer and 10 micrometers, the height of the metal pillar is between 10 micrometers and 100 micrometers', and the shortest distance from the edge of the transition body to the edge of the metal pillar is greater than 0.5 micrometer. Furthermore, the transition body has an upper surface and a corresponding lower surface. The upper surface is in contact with the solder bump and the lower surface is in contact with the metal pillar. In the transition body, the metal material on the upper surface must be compatible with the solder bump and be on the lower surface. The metal material is not easily miscible with the solder bump. In addition, the process of removing part of the seed layer and the process of removing part of the metal pillars can be performed simultaneously. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A To FIG. 1] is an enlarged schematic cross-sectional view of a process for reconfiguring a circuit structure and a bump on a wafer according to a preferred embodiment of the present invention. Figures 1K to 1M are enlarged schematic cross-sectional views corresponding to bump portions of a flip-chip wafer process according to a second preferred embodiment of the present invention. (Please read the phonetic on the back?-Matters to write on this page) P1 Pack ------ Order -------- Line «This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 515016 7824twf.doc / 〇〇6 5. Description of the invention ((〇) Figure 1N shows a semiconductor wafer structure according to the third preferred embodiment of the present invention. ----------- --- Packing- (Please read the note on the back HI first to write this page) Figure 10 shows a semiconductor wafer structure that does not follow the fourth preferred embodiment of the present invention. Figure 1P shows the fifth comparison according to the present invention. A semiconductor wafer structure according to a preferred embodiment. FIG. 1Q shows a semiconductor wafer structure according to a sixth preferred embodiment of the present invention. FIGS. 2A to 2N show reconfiguration circuit structures on a conventional wafer and FIG. An enlarged schematic cross-sectional view of the process of the bumps. Symbols of the drawings: 100, 300: flip-chip wafers 110, 310, 700, 900: wafers 112, 312: active surfaces 114, 314: protective layers 116, 316: pads 118, 318: Protective layer opening Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 120, 320: Insulating layer 122, 322: Insulating layer opening 130, 150, 180, 200, 350, 370 photoresist 132, 152, 182, 202, 352, 372 photoresist opening 140, 19, 340, 540: seed layer 164, 364, 564: metal circuit This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 515016 7824twf.doc / 006 ___B7 V. Description of the invention (丨 () 170: Welding cover layer 172 : Welding mask layer openings 220, 420, 730, 830, 930, 1030: Reconfiguration line structure 210, 410, 610, 710, 810, 1010: Bumps 380, 580: Metal pillars 382: Peripheral surfaces 390, 590 Transition bodies 392, 592: lower surface 394: upper surface 396: sides 400, 600, 712: solder bumps 750, 850, 950: substrates 760, 770, contact 790: solder balls 780, 980: packaging material 882 , 982, 1082: Rechargeable material 1050: Printed circuit board d = Figures 1A to 26 of the embodiment illustrate the process of reconfiguring a circuit structure and a bump on a wafer according to a preferred embodiment of the present invention. Schematic drawing, in order to describe the technical content of the present invention in detail, only the pad pad area of the wafer is shown. Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the notes on the back to write this page) > I · n ϋ 1 · 1 · _1 n ϋ I I ϋ ϋ gt > ϋ »ϋ I» ^ 16 ^ 16 A7 B7 ^ 24twf.doc / 006, enlarged sectional view of the description of the invention ((z). First, please refer to FIG. 1A. First, a wafer 310 is provided. The wafer 310 has an active surface 312, and the wafer 310 also has a protective layer 314 and at least one solder pad 316. The protective layer 314 and the solder pad 316 are both located on the active surface. On 312, the protective layer 314 has at least one protective layer opening 318 to expose the bonding pad 316. The material of the protective layer 314 may be silicon dioxide or silicon nitride. Next, a photosensitive insulation layer 320 'is formed on the active surface by spin coating and curing, and the material may be photosensitive polyimide. Referring to FIG. 1B, a process of exposure and development is performed, so that the insulating layer 320 forms an insulating layer opening 322 above the corresponding pad 316 to expose the pad 316. Please refer to FIG. 1c. Next, a seed layer manufacturing process is performed. A sub-layer 340 can be formed on the insulating layer 320, the side wall of the insulating layer T opening 322, and the bonding pad 316 by sputtering. The material of the seed layer 340 may be 駄, He Huaqin, Luo, and copper. Next, a photoresist coating process is performed, and a photoresist 350 is formed on the seed layer 340 by spin coating. Referring to FIG. 1D, a process of exposure and development is performed, so that the photoresist 350 forms a photoresist opening 352 at a place where a metal circuit is to be formed to expose the seed layer 340. Next, a metal intrusion process is performed, and a metal can be infiltrated into the insulating layer opening 322 and the photoresist opening 352 by electroplating to form a metal line 364 in the insulating layer opening 322 and the photoresist opening 352. . Next, the photoresist removal process can be performed. The photoresist 350 can be removed using dry or wet photoresist, so that the paper size of the seed can be applied to the Chinese National Standard (CNS) A4 specification (210 x 297 mm). (Please read the notes on the back first to write this page) ^-Line. Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 515016 7824twf.doc / 006 A7 _B7 _ 5. Description of the Invention (丨 >) The layer 340 is exposed to the outside. Please refer to FIG. 1E. Next, a photoresist coating process is performed, and a photoresist 370 is formed on the seed layer 340 and the metal line 364 by spin coating. Please refer to FIG. 1F, and then perform the exposure and development process, so that the photoresist 370 forms at least one photoresist opening 372 at the place where the metal pillars, transition metals and solder bumps are to be formed to expose the metal wiring 364. Next, a metal pillar manufacturing process is performed. At least one metal pillar 380 can be fabricated in the photoresist opening 372 by electroplating, so that the metal pillar 380 is disposed on the metal circuit 364. The height of the metal pillar 380 is between about 10 micrometers and about 100 micrometers, and the material of the metal pillar 380 can be copper. Then, a transition process is performed, and at least one transition body 390 can be fabricated on the metal pillar 380 by electroplating. The height of the transition body 390 is about 1 micrometer to 10 micrometers, and the material can be nickel. Then, a process of making solder bumps is performed. A plurality of solder bumps 400 can be fabricated on the transition body 390 by electroplating, and the material of the solder bumps 400 can be tin alloy. Please refer to FIG. 1G and FIG. 1H. Next, the photoresist removal process is performed. The photoresist 370 can be removed by using a dry photoresist method or a wet photoresist method, so that the seed layer 340 and the metal circuit 364 are exposed to the outside. . Please refer to FIG. 1H, and then perform a process of removing part of the metal pillars. Wet etching is used to etch from the side of the metal pillars 380 so that the cross-sectional area of the metal pillars 380 is smaller than the cross-sectional area of the transition body 390. The edge of the lower surface 392 of 390 is exposed. The distance d is the shortest distance from the edge of the transition body 390 to the edge of the metal pillar 380. This distance is preferably greater than · ϋ n I n ϋ n ϋ_tfJI I ϋ an ϋ I ϋ n-(Please read the note on the back? (Write this page) _ # 装 写 夫
本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 515016 7824twf.doc/006 A7 B7 ^___ 經濟部智慧財產局員工消費合作社印製 發明說明(A/0 -------------裝--- (請先閱讀背面之注意事項Hi寫本頁) 0.5微米。如此暴露於外的過渡體390與金屬柱380,會 與空氣進行氧化,其中過渡體390的側邊396及其下表面 392邊緣會形成一鎳氧化物層,而金屬柱380的周圍表面 382會形成一銅氧化物層。若是再進行一熱氧化(Thermal Oxidation)製程,可以使過渡體390及金屬柱380暴露於 外的區域氧化更完全。或者亦可以將金屬柱380及過渡體 390浸於氧化劑中,以達到氧化的目的,其中氧化劑可以 是雙氧水。 請參照第π圖、第1〗圖,然後進行濕蝕刻或乾蝕 刻製程,將未受金屬線路364覆蓋的種子層340蝕刻去掉, 以暴露出絕緣層320。如此重配置線路結構體420便製作 完成,其中重配置線路結構體420僅具有絕緣層320、種 子層340及金屬線路364。 •線: 請參照第1J圖,最後進行一迴焊製程,利用加熱 的方式使焊塊400軟化而形成類似球體之形狀’如此凸塊 410的製作即完成,其中凸塊410係由金屬柱380、過渡 體390、焊塊400所組成,而晶片310可以透過凸塊410 與基板(未繪示)電性接合。然而就鎳與錫鉛合金的金屬特 性而言,鎳與錫鉛合金相互間的表面張力甚小’因此錫給 合金會在鎳金屬的表面上快速擴散流動;然而鎳的氧化物 與錫鉛合金相互間的表面張力甚大,因此錫錯合金不易在 鎳氧化物的表面上快速擴散流動,而聚集在一起。在進行 此迴焊製程時,由於過渡體390的側邊396及下表面392 的邊緣暴露於外,並且過渡體390的材質係爲錬’而錬會 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 515〇l6 7824twf.doc/006 __B7__________ i、發明說明(γ) 與氧作用而形成鎳的氧化物,因此加熱軟化時的焊塊400 不會流至過渡體390的側邊396及其下表面392,而黏附 在過渡體390的上表面394。同時焊塊400與過渡體39〇 間的互溶速度不能太快,否則焊塊400也容易從金屬柱380 上崩潰下來,因此過渡體390必須要有足夠的厚度以承受 焊塊400在迴焊時與過渡體390產生的互溶效果。 而過渡體390的材質並非只限於鎳’亦可以是複合 材料,由多層金屬所疊合而成,只要是位於上表面394的 金屬能夠與焊塊400互溶,而位於下表面392的金屬是不 易與焊塊400互溶的金屬即可。 然而在上述製程中,即使過渡體390及金屬柱380 暴露於外的表面沒有氧化的情形發生’在進行迴焊的時 候,焊塊400就可以順利地形成在過渡體390上。但是一 般而言,過渡體390及金屬柱380均會在凸塊410製作過 程中氧化,如此更可以確保在迴焊時焊塊400不會從金屬 柱380上崩潰下來。然而若是再進行一道熱氧化製程,使 過渡體390及金屬柱380暴露於外的區域氧化更完全,如 此更可以進一步確保其在迴焊時,焊塊400不會滑落到過 渡體390邊緣及其下表面。或者亦可以將金屬柱380及過 渡體390浸於氧化劑中,以達到氧化的目的,其中氧化劑 可以是雙氧水。 如上所述,由於焊塊400形成在過渡體390上,因 此不論在進行迴焊時,或在進行焊塊400與基板的接合時, 藉由過渡體390的作用’可以使焊塊400不會崩落到金屬This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 515016 7824twf.doc / 006 A7 B7 ^ ___ Description of Inventions printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (A / 0 ----- -------- Packing --- (Please read the note on the back Hi first to write this page) 0.5 micron. The transition body 390 and metal pillar 380 exposed in this way will be oxidized with air, among which the transition body A nickel oxide layer is formed on the side 396 of the 390 and the edge of the lower surface 392, and a copper oxide layer is formed on the peripheral surface 382 of the metal pillar 380. If a thermal oxidation process is performed, the transition may be performed. The exposed areas of the body 390 and the metal pillar 380 are more completely oxidized. Alternatively, the metal pillar 380 and the transition body 390 may be immersed in an oxidant to achieve the purpose of oxidation, wherein the oxidant may be hydrogen peroxide. Please refer to the figure π, 1〗 map, and then perform a wet or dry etching process to etch away the seed layer 340 that is not covered by the metal circuit 364 to expose the insulating layer 320. The reconfiguration circuit structure 420 is thus completed, and the circuit structure is reconfigured Body 4 20 has only an insulating layer 320, a seed layer 340, and a metal line 364. • Wire: Please refer to Figure 1J, and finally perform a reflow process to soften the solder block 400 by heating to form a sphere-like shape. The production of 410 is completed, wherein the bump 410 is composed of a metal pillar 380, a transition body 390, and a solder bump 400, and the wafer 310 can be electrically bonded to a substrate (not shown) through the bump 410. However, nickel and tin In terms of the metal properties of lead alloys, the surface tension between nickel and tin-lead alloys is very small. Therefore, the tin-to-alloy will rapidly diffuse and flow on the surface of nickel metals; however, the surface tension between nickel oxides and tin-lead alloys It is very large, so tin alloy is not easy to diffuse and flow quickly on the surface of nickel oxide, and gather together. During this reflow process, the side 396 of the transition body 390 and the edge of the lower surface 392 are exposed to the outside, and The material of the transition body 390 is 錬 ', and the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 515〇16 7824twf.doc / 006 __B7__________ i. Description of the invention (γ) It reacts with oxygen to form nickel oxide, so the solder bump 400 during heating and softening does not flow to the side 396 and the lower surface 392 of the transition body 390, but adheres to the upper surface 394 of the transition body 390. At the same time, the solder pad 400 The rate of mutual dissolution with the transition body 39o cannot be too fast, otherwise the solder bump 400 will easily collapse from the metal pillar 380, so the transition body 390 must have sufficient thickness to withstand the solder bump 400 and the transition body 390 during re-soldering. The resulting miscibility effect. The material of the transition body 390 is not limited to nickel. It can also be a composite material, which is made of multiple layers of metal. As long as the metal on the upper surface 394 can be miscible with the solder bump 400, the metal on the lower surface 392 is not easy. A metal that is miscible with the solder bump 400 is sufficient. However, in the above process, even if the surface of the transition body 390 and the metal pillar 380 exposed to the outside is not oxidized ', the solder bump 400 can be smoothly formed on the transition body 390 when the reflow is performed. However, in general, both the transition body 390 and the metal pillar 380 are oxidized during the fabrication of the bump 410, which can further ensure that the solder bump 400 does not collapse from the metal pillar 380 during re-soldering. However, if another thermal oxidation process is performed, the exposed areas of the transition body 390 and the metal pillars 380 are more fully oxidized, which can further ensure that during the reflow, the solder bump 400 will not slide to the edge of the transition body 390 and its edges. lower surface. Alternatively, the metal column 380 and the transition body 390 can also be immersed in an oxidant to achieve the purpose of oxidation. The oxidant may be hydrogen peroxide. As described above, since the solder bump 400 is formed on the transition body 390, the solder bump 400 can be prevented by the action of the transition body 390 regardless of the reflow soldering or bonding of the solder bump 400 to the substrate. Falling to metal
(請先閱讀背面之注咅?事項I 裝·! !1 訂-------I ·線 寫· Γ本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 515016 7824twf.doc/006 Λ7 五、發明說明(A) 線路3 6 4上,故本發明可以省去製作焊罩層的步驟。 另外,就覆晶晶片結構而言,如第26圖所示,一 覆晶晶片300包括一晶片310、一絕緣層320、種子層340、 190、至少一金屬線路364、至少一金屬柱380、至少一過 渡體390及至少一焊塊400。晶片3 10具有一主動表面312, 並且晶片310還具有一保護層314及至少一焊墊316,保 護層314及焊墊316均位在主動表面312上,保護層314 具有至少一保護層開口 318,以暴露出焊墊316。絕緣層320 係位在晶片310之主動表面312上,絕緣層320具有一絕 緣層開口 322,暴露出晶片310之焊墊316。種子層340 係配置在絕緣層320上、絕緣層開口 322之側壁上及晶片 310之焊墊316上。金屬線路364係位在種子層340上及 絕緣層開口 322中。金屬柱380係配置在金屬線路364上。 過渡體390配置在金屬柱上,其中過渡體390之截面積大 於金屬柱380的截面積。焊塊400配置在過渡體390上。 請參照第1J圖,在上述的製程中,由於焊塊400 並不會崩潰下來,而可以穩固地附著在過渡體390之上表 面上394,因此在製作重配置線路結構體420時,可以省 下製作焊罩層的步驟。另外,在上述的製程中,僅需進行 一次以濺鍍的方式製作種子層340,在製程上甚具效率性。 此外,由於凸塊410係由焊塊400、過渡體390及金屬柱 380所組成,因此可以在不縮減甚至增加晶片310與基板 間之距離的情況下,大幅地減少凸塊410的體積,同時可 以縮短相鄰凸塊410間的距離。另外,相較於習知技藝凸 18 本纸張尺度適用中國國家標準(CNS)A〗規格(2丨公釐) -------------裝--- (請先閱讀背面之注意事項寫本頁) 0 .線. 經濟部智慧財產局員工消費合作社印製 515016 7824twf . doc/006 y\7 _____B7 五、發明說明(q) ------I------^ i I (請先閱讀背面之注意事寫本頁) .線- 經濟部智慧財產局員工消費合作社印製 塊的形式,由於本發明之錫鉛焊塊400距離晶片表面較遠, 故錫鉛合金內的α粒子對晶片31〇造成軟錯記(soft error·) 的問題會減少’進而可減少記憶體資料存取發生錯誤,其 效能甚至可以達到以低α粒子錫鉛合金作爲習知凸塊結構 的材料所展現的效能;如上所述,本發明之焊塊400可以 利用普通錫鉛合金來取代低α粒子錫鉛合金,即可達到高 效能的晶片運作,而普通錫鉛合金之材料成本甚低,如此 可大幅降低覆晶晶片製作成本。而普通的錫給合金之材料 成本甚低,故可以大幅降低覆晶晶片製作的成本。此外, 由於本發明可以透過金屬柱380將晶片310與基板間的距 離墊得更高,並且金屬柱380的線徑甚細微,再者,金屬 柱380所使用的材質爲銅,銅的延展性甚佳,如此凸塊410 可以容忍晶片310與基板間因熱而產生之較大的變形,提 高晶片310與基板接合的可靠度。並且透過金屬柱380墊 高後的覆晶晶片,在進行覆晶製程時,可以較容易且迅速 地塡入一塡充材料(underfill)於晶片310與基板間。而 藉由金屬柱380墊高後的晶片310,當晶片310與基板迴 焊焊合後,淸洗液也較容易流入到晶片310與基板間的縫 隙’如此可以將迴焊製程後所殘留的助焊劑(flux)淸除得 較乾淨。 請參照第1K圖至第1M圖,其繪示依照本發明第二 較佳實施例的一種覆晶晶片製程對應於凸塊部份之剖面放 大示意圖。在前述的第一較佳實施例中,係先對金屬柱進 行側向蝕刻,接下來再對種子層進行蝕刻,然而本發明之 本紙張尺度適用中國國家標準(CNSM·〗规格(210 X四7公釐) 515016 五、發明說明(β) 製程並非侷限於上述方式,亦可以是其他方式’如下所述。 請參照第1Κ圖、第1L圖,本實施例所述的製程大 致與第一較佳實施例雷同,只是其去除部份金屬柱製程與 蝕刻種子層製程的順序與第一較佳實施例所述的順序相 反。在本實施例中,在進行完去除光阻製程後(接弟2 3 Η ) ’ 便進行蝕刻種子層製程,可以藉由反應性離子蝕刻 (Reactive Ion Etch,RIE)的方式,將種子層540在未被 金屬線路564覆蓋的區域去除。 請參照第1L圖,然後再進行去除部份金屬柱製程’ 透過濕蝕刻的方式,從金屬柱580之側邊進行蝕刻’使金 屬柱580的截面積小於過渡體590的截面積,也使得過渡 體590的下表面592邊緣暴露於外。 請參照第1M圖,最後再進行迴焊製程’利用加熱 的方式使焊塊600軟化而成類似球體之形狀’如此凸塊610 的製作即完成。 另外,當金屬柱與種子層的材質在一樣的情況下’ 比如金屬柱與種子層的材質均爲銅,其可以利用等向性蝕 刻的方式,同時將金屬柱的側邊及種子層去除,如此可以 省去一道製程步驟。 本發明的覆晶晶片製作完成之後,可以與球格陣列 基板接合,如第1N圖所示,其繪示依照本發明第三較佳 實施例之一種半導體晶片構裝。當製作完凸塊710之後, 便進行接合之製程,透過迴焊的步驟可以藉由焊塊712使 晶片700與基板750正面之接點76〇接合。然後再進行封 20 本紙張尺度適用中國國家標準(CNS)A丨规恪(21〇χ 297公釐) -------------裝—— (請先閱讀背面之注意事項寫本頁) · --線· 經濟部智慧財產局員工消費合作社印製 7824twf.d〇c/〇〇6 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明((,) 膠之製程,使一封裝材料 7,π 枓78()包覆晶片700、重配置線路 結構體730、凸塊710。 _ 取俊,再進行植球的動作,可以 植上多個錫球790到基板75〇背 然而本發明的封裝方式亦 回%— 丨衣万式亦可以是其他的形式,如第 1〇圖所不,其繪示依昭t益m〜^ 众…、本發明弟四較佳實施例之一種半導 體曰曰片構衣。-塡充材料Μ2係塡充於重配置線路結構體 830,、基板850之間,並且塡充材料撕包覆凸塊81〇及 重配置線路結構體830的周圍。另外,如第1P圖所示, 其繪示依照本發明第五較佳實施例之一種半導體晶片構 裝。當塡充材料982塡充於重配置線路結構體93〇與基板 950之間後’還可以利用一封裝材料98〇將晶片9〇〇及塡 充材料982包覆住。 本發明的覆晶晶片製作完成之後,亦可利用直接晶 片貼覆(direct chip attach,DCA)的方式,直接接合在 印刷電路板上,如第1Q圖所示,其繪示依照本發明第六 較佳實施例之一種半導體晶片構裝。晶片1000係直接接 合於印刷電路板1050上,而一塡充材料1082係塡充於重 配置線路結構體1030與印刷電路板1050之間,並且塡充 材料1082包覆凸塊1010及重配置線路結構體1030的周 圍。 綜上所述,本發明至少具有下列優點: 1 .本發明之覆晶晶片及其製程’由於由於焊塊並不 會崩潰下來,而可以穩固地附著在過渡體之上表面上’因 此在製作重配置線路結構體時’可以省下製作焊罩層的步 (請先閱讀背面之注意事項Λ寫本頁) Μ 裝 ΟΓ-ΰ. •線· 本紙張&度適用中國國家標準(CNS)Al規烙(21〇χ^7公堃) 515016 五、發明說明( 驟。 2.本發明之覆晶晶片及其製程,由於僅需進行一次 以濺鍍的方式製作種子層,並且僅進行一次移除部份種子 層之製程,在製程上甚具效率性。 3 .本發明之覆晶晶片及其製程’由於凸塊係由焊 塊、過渡體及金屬柱所組成,因此可以在不縮減晶片與基 板間之距離的情況下,大幅地減少凸塊的體積’同時可以 縮短相鄰凸塊間的距離。 4. 本發明之覆晶晶片及其製程,由於錫鉛合金凸塊 距離晶片表面較遠,故錫鉛合金內的α粒子對晶片造成軟 錯記的問題會減少,進而可降低記憶體資料存取錯誤的發 生。 5. 本發明之覆晶晶片及其製程,由於焊塊可以利用 普通錫鉛合金來取代低α粒子錫鉛合金,即可達到高效能 的晶片運作,而普通錫鉛合金之材料成本甚低,如此可大 幅降低覆晶晶片製作成本。 6·本發明之覆晶晶片及其製程,由於凸塊之金屬柱 的線徑甚細微,且其所使用的材質爲銅,而銅的延展性甚 佳,故凸塊可以容忍晶片與基板間因熱而產生之較大的變 形。 7·本發明之覆晶晶片及其製程,透過金屬柱墊高後 的覆晶晶片,在進行覆晶製程時,可以較容易塡入一塡充 材料於晶片與基板間。 ~ 、 8.本發明之覆晶晶片h製程,藉由金屬柱墊高後 -------------裝— (請先閱讀背面之注音?事項HI寫本頁) 訂·· --線- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A.'l規恪(210 X 297^^^ 515016 7824twf.doc/006 Λ7 B7 五、發明說明( 的晶片,當晶片與基板迴焊焊合後,淸洗液也較容易流入 到晶片與基板間的縫隙,如此可以將迴焊製程後所殘留的 助焊劑淸除得較乾淨。 雖然本發明已以一較佳實施例揭露如上,然其並非 用以限定本發明,任何熟習此技藝者,在不脫離本發明之 精神和範圍內,當可作些許之更動與潤飾,因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 ---— — — — — — —--- - · 11 (請先閱讀背面之注意事項HI寫本頁) 訂· 線· 經濟部智慧財產局員工消費合作社印製 23 本'氏張尺/Xi_中國國家標準(CNSM1縣⑵Οχ 297公髮)(Please read the note on the back first? Matters I Packing !!!!! 1 Order ------- I · Line Writing · Γ This page) Printed on paper standards of the Ministry of Economic Affairs and Intellectual Property Bureau Staff Consumer Cooperatives This paper applies Chinese national standards (CNS) A4 specification (210 X 297 mm) 515016 7824twf.doc / 006 Λ7 V. Description of the invention (A) On line 3 64, the present invention can omit the step of making a solder mask layer. In addition, as for the flip-chip wafer structure, as shown in FIG. 26, a flip-chip wafer 300 includes a wafer 310, an insulating layer 320, a seed layer 340, 190, at least one metal line 364, at least one metal pillar 380, At least one transition body 390 and at least one solder bump 400. The wafer 3 10 has an active surface 312, and the wafer 310 also has a protective layer 314 and at least one solder pad 316, the protective layer 314 and the solder pad 316 are both located on the active surface 312, and the protective layer 314 has at least one protective layer opening 318 To expose the pad 316. The insulating layer 320 is located on the active surface 312 of the wafer 310. The insulating layer 320 has an insulating layer opening 322, and the pads 316 of the wafer 310 are exposed. The seed layer 340 is disposed on the insulating layer 320, on the sidewall of the opening 322 of the insulating layer, and on the pad 316 of the wafer 310. The metal line 364 is located on the seed layer 340 and in the insulating layer opening 322. The metal pillar 380 is arranged on the metal line 364. The transition body 390 is disposed on a metal pillar, and the cross-sectional area of the transition body 390 is larger than the cross-sectional area of the metal pillar 380. The solder bump 400 is disposed on the transition body 390. Please refer to FIG. 1J. In the above-mentioned process, since the solder bump 400 does not collapse, it can be firmly attached to the upper surface 394 of the transition body 390. Therefore, when the reconfiguration circuit structure 420 is produced, it can be saved. The steps for making a solder mask layer are as follows. In addition, in the above process, the seed layer 340 only needs to be produced by sputtering once, which is very efficient in the process. In addition, since the bump 410 is composed of the solder bump 400, the transition body 390, and the metal pillar 380, the volume of the bump 410 can be greatly reduced without reducing or even increasing the distance between the wafer 310 and the substrate, and at the same time The distance between adjacent bumps 410 can be shortened. In addition, compared with the known skills, 18 paper sizes are applicable to the Chinese National Standard (CNS) A. Specification (2 丨 mm) ------------- Loading --- (please first (Read the notes on the back to write this page) 0. Line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 515016 7824twf. Doc / 006 y \ 7 _____B7 V. Description of the invention (q) ------ I --- --- ^ i I (Please read the note on the back first to write this page). Line-The printed form of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, because the tin-lead solder 400 of the present invention is far from the surface of the wafer, Therefore, the α particles in the tin-lead alloy cause soft errors to the wafer 31. The problem of soft errors will be reduced, thereby reducing memory data access errors, and its performance can even be achieved with low-alpha particles of tin-lead alloy. The effectiveness exhibited by the materials of the conventional bump structure; as described above, the solder bump 400 of the present invention can use ordinary tin-lead alloys instead of low-alpha particles tin-lead alloys to achieve high-efficiency wafer operation. The material cost of the alloy is very low, which can greatly reduce the manufacturing cost of flip-chip wafers. However, the cost of ordinary tin-to-alloy materials is very low, so the cost of manufacturing flip-chip wafers can be greatly reduced. In addition, the present invention can pad the distance between the wafer 310 and the substrate higher through the metal pillar 380, and the wire diameter of the metal pillar 380 is very small. Furthermore, the material used for the metal pillar 380 is copper, and the ductility of copper is used. Very good, such a bump 410 can tolerate large deformation caused by heat between the wafer 310 and the substrate, and improve the reliability of bonding between the wafer 310 and the substrate. In addition, the flip-chip wafer that has been lifted through the metal pillars 380 can be easily and quickly filled with an underfill between the wafer 310 and the substrate during the flip-chip process. By using the metal pillar 380 to raise the wafer 310, after the wafer 310 and the substrate are re-soldered, the cleaning solution also flows into the gap between the wafer 310 and the substrate more easily. The flux is removed relatively cleanly. Please refer to FIG. 1K to FIG. 1M, which are schematic enlarged cross-sectional views of a flip-chip wafer process corresponding to a bump portion according to a second preferred embodiment of the present invention. In the foregoing first preferred embodiment, the metal pillars are first etched sideways, and then the seed layer is etched. However, the paper size of the present invention is applicable to the Chinese National Standard (CNSM · 〖Specification (210 X4) 7mm) 515016 5. Description of the invention (β) The process is not limited to the above method, but may be other methods' as described below. Please refer to FIG. 1K and FIG. 1L. The process described in this embodiment is roughly the same as the first. The preferred embodiment is the same, except that the order of the process of removing part of the metal pillars and the process of etching the seed layer is opposite to the order described in the first preferred embodiment. In this embodiment, after the photoresist removal process is completed (continued) Brother 2 3)) 'Then the seed layer process is performed, and the seed layer 540 can be removed in a region not covered by the metal line 564 by means of Reactive Ion Etch (RIE). Please refer to FIG. 1L Then, the process of removing part of the metal pillars is carried out through the wet etching method, and the etching is performed from the side of the metal pillars 580 to make the cross-sectional area of the metal pillars 580 smaller than the cross-sectional area of the transition body 590, which also makes the transition The edge of the lower surface of 590 is exposed to the outside. Please refer to Figure 1M, and finally perform the reflow process 'softening the solder bump 600 into a sphere-like shape by heating', so that the production of the bump 610 is completed. In addition, When the material of the metal pillar and the seed layer is the same, for example, the material of the metal pillar and the seed layer is copper. It can use isotropic etching to remove the sides of the metal pillar and the seed layer at the same time. One process step is omitted. After the flip-chip wafer of the present invention is manufactured, it can be bonded to the ball grid array substrate, as shown in FIG. 1N, which shows a semiconductor wafer structure according to the third preferred embodiment of the present invention. After the bump 710 is manufactured, the bonding process is performed. Through the step of reflow, the wafer 700 can be bonded to the contact 76 on the front surface of the substrate 750 by the solder block 712. Then, the sealing is performed. Standard (CNS) A 丨 Regulations (21〇χ 297 mm) ------------- Installation—— (Please read the precautions on the back first to write this page) ·-Line · Economy Intellectual Property Bureau employee consumption Printed by the agency 7824twf.d〇c / 〇〇6 A7 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention ((,) The process of glue makes a packaging material 7, π 枓 78 () cover the wafer. 700, reconfigure the line structure 730, the bump 710. _ Take Jun, and then perform the ball planting operation, you can plant multiple solder balls 790 to the substrate 75. However, the packaging method of the present invention also returns to% — The formula can also be in other forms, as shown in FIG. 10, which shows the semiconductor film structure according to the four preferred embodiments of the present invention. The M2 series is filled between the rearranged circuit structure 830 and the substrate 850, and the filling material tears and covers the bump 810 and the surroundings of the rearranged circuit structure 830. In addition, as shown in FIG. 1P, it shows a semiconductor wafer structure according to a fifth preferred embodiment of the present invention. After the filling material 982 is filled between the reconfigured circuit structure body 93 and the substrate 950, the chip 900 and the filling material 982 can be covered with a packaging material 98. After the fabrication of the flip-chip wafer of the present invention is completed, direct chip attach (DCA) can also be used to directly bond to the printed circuit board. As shown in FIG. 1Q, it shows the sixth embodiment of the present invention. A semiconductor wafer structure of the preferred embodiment. The chip 1000 is directly bonded to the printed circuit board 1050, and a filling material 1082 is filled between the reconfiguration circuit structure 1030 and the printed circuit board 1050, and the filling material 1082 covers the bump 1010 and the reconfiguration circuit. Around the structure 1030. In summary, the present invention has at least the following advantages: 1. The flip-chip wafer of the present invention and its process 'because the solder bump does not collapse, it can be firmly attached to the surface of the transition body', so it is being manufactured When reconfiguring the circuit structure, 'the step of preparing the solder mask layer can be saved (please read the precautions on the back Λ to write this page) Μ Install 〇Γ-ΰ. • The wire and the paper & degree apply the Chinese National Standard (CNS) Al gauge soldering (21〇χ ^ 7 公 堃) 515016 V. Description of the invention (). 2. The flip-chip wafer and the process of the present invention require only one time to make a seed layer by sputtering, and only once. The process of removing part of the seed layer is very efficient in the process. 3. The flip-chip wafer and its process of the present invention, because the bumps are composed of solder bumps, transition bodies and metal pillars, can be reduced without reduction. In the case of the distance between the wafer and the substrate, the volume of the bumps is greatly reduced, and the distance between adjacent bumps can be shortened. 4. The flip-chip wafer and the process of the present invention, because the tin-lead alloy bumps are away from the wafer surface Long distance, so tin lead The problem that the alpha particles in gold cause soft misremembering on the wafer will be reduced, which can reduce the occurrence of memory data access errors. 5. The flip-chip wafer and the process of the present invention, because the solder bump can use ordinary tin-lead alloy to Instead of low alpha particle tin-lead alloy, high-efficiency wafer operation can be achieved, while the material cost of ordinary tin-lead alloy is very low, which can greatly reduce the manufacturing cost of flip-chip wafers. 6. The flip-chip wafers of the present invention and their manufacturing processes, Because the wire diameter of the metal pillar of the bump is very small, and the material used is copper, and the ductility of copper is very good, the bump can tolerate large deformation caused by heat between the wafer and the substrate. 7 · The flip-chip wafer and its process of the present invention can be easily filled with a filling material between the wafer and the substrate when the flip-chip process is carried out through the flip-chip wafer after the metal pillars have been elevated. Chip-on-chip h manufacturing process, after the metal pillars are raised ------------- installation-(Please read the note on the back? Matters HI write this page) Order ·· --- Line-Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives Chinese National Standard (CNS) A.'l regulations (210 X 297 ^^^ 515016 7824twf.doc / 006 Λ7 B7 V. Description of the invention, when the wafer and the substrate are re-welded, the cleaning solution is also relatively low. It easily flows into the gap between the wafer and the substrate, so that the flux remaining after the reflow process can be removed relatively cleanly. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this technique can make some changes and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. ----- — — — — — —----· 11 (Please read the note on the back HI to write this page) Order · Thread · Printed by the Intellectual Property Bureau of the Ministry of Economy Staff Consumer Cooperatives 23 copies of 'Zhang Zhang / Xi_China Country Standard (CNSM1 County ⑵Οχ 297)