TW516133B - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
- Publication number
- TW516133B TW516133B TW090123961A TW90123961A TW516133B TW 516133 B TW516133 B TW 516133B TW 090123961 A TW090123961 A TW 090123961A TW 90123961 A TW90123961 A TW 90123961A TW 516133 B TW516133 B TW 516133B
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- Taiwan
- Prior art keywords
- substrate
- resin
- manufacturing
- semiconductor device
- semiconductor
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 68
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
- B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
- B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
516133 A7 ___ B7 五、發明説明(1 ) 【發明所屬之技術領域】 本發明係關於半導體裝置的製造技術,特別是關於適 用在採用藉由移送模鑄法之總括密封方式的半導體裝置的 製造技術有效的技術。 【習知技術】 於半導體裝置的製造中,以1個之樹脂密封體總括密 封被構裝在基板的一主面上之複數的半導體晶片,之後, 各半導體晶片地(各產品地)同時分割樹脂密封體以及基 板而製造之方法爲所周知。關於此製造,例如揭示在:特 開平8 - 1 0 7 1 6 1號公報(周知文獻1 )以及特開平 2 0 0 0 - 1 2 5 7 8號公報(周知文獻2 )。又,於周 知文獻1中揭示藉由裝罐法(potting )以形成總括密封之 樹脂密封體之方法,於周知文獻2中揭示藉由移送模鑄法 形成總括密封之樹脂密封體之方法。 【發明欲解決之課題】 本發明者等關於藉由移送模鑄法形成總括密封之樹脂 密封體之方法(以下,稱爲移送模鑄總括密封方式)做檢 討之結果,發現以下之問題點。 Η 2 3至圖2 6係顯示關於習知的半導體裝置的製造 中’以移送模鑄總括密封方式形成樹脂密封體時的樹脂之 流向圖((A )係模型平面圖、(b )係模型剖面圖)。 於圖23至圖26中,60係基板、60 X係基板60之 本&張尺度適用中國國家標準(CNsT^格(210x2^^- -4 - (請先閱讀背面之注意事¾ •裝--I π寫本頁) 經濟部智慧財產局員工消費合作社印製 516133 A7 __ B7 _ 五、發明説明(2 ) 一主面、6 1係半導體晶片、6 2係成形模具、6 2 A係 成形模具6 2之上模、6 2 B係成形模具6 2之下模、 (請先閱讀背面之注意事項寫本頁) 6 3係模穴、6 4係澆口、6 5係澆道、6 6係排氣口、 6 7 A係樹脂、6 7 B係空隙、S係樹脂之注入方向。 移送模鑄總括密封方式係被採用於具有基板之封裝構 造之B G A ( Ball Grid Array :球柵陣列)型半導體裝置 、C S P ( Chip Size Package 或 Chip Scale Package:晶片 尺寸封裝)型半導體裝置等之製造。此種半導體裝置的製 造中,如圖2 3所示般地,使用複數的產品形成區域 6 〇 A留有指定之間隔呈行列狀被配置於一主面6 Ο X之 基板6 0之故,被構裝在基板6 0之複數的半導體晶片 6 1也留有指定之間隔而被配置呈行列狀。 在移送模鑄總括密封方式中,如同圖所示般地,使用 具備:模穴6 3、澆口 6 4、澆道6 5、通風帽(未圖示 出)、罐(pot)(未圖示出)以及排氣口 66等之成 形模具6 2,樹脂6 7 A由罐通過通風帽、澆道6 5以及 澆口 6 4被注入模穴6 3之內部。 經濟部智慧財產局員工消費合作社印製 基板6 0通常係使用平面爲長方形者之故,對應此, 模穴6 3之平面形狀也成爲長方形。在此情形,橫跨模穴 6 3之內部的全部區域,樹脂6 7 A可以均勻被塡充地, 在模穴6 3之相互對向的2個長邊之中的一方的長邊側沿 著此一方之長邊設置有複數的澆口 6 4之故,樹脂6 7 A 在模穴6 3之內部由基板6 0之一方的長邊側朝向另一方 之長邊側而被注入。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -5- 516133 Μ _ Β7 _ 五、發明説明(3 ) 如此,被注入模穴6 3之內部的樹脂6 7 A如圖2 3 至圖2 5所示般地,由基板6 0之一方的長邊側朝向另一 方之長邊側流動,如圖2 6所示般地,被塡充於模穴6 3 之內部。 可是,被注入模穴6 3之內部的樹脂6 7 A沿著半導 體晶片6 1之一主面以及側面流動。沿著半導體晶片6 1 之一主面以及側面流動之樹脂6 7 A雖流入半導體晶片 6 1間,但是沿著半導體晶片6 1之一主面流動之樹脂 6 7 A由於半導體晶片6 1妨礙流動之故,比沿著半導體 晶片6 1之側面流動的樹脂6 7 A其流速慢。因此,沿著 半導體晶片6 1之一主面流動之樹脂6 7 A與沿著半導體 晶片6 1之側面流動的樹脂6 7 A交會地方(參考圖2 5 )發生空隙6 7 B。此空隙6 7 B在樹脂注入過程中,雖 然由於樹脂6 7 A之流動而一面移動一面逐漸變小,但是 ,對於樹脂6 1 A之注入方向S .,在由於半導體晶片6 1 而形成影子處(參考圖2 6 )殘留空隙6 7 C。在移送模 鑄法中,樹脂塡充終了後,雖然施行施加比注入時之壓力 還高之壓力,以使被捲入樹脂中的空隙變小之工程,但是 即使施以此工程,空隙6 7 C在溫度循環試驗時,比起不 引起爆米花現象之程度的空隙還大很多之故,成爲降低半 導體裝置的產品率之原因。 在前述之周知文獻1 (特開平8 - 1 0 7 1 6 1號公 報)中,揭示:作爲防止未塡充部之發生的手段,使用靜 凝性低之模鑄材料,以及在前述之情形,進而倂用真空脫 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項寫本頁) -裝· 訂 經濟部智慧財產局員工消費合作社印製 516133 A7 ___ B7 五、發明説明(4 ) 泡。但是,在移送模鑄法中,藉由適用前述手段,還是無 法解決空隙發生之問題。 (請先閲讀背面之注意事項寫本頁) 在採用移送模鑄法之情形,樹脂之流動藉由澆口來之 注入而被控制。因此,藉由於與澆口對向之位置、樹脂最 後被塡充之區域設置排氣口,在樹脂被塡充於模穴中爲止 之間,可以由排氣口排除模穴中之空氣。 但是,於移送模鑄法中,樹脂之流動由於靜凝性而被 支配之程度爲止地降低靜凝性,或如使樹脂之注入速度降 低,樹脂之流動的控制變得困難,設定應該設置在樹脂最 後被塡充之區域之排氣口的位置實質上成爲不可能。 因此,在移送模鑄法中,樹脂藉由採用靜凝性低者_, 控制樹脂之注入過程的狀態,使空隙之捲入不見,事實上 .爲不可能。 經濟部智慧財產局員工消費合作社印製 又,以降低由於密封樹脂之硬化收縮之變形,使切割 工程變得容易爲目的,或使樹脂熱膨脹係數與半導體晶片 近似,以在熱循環時降低施加於半導體晶片之應力爲目的 ,於密封樹脂大量添加塡充物(例如8 0 %以上)之情形 ,作爲模鑄材料在採用靜凝性低者之情形,由於塡充物之 存在,靜凝性變高之故,無法獲得解決空隙之捲入程度之 低靜凝性。 又,於裝罐法中,雖然可以採用於裝罐後,藉由將樹 脂硬化前之狀態的半導體裝置至於氣壓低之氣氛中,將氣 泡排除於樹脂外之真空脫泡之手段,但是在移送模鑄法中 ,樹脂之注入以及硬化在模穴內進行之故,無法採用藉由 本紙張尺度適用中國國家標準(CNS ) A4規格(21〇χ297公釐) 516133 A7 __ B7 _ 五、發明説明(5 ) 真空脫泡以降低空隙之方法。 (請先閲讀背面之注意事項寫本頁) 由此種情形,在移送模鑄法中,藉由適用記載於周知 文獻1之技術,無法防止空隙之發生之故,作爲空隙對策 需要採用新的方法。 因此,本發明者等如圖2 6所示般地,由於空隙 6 7 B與基板6 0之一主面接觸而殘留之故,著眼於對於 基板6 0之一主面之樹脂6 7 A的濡濕性,完成本發明。 本發明之目的在於提供:可以謀求半導體裝置的產品 率之提升之技術。 本發明之前述以及其它之目的與新的特徵,由本詳細 說明書之記載以及所附圖面,理應可以變明白。 【解決課題用之手段】 於本申請案所揭示之發明之中,如簡單說明代表性者 之槪要,則如下述: (1 ) 一種半導體裝置的製造方法,其特徵爲: 經濟部智慧財產局員工消費合作社印製 具備:將由基板的一主面之第1邊側朝向與前述第1 邊對向之第2邊側留有指定之間隔而被構裝在前述基板之 一主面上的複數的半導體晶片與則述基板一齊地配置於成 形模具之模穴的內部,之後,在前述模穴之內部由前述基 板之一主面之第1邊側朝向第2邊側注入樹脂,形成總括 密封前述複數的半導體晶片之樹脂密封體的工程, 進而,具備在形成前述樹脂密封體的工程之前,去除 殘留在前述基板之一主面之不純物之工程。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) ' 516133 A7 B7 五、發明説明(6 ) 去除殘留在前述基板之一主面之不純物之工程係以電 漿潔淨法進行。 (2 ) —種半導體裝置的製造方法,其特徵爲: 具備:將由基板的一主面之第1邊側朝向與前述第1 邊對向之第2邊側留有指定之間隔而被構裝在前述基板之 一主面上的複數的半導體晶片與前述基板一齊地配置於成 形模具之模穴的內部,之後,在前述模穴之內部由前述基 板之一主面之第1邊側朝向第2邊側注入樹脂,形成總括 密封前述複數的半導體晶片之樹脂密封體的工程, 進而,具備在形成前述樹脂密封體的工程之前,於前 述基板之一主面施以粗面化處理之工程。 前述粗面化處理係以電漿潔淨法進行。 【發明之實施形態】 以下,參考圖面詳細說明本發明之實施形態。又,於 說明發明之實施形態用之全部圖面中,具有相同機能者係 賦予相同標號,省略其之重覆說明。 (實施形態1 ) 在本實施形態中,係就B G A型之半導體裝置適用本 發明之例做說朋。 圖1係顯示本發明之實施形態1之半導體裝置的槪略 構成圖((A )係去除樹脂密封體之狀態的模型平面圖、 (B )係沿著(A )之a - a線之模型剖面圖),圖2係 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項!^寫本頁) •裝· 訂 經濟部智慧財產局員工消費合作社印製 -9 - 516133 A7 B7 五、發明説明(7 ) 放大圖1 ( B )之一部份之模型剖面圖。 (請先閲讀背面之注意事項寫本頁) 如圖1以及圖2所示般地,本實施形態之半導體裝置 1 A係主要具有:基板(配線基板)2、半導體晶片1 0 、複數之銲線1 3、樹脂密封體1 4以及複數的突起狀電 極1 5等之構成。半導體晶片1 0以及複數的銲線1 3係 藉由樹脂密封體1 4所密封。 半導體晶片1 〇係透過黏著層1 2被黏著固定在基板 2之相互對向之一主面(晶片搭載面)2 X以及其它之主 面(裏面)2Y之中的一主面2X。半導體晶片1 0之平 面形狀係被形成爲方形,於本實施形態中,例如被形成爲 正方形。半導體晶片1 0例如係具有:由單晶矽形成之半 導體基板;以及在此半導體基板之電路形成面上,複數層 堆疊個個之絕緣層、配線層之多層配線層;以及覆蓋此多 層配線層而被形成之表面保護膜之構成。作爲表面保護膜 例如使用聚亞醯胺樹脂。 經濟部智慧財產局員工消費合作社印製 於半導體晶片1 〇中作爲集成電路例如內藏有控制電 路。此控制電路主要係藉由:被形成在半導體基板之電路 形成面之電晶體元件以及被形成在配線層之配線所構成。 於半導體晶片1 〇之相互對向之一主面(電路形成面 )1 0 X以及其它之主面(裏面)之中的一主面1 0 X沿 著半導體晶片10之外周圍的各邊形成有複數的電極焊墊 (焊墊)1 1。此複數的電極焊墊1 1之個個係被形成在 半導體晶片1 〇之多層配線層之中的最上層之配線層,與 構成控制電路之電晶體元件電氣地連接著。複數的電極焊 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -10- 516133 Α7 Β7 五、發明説明(8 ) 墊1 1之個個例如係以:鋁(A 1 )膜或鋁合金膜等之金 屬膜所形成。 (請先閱讀背面之注意事項^^寫本頁) 基板2雖沒有詳細圖示,但是成爲依序堆疊絕緣層、 導電層之個個之多層配線構造。各絕緣層例如係以:在玻 璃纖維含浸環氧樹脂系之樹脂之玻璃環氧樹脂基板所形成 ’各配線層例如以由銅(C u )所形成之金屬膜所形成。 基板2之平面形狀被形成爲方形,於本實施形態中,例如 被形成爲正方形。 於基板2之一主面2 X配置有由被形成在其之最上層 之導電層的配線之一部份所形成之複數的連接部(島)3 。又,於基板2之一主面2 X形成有:保護被形成在其之 最上層之導電層的配線之樹脂膜4。於此樹脂膜4形成有 露出連接部3之表面之開口。 經濟部智慧財產局員工消費合作社印製 於基板2之裏面2 Y配置有由被形成在其之最下層之 導電層的配線之一部份所形成之複數的電極焊墊(島)5 。又,於基板2之裏面2 Y形成有保護被形成在其之最下 層的導電層之配線的樹脂膜6。於此樹脂膜6形成有露出 電極焊墊5之表面之開口。樹脂膜4以及6係例如以環氧 樹脂系之樹脂或聚亞醯胺系之樹脂所形成。 複數的突起狀電極1 5係分別被固定在被配置於基板 2之裏面2 Y之複數的電極焊墊5,電氣而且機械地被連 接著。突起狀電極1 5例如係以P b - S η組成之焊錫材 料所形成之球狀凸塊而形成。 樹脂密封體1 4之平面形狀係被形成爲方形,於本實 本紙張尺度適用中國國家標準(CNS〉Μ規格(210Χ297公釐) -11 - 516133 A7 _ B7 _ 五、發明説明(9 ) (請先閱讀背面之注意事項寫本頁) 施形態中,例如形成爲正方形。樹脂密封體1 4以謀求低 應力化爲目的,例如以添加有酚系硬化劑、矽橡膠以及多 數之塡充物(例如,二氧化矽)等之環氧樹脂系的熱硬化 性絕緣樹脂。 被配置在半導體晶片1 0之一主面1 0 X之複數的電 極焊墊1 1透過銲線1 1分別電氣地被連接於被配置在基 板2之一主面2 X之複數的連接部3。銲線1 3例如使用 金(A u )線。銲線1 3之連接方法例如使用於熱壓接倂 用超音波振動之球銲(釘頭銲接)法。 樹脂密封體1 4以及基板2之外形尺寸幾乎成爲相同 ,樹脂密封體1 4以及基板2之側面成爲同一平面。於本 實施形態之半導體裝置1 A之製造中,雖然之後詳細說明 ,係採用:以樹脂密封體總括密封留有指定之間隔被夠裝 在基板之一主面之複數的半導體晶片1 0,之後,於各半 導體晶片1 0 (各產品形成區域)同時分割樹脂密封體以 及基板而製造之方法。 經濟部智慧財產局員工消費合作社印製 圖3係被使用在本實施形態之半導體裝置1 A之製造 的基板的模型平面圖,圖4係放大圖3之一部份之模型平 面圖,圖5係沿著圖4之b - b線之模型剖面圖。 如圖3至圖5所示般地,基板(配線基板)2 0之平 面形狀係形成爲方形,於本實施形態中,例如被形成爲長 方形。在基板2 0之一主面(晶片搭載面)係留有指定之 間隔成行列狀地配置有複數的產品形成區域2 2。於產品 形成區域2 2配置有晶片搭載區域2 2,於其之周圍配置 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 一 -12- 516133 A7 B7 五、發明説明(ι〇) 有複數的連接部3。各產品形成區域2 2係被配置在形成 有樹脂密封體之模鑄區域2 1之中。各產品形成區域2 2 之構成係與基板2爲相同之構成。即,於基板2 0隻一主 面20X橫跨其之全面形成有樹脂膜(4),在與一主面 2 ◦ X對向之其它的主面(裏面)橫跨其之全面形成有樹 脂膜(6 )。又,各產品形成區域2 2係透過分割基板 2 0用之分離區域,以相互分離之狀態被配置著。 圖6係顯示被使用在本實施形態之半導體裝置1 A之 製造的成形模具之上模的槪略構成之模型平面圖,圖7係 顯示前述成形模具之下模之槪略構成之模型平面圖,圖8 係顯示前述成形模具之槪略構成之模型剖面圖。 如圖6至圖8所示般地,成形模具3 0係具備:模穴 3 1、複數的澆口 3 2、複數的副澆道3 3、複數的主澆 道3 4、複數的通風帽3 5、連結澆道3 6、複數的排氣 口 3 7、複數的罐3 8以及基板搭載區域3 9等。3 1〜 3 7之各構成部係被設置在上模3 0A,3 8〜3 9之各 構成部係被設置在下模。模穴3 7以及基板搭載區域3 9 之平面形狀係以對應於基板2 0之平面形狀的平面形狀而 被形成,於本實施形態中,例如被形成爲長方形。模穴 3 1由上模3 0 A之對合面往深度方向凹進。基板搭載區 域3 9由下模3 0 B之對合面往深度方向凹進。 於成形模具3 0中,樹脂由罐3 8通過通風帽3 5、 主澆道3 4、副澆道3 3以及澆口 3 2被注入模穴3 1之 內部。複數之澆口 3 2係沿著模穴3 1之相互對應之2個 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) (請先閲讀背面之注意事項ν -裝-- π寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -13- 516133 A7 B7 五、發明説明(11) (請先閲讀背面之注意事項寫本頁) 長邊之中的一方之長邊而配置以使得樹脂橫跨模穴6 3之 內部的全區域可以均勻塡充。因此,樹脂在模穴3 1之內 部由模穴3 1之一方的長邊側朝向另一方之長邊側而被注 入。複數的排氣口 3 7係沿著除了配置有澆口 3 2之模穴 3 1之一方的長邊的3邊而被配置。 接著,利用圖9至圖1 6說明本實施形態之半導體裝 置1A之製造。圖9、圖1〇、圖1 1以及圖16係說明 半導體裝置之製造用的模型剖面圖,圖1 2至圖1 5係以 移送模鑄總括方式形成樹脂密封體時的樹脂之流動圖(( A )係模型平面圖、(:6)係模型剖面圖)。 首先準備圖3所示之基板20。 接著,於基板2 0之一主面2 0 X的各產品形成區域 之晶片搭載區域例如形成由環氧樹脂系之熱硬化性樹脂形 成之黏著層1 2,之後,於晶片搭載區域透過黏著層1 2 搭載半導體晶片1 〇,之後,施以熱處理,使黏著層1 2 硬化,如圖9 ( A )所示般地,於各晶片搭載區域黏著固 經濟部智慧財產局員工消費合作社印製 定半導體晶片1 0。於此工程中,基板2 0例如被加熱爲 1 5 0 °C之程度之故,自然氧化膜形成在半導體晶片1 0 的電極焊墊1 1之表面以及基板2 0之連接部3的表面。 又,被含於樹脂模4之油脂以及有機溶媒等之不純物成爲 外部氣體而被排出,基板2 0之一主面2 X、連接部3之 表面以及電極焊墊1 1之表面等被污染。 接著,如圖9 (B)所7^:般地,對半導體晶片10之 電極焊墊1 1的表面以及2 0之連接部3的表面施以潔淨 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -14 - 516133 A7 B7 五、發明説明(12) (請先閲讀背面之注意事項寫本頁) 處理,去除殘留在這些之表面的自然氧化膜或油脂以及有 機溶媒等之不純物。此潔淨處理例如以利用氧氣或氬氣之 電漿潔淨法進行。 接著’如圖1 0 ( A )所币般地,以銲線1 3電氣地 連接半導體晶片1 〇之1 1與基板2 0之連接部3。於此 工程中,殘留在半導體晶片1 0的電極焊墊1 1之表面以 及基板2 0之連接部3的表面之自然氧化膜或油脂以及有 機溶媒等之不純物在前段之潔淨工程被去除之故,銲線工 程之連接信賴性提升。又,於此工程中,基板2 0例如被 加熱至1 2 5 °C之程度之故,被含於樹脂模4之油脂以及 有機溶媒等之不純物成爲外部氣體被排出,基板2 0之一 主面2 Ο X等被污染。又,於此工程中,複數的半導體晶 片10被構裝在基板20之一主面20X。 經濟部智慧財產局員工消費合作社印製 接著,如圖1 0 ( B )所示般地,對基板2 0之一主 面2 0 X施以潔淨處理,去除殘留在基板2 0之一主面 2 0 X的油脂以及有機溶媒等之不純物。此潔淨處理係以 使用氧氣或氬氣之電漿潔淨法進行。電漿潔淨法可以去除 油脂等之不純物之同時,也可以粗面化基板2 0之一主面 2 0 X的表面。 接著,如圖1 1所示般地,於成形模具3 0之上模 3 0 A與下模3 0 B之間定位基板2 0,將被構裝於基板 2 0上之複數的半導體晶片1 〇與基板2 〇 —齊地配置在 成形模具2 0之模穴3 1的內部。此時,基板2 0被搭載 於設置於下模3 0 B之基板搭載區域3 9。 本Ϊ氏張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) " ''~ -15- 516133 A7 _ B7 _ 五、發明説明(13) (請先閱讀背面之注意事項寫本頁) 接著,由罐3 8、通過通風帽3 5、主澆道3 4、副 澆道3 3以及澆口,於模穴3 1之內部例如注入環氧系之 熱硬化性樹脂,形成總括密封被構裝在基板2 0之一主面 2 Ο X之複數的半導體晶片1 0之樹脂密封體2 4。 於此工程中,如圖1 2所示般地,橫跨模穴3 1之內 部的全部區域,樹脂2 4 A被均勻塡充地,沿著模穴3 1 之相互對向之2個長邊之中的一方之長邊設置複數的澆口 3 2之故,樹脂2 4A在模穴3 1之內部由基板2 0之一 方之長邊側朝向另一方之長邊側而被注入。此時,半導體 晶片1 0之相互對向之2個的邊成爲對於樹脂2 4 A之注 入方向S爲幾乎垂直交叉之配置。 被注入模穴3 1之內部的樹脂2 4 A係如圖1 2至圖 1 4所示般地,由基板2 0之一方的長邊側朝向另一方之 長邊側流動,如圖1 5所示般地.,被塡充於模穴3 1之內 部。 被注入模穴3 1之內部的樹脂2 4 A沿著半導體晶片 經濟部智慧財產局員工消費合作社印製 1 0之一主面1 0 X以及側面流動。沿著半導體晶片1 0 之一主面10X以及側面流動之樹脂2 4 A雖流入半導體 晶片1 0間,但是沿著半導體晶片1 0之一主面1 0 X流 動之樹脂2 4 A比沿著半導體晶片1 〇之側面流動之樹脂 2 4 A其流速慢之故,在沿著半導體晶片1 〇之一主面 1 Ο X流動之樹脂2 4 A與沿著半導體晶片1 0之側面流 動之樹脂24A交會之處(參考圖1 4)發生空隙24B 。另一方面,殘留在基板2 0之一主面2 0之油脂等之不 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 一 -16- 516133 A7 B7 五、發明説明(14) 純物於前述之潔淨工程被去除,進而,基板2 0之一主面 2 Ο X被粗面化之故,對於基板2 0之一主面2 Ο X,樹 脂2 4 A之濡濕性提升。因此,對於樹脂2 4 A之注入方 向S,在由於半導體晶片1 〇而成爲影子之處,沿著半導 體晶片1 0之側面流動之樹脂2 4 A容易流入。因此,在 沿著半導體晶片1 〇之一主面1 〇 X流動之樹脂2 4 A與 沿著半導體晶片1 0之側面流動之樹脂2 4 A交會之處( 參考圖1 4 )所發生之空隙2 4 B離開基板2 0之一主面 2X。如此,由基板20之一主面2X分離之空隙24B 在樹脂注入過程中,由於樹脂2 4 A之流動變得容易移動 之故,如圖1 5所示般地,空隙2 4 B不會殘留在由於半 導體晶片1 0而成爲影子之處。由基板2 0之一主面2 0 X分離之空隙2 4 B由於樹脂2 4 A之流動而一面移動一 面逐漸變小,變小至於溫度循環試驗時,不會引起爆米花 現象之程度。 即,藉由在形成樹脂密封體2 4之工程之前,對基板 2 0之一主面2 0 X施以潔淨處理,去除殘留在基板2 0 之一主面2 0 X之油脂等之不純物,對於2 0之一主面 2〇X的樹脂2 4 A之濡濕性提升,沿著半導體晶片1 〇 之側面流動之樹脂2 4 A對於樹脂2 4 A之注入方向S ’ 變得容易流入由於半導體晶片1 〇而成爲影子之處之故’ 發生在沿著半導體晶片1 〇之一主面1 0 X流動之樹脂 2 4 A與沿著半導體晶片1 〇之側面流動之樹脂2 4 A交 會之地方的空隙2 4 B由基板2 0之一主面2 〇x被去除 本紙張尺度適用中國國家標準(CNS ) A4規格(21〇χ297公釐) (請先閱讀背面之注意事項^^寫本頁) -- ^^寫太 經濟部智慧財產局員工消費合作社印製 -17- 516133 A7 B7 五、發明説明(15) 〇 又,藉由以電漿潔淨法進行潔淨處理,可以去除殘留 在基板2 0之一主面2 Ο X的油脂等之不純物之同時,基 板2 0之一主面2 Ο X的表驗被粗面化之故,對於2 0之 一主面2 Ο X的樹脂2 4 A之濡濕性更提升。樹脂2 4 A 之濡濕性藉由去除殘留於流動面之油脂等之不純物而變高 ,又,藉由使流動面變粗而變高。但是,當然藉由粗面化 之樹脂的濡濕性的提升有其限度。 接著,如圖1 6 ( A )所示般地,在被配置於基板 2 0之裏面的電極焊墊5之表面上例如以球供給法形成突 起狀電極1 5,之後,總括密封之樹脂密封體2 4在與切 割片2 5相對之狀態於切割片2 5黏著固定基板2 0,之 後,如圖1 6 ( B )所示般地,以切割裝置各半導體晶片 1 0 (各產品形成區域)地同時切割樹脂密封體2 4以及 基板2 0。藉由此工程,幾乎完成圖1至圖3所示之半導 體裝置1 A。 如此,如依據本實施形態,可以獲得以下之效果: 一種半導體裝置1 A之製造方法,具備:將由一主面 2 0之一方的長邊側朝向與此一方之長邊對向之另一方的 長邊側留有指定之間隔而被構裝於基板2 0之一主面2 0 X上之複數的半導體晶片1 0與基板2 0 —齊地配置於成 形模具3 0之模穴3 1的內部,之後,在模穴3 1之內部 由基板2 0之一主面2 Ο X的一方之長邊側朝向另一方之 長邊側注入樹脂2 4 A,形成總括密封複數的半導體晶片 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項d 裝-- Η舄本頁) 訂 經濟部智慧財產局員工消費合作社印製 -18- 516133 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明(16) 1 〇之樹脂密封體2 4的工程,進而,具備:在形成樹脂 密封體2 4之工程之前,以電漿潔淨法去除殘留在基板 2 0之一主面2 Ο X之不純物之工程。 藉由此,去除殘留在基板2 0之一主面2 Ο X之油脂 以及有機溶媒等之不純物’於基板2 0之一主面2 Ο X使 露出與樹脂2 4 A之濡濕性高的材料多一些,或使基板 2 0之一主面2 Ο X成爲具有微細之凹凸的狀態,以提高 樹脂2 4 A與基板2 0之一主面2 Ο X的濡濕性,藉由伴 隨樹脂2 4 A之注入的流動,可以更促進樹脂2 4 A中的 空隙之排除。此結果爲:能夠謀求半導體裝置1 A之產品 率的提升。 又,在本實施形態中,雖就使用於一主面2 Ο X具有 .樹脂膜4之基板2 0之例做說明,如係樹脂基板,即使在 一主面2 Ο X不具有樹脂膜4,藉由製造工程之熱處理, 被含在樹脂基板之油脂以及有機溶媒等之不純物成爲外氣 被排出。 又,在本實施形態中,基板2 〇雖就利用玻璃環氧基 板之例做說明’但是本發明在使用由B T樹脂形成之基板 以作爲基板2 0之情形也有效。 又,作爲基板2 0在使用樹脂帶之情形,基於樹脂密 封體之硬化收縮,變形變激烈之故,必須增加塡充物之添 加量。在此種情形,樹脂之流動性降低之故,容易發生空 隙。 本紙張尺度適用中國國家標準(CNS ) A4規抬ΓΤ710><297公釐) (請先閱讀背面之注意事項\?^寫本頁) -裝·
、1T ♦ -19- 516133 A7 B7 五、發明説明(17) (實施形態2 ) 圖1 7係本發明之實施形態2之半導體裝置的模型剖 面圖。 如圖1 7所示般地,本實施形態之半導體裝置1 B基 本上與前述之實施形態1爲相同之構成,以下之構成不同 〇 即’半導體晶片1 0透過黏著層1 2被黏著固定於基 板2之一主面2X,半導體晶片4 0透過黏著層1 2被黏 著固定在半導體晶片1 〇之一主面1 〇。半導體晶片4 2 被形成爲比半導體晶片1 〇還小之平面尺寸。被配置在半 導體晶片4 2之一主面之電極焊墊4 1透過銲線4 3電氣 地被連接於形成在基板2 0之一主面2 Ο X之連接部3。 半導體晶片1 〇以及4 2係藉由樹脂密封體2 4被密封。 以下,利用圖1 8以及圖1 9說明半導體裝置1 B之 製造。 圖1 8以及圖1 9係說明半導體裝置之製造用之模型 剖面圖。 首先,準備基板20,之後,於基板20之一主面 2 〇 X的各產品形成區域的晶片搭載區域例如形成由環氧 系之熱硬化性樹脂所形成之黏著層1 2,之後,透過黏著 層1 2在晶片搭載區域搭載半導體晶片1 0,之後,施以 熱處理,使黏著層1 2硬化,於晶片搭載區域黏著固定半 導體晶片1 0。於此工程中,基板2 0例如被加熱至 1 8 0°c之故,在半導體晶片1 0之電極焊墊1 1之表面 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) (請先閲讀背面之注意事項一?%寫本頁) -裝· 訂 經濟部智慧財產局員工消費合作社印製 -20- 516133 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明(18) 以及基板2 0之連接部3之表面形成自然氧化膜。又,被 含於樹脂膜4之油脂以及有機溶媒等之不純物成爲外氣被 排出,基板2 0之一主面、連接部3之表面以及電極焊墊 1 1之表面等被污染。 接著,於各半導體晶片1 0之一主面1 0 X例如形成 由環氧系之熱硬化性樹脂所形成之黏著層4 2,之後,在 半導體晶片1 〇之一主面1 0X透過黏著層4 2搭載半導 體晶片4 0,之後,施以熱處理,使黏著層4 2硬化,如 圖1 8 ( A )所示般地,於半導體晶片1 0固定半導體晶 片4 2。於此工程中,基板2 0例如被加熱至1 8 0 °C之 程度之故,在半導體晶片1 0之電極焊墊1 1的表面以及 基板2 0之連接部3的表面形成自然氧化膜。又,被包含 .在樹脂模4之油脂等之不純物成爲外氣被排出,基板2 0 之一主面、連接部3之表面以及電極焊墊1 1之表面等被 污染。 接著,如圖1 8 ( B )所示般地,以利用氧氣或氬氣 之電漿潔淨法去除殘留在半導體晶片1 0以及4 2之電極 焊墊(1 1、4 1 )之表面以及基板2 0之連接部3的表 面之不純物。 接著,如圖1 9 ( A )所示般地,以銲線1 3電氣地 連接半導體晶片1 0之1 1與基板2 0之連接部3之同時 ,以銲線1 3電氣地連接半導體晶片4 0之電極焊墊4 1 與基板2 0之連接部3。於此工程中,基板2 0例如被加 熱至1 2 5 °C之程度之故,被包含在樹脂模4之油脂等之 本紙張尺度適用中國國家標準(CNS )八4規格(210X297公釐) (請先閱讀背面之注意事項^^寫本頁) 裝· 訂 漆 -21 - 516133 A7 B7 五、發明説明(19) 不純物成爲外氣被排出,基板2 0之一主面等被污染。 接著,如圖1 9 ( B )所示般地’以利用氧氣或氬氣 (請先閱讀背面之注意事項^^寫本頁) 之電漿潔淨法去除殘留在基板2 0之一主面2 Ο X之不純 物。於此工程中,電漿潔淨法可以粗面化基板2 0之一主 面2 Ο X之故,能夠進行不純物之去除以及基板2 0之一 主面2 Ο X的粗面化。 接著,與前述實施形態同樣地,於成形模具3 0之上 模3 Ο A與下模3 Ο B之間定位基板2 0,將被構裝於基 板2 0之一主面2 0X上之複數的半導體晶片1 〇與各被 積層於各半導體晶片1 0之複數的半導體晶片4 0與基板 2 0 —齊地配置在成形模具2 0之模穴3 1的內部,之後 ,由罐3 8通過通風帽3 5、主澆道3 4、副澆道3 3以 及澆口 3 2,於模穴3 1之內部注入樹脂,形成總括密封 被構裝在基板2 0之一主面2 0X之複數的半導體晶片 1 0以及4 0之樹脂密封體。 之後,藉由施以與前述實施形態相同之工程,完成圖 1 7所示之半導體裝置1 B。 經濟部智慧財產局員工消費合作社印製 於本實施形態之半導體裝置1 B之製造中,於基板 2 0之一主面2 0X上積層有2個之半導體晶片(1 0、 4 0 )之故,對於樹脂2 4 A之注入方向S,在由於半導 體晶片1 0以及4 0而成爲影子之部份雖然容易產生空隙 ,但是在形成樹脂密封體之工程前,藉由以電漿潔淨法對 基板2 0之一主面2 〇 X施以潔淨處理,可以獲得與前述 實施形態1同樣之效果。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) -22- 516133 A7 B7 五、發明説明(20) (實施形態3 ) (請先閱讀背面之注意事項寫本頁) 圖2 0係本發明之實施形態3之半導體裝置之模型剖 面圖。 如圖2 0所示般地,本實施形態之半導體裝置1 c基 本上係與前述之實施形態2爲相同之構成,以下之構成不 同。 即’半導體晶片5 0透過突起狀電極5 3被構裝於基 板2 0之一主面2X,半導體晶片1 〇透過黏著層1 2被 黏著固定於與半導體晶片5 〇之一主面對向之其它的主面 (裏面)。半導體晶片50係被配置在其之一主面之電極 焊墊5 0透過突起狀電極5 3電氣地被連接於被配置在基 板2 0之一主面2 X之電極焊墊3 A。在半導體晶片5 〇 與基板2 0之間例如塡充有環氧系之熱硬化性樹脂5 2。 半導體晶片1 〇之電極焊墊1 1透過銲線1 3被電氣地連 接於基板2 0之連接部3。半導體晶片5 0以及1 0係藉 由樹脂密封體2而被密封。 經濟部智慧財產局員工消費合作社印製 以下,利用圖2 1以及圖2 2說明半導體裝置1 C之 製造。圖2 1以及圖2 2係說明半導體裝置之製造用的模 型剖面圖。 首先,準備基板2 0,之後,在被配置於基板2 0之 一主面2 0 X之各產品形成區域之晶片搭載區域的電極焊 墊3 A與被配置於半導體晶片5 〇之一主面之電極焊墊 5 1之間以透過突起狀電極5 3之狀態熔解突起狀電極 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -23- 516133 A7 B7 五、發明説明(21) (請先閲讀背面之注意事項本頁) 5 3,於基板2 0之一主面的各產品形成區域構裝半導體 晶片5 1。於此工程中,基板2 0例如被加熱至2 5 0 之程度之故,在基板2 0之連接部3的表面形成自然氧化 膜。又,被包含於樹脂模4之油脂以及有機溶媒等之不純 物成爲外氣被排出,基板2 0之一主面、連接部3之表面 等被污染。 接著,在半導體晶片5 0與基板2 0之間例如塡充環 氧系之熱硬化性樹脂5 2,之後,施以熱處理,使熱硬化 性樹脂5 2硬化。於此工程公,基板2 0例如被加熱至 1 5 0 °C之程度之故,於基板2 0之連接部3的表面形成 自然氧化膜。又,被包含於樹脂模4之油脂以及有機溶媒 等之不純物成爲外氣被排出,基板2 0之一主面、連接部 3之表面等被污染。 接著,於各半導體晶片5 0之裏面例如形成由環氧系 之熱硬化性樹脂形成之黏著層4 2,之後,於半導體晶片 5〇之裏面透過黏著層1 〇形成半導體晶片1 〇,之後, 施以熱處理,使黏著層1 0硬化,如圖2 1 ( A )所示般 經濟部智慧財產局員工消費合作社印製 地,於半導體晶片1 0黏著固定半導體晶片4 2。於此工 程中,基板2 0例如被加熱至1 8 0 °C之程度之故,在半 導體晶片1 0之電極焊墊1 1之表面以及基板2 0之連接 部3的表面形成自然氧化膜。又,被包含於樹脂模4之油 脂等之不純物成爲外氣被排出,基板2 0之一主面、連接 部3之表面以及電極焊墊1 1之表面等被污染。 接著,如圖2 1 ( B )所示般地,以利用氧氣或氬氣 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -24- 516133 A7 B7 五、發明説明(22) 之電漿潔淨法去除殘留在半導體晶片1 〇之電極焊墊1 1 之表面以及基板2 0之連接部3的表面之不純物。 (請先閱讀背面之注意事項寫本頁) 接著,如圖2 2 ( A )所示般地,以銲線1 3電氣地 連接半導體晶片1 0之電極焊墊1 1與基板2 0之連接部 3。於此工程中,基板2 0例如被加熱至1 2 5 °C之程度 之故,被包含於樹脂模4之油脂等之不純物成爲外氣被排 出,基板2 0之一主面、等被污染。 接著,如圖2 2 ( B )所示般地,以利用氧氣或氬氣 之電漿潔淨法去除殘留在基板2 0之一主面2 Ο X之不純 物。於此工程中,電漿潔淨法可以粗面化基板2 0之一主 面2 Ο X之故,可以進行不純物之去除以及基板2 0之一 主面2 Ο X的粗面化。 經濟部智慧財產局員工消費合作社印製 接著,與前述實施形態同樣地,於成形模具3 0之上 模3 Ο A與下模3 Ο B之間定位基板2 〇,將被構裝於基 板2 0之一主面2 0X上之複數的半導體晶片5 0與各被 積層於各半導體晶片5 0之複數的半導體晶片1 0與基板 2 0 —齊地配置在成形模具2 0之模穴3 1的內部,之後 ,由罐3 8通過通風帽3 5、主澆道3 4、副澆道3 3以 及澆口 3 2,於模穴3 1之內部注入樹脂,形成總括密封 被構裝在基板2 0之一主面2 0 X之複數的半導體晶片 5 ◦以及1 0之樹脂密封體。 之後,藉由施以與前述實施形態1相同之工程’完成 圖2 0所示之半導體裝置1 C。 於本實施形態之半導體裝置1 c之製造中,於基板 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -25- 516133 A7 ____B7 _ 五、發明説明(23) 2 0之一主面2 0X上積層有2個之半導體晶片(5 0、 1 〇 )之故,對於樹脂2 4 A之注入方向S,在由於半導 體晶片5 0以及1 〇而成爲影子之部份雖然容易產生空隙 ’但是在形成樹脂密封體之工程前,藉由以電漿潔淨法對 基板2 0之一主面2 Ο X施以潔淨處理,可以獲得與前述 實施形態1同樣之效果。 以上,雖然依據前述實施形態具體說明由本發明者所 完成之發明,但是本發明並不限定於前述實施形態,在不 脫離其之要旨之範圍內,不用說有種種變更之可能。 例如,本發明也可以適用於C S P構造之半導體裝置 的製造技術。 又,本發明也可以適用於在基板上構裝複數的半導體 .晶片之M C Μ構造的半導體裝置的製造技術。 【發明之效果】 於本申請案所揭示之發明之中,如簡單說明由代表性 者所獲得之效果,則如下述: 如依據本發明,可以謀求半導體裝置的產品率之提升 〇 【圖面之簡單說明】 圖1係顯示本發明之實施形態1之半導體裝置的槪略 構成圖((A )係去除樹脂密封體之狀態的模型平面圖、 (B )係沿著(a )之a - a線之模型剖面圖。 I紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 一~~一 (請先閱讀背面之注意事項\^寫本頁) -裝· 訂 經濟部智慧財產局員工消費合作社印製 516133 A7 B7___ 五、發明説明(24) 圖2係放大圖1 ( B )之一部份之模型剖面圖。 (請先閲讀背面之注意事項寫本頁) 圖3係使用於實施形態1之半導體裝置之製造的基板 (分割用基板)之模型平面圖。 圖4係放大圖3之一部份之模型剖面圖。 圖5係沿著圖4之b - b線之模型剖面圖。 圖6係顯示使用於實施形態1之半導體裝置的製造之 成形模具之上模的槪略構成之模型平面圖。 圖7係顯示使用於實施形態1之半導體裝置的製造之 成形模具之下模的槪略構成之模型平面圖。 圖8係顯示使用於實施形態1之半導體裝置的製造之 成形模具的槪略構成之模型剖面圖。 圖9 ( A ) 、( B )係說明實施形態1之半導體裝置 .之製造用之模型剖面圖。 圖1 0 ( A ) 、( B )係說明實施形態1之半導體^ 置之製造用之模型剖面圖。 圖1 1係說明半導體裝置之製造用之模型剖面H。 經濟部智慧財產局員工消費合作社印製 圖1 2係說明實施形態1之半導體裝置之製造ψ,_ 脂密封工程用之圖((A )係模型平面圖、(B )丨系丨莫型 剖面圖)。 圖1 3係說明實施形態1之半導體裝置之製造ψ , ^ 脂密封工程用之圖((A )係模型平面圖、(B ) # _ ^ 剖面圖)。
圖1 4係說明實施形態1之半導體裝置之製造ψ,胃 脂密封工程用之圖((A )係模型平面圖、(B ) ^ ^fJ I紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) ' ^----- -27- 516133 A7 B7 五、發明説明(26) 圖2 5係說明於習知之半導體裝置之製造中,樹脂密 封工程用之圖((A )係模型平面圖、(B )係模型剖面 圖)。 圖2 6係說明於習知之半導體裝置之製造中,樹脂密 封工程用之圖((A )係模型平面圖、(B )係模型剖面 圖)。 【標號之說明】 1A、1B、1C:半導體裝置, 2 、2〇:基板, 3:連接部, 4、6 :樹脂層, 5 :電極焊墊, 1〇:半導體晶片, 1 1 :電極焊墊, 1 2 :黏著層, 1 3 :銲線, 14:樹脂密封體, 21:樹脂密封體形成區域, 2 2 :產品形成區域, 2 3 :晶片搭載區域, 3 0 :成形模具, 3 2 :模穴, 3 3 :澆口, 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項\?^寫本頁) -裝·
II 經濟部智慧財產局員工消費合作社印製 -29- 516133 A7 B7 五、發明説明(27) 3 3 :副澆道, 3 4 :主澆道, 域 , 區 , 道, 載 帽澆口 搭 風結氣,板 通連排罐基 ·»*··♦···· 5 6 7 8 9 3 3 3 3 3 (請先閱讀背面之注意事項^^寫本頁) 裝· 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -30-
Claims (1)
- 516133 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8々、申請專利範圍 第90123961號專利申請案 中文申目靑專利車B圍修正本 民國91年11月6日修正 1·一種半導體裝置之製造方法,其特徵爲: 具備:將由基板的一主面之第1邊側朝向與前述第1 邊對向之第2邊側留有指定之間隔而被構裝在前述基板之 一主面上的複數的半導體晶片與前述基板一齊地配置於成 形模具之模穴的內部,之後,在前述模穴之內部由前述基 板之一主面之第1邊側朝向第2邊側注入樹脂,形成總括 密封前述複數的半導體晶片之樹脂密封體的工程, 進而,具備在形成前述樹脂密封體的工程之前,去除 殘留在前述基板之一主面之不純物之工程。 2 ·如申請專利範圍第1項記載之半導體裝置之製造 方法,其中去除殘留在前述基板之一主面之不純物之工程 係以電漿潔淨法進行。 3 ·如申請專利範圍第2項記載之半導體裝置之製造 方法,其中前述電漿潔淨法係去除殘留在前述基板之一主 粗面化者。 半導體裝置之 製造方法,其中進而具備:在形成前述旨密封體之工程 前,在前述基板之一主面構裝前述複數的半導體晶片之工 程, 去除殘留在前述基板之一主面的不純物之工程係在構 裝前述複數的半導體晶片之工程之後,在形成前述樹脂密 本餓Γ浪尺度適用中國國家標準(CNS ) Α4規格(210Χ297公着) ~~(請先閲讀背面之注意事項再填寫本頁) 面;Ζ十純籾乙冋時,怛便前述基d 4 ·如申請專利範圍第1 〃516133 A8 B8 C8 D8 六、申請專利範圍 封體之工程之前進行。 5 ·如申請專利範圍第4項記載之半導體裝置之製造 方法,其中構裝前述複數的半導體晶片之工程係包含:在 前述配線基板之一主面黏著固定前述半導體晶片之工程; 以及以銲線電氣地連接被形成在前述半導體晶片之一主面 的電極焊墊與被形成在前述配線基板之一主面之連接之工 程。 6 ·如申請專利範圍第5項記載之半導體裝置之製造 方法,其中進而具備:在黏著固定前述半導體晶片之工程 之後,在以銲線電氣地連接之工程之前,以電漿潔淨法去 除殘留在前述半導體晶片之電極焊墊之表面以及前述基板 的連接部之表面的不純物之工程。 7 ·如申請專利範圍第1項記載之半導體裝置之製造 方法,其中前述基板係樹脂基板。 8 ·如申請專利範圍第1項記載之半導體裝置之製造 方法,其中前述基板係於其之一主面具有樹脂模。 9 ·如申請專利範圍第1項記載之半導體裝置之製造 方法’其中前述半導體晶片係其之平面形成爲方形, 前述半導體晶片之相互對向之2個邊對於前述樹脂之 注入方向爲交叉。 1 〇 ·如申請專利範圍第1項記載之半導體裝置之製 造方法,其中前述樹脂係混入多數之塡充物。 1 1 .如申請專利範圍第1項記載之半導體裝置之製 造方法’其中前述樹脂係混入有多數之塡充物之環氧系的 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂 絲 經濟部智慧財產局員工消費合作社印製 -2- 516133 A8 B8 C8 D8 六、申請專利範圍 熱硬化性樹脂。 1 2 .如申 ,其中進 述各半導 造方法 後,前 板之工 程。 請專利範圍第1項記載之半導體裝置之製 而具備:在形成前述樹脂密封體之工程之 體晶片地分割前述樹脂密封體以及前述基 • 一種半導體晶 經濟部智慧財產局員工消費合作社印製 具備=將由 邊對向之第2邊 一主面上的複數 形模具之模穴的 板之一主面之第 密封前述複數的 進而,具備 述基板之一主面 1 4 ·如申 製造方法,其中 1 5 ·如申 製造方法,其中 主面之不純物 基板的一 側留有指 的半導體 內部,之 1邊側朝 半導體晶 在形成前 施以粗面 請專利範 前述粗面 請專利範 前述電漿 之同時, 片之製造方法 主面之第1邊 定之間隔而被 晶片與前述基 後,在前述模 向第2邊側注 片之樹脂密封 述樹脂密封體 化處理之工程 圍第1 3項記 哪 潔淨法除 也使前述基板 ,其特徵爲: 側朝向與前述第1 構裝在前述基板之 板一齊地配置於成 穴之內部由前述基 入樹脂,形成總括 體的工程, 的工程之前,於前 〇 載之半導體裝置之 漿潔淨法進行。 載之半導體裝置之 殘留在前述基板之 之一主面粗面化者 1 6 .如申請專利範圍第1 3項記載之半導體裝置之 製造方法,其中進而具備:在形成前述樹脂密封體之工程 前,在前述配線基板之一主面構裝前述複數的半導體晶片 之工程, 本紙張尺度適用中國國家標準(CNS ) Μ規格(21〇χ297公釐) (請先閲讀背面之注意事項再填寫本頁) p 、言 -3 - 經濟部智慧財產局員工消費合作社印製 516133 A8 B8 C8 _____ D8 六、申請專利範圍 施行前述粗面化處理之工程係在構裝前述複數的半導 體晶片之工程之後,在形成前述樹脂密封體之工程之前進 行。 1 7 ·如申請專利範圍第1 6項記載之半導體裝置之 製造方法,其中構裝前述複數的半導體晶片之工程係包含 :在前述配線基板之一主面黏著固定前述半導體晶片之工 程;以及以銲線電氣地連接被形成在前述半導體晶片之一 主面的電極焊墊與被形成在前述配線基板之一主面之連接 之工程。 1 8 ·如申請專利範圍第1 7項記載之半導體裝置之 製造方法,其中進而具備:在黏著固定前述半導體晶片之 工程之後,在以銲線電氣地連接之工程之前,以電漿潔淨 法對前述半導體晶片之電極焊墊之表面以及前述基板的連 接部之表面施以潔淨處理之工程。 1 9 ·如申請專利範圍第1 3項記載之半導體裝置之 製造方法,其中前述基板爲樹脂基板。 2 0 .如申請專利範圍第1 3項記載之半導體裝置之 製造方法,其中前述基板爲在其之一主面具有樹脂層。 2 1 ·如申請專利範圍第1 3項記載之半導體裝置之 製造方法,其中前述半導體晶片係其之平面形成爲方形, 前述半導體晶片之相互對向之2個邊對於前述樹脂之 注入方向爲交叉。 2 2 ·如申請專利範圍第1 3項記載之半導體裝置之 製造方法,其中前述樹脂係混入多數之塡充物。 本I張尺度適财關家縣(CNS ) A4^ ( 210X297公釐}— ' 明 -4- (請先閱讀背面之注意事項再填寫本頁)516133 A8 B8 C8 一 _ D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 2 3 ·如申請專利範圍第1 3項記載之半導體裝置之 製造方法,其中前述樹脂係混入有多數之塡充物之環氧系 的熱硬化性樹脂。 2 4 ·如申請專利範圍第1 3項記載之半導體裝置之 製造方法,其中進而具備:在形成前述樹脂密封體之工程 之後’前述各半導體晶片地分割前述樹脂密封體以及前述 基板之工程。 2 5 · —種半導體裝置之製造方法,其特徵爲: 具備:將由基板的一主面之第1邊側朝向與前述第1 邊對向之弟2邊側留有指定之間隔而被構裝在前述基板之 一主面上的複數的第1半導體晶片與分別被積層在前述各 第1半導體晶片上之複數的第2半導體晶片與前述基板一 齊地配置於成形模具之模穴的內部,之後,在前述模穴之 內邰由前述基板之一主面之第1邊側朝向第2邊側注入樹 月旨,形成總括密封前述複數的半導體晶片之樹脂密封體的 工程, 經濟部智慧財產局員工消費合作社印製 進而,具備在形成前述樹脂密封體的工程之前,去除 殘留在前述基板之一主面之不純物之工程。 2 6 .如申請專利範圍第2 5項記載之半導體裝置之 製造方法,其中去除殘留在前述基板之一主面之不純物的 工程係以電漿潔淨法進行。 2 7 _ —種半導體裝置之製造方法,其特徵爲: 具備:將由基板的一主面之第1邊側朝向與前述第1 邊對向之第2邊側留有指定之間隔而被構裝在前述基板之 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) ''" —— -5- 516133 A8 B8 C8 D8 々、申請專利範圍 一主面上的複數的第1半導體晶片與分別被積層在前述各 第1半導體晶片上之複數的第2半導體晶片與前述基板一 齊地配置於成形模具之模穴的內部,之後,在前述模穴之 內部由前述基板之一主面之第1邊側朝向第2邊側注入樹 月旨,形成總括密封前述複數的半導體晶片之樹脂密封體的 工程, 進而,具備在形成前述樹脂密封體的工程之前,於前 述基板之一主面施以粗面化處理之工程。 2 8 .如申請專利範圍第2 7項記載之半導體裝置之 製造方法,其中前述粗面化處理係以電漿潔淨法進行。 (請先閱讀背面之注意事項再填寫本頁) 、?T 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) -6- 516133 第90123961號專利申請案 圖式修正頁
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2004186460A (ja) * | 2002-12-04 | 2004-07-02 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP2005136246A (ja) * | 2003-10-31 | 2005-05-26 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
US7495344B2 (en) * | 2004-03-18 | 2009-02-24 | Sanyo Electric Co., Ltd. | Semiconductor apparatus |
JP2008112928A (ja) * | 2006-10-31 | 2008-05-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
KR101497936B1 (ko) * | 2007-08-28 | 2015-03-03 | 에이전시 포 사이언스, 테크놀로지 앤드 리서치 | 유기 전자 소자 또는 광전자 소자의 제조 방법 |
US8541263B1 (en) * | 2008-08-22 | 2013-09-24 | Altera Corporation | Thermoset molding for on-package decoupling in flip chips |
US20120154974A1 (en) * | 2010-12-16 | 2012-06-21 | Applied Materials, Inc. | High efficiency electrostatic chuck assembly for semiconductor wafer processing |
CN103843135B (zh) * | 2011-09-29 | 2016-10-26 | 丰田自动车株式会社 | 半导体装置 |
JP2017183511A (ja) | 2016-03-30 | 2017-10-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US11049898B2 (en) | 2017-04-01 | 2021-06-29 | Ningbo Sunny Opotech Co., Ltd. | Systems and methods for manufacturing semiconductor modules |
CN208572212U (zh) | 2017-04-12 | 2019-03-01 | 宁波舜宇光电信息有限公司 | 摄像模组及其模塑感光组件以及电子设备 |
US10804305B2 (en) | 2018-04-23 | 2020-10-13 | Sunny Opotech North America Inc. | Manufacture of semiconductor module with dual molding |
Family Cites Families (14)
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US4715941A (en) * | 1986-04-14 | 1987-12-29 | International Business Machines Corporation | Surface modification of organic materials to improve adhesion |
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JPH0673167A (ja) * | 1992-08-27 | 1994-03-15 | Hitachi Chem Co Ltd | 電子部品封止用エポキシ樹脂成形材料及びその製造方法 |
JPH08153742A (ja) * | 1992-10-20 | 1996-06-11 | M Tex Matsumura Kk | 電子部品樹脂モールド方法 |
JPH06151477A (ja) * | 1992-11-04 | 1994-05-31 | Clarion Co Ltd | 半導体装置 |
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JPH10116940A (ja) * | 1996-10-09 | 1998-05-06 | Toshiba Corp | 樹脂封止型半導体装置及びその製造方法 |
JP3339354B2 (ja) * | 1997-03-27 | 2002-10-28 | 松下電器産業株式会社 | チップの片面モールド方法 |
US5969427A (en) * | 1998-02-05 | 1999-10-19 | Micron Technology, Inc. | Use of an oxide surface to facilitate gate break on a carrier substrate for a semiconductor device |
JP3127889B2 (ja) | 1998-06-25 | 2001-01-29 | 日本電気株式会社 | 半導体パッケージの製造方法およびその成形用金型 |
US6344162B1 (en) * | 1998-07-10 | 2002-02-05 | Apic Yamada Corporation | Method of manufacturing semiconductor devices and resin molding machine |
JP2000025074A (ja) * | 1998-07-14 | 2000-01-25 | Aoi Denshi Kk | モールド装置、モールド方法、モールドされた半導体装置の切断方法及び半導体装置の作製方法 |
US6338813B1 (en) * | 1999-10-15 | 2002-01-15 | Advanced Semiconductor Engineering, Inc. | Molding method for BGA semiconductor chip package |
US6462421B1 (en) * | 2000-04-10 | 2002-10-08 | Advanced Semicondcutor Engineering, Inc. | Multichip module |
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