TW512540B - An RF power LDMOS transistor - Google Patents

An RF power LDMOS transistor Download PDF

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TW512540B
TW512540B TW090106969A TW90106969A TW512540B TW 512540 B TW512540 B TW 512540B TW 090106969 A TW090106969 A TW 090106969A TW 90106969 A TW90106969 A TW 90106969A TW 512540 B TW512540 B TW 512540B
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gate
transistor
fingers
gate fingers
metal
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Jan Johansson
Nils Af Ekenstam
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Ericsson Telefon Ab L M
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

經濟部智慧財產局員工消費合作社印製 512540 A7 B7 五、發明說明（i ) 技術範疇 本發明大體上係關於射頻功率LDMOS電晶體，更明確地 説，本發明係關於第三代無線通訊系統中所使用的射頻功 率LDMOS電晶體。 發明背景 離散式射頻功率LDMOS電晶體主要是用來建構無線電基 地台中所使用的功率放大器。 圖1爲一傳統射頻功率LDMOS電晶體設計之一部份的上 視圖。該電晶體包含多個平行的LDMOS電晶體單元 (transistor cell)，圖1晝出其中2個，該等電晶體單元爲含有 若干對没極指狀物1、若干對閘極指狀物2及若干個源極/體 金屬夾3的交叉指形結構。該等成對的汲極指狀物1和閘極 指狀物2分別連接到位在該等電晶體單元相對兩側的一個汲 極饋線排4和一個閘極饋線排5上，如圖1所示。傳統的 LDMOS功率電晶體包含多個平行的電晶體單元。 然而，第三代（3G)無線系統對於射頻功率電晶體有新的 要求。不但是要求高頻（〉2GHz)，此要求本身就是一項挑戰 ，而且極度地要求線性，這些要求迫使功率放大器的設計 者在使用功率電晶體時是以低於其額定最大輸出功率的方 式使用它們。以這種退卻的輸出功率量讓電晶體有效運轉 ，即具有高增益及良好效率。. - 這些新的要求已經迫使射頻功率電晶體的設計者放棄“平 行單元”的舊式電晶體設計，而轉向稍微不同的設計。3G設 計只使用一個交叉相接的電晶體單元，相對於舊式設計的 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 512540 經濟部智慧財產局員工消費合作社印製 第二金屬 A7 B7 五、發明說明（2 ) 單元轉90度角。 這種新式設計的最大優點是能夠相當程度地降低每一個 有效電晶體（active transistor)區域的週圍面積，因而獲致較 低的輸出電容及較好的效能。 爲了使閘極區域的週圍面積能夠和具有多個平行單元的 電晶體相等，因此單一個電晶體單元的兩個維度方向都要 拉長，以便包含更多的指狀物。爲了維保持電晶體鑄模 (transistor die)適當的縱橫比（aspect ratio)，該等指狀物的 長度也必須增加很多。 3G設計的原則如圖2所示，圖示爲一已知3G射頻功率 LDM0S電晶體設計之一部份的上視圖。若干對的汲極指狀 物6(圖2只畫出一對）連接到一個共同的汲極結點（未畫出）。 若干對閘極指狀物7(圖2只畫出一對）在它們的端部和長度的 預足位置上利用一第一層金屬層的片互連。此種互連片8的 其中一個如圖2所示。源極/體金屬失9也是從該第一金屬層 做出，它延伸於位在互連片間之成對的閘極指狀物7的上= 〇 如前述，3G設計無可避免地必須結合較長的指狀物。對 於電晶體的閘極那一側而言，這尤其是一個問題。閘極指 狀物通常是以經過高度摻雜的聚矽物做成，可在它自、 曰 做-層金屬矽化物’以降低電阻。.然而，閘極指：::：： 電阻是不能忽視的，而且閘極指狀物的县冷 7长度對於電晶體的 效能多少會有一些負面的影響。 此問題在已知的3G電晶體設計中是利用加入 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --* J.--I--I---I ---I--— —訂--------I (請先閱讀背面之注意事項再填寫本頁) ^12540 A7 五、發明說明（3 ) 層來解決。利用這種方式，可在源極/體金屬夫9的上面設 計出一條金屬導板10。金屬導板10藉由—介電層（圖2未芒 出）與金屬爽9隔離，i經由互連片8，在沿間極指狀物7長 度在預定位置以及其兩端連接到該成對的閘極指狀物7。金 屬導板10的一端連接到一個共同的閘極結點（未畫出）。 由此，每一個閘極指狀物的有效長度等於兩個閘極互連 片之間距離的一半。 然而，加入第二層金屬層到電晶體中的設計不但增加設 計的複雜性，也增加製程的複雜性。關於這一點，必須^ 出，在圖2中，汲極指狀物6是由2層金屬所組成，亦即，在 该第-金屬層上有一第層二金屬層。電晶體鑄模的製程必 須額外增加兩個的掩蔽步驟和一些額外的製程步驟。 發明概述 本發明之目的係提供一種3G射頻1^]〇%〇3電晶體，其製造 上的複雜性低於目前已知之3G射頻LDMOS電晶體。 按照本發明，此一目的主要是藉由只使用一層中間與長 閘極指狀物接觸的金屬層來達成。 〃 圖示簡單説明 以下將參考附圖，更詳細地説明本發明。其中，圖丨爲一 傳統的射頻功率LDMOS電晶體設計，圖2爲一已知的3〇射 頻功率LDMOS電晶體設計，圖3爲按照本發明之3(}射頻功 率LDMOS電晶體設計，圖4爲圖3所示之按照本發明之3〇射 頻功率LDMOS電晶體沿A-Α線的剖面圖。 發明詳細説明 -6 - ^紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公 —-------------裝 (請先閱讀背面之注咅？事項再填寫本頁) .線. 經濟部智慧財產局員工消費合作社印製 A7 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（4 ) 圖3馬桉知本發明（3G射頻功率⑶以⑽電晶體設計。與 圖2所不心含有2層金屬層的已知π電晶體不同，按照本發 明的3G電晶體只包含一層金屬層。 在按照圖3所示之本發明的兩 乃们％晶體中，每一對閘極指狀物 的兩個閘極指狀物11在其端部和沿長度的㈣位置上利用 一金屬層之片互相i牵技。甘+ 一 5祁運接。其中一個該等連接片12如圖3所 不 〇 \、本*明’製造—金屬導板13與連接片12構成-體用 來仏每對閘&狀物i i連接_共同閘結點（未顯示）。 此外，按照本發明，從和互連片12及金屬導板Η同一個 金屬層做出之分開的源極/體金屬夾14與每一對閘極指狀物 的每-個閘極指狀仙結合。與每—對閘極指狀物的個別 閘極札狀物11結合之該金屬夾14由一條延伸於每一對閘極 指狀物的平行閘極指狀物11之間的狹槽15分隔開。 按照本發明，該等金屬導板13係做在該等金屬夾14之間 的狹槽15中。 從和互連片12、金屬導板13及金屬夾14同一個金屬層做 出之若干對汲極指狀物16連接到電晶體中的一個汲極結點 (未畫出）上。 圖4爲按照圖3所示之本發明的電晶體沿A_A線的剖面圖。 圖4中，與圖3相同的參考號碼代表相同的元件。 該電晶體係以一般所知道的方式裝到其上有一層p—epi 18 勺P基板1 7中’而且該電晶體含有交替配置的n+没極區域 19和Π+源極區域2〇，其中，n+汲極區域19由一卜漂移區域η 泰紙張尺度適用中國國家標準（CNS)A4規格（21G χ 297公髮） —-------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 512540
五、發明說明（ 與閘極1 1分隔開。 一P-型通道摻質或p_井22從其源極的那一側橫向擴展於 閘極11的下面。 、深P擴散或P+沉降墊23使得利用金屬夾i 4造成這些區 域與另一個區域之間形成短路，而讓電流能夠在電壓降^ 小的的情況下從n+源極區域2〇傳到〆基板丨7。 一介電層24把閘極指狀物n和金屬夾14分隔開，以及把 金屬導板13和p +沉降墊區域23分隔開。 I------------^-------- (請先閱讀背面之注意事項再填寫本頁) _線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 L 種射頻功率LDMOS電晶體，該電晶體包含多對平行的 閘極指狀物（11 )，每一對閘極指狀物的兩 個閘極指狀物位 在一個與它結合之p+沉降墊（23)的相對兩側，該電晶體尚 包含若干個金屬夾（14)，用於使該等p+沉降墊（23)與位 在該等p沉降墊（23)相對兩侧的n+源極區域（2〇)形成短路 ’該電晶體的特徵為： -每一對該等閘極指狀物中的每一個閘極指狀物（11)與使該 n+源極區域（20)和與特定閘極指狀物（u)結合之〆沉降墊 (23)形成短路之分開的金屬夾（14)結合， -與每一對該等閘極指狀物結合之該等分開的金屬夾由一 條延伸在該等平行閘極的指狀物丨丨之間的狹槽（丨5)分隔 開， 金屬導板（13)從一閘極磬延伸過來，並延伸於該狹槽 (15)中與每一對該等閘極指狀物結合之該等分開的金屬夾 (I4)之間，及 "每一對該等閘極指狀物（11)的兩個閘極指狀物在它們的端. 部和沿長度的預定位置上連接到它們的相關金屬導板（13) 上。 2·如申請專利範圍第1項之電晶體，該電晶體的特徵為，該 等金屬導板（Π)係做在該等p+沉降墊（23)上面的一層介電 層（24)上。 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------訂---------線 (請先閱讀背面之注意事項再填寫本頁)
TW090106969A 2001-03-09 2001-03-23 An RF power LDMOS transistor TW512540B (en)

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SE0100804A SE522576C2 (sv) 2001-03-09 2001-03-09 Effekt-LDMOS-transistor för radiofrekvens

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EP1366526A1 (en) 2003-12-03
WO2002073701A1 (en) 2002-09-19
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CN1524296A (zh) 2004-08-25
US7095080B2 (en) 2006-08-22
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US20040089897A1 (en) 2004-05-13
SE0100804L (sv) 2002-09-10

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