CN103839982A - 平面栅超级结产品栅极版图结构 - Google Patents

平面栅超级结产品栅极版图结构 Download PDF

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CN103839982A
CN103839982A CN201210484655.1A CN201210484655A CN103839982A CN 103839982 A CN103839982 A CN 103839982A CN 201210484655 A CN201210484655 A CN 201210484655A CN 103839982 A CN103839982 A CN 103839982A
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gate
grid
polycrystalline silicon
polysilicon gate
epitaxy layer
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王飞
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Abstract

本发明公开了一种平面栅超级结产品栅极版图结构，具有多个原包结构，每个原包结构包括：N型衬底上生长N型外延，N型外延上部形成P阱区，P阱区和N型外延上形成有栅极氧化膜，栅极氧化膜上形成有多晶硅栅极，多晶硅栅极上形成有金属硅化物；所述多晶硅栅极是彼此分离的两个多晶硅栅极，在P阱区之间N型外延上方形成一窗口，多晶硅栅极一侧边缘位于P阱区上方，另一侧边缘位于P阱区之间的N型外延上方。本发明通过减小多晶栅极和N外延的重叠面积能减小栅-漏电容，减小MOSFET管的开关时间，降低产品在交流应用时的损耗；去掉了在原包结构两个P阱区之间的栅极板的覆盖，使产品在开启工作时，降低了导电电流受栅极电压的影响，降低了导通电阻。

Description

平面栅超级结产品栅极版图结构
技术领域
本发明涉及集成电路领域，特别是涉及一种平面栅超级结产品栅极版图结构。
背景技术
现有的超级结产品中，多晶栅极的结构是直接盖在原包结构（元胞结构是构成半导体器件的基础单体结构，半导体器件是有多个结构相同的元胞结构所构成）的N外延上面的栅极氧化膜上的。在原包结构上的N外延只在P阱区和多晶栅极形成重叠的部分能提供导电通道，而在N外延中间部分只会形成寄生的栅-源电容，同时在开启时，这部分在栅极下的N外延还会受到由栅极加的开启电压而导致的可动电荷向栅极板下面聚集，进而影响开启电阻的JFET效应。
发明内容
本发明要解决的技术问题是提供一种平面栅超级结产品栅极版图结构，其能在保证沟道开启电压和导电通道电流不变的前提下，减小栅-漏电容，降低功率管的损耗，降低导通电阻。
为解决上述技术问题，本发明平面栅超级结产品栅极版图结构，具有多个原包结构，每个原包结构包括：N型衬底上生长的N型外延，所述N型外延上部形成有P阱区，所述P阱区和N型外延的上形成有栅极氧化膜，所述栅极氧化膜上形成有多晶硅栅极，所述多晶硅栅极上形成有金属硅化物；其中，所述多晶硅栅极是彼此分离的两个多晶硅栅极，在所述P阱区之间的N型外延上方形成一窗口，所述多晶硅栅极一侧的边缘位于P阱区上方，另一侧的边缘位于所述P阱区之间的N型外延上方。
其中，所述原包结构多晶硅栅极位于N型外延上方的宽度小于1um。
其中，各所述原包结构分离的多晶硅栅极采用在原包结构结束处合并在一起连接到栅总线的方式。
其中，各所述原包结构分离的多晶硅栅极采用直接连接到栅总线的方式。
本发明通过减小多晶栅极和N外延的重叠面积首先能减小栅漏电容，减小MOSFET管的开关时间，同时降低产品在交流应用时的损耗；其次，由于去掉了的在原包结构两个P阱区之间的栅极板的覆盖，使产品在开启工作时，降低了导电电流受栅极电压的影响，降低了导通电阻。
附图说明
下面结合附图与具体实施方式对本发明作进一步详细的说明：
图1是一种现有平面栅超级结产品栅极版图原包结构的示意图。
图2是本发明的平面栅超级结产品栅极版图原包结构的示意图。
图3是本发明的平面栅超级结产品栅极版图结构的俯视图一，其显示分离的多晶硅栅极采用在原包结束处合并在一起连接到栅总线的方式。
图4是本发明的平面栅超级结产品栅极版图结构的俯视图二，其显示分离的多晶硅栅极采用直接连接到栅总线的方式。
附图标记说明
1是N型衬底
2是N型外延
3是P阱区
4是栅极氧化膜
5是导电通道
6是多晶硅栅极
7是金属硅化物
8是原包结构结束处
9是栅总线。
具体实施方式
如图2所示，本发明的平面栅超级结产品栅极版图结构，具有多个原包结构，每个原包结构包括：N型衬底1上生长的N型外延2，N型外延2上部形成有P阱区3，P阱区3和N型外延2的上形成有栅极氧化膜4，栅极氧化膜4上形成有彼此分离的两个多晶硅栅极6，多晶硅栅极6上形成有金属硅化物7；在P阱区3之间的N型外延2上方形成一窗口，多晶硅栅极6一侧的边缘位于P阱区3上方，另一侧的边缘位于两个P阱区3之间的N型外延2上方，本实施例中多晶硅栅极6位于N型外延2上方的宽度小于1um。
如图3所示，本发明的平面栅超级结产品栅极版图结构，在构建版图时分离的多晶硅栅极6可采用在原包结构结束处8合并在一起连接到栅总线9的方式。
如图4所示，本发明的平面栅超级结产品栅极版图结构，在构建版图时分离的多晶硅栅极6可采用直接连接到栅总线9的方式。
以上通过具体实施方式和实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (4)

1.一种平面栅超级结产品栅极版图结构，具有多个原包结构，每个原包结构包括：N型衬底上生长的N型外延，所述N型外延上部形成有P阱区，所述P阱区和N型外延的上形成有栅极氧化膜，所述栅极氧化膜上形成有多晶硅栅极，所述多晶硅栅极上形成有金属硅化物；其特征是：所述多晶硅栅极是彼此分离的两个多晶硅栅极，在所述P阱区之间的N型外延上方形成一窗口，所述多晶硅栅极一侧的边缘位于P阱区上方，另一侧的边缘位于所述P阱区之间的N型外延上方。
2.如权利要求1所述平面栅超级结产品栅极版图结构，其特征是：所述原包结构的多晶硅栅极位于N型外延上方的宽度小于1um。
3.如权利要求2所述平面栅超级结产品栅极版图结构，其特征是：各所述原包结构的分离的多晶硅栅极采用在元胞区结束处合并在一起连接到栅总线的方式。
4.如权利要求2所述平面栅超级结产品极版图结构，其特征是：各所述原包结构的分离的多晶硅栅极采用直接连接到栅总线的方式。
CN201210484655.1A 2012-11-23 2012-11-23 平面栅超级结产品栅极版图结构 Pending CN103839982A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105529365A (zh) * 2016-01-29 2016-04-27 上海华虹宏力半导体制造有限公司 超级结器件
CN106533163A (zh) * 2016-01-22 2017-03-22 东莞市清能光伏科技有限公司 光伏功率转换器
CN112885827A (zh) * 2019-11-29 2021-06-01 苏州东微半导体股份有限公司 一种半导体超结功率器件
CN112928160A (zh) * 2021-01-22 2021-06-08 上海华虹宏力半导体制造有限公司 晶体管器件版图的形成方法

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US20030020115A1 (en) * 2001-07-05 2003-01-30 International Rectifier Corp. Power MOSFET with ultra-deep base and reduced on resistance
US20070278571A1 (en) * 2006-05-31 2007-12-06 Alpha & Omega Semiconductor, Ltd Planar split-gate high-performance MOSFET structure and manufacturing method
CN101552291A (zh) * 2009-03-30 2009-10-07 东南大学 N沟道超结纵向双扩散金属氧化物半导体管

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030020115A1 (en) * 2001-07-05 2003-01-30 International Rectifier Corp. Power MOSFET with ultra-deep base and reduced on resistance
US20070278571A1 (en) * 2006-05-31 2007-12-06 Alpha & Omega Semiconductor, Ltd Planar split-gate high-performance MOSFET structure and manufacturing method
CN101552291A (zh) * 2009-03-30 2009-10-07 东南大学 N沟道超结纵向双扩散金属氧化物半导体管

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106533163A (zh) * 2016-01-22 2017-03-22 东莞市清能光伏科技有限公司 光伏功率转换器
CN105529365A (zh) * 2016-01-29 2016-04-27 上海华虹宏力半导体制造有限公司 超级结器件
CN112885827A (zh) * 2019-11-29 2021-06-01 苏州东微半导体股份有限公司 一种半导体超结功率器件
CN112885827B (zh) * 2019-11-29 2022-04-15 苏州东微半导体股份有限公司 一种半导体超结功率器件
CN112928160A (zh) * 2021-01-22 2021-06-08 上海华虹宏力半导体制造有限公司 晶体管器件版图的形成方法
CN112928160B (zh) * 2021-01-22 2024-02-02 上海华虹宏力半导体制造有限公司 晶体管器件版图的形成方法

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Application publication date: 20140604