CN105529365A - 超级结器件 - Google Patents

超级结器件 Download PDF

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CN105529365A
CN105529365A CN201610064123.0A CN201610064123A CN105529365A CN 105529365 A CN105529365 A CN 105529365A CN 201610064123 A CN201610064123 A CN 201610064123A CN 105529365 A CN105529365 A CN 105529365A
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王飞
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region

Abstract

本发明公开了一种超级结器件，在N型外延中具有体区和平行的沟槽型的P柱，所述P柱位于体区的下方；体区之间的区域为JFET区域，外延表面具有栅极，所述栅极位于体区之上的硅表面；所述体区与P柱呈不对称结构，P柱的一侧与体区的一侧对齐，即垂直投影重叠；体区的另相对一侧超出P柱的一侧。本发明通过新的P柱与体区的相对位置，可以在缩小沟槽间距的同时，保持沟道的长度，以及沟槽间的JFET区域，保证MOSFET管的正常沟道开启特性，得到较小的导通电阻。

Description

超级结器件
技术领域
本发明涉及半导体集成电路制造领域，特别是指一种超级结器件。
背景技术
超级结功率器件是一种发展迅速、应用广泛的新型功率半导体器件。它是在双扩散金属氧化物半导体(DMOS)的基础上，通过引入超级结(SuperJunction)结构，除了具备DMOS输入阻抗高、开关速度快、工作频率高、热稳定好、驱动电路简单、易于集成等特点外，还克服了DMOS的导通电阻随着击穿电压成2.5次方关系增加的缺点。目前超级结DMOS已广泛应用于面向个人电脑、笔记本电脑、上网本、手机、照明(高压气体放电灯)产品以及电视机(液晶或等离子电视机)和游戏机等消费电子产品的电源或适配器。
目前超级结功率器件的制备工艺主要分成两大类，一种是利用多次外延和注入的方式在N型外延衬底上形成P柱；另外一种是在深沟槽刻蚀加P柱填充的方式形成。
现有的深槽型超级结器件，如图1所示，在衬底或外延中具有P柱，P柱之上为体区，P柱位于体区的中心处形成一种平衡的左右对称状态。体区之间为JFET区域，外延之上体区之间为栅极。图2是器件的俯视图。为了进一步降低导通电阻，必须要用更低电阻的外延基片，同时为了保持击穿电压不下降，需要将深槽的间距不断缩短，来保证耗尽区能够在沟槽之间完全展开。相对大尺寸深槽间距的超级结产品，深槽间的空间有足够大用来形成对称的双沟道器件结构，而随着沟槽之间距离的减小，没有足够空间形成双沟道。而沟槽间距的降低，会限制JFET区域的大小，影响到器件的沟道长度，提高导通电阻。
基于现有结构，如图3及图4所示(图4为俯视图)，缩小P柱之间距离，会引起JFET区域电阻增大，如果增加JFET注入还会影响MOSFET沟道的浓度和有效长度。
发明内容
本发明所要解决的技术问题是提供一种超级结器件，其具有耐击穿的性能，同时又保证器件的开启电压和低导通电阻特性。
为解决上述问题，本发明提供一种超级结器件，在N型外延中具有P柱和体区，所述P柱位于体区的下方，P柱呈平行沟槽型；体区之间的区域为JFET区域，外延表面具有栅极，所述栅极位于体区之间的硅表面，并且栅极与P柱沟槽平行；位于体区之下的P柱，其一侧与体区的边界对齐，P柱的另一侧在体区的另一侧边界范围内，且与栅极的一侧对齐，与栅极没有重叠。
进一步地，所述外延中还存在P阱，所述P阱为栅极和P柱以外的区域。
进一步地，超级结器件的沟道区为栅极和P阱重叠的区域。
本发明所述的超级结器件，通过新的体区与P柱沟槽的相对位置，在能缩小P柱沟槽间距的同时，保持沟道足够的长度，以及沟道间JFET区域的大小，保证MOSFET管的正常沟道开启特性，得到较小的导通电阻。
附图说明
图1是现有超级结器件的剖面图。
图2是图1的俯视图。
图3是缩小P柱之间间距的剖面示意图。
图4是图3的俯视图。
图5是本发明器件的剖视图。
图6是本发明器件的俯视图。
附图标记说明
1是衬底或外延，2是体区，3是P柱，4是栅极。
具体实施方式
本发明提供一种超级结器件，如图5所示，在N型外延1中具有P柱3和体区2，所述P柱3位于体区2的下方，P柱3呈平行沟槽型；体区2之间的区域为JFET区域，外延表面具有栅极4，所述栅极4位于体区2之间的硅表面，并且栅极4与P柱沟槽3平行；位于体区2之下的P柱3，其一侧与体区2的边界对齐，P柱3的另一侧在体区2的另一侧边界范围内。即P柱3与体区2是一种不对称的结构，P柱2并不像传统结构的设计位于体区3的中心处，形成左右对称的结构，而是偏向一侧，P柱3和体区2的一侧平齐，垂直投影重叠，而另一侧则体区2超出P柱3的范围，P柱3位于其垂直投影范围内，P柱的这一侧与栅极边缘对齐，与栅极不形成重叠。其俯视图如图6所示。
所述外延1中还存在P阱，所述P阱为栅极和P柱以外的区域。
超级结器件的沟道区为栅极和P阱重叠的区域。
本发明所述的超级结器件，通过新的体区与P柱沟槽的相对位置，将P柱和体区做成不对称的结构，形成单沟道超级结器件，保持器件的开启电压和低的导通电阻。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (3)

1.一种超级结器件，其特征在于：在N型外延中具有P柱和体区，所述P柱位于体区的下方，P柱呈平行沟槽型；体区之间的区域为JFET区域，外延表面具有栅极，所述栅极位于体区之间的硅表面，并且栅极与P柱沟槽平行；位于体区之下的P柱，其一侧与体区的边界对齐，P柱的另一侧在体区的另一侧边界范围内，与栅极的一侧对齐，与栅极没有重叠。
2.如权利要求1所述的超级结器件，其特征在于：所述外延中还存在P阱，所述P阱为栅极和P柱以外的区域。
3.如权利要求2所述的超级结器件，其特征在于：超级结器件的沟道区为栅极和P阱重叠的区域。
CN201610064123.0A 2016-01-29 2016-01-29 超级结器件 Pending CN105529365A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114864696A (zh) * 2022-04-22 2022-08-05 捷捷微电(上海)科技有限公司 一种sjmos器件结构及其制作工艺

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005064685A1 (ja) * 2003-12-26 2005-07-14 Rohm Co., Ltd. 半導体装置およびその製造方法
CN103839982A (zh) * 2012-11-23 2014-06-04 上海华虹宏力半导体制造有限公司 平面栅超级结产品栅极版图结构
CN104779296A (zh) * 2015-04-24 2015-07-15 无锡同方微电子有限公司 一种非对称超结mosfet结构及其制作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005064685A1 (ja) * 2003-12-26 2005-07-14 Rohm Co., Ltd. 半導体装置およびその製造方法
CN103839982A (zh) * 2012-11-23 2014-06-04 上海华虹宏力半导体制造有限公司 平面栅超级结产品栅极版图结构
CN104779296A (zh) * 2015-04-24 2015-07-15 无锡同方微电子有限公司 一种非对称超结mosfet结构及其制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114864696A (zh) * 2022-04-22 2022-08-05 捷捷微电(上海)科技有限公司 一种sjmos器件结构及其制作工艺

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