CN103579301B - 用于高压半导体器件的拐角布局及其制备方法 - Google Patents

用于高压半导体器件的拐角布局及其制备方法 Download PDF

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CN103579301B
CN103579301B CN201310319450.2A CN201310319450A CN103579301B CN 103579301 B CN103579301 B CN 103579301B CN 201310319450 A CN201310319450 A CN 201310319450A CN 103579301 B CN103579301 B CN 103579301B
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管灵鹏
安荷·叭剌
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本发明提出了一种用于高压半导体器件的拐角布局及其制备方法，使半导体器件的击穿电压达到最大。该器件包括条纹晶胞阵列的第一和第二子集。第一阵列中每个条纹晶胞的末端都与最近的端接器件结构保持一段统一的距离。在第二子集中，配置有源晶胞区的拐角附近条纹晶胞末端，通过将每个条纹晶胞末端都与最近的端接器件结构保持不一样的距离，使击穿电压达到最大。

Description

用于高压半导体器件的拐角布局及其制备方法
技术领域
本发明主要涉及半导体功率器件。更确切地说，本发明涉及用于带有沟槽的半导体晶体管器件的端接结构，或用于电荷平衡的半导体晶体管器件的新型结构与制备方法。
背景技术
配置和制备高压半导体功率器件的传统技术出于各种权衡考虑，在进一步提升性能方面，仍然面临许多困难与局限。在垂直半导体功率器件中，作为性能属性的漏源电阻(即导通状态电阻，通常用RdsA表示(即漏源电阻×有源区))，与功率器件可承受的击穿电压之间存在一种取舍关系。通常认可的击穿电压(BV)和RdsA之间的关系表示为：RdsA与BV2.5成正比。为了降低RdsA，制备的外延层掺杂浓度较高。然而，重掺杂外延层也会降低半导体功率器件可承受的击穿电压。
原有技术提出了许多提高功率MOSFET器件BV的方法。示例器件包括超级结MOSFET等电荷平衡器件，以及场平衡MOSFET(FBM)等带有沟槽的表面平衡器件。
超级结是一种众所周知的半导体器件。超级结晶体管提供了一种获得低RdsA，同时保持很高的断开状态BV的方式。超级结器件含有交替的P-型和N-型掺杂立柱，形成在漂流区中。在MOSFET的断开状态下，立柱在很低的电压下完全耗尽，从而可以承受很高的击穿电压(立柱横向耗尽，使整个p和n立柱耗尽)。对于超级结器件来说，RdsA与BV成正比地增大。因此，对于同样的高BV而言，超级结器件比传统的MOSFET器件的RdsA低得多(或者换言之，对于指定的RdsA，超级结器件的BV比传统的MOSFET器件高得多)。
所述的超级结器件，例如在“24mΩcm2 680V硅超级结MOSFET”中，Onishi,Y.；Iwamoto,S.；Sato,T.；Nagaoka,T.；Ueno,K.；Fujihira,T.,第14届功率半导体器件及集成电路国际专题研讨会会刊2002，241-244页，特此引用其全文，以作参考。图1A表示一种传统的超级结结构100的有源晶胞部分的剖面图。在本例中，器件100的有源晶胞部分包括一个垂直FET结构(例如N-通道)，形成在一个适当掺杂的(例如N+)衬底102上，作为漏极接头105的漏极区。适当掺杂的(例如N-外延或N-漂流)层104位于衬底102上方。在本例中，器件100也包括一个P-本体区106、一个N+源极区108以及一个N+多晶硅栅极区112。器件100还包括一个栅极接头(图中没有表示出)以及一个源极金属114。如图1A所示，超级结结构包括交替电荷平衡的P-型立柱130和n-型立柱132。在很低的电压下，这些立柱横向完全耗尽，因此可以在垂直方向上，承受很高的击穿电压。N-型立柱132由位于p-型立柱130附近的那部分n-型外延层104构成。
发明内容
正是在这一前提下，为了使半导体器件的击穿电压达到最大，提出了本发明所述一种用于高压半导体器件的拐角布局及其制备方法的实施例。
本发明的一个技术方案是提供一种半导体器件，包括：
一个掺杂层；
一个具有多个有源晶胞结构的有源晶胞区，具有的第一末端和第二末端，形成在掺杂层中，并排布在条纹晶胞阵列中；以及一个具有多个端接器件结构的端接区，形成在包围着有源晶胞区的掺杂层中，
其中配置条纹晶胞的第一子集，通过使第一子集中每个条纹晶胞的末端都与最近的端接器件结构保持一段统一的距离，使半导体器件的击穿电压达到最大；并且
其中配置有源晶胞区的拐角区域附近的条纹晶胞的第二子集，通过使第二子集中每个条纹晶胞的末端到距离最近的端接器件结构不一样远，使击穿电压达到最大。
一种优选的示例中，所述条纹晶胞的第二子集包括拱形末端部分。
一种优选的示例中，所述拱形末端部分的形状为同心1/4圆。
一种优选的示例中，所述第二子集中每个条纹晶胞末端都与第一子集中最近的条纹晶胞保持一段统一的距离。
一种优选的示例中，拐角区域附近的所述端接器件结构包括拱形部分，拱形部分与条纹晶胞第二子集的拱形末端部分同心。
一种优选的示例中，所述端接器件结构的排列呈同心环阵列。
一种优选的示例中，所述端接器件结构最里面的环阵列具有多个接杆，朝着有源晶胞区向内延伸，其中配置每个接杆和附近第二子集中的条纹晶胞之间的距离，使器件的击穿电压达到最大。
本发明的另一个技术方案是提供一种制备半导体器件的方法，其包括：
制备一个掺杂层；
制备一个具有多个有源晶胞结构的有源晶胞区，具有的第一末端和第二末端，形成在掺杂层中，并排布在条纹晶胞阵列中；并且制备一个具有多个端接器件结构的端接区，形成在包围着有源晶胞区的掺杂层中，
其中配置条纹晶胞的第一子集，通过使第一子集中每个条纹晶胞的末端都与最近的端接器件结构保持一段统一的距离，使半导体器件的击穿电压达到最大；并且
其中配置有源晶胞区的拐角区域附近的条纹晶胞的第二子集，通过使第二子集中每个条纹晶胞的末端到距离最近的端接器件结构不一样远，使击穿电压达到最大。
一种优选的示例中，所述第二子集的条纹晶胞包括拱形末端部分。
一种优选的示例中，所述拱形末端部分配置成同心1/4圆。
一种优选的示例中，所述第二子集中每个条纹晶胞末端都与第一子集中最近的条纹晶胞阵列保持一段统一的距离。
一种优选的示例中，其中拐角区域附近的所述端接器件结构包括拱形部分，拱形部分与第二子集条纹晶胞的拱形末端部分同心。
一种优选的示例中，所述端接器件结构的排列呈同心环阵列。
一种优选的示例中，所述端接器件结构最里面的环阵列具有多个接杆，朝着有源晶胞区向内延伸，其中配置每个接杆与附近第二子集中的条纹晶胞之间的距离，使器件的击穿电压达到最大。
本发明用于高压半导体器件的拐角布局及其制备方法，其优点在于：本发明的一个实施例中提供一种拐角布局，其中优化每个条纹晶胞阵列的末端都远离端接区中的第一端接器件结构。或者，在另一个实施例中使用有源区中传统的条纹晶胞阵列，但与计算每个条纹晶胞阵列末端和端接区之间的间距不同，通过制备端接区中的器件，以促使它们调节这两个区域之间的间距。这两种方案中，通过利用适当地设计假设，能够将每个条纹晶胞阵列之间的距离的排布数量减至100种左右，然后可以制备在一个单独的晶圆上则对于每一种排布都可以测试，利用这种技术，可以获得的BV(击穿电压)达到理想BV的90％。
本发明还可以利用有源晶胞区中两种类型的条纹晶胞阵列，制备有源器件结构。第一种类型的条纹晶胞阵列是传统的条纹晶胞阵列。传统的条纹晶胞阵列是由连续排列的有源器件结构组成。每一排都从有源器件区的一个边缘开始，穿过有源区，直到触及对边上的边缘为止。虽然这些排都在与端接区交叉之前结束，但是它们是定向的，垂直于端接区。第一类型的条纹晶胞阵列包括相对较直的晶胞，方向相互平行。第二类型的条纹晶胞阵列结构由传统的条纹晶胞阵列组成，每个阵列末端都带有拱形部分。第二类型的条纹晶胞阵列用在拐角区附近的区域中。拱形部分的形状通常与拐角端接区附近的拱形部分相同，以便在第二类型的条纹晶胞和附近的拐角端接区之间保持恒定的间距。例如，如果端接区的拐角区形状为1/4圆，那么附近的第二类型条纹晶胞的拱形部分可以是同心1/4圆。关于端接区，最外面的拱形部分保持恒定的间距。凭借这种结构，可以大幅减少最佳间距的计算量，十分有可能实现BV100％接近理论BV值。
附图说明
阅读以下详细说明并参照附图之后，本发明的其他特点和优势将显而易见，其中：
图1A表示一种原有技术的超级结器件的示意图。
图1B表示一种FBM器件的示意图。
图2表示依据本发明的一个实施例，有源区和端接区的器件晶片的俯视图。
图3A表示本发明的第一实施例，一种拐角布局的俯视图。
图3B表示本发明的第二实施例，一种拐角布局的俯视图。
图3C表示本发明的第二实施例，拐角结构的放大视图。
图3D表示本发明的第三实施例，一种拐角布局的俯视图。
具体实施方式
尽管为了解释说明，以下详细说明包含了许多具体细节，但是本领域的技术人员应明确以下细节的各种变化和修正都属于本发明的范围。因此，提出以下本发明的典型实施例，并没有使所声明的方面损失任何普遍性，也没有提出任何局限。
在以下详细说明中，参照附图，表示本发明可以实施的典型实施例。就这一点而言，根据图中所示方向，使用“顶部”、“底部”、“正面”、“背面”、“向前”、“向后”等方向术语。由于本发明实施例的零部件，可以位于各种不同方向上，因此所用的方向术语仅用于解释说明，不用于局限。应明确，无需偏离本发明的范围，就能实现其他实施例，做出结构或逻辑上的变化。因此，以下详细说明不用于局限，本发明的范围应由所附的权利要求书限定。
引言
场平衡金属氧化物场效应晶体管(FBM)的独特设计，可以大幅提高器件的BV，同时最小限度地增大RdsA。图1B表示FBM器件101的基本结构。在FBM器件中，BV在表面屏蔽区104和电压闭锁区103之间分开。作为示例，但不作为局限，所设计的FBM器件的660V的BV可以使表面屏蔽区104承受140V，使电压闭锁区103承受520V。电压闭锁区103作为传统的外延层，遵循下述关系式：RdsA∝BV2.5。因此，由于电压闭锁区103所承受的电压从660V降至520V，导致RdsA成比例地降低(660/520)2.5＝1.81。例如，如果器件的RdsA一开始是82mΩ·cm2，那么外延层必须承受整体的660V，电压闭锁区103只需承受520V，仅仅需要降低45.2mΩ·cm2的RdsA。
配置表面屏蔽区104，承受剩余的电压，增大的电阻可忽略不计。为了达到上述目标，使RdsA最小，要重掺杂表面屏蔽区104。然而，掺杂浓度增大后，外延层本身无法承受足够的电压。因此，必须对表面屏蔽区104进行电荷补偿。电荷补偿由两个单独的部分进行：(1)由氧化物107制成的MOS电容器，包围着屏蔽电极111；以及(2)掩埋P-区109。两种部件均可配置以便各自承受期望的电压量。作为示例，但不作为局限，表面屏蔽区104所承受的电压，由掩埋P-区109承担一半，另一半由氧化物107承担。
在指定的RdsA下，使用FBM器件比传统的MOSFET器件承受的击穿电压BV更高，但是FBM结构本身不能降低指定位置的BV。确切地说，器件晶片边缘处的BV通常远远低于漂流层可承受的BV。为了使器件边缘处的峰值电场最小，需使用端接结构，以削弱局域击穿效果。
局域击穿的效果可以参见图2，图2表示局域有源区220和端接区221的器件晶片200的俯视图。电荷平衡和表面增强器件可以提高有源区220中的器件BV，但是仅靠这个结构并不能避免有局限地降低BV。这些受限位置通常出现在器件晶片200的拐角229和边缘228处。关于超级结类型器件，由于很难平衡交替立柱产生的电荷，因此拐角229表示局域击穿的区域。电荷不平衡的区域防止立柱完全耗尽，从而不能承受整体的理论BV。关于FBM类型器件，由于器件的结构与端接区有关，致使电场与器件剩余部分的电场相比变化很大，因此拐角229表示局域击穿区域。对于指定的高功率MOSFET来说，无论理论BV值多高，器件真实的BV总会受到这些局域区域处低BV的限制。
本发明的实施例通过将器件布局设计在易受局域击穿影响的区域中，提出了与局域击穿有关的问题。
本发明的第一实施例涉及一种拐角布局，其中优化每个条纹晶胞阵列的末端都远离端接区中的第一端接器件结构。分析确定每个条纹晶胞阵列之间的最佳距离，将是非常复杂繁琐、不切实际的。然而，通过利用适当地设计假设，有可能将距离的排布数量减至100种左右，然后可以制备在一个单独的晶圆上。一旦制成，每一种排布都可以测试，而且利用这种技术，可以获得的BV达到理想BV的90％。
本发明的第二实施例，利用有源晶胞区中两种类型的条纹晶胞阵列，制备有源器件结构。第一种类型的条纹晶胞阵列是传统的条纹晶胞阵列。传统的条纹晶胞阵列是由连续排列的有源器件结构组成。每一排都从有源器件区的一个边缘开始，穿过有源区，直到触及对边上的边缘为止。虽然这些排都在与端接区交叉之前结束，但是它们是定向的，垂直于端接区。第一类型的条纹晶胞阵列包括相对较直的晶胞，方向相互平行。第二类型的条纹晶胞阵列结构由传统的条纹晶胞阵列组成，每个阵列末端都带有拱形部分。第二类型的条纹晶胞阵列用在拐角区附近的区域中。拱形部分的形状通常与拐角端接区附近的拱形部分相同，以便在第二类型的条纹晶胞和附近的拐角端接区之间保持恒定的间距。例如，如果端接区的拐角区形状为1/4圆，那么附近的第二类型条纹晶胞的拱形部分可以是同心1/4圆。关于端接区，最外面的拱形部分保持恒定的间距。凭借这种结构，可以大幅减少最佳间距的计算量，十分有可能实现BV100％接近理论BV值。
本发明的第三实施例使用有源区中传统的条纹晶胞阵列。然而，与计算每个条纹晶胞阵列末端和端接区之间的间距不同，制备端接区中的器件，以促使它们调节这两个区域之间的间距。分析确定每个条纹晶胞阵列之间的最佳距离，将是非常复杂繁琐、不切实际的。然而，通过利用适当地设计假设，有可能将距离的排布数量减至100种左右，然后可以制备在一个单独的晶圆上。一旦制成，每一种排布都可以测试，而且利用这种技术，可以获得的BV达到理想BV的90％。
典型实施例
本发明的第一实施例涉及一种高压MOSFET器件的拐角布局，使用形成在条纹晶胞阵列中的有源器件结构。图3A表示器件晶片300的有源区220的拐角区229。有源器件结构形成在条纹晶胞阵列305中。作为示例，但不作为局限，条纹晶胞阵列305可以和超级结器件等电荷平衡结构一起使用，或者和FBM器件等基于沟槽的结构一起使用。关于超级结结构，黑色条纹表示用第二导电类型掺杂物(即P-型)掺杂的立柱，白色条纹表示用第一导电类型掺杂物(即N-型)掺杂的立柱。关于基于沟槽的结构，黑色条纹表示器件的垂直沟槽部分。为了简便，附图中省去器件结构的剩余部分。
在端接区221中，端接器件结构形成在同心端接环阵列307中，同心端接环阵列307包围着有源区220的外围。同心端接环阵列307继续向外，直到触及器件晶片的边缘为止。如图3A所示，每个条纹晶胞阵列305的末端和第一端接环阵列307之间的间距用距离Si表示。为了优化器件的BV，对于每个在拐角区域周围的条纹晶胞阵列305来说，必须单独计算Si的真实距离。每个与端接环阵列307呈直角的条纹晶胞阵列305的Si值是恒定的。
要计算每个条纹晶胞305和第一端接环307之间的最佳间距Si，将是十分繁琐复杂的。然而，为了简化设计问题的复杂程度，可以进行适当地工艺假设。利用工艺假设，省去对于本领域的技术人员来说并不是可行的解决方案的可能的间距Si。
例如，对于基于沟槽的结构设计来说，如果间距Si过大，那么器件就不能完全耗尽，从而无法承受器件的理论BV。因此，对于存在Si的器件的设计方式，如果器件不能完全耗尽，那么就要删除这种设计方式。另外，如果Si过小，器件会耗尽得过快。这将会使电压闭锁层被迫承载过多的BV，而且器件将受损。因此，如果器件的Si大于或小于闭锁所需电压的间距，可以去掉这样的器件。
一旦减少了必须的计算量，就可以制备器件测试晶圆了。通过上述删除过程，设计工程师可以将每个条纹阵列305和端接环307之间的间距变化数量减至100种可能性左右。这些可能的解决方案可以制备在一个测试晶圆上，每种方案都要测试，以便确定能使BV最大的方案。尽管这种方法也许并不能制备出可以承受理论上最大BV的理想布局，但是却可以提供承受大约90％的理论BV的方法。第一轮测试后，通过额外的迭代法，进一步提高BV。
图3B表示本发明的第二实施例，高压MOSFET器件301的一种拐角布局，利用形成在笔直的条纹晶胞阵列305中以及带有拱形末端306的条纹晶胞阵列中。利用有源区中两种不同的阵列结构，可以减少优化BV所需的计算量。
在本实施例中，在不靠近拐角229的那部分有源区220中，使用笔直的条纹晶胞阵列305。每个笔直的条纹晶胞阵列都从有源区220的一个边缘附近开始，然后穿过有源区220，直到触及对边上的边缘为止。条纹晶胞阵列305的末端距离第一端接环307的距离为SA(如图3C所示)。笔直的条纹晶胞阵列305相互平行，与笔直的条纹晶胞阵列305末端附近的那部分端接环307垂直。
图3C表示图3B所示的拐角部分302。如图3B-3C所示，拐角部分229附近的条纹晶胞阵列在它们的长度部分上方是笔直的，还包括在它们末端附近的拱形部分306，它们的末端与拐角区229中的端接环曲率是同心的。拱形部分306是同心的，其中最外面的拱形部分306最靠近端接环307，最里面的拱形部分306离端接环307最远。作为示例，但不作为局限，拱形部分306的形状为1/4圆。本实施例中的端接环307与拱形部分306的曲率一致。使最外面的条纹晶胞阵列305和最里面的端接环307之间的间距SB是恒定的。对于有源阵列来说，SB等于晶胞间距。
定位拱形部分306的每个末端，使其拦截最外面不变的条纹晶胞305呈90°角。为了明确表示，应注意有源区220中没有一个条纹晶胞阵列是真实交叉的。最外面不变的条纹晶胞阵列305与拱形部分306末端之间的间距定义为SC。
依据本发明的部分实施例，可以使用一种中间条纹晶胞阵列305’，进一步优化器件的BV。中间条纹阵列305’从一个拐角的拱形部分306开始延伸，穿过有源区，直到触及对面拐角上的拱形部分306为止。间距SD限定了中间条纹晶胞阵列305’和带有拱形部分306的最里面的条纹晶胞阵列305之间的距离。
本实施例仅需要四个单独的间距测定SA、SB、SC和SD。有限数量的可能性，使计算不再复杂，通过有限数量的过程和器件(例如TCAD)模拟，就可以优化设计方案。因此，本实施例可以获得理论上最大的BV。
图3C表示本发明的第三实施例，涉及一种高压MOSFET器件的拐角布局，该MOSFET器件使用的是形成在条纹晶胞阵列中的有源器件结构。图3C表示器件晶片303的有源区220的拐角区229。条纹晶胞阵列305的布局方式与第一实施例中条纹晶胞阵列的布局方式类似。在端接区221中，端接器件结构形成在包围着有源区220外围的同心端接环阵列307中，延续到器件晶片的边缘。另外，最里面的端接环307具有很小的接杆308，朝着有源区220突起。对于基于沟槽的器件来说，接杆308为沟槽，对于超级结型器件来说，接杆308为适当掺杂的立柱，使区域中的电荷平衡。
如图3D所示，每个接杆308末端和最近的条纹晶胞阵列305之间的距离用Si表示。为了优化器件的BV，对于拐角区域附近的每个接杆305来说，Si的真实距离必须单独计算。要注意的是，每个条纹晶胞阵列附近的接杆305的数量可以不同。
确定接杆308的最佳数量，以及每个接杆308和最近的条纹晶胞阵列305最近的最佳距离Si，需要许多繁琐的计算过程。为了简化该设计问题的复杂程度，可以进行适当的工艺假设。利用工艺假设，省去对于本领域的技术人员并不可行的可能的距离Si。
例如，对于基于沟槽类型的器件设计，如果间距Si过大，那么器件将无法完全耗尽，从而不能承受器件的理论BV。因此，对于存在Si的器件的设计方式，如果器件不能完全耗尽，那么就要删除这种设计方式。另外，如果Si过小，器件会耗尽得过快。这将会使电压闭锁层被迫承载过多的BV，而且器件将受损。因此，如果器件的Si大于或小于闭锁所需电压的间距，可以去掉这样的器件。
一旦减少了必须的计算量，就可以制备器件测试晶圆了。通过上述删除过程，设计工程师可以将每个接杆308和条纹晶胞阵列305之间的间距变化数量减至100种可能性左右。这些可能的解决方案可以制备在一个测试晶圆上，每种方案都要测试，以便确定能使BV最大的方案。尽管这种方法也许并不能制备出可以承受理论上最大BV的理想布局，但是却可以提供承受大约90％的理论BV的方法。第一轮测试后，通过额外的迭代法，进一步提高BV。
尽管以上是本发明的较佳实施例的完整说明，但是也有可能使用各种可选、修正和等效方案。因此，本发明的范围不应局限于以上说明，而应由所附的权利要求书及其全部等效内容决定。本方法中所述步骤的顺序并不用于局限进行相关步骤的特定顺序的要求。任何可选件(无论首选与否)，都可与其他任何可选件(无论首选与否)组合。

Claims (2)

1.一种半导体器件，其特征在于，包含：
一个掺杂层；
一个具有多个有源晶胞结构的有源晶胞区，具有的第一末端和第二末端，形成在掺杂层中，并排布在条纹晶胞阵列中；以及一个具有多个端接器件结构的端接区，形成在包围着有源晶胞区的掺杂层中，
其中配置条纹晶胞的第一子集，通过使第一子集中每个条纹晶胞的末端都与最近的端接器件结构保持一段统一的距离，使半导体器件的击穿电压达到最大；并且
其中配置有源晶胞区的拐角区域附近的条纹晶胞的第二子集，通过使第二子集中每个条纹晶胞的末端到距离最近的端接器件结构不一样远，使击穿电压达到最大；
所述端接器件结构的排列呈同心环阵列；
所述端接器件结构最里面的环阵列具有多个接杆，朝着有源晶胞区向内延伸，其中配置每个接杆和附近第二子集中的条纹晶胞之间的距离，使器件的击穿电压达到最大。
2.一种制备半导体器件的方法，其特征在于，包含：
制备一个掺杂层；
制备一个具有多个有源晶胞结构的有源晶胞区，具有的第一末端和第二末端，形成在掺杂层中，并排布在条纹晶胞阵列中；并且制备一个具有多个端接器件结构的端接区，形成在包围着有源晶胞区的掺杂层中，
其中配置条纹晶胞的第一子集，通过使第一子集中每个条纹晶胞的末端都与最近的端接器件结构保持一段统一的距离，使半导体器件的击穿电压达到最大；并且
其中配置有源晶胞区的拐角区域附近的条纹晶胞的第二子集，通过使第二子集中每个条纹晶胞的末端到距离最近的端接器件结构不一样远，使击穿电压达到最大；
所述端接器件结构的排列呈同心环阵列；
所述端接器件结构最里面的环阵列具有多个接杆，朝着有源晶胞区向内延伸，其中配置每个接杆与附近第二子集中的条纹晶胞之间的距离，使器件的击穿电压达到最大。
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