CN105702711A - 超级结器件 - Google Patents

超级结器件 Download PDF

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Publication number
CN105702711A
CN105702711A CN201610065809.1A CN201610065809A CN105702711A CN 105702711 A CN105702711 A CN 105702711A CN 201610065809 A CN201610065809 A CN 201610065809A CN 105702711 A CN105702711 A CN 105702711A
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王飞
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种超级结器件，在N型外延中具有平行的P柱沟槽，P柱沟槽之间为体区，在体区与P柱的交界处具有沟槽型栅极；所述沟槽型栅极是沟槽内壁附着氧化层后填充多晶硅形成，P柱与体区通过沟槽型栅极隔离。本发明通过新的沟槽型栅极的位置，通过沟槽型栅极将P柱与体区隔离开来，在缩小沟槽间距的同时保证沟道附近有足够的电流导通区域保证导通电阻不受影响。P柱与体区的隔离也可以对P柱和体区的电势分别进行调节，进而控制器件的关断速度。

Description

超级结器件
技术领域
本发明涉及半导体集成电路制造领域，特别是指一种超级结器件。
背景技术
超级结功率器件是一种发展迅速、应用广泛的新型功率半导体器件。它是在双扩散金属氧化物半导体(DMOS)的基础上，通过引入超级结(SuperJunction)结构，除了具备DMOS输入阻抗高、开关速度快、工作频率高、热稳定好、驱动电路简单、易于集成等特点外，还克服了DMOS的导通电阻随着击穿电压成2.5次方关系增加的缺点。目前超级结DMOS已广泛应用于面向个人电脑、笔记本电脑、上网本、手机、照明(高压气体放电灯)产品以及电视机(液晶或等离子电视机)和游戏机等消费电子产品的电源或适配器。
目前超级结功率器件的制备工艺主要分成两大类，一种是利用多次外延和注入的方式在N型外延衬底上形成P柱；另外一种是在深沟槽刻蚀加P柱填充的方式形成。
现有的深槽型超级结器件，如图1所示，在衬底或外延中具有P柱，P柱之上为体区，P柱位于体区的中心处形成一种平衡的左右对称状态。体区之间为JFET区域，外延之上体区之间为栅极。图2是器件的体区和栅极俯视图。为了进一步降低导通电阻，必须要用更低电阻的外延基片，同时为了保持击穿电压不下降，需要将P柱深槽的间距不断缩短，来保证耗尽区能够在沟槽之间完全展开。相对大尺寸深槽间距的超级结产品，深槽间的空间有足够大用来形成对称的双沟道器件结构，而随着沟槽之间距离的减小，没有足够空间形成双沟道。而沟槽间距的降低，会限制JFET区域的大小，影响到器件的沟道长度，提高导通电阻。
图3是另一种沟槽型栅极的超级结器件示意图，图中形成沟槽型栅极位于P柱之间的体区中，基于这种结构，如图4所示，缩小P柱之间的间距会引起平面栅结构的沟道没有足够的区域形成，如果P柱与沟槽栅极的间距太近，还是会引起器件的导通电阻增大的问题。
发明内容
本发明所要解决的技术问题是提供一种超级结器件，其能有效解决超级结器件的导通电阻问题，同时还可以对超级结器件的开关时序进行调节。
为解决上述问题，本发明提供一种超级结器件，在N型外延中具有平行的P柱沟槽，P柱沟槽之间为体区，在体区与P柱的交界处具有沟槽型栅极；所述沟槽型栅极是沟槽内壁附着氧化层后填充多晶硅形成。
进一步地，所述的沟槽型栅极位于P柱与体区的交界处，即沟槽型栅极一部分位于P柱中，另一部分位于体区中。
进一步地，所述的P柱与体区通过沟槽型栅极隔离。
本发明所述的超级结器件，通过新的沟槽型栅极的位置，通过沟槽型栅极将P柱与体区隔离开来，在缩小沟槽间距的同时保证沟道附近有足够的电流导通区域保证导通电阻不受影响。P柱与体区的隔离也可以对P柱和体区的电势分别进行调节，进而控制器件的关断速度。
附图说明
图1是现有超级结器件的剖面图。
图2是图1的俯视图。
图3是另一种沟槽型栅极超级结器件的剖面示意图。
图4是将图3所示结构P柱之间间距进一步缩小的示意图。
图5是本发明超级结器件的剖视图。
附图标记说明
1是衬底或外延，2是体区，3是P柱，4是栅极,5是栅氧化层。
具体实施方式
本发明提供一种超级结器件，如图5所示，在N型外延1中具有平行的P柱沟槽3，P柱沟槽3之间为体区2，在体区2与P柱3的交界处具有沟槽型栅极4，即沟槽型栅极4一部分位于P柱3中，另一部分位于体区2中，P柱3与体区2通过沟槽型栅极4隔离。所述沟槽型栅极4是沟槽内壁附着氧化层5后填充多晶硅形成。
本发明所述的超级结器件，将沟槽型栅极挪到P柱与体区的交界处，通过沟槽型栅极将P柱与体区隔离开来，可以进一步的缩小P柱沟槽之间的间距。在缩小沟槽间距的同时保证沟道附近有足够的电流导通区域来保证导通电阻不受影响。P柱与体区的隔离也可以更方便地对P柱和体区的电势分别进行调节，进而控制超级结器件的关断速度。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (3)

1.一种超级结器件，其特征在于：在N型外延中具有平行的P柱沟槽，P柱沟槽之间为体区，在体区与P柱的交界处具有沟槽型栅极；所述沟槽型栅极是沟槽内壁附着氧化层后填充多晶硅形成。
2.如权利要求1所述的超级结器件，其特征在于：所述的沟槽型栅极位于P柱与体区的交界处，即沟槽型栅极一部分位于P柱中，另一部分位于体区中。
3.如权利要求1所述的超级结器件，其特征在于：所述的P柱与体区通过沟槽型栅极隔离。
CN201610065809.1A 2016-01-29 2016-01-29 超级结器件 Pending CN105702711A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037357A (zh) * 2018-08-06 2018-12-18 南京方旭智芯微电子科技有限公司 低米勒电容制造方法
CN112864244A (zh) * 2019-11-12 2021-05-28 南通尚阳通集成电路有限公司 超结器件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050006717A1 (en) * 2003-06-24 2005-01-13 Hitoshi Yamaguchi Semiconductor device having super junction construction and method for manufacturing the same
CN101267000A (zh) * 2008-04-29 2008-09-17 西安理工大学 氧化物填充扩展沟槽栅超结mosfet及其制造方法
US20110233684A1 (en) * 2010-03-24 2011-09-29 Kabushiki Kaisha Toshiba Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050006717A1 (en) * 2003-06-24 2005-01-13 Hitoshi Yamaguchi Semiconductor device having super junction construction and method for manufacturing the same
CN101267000A (zh) * 2008-04-29 2008-09-17 西安理工大学 氧化物填充扩展沟槽栅超结mosfet及其制造方法
US20110233684A1 (en) * 2010-03-24 2011-09-29 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037357A (zh) * 2018-08-06 2018-12-18 南京方旭智芯微电子科技有限公司 低米勒电容制造方法
CN112864244A (zh) * 2019-11-12 2021-05-28 南通尚阳通集成电路有限公司 超结器件

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