CN105679830A - 超级结器件 - Google Patents

超级结器件 Download PDF

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Publication number
CN105679830A
CN105679830A CN201610065836.9A CN201610065836A CN105679830A CN 105679830 A CN105679830 A CN 105679830A CN 201610065836 A CN201610065836 A CN 201610065836A CN 105679830 A CN105679830 A CN 105679830A
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junction device
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王飞
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN201610065836.9A priority Critical patent/CN105679830A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种超级结器件，在N型外延中具有P柱和体区，所述P柱位于体区的下方，P柱呈平行沟槽型；体区之间的区域为JFET区域，外延表面具有栅极，所述栅极位于体区之间的硅表面，并且栅极与P柱在平面的投影是呈垂直相交的状态。本发明通过新的栅极与P柱沟槽的相对位置，在能缩小P柱沟槽间距的同时，保持沟道足够的长度，以及沟道间JFET区域的大小，保证MOSFET管的正常沟道开启特性，得到较小的导通电阻。

Description

超级结器件
技术领域
本发明涉及半导体集成电路制造领域，特别是指一种超级结器件。
背景技术
超级结功率器件是一种发展迅速、应用广泛的新型功率半导体器件。它是在双扩散金属氧化物半导体(DMOS)的基础上，通过引入超级结(SuperJunction)结构，除了具备DMOS输入阻抗高、开关速度快、工作频率高、热稳定好、驱动电路简单、易于集成等特点外，还克服了DMOS的导通电阻随着击穿电压成2.5次方关系增加的缺点。目前超级结DMOS已广泛应用于面向个人电脑、笔记本电脑、上网本、手机、照明(高压气体放电灯)产品以及电视机(液晶或等离子电视机)和游戏机等消费电子产品的电源或适配器。
目前超级结功率器件的制备工艺主要分成两大类，一种是利用多次外延和注入的方式在N型外延衬底上形成P柱；另外一种是在深沟槽刻蚀加P柱填充的方式形成。
现有的深槽型超级结器件，如图1所示，在衬底或外延中具有P柱，P柱之上为体区。体区之间为JFET区域，外延之上体区之间为栅极。图2是器件的俯视图。为了进一步降低导通电阻，必须要用更低电阻的外延基片，同时为了保持击穿电压不下降，需要将深槽的间距不断缩短，来保证耗尽区能够在沟槽之间完全展开。而沟槽间距的降低，会限制JFET区域的大小，影响到器件的沟道长度，提高导通电阻。
基于现有结构，如图2所示，缩小P柱之间距离，使得P柱和栅极的投影有重叠(如图3所示)，会引起JFET区域电阻增大，如果增加JFET注入还会影响MOSFET沟道的浓度和有效长度。
发明内容
本发明所要解决的技术问题是提供一种超级结器件，其具有耐击穿的性能，同时又保证器件的开启电压和低导通电阻特性。
为解决上述问题，本发明提供一种超级结器件，在N型外延中具有P柱和体区，所述P柱位于体区的下方，P柱呈平行沟槽型；体区之间的区域为JFET区域，外延表面具有栅极，所述栅极位于体区之间的硅表面，并且栅极与P柱在平面的投影是呈垂直相交的状态。
进一步地，所述外延中还存在P阱，所述P阱为栅极和P柱以外的区域，且允许和栅极有重叠。
进一步地，超级结器件的沟道区为栅极和P阱重叠的区域。
进一步地，超级结器件的耐压由P柱和N型外延形成的耗尽区提供。
本发明所述的超级结器件，通过新的栅极与P柱沟槽的相对位置，在能缩小P柱沟槽间距的同时，保持沟道足够的长度，以及沟道间JFET区域的大小，保证MOSFET管的正常沟道开启特性，得到较小的导通电阻。
附图说明
图1是现有超级结器件的剖面图。
图2是图1的俯视图。
图3是缩小P柱之间间距的剖面示意图。
图4是图3的俯视图。
图5是本发明器件的俯视图。
图6是图5沿a线剖视图。
图7是图5沿b线剖视图。
附图标记说明
1是衬底或外延，2是体区，3是P柱，4是栅极。
具体实施方式
本发明提供一种超级结器件，在N型外延中具有P柱和体区，所述P柱位于体区的下方，P柱呈平行沟槽型；体区之间的区域为JFET区域，外延表面具有栅极，所述栅极位于体区之间的硅表面，并且栅极与P柱在平面的投影是呈垂直相交的状态，如图5所示。
所述外延中还存在P阱5，所述P阱为栅极及和P柱以外的区域，且允许和栅极有重叠。
超级结器件的沟道区为栅极和P阱重叠的区域。
如图6所示，为图5沿a线的剖视图，超级结器件的耐压由P柱和N型外延形成的耗尽区提供。如图7所示，是图5由沿b线剖视的示意图，器件的导通特性是由栅极和沟道来确定，在P柱沟槽延伸方向可以提供足够的空间来保持沟道和JFET区域的尺寸。
本发明所述的超级结器件，通过新的栅极与P柱沟槽的相对位置，在能缩小P柱沟槽间距的同时，保持沟道足够的长度，以及沟道间JFET区域的大小，本发明将超级结器件的耐压能力和导通特性在垂直相交的两个方向上分开来优化实现，保证MOSFET管的正常沟道开启特性，得到较小的导通电阻。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (4)

1.一种超级结器件，其特征在于：在N型外延中具有P柱和体区，所述P柱位于体区的下方，P柱呈平行沟槽型；体区之间的区域为JFET区域，外延表面具有栅极，所述栅极位于体区之间的硅表面，并且栅极与P柱在平面的投影是呈垂直相交的状态。
2.如权利要求1所述的超级结器件，其特征在于：所述外延中还存在P阱，所述P阱为栅极和P柱以外的区域，且允许和栅极有重叠。
3.如权利要求2所述的超级结器件，其特征在于：超级结器件的沟道区为栅极和P阱重叠的区域。
4.如权利要求1所述的超级结器件，其特征在于：超级结器件的耐压由P柱和N型外延形成的耗尽区提供。
CN201610065836.9A 2016-01-29 2016-01-29 超级结器件 Pending CN105679830A (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080246096A1 (en) * 2007-04-03 2008-10-09 Denso Corporation Semiconductor device including schottky barrier diode and method of manufacturing the same
CN101308875A (zh) * 2007-05-14 2008-11-19 株式会社电装 具有超结结构的半导体器件及其制造方法
CN102306662A (zh) * 2011-09-21 2012-01-04 苏州博创集成电路设计有限公司 超结纵向双扩散金属氧化物场效应管的终端结构
US20120007173A1 (en) * 2010-07-12 2012-01-12 Denso Corporation Semiconductor device and manufacturing method of the same
US20120086076A1 (en) * 2009-07-15 2012-04-12 Fuji Electric Co., Ltd. Super-junction semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080246096A1 (en) * 2007-04-03 2008-10-09 Denso Corporation Semiconductor device including schottky barrier diode and method of manufacturing the same
CN101308875A (zh) * 2007-05-14 2008-11-19 株式会社电装 具有超结结构的半导体器件及其制造方法
US20120086076A1 (en) * 2009-07-15 2012-04-12 Fuji Electric Co., Ltd. Super-junction semiconductor device
US20120007173A1 (en) * 2010-07-12 2012-01-12 Denso Corporation Semiconductor device and manufacturing method of the same
CN102306662A (zh) * 2011-09-21 2012-01-04 苏州博创集成电路设计有限公司 超结纵向双扩散金属氧化物场效应管的终端结构

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