CN1524296A - 一种射频功率ldmos(横向扩散金属氧化物半导体)晶体管 - Google Patents
一种射频功率ldmos(横向扩散金属氧化物半导体)晶体管 Download PDFInfo
- Publication number
- CN1524296A CN1524296A CNA028062507A CN02806250A CN1524296A CN 1524296 A CN1524296 A CN 1524296A CN A028062507 A CNA028062507 A CN A028062507A CN 02806250 A CN02806250 A CN 02806250A CN 1524296 A CN1524296 A CN 1524296A
- Authority
- CN
- China
- Prior art keywords
- gate
- metal
- pair
- transistor
- fingers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
在一种射频功率LDMOS晶体管中,其包含多对平行的栅极指针(11),其中栅极指针位于一种相关的p+向下扩展(23)的对立边之上,而且包含用于造成p+向下扩展短路的金属夹(14),每一对栅极指针(11)中的一种栅极指针与分离的金属夹(14)相关,该金属夹造成n+源极区域(20)的短路以及与特定的栅极指针(11)相关的p+向下扩展(23)的短路。与每个栅极指针对相关的分离金属夹(14)被一种槽(15)分开,该槽在平行的栅极指针(11)之间延伸,而且一种金属转轮(13)在分离的金属夹(14)之间的槽(15)中延伸,该夹与来自一种栅极填充的每个指针对相关。一种栅极指针对的两个栅极指针(11)都被连接到相关的金属转轮(13),连接处位于指针的两端以及沿其长度的预定位置。
Description
技术领域
本发明通常涉及射频功率LDMOS晶体管,更具体而言,涉及这种用于第三代无线通信系统的晶体管。
背景技术
离散的射频功率LDMOS晶体管主要用于建造在射频基站中所使用的功率放大器。
图1显示一种传统射频功率LDMOS晶体管的一部分布局的顶端视图。该晶体管包含多个平行LDMOS晶体管单元,图1显示其中的两个单元,其中这些单元是一种互相交叉的指针结构,包含多对漏指针1,多对栅极指针2和源极/容积金属夹3。漏指针1和栅极指针2分别连接到位于晶体管单元对立边上的一种漏馈电棒4和一种栅极馈电棒5上,如图1所示。传统的LDMOS功率晶体管包含许多平行单元。
然而,第三代(3G)无线系统对射频功率晶体管设定了新的要求。不但要求较高的频率(>2GHz),这本身就是一种挑战,而且在线性上的极高要求也迫使功率放大器的设计者们在远远低于额定最大输出功率时使用功率晶体管。晶体管必须在此后退输出功率水平上运行,即具有较高的增益和较好的效率。
这些新的要求迫使射频功率晶体管的设计者们脱离晶体管旧的″平行单元″布局,而转向一种微有不同的设计。该第三代设计仅使用一个互相交叉的晶体管单元,与较旧设计中的单元方向相比,该单元有90度的旋转。
这种新设计最大的优点是在每个有源晶体管区域中都极大地降低了晶体管外围,其因此产生较低的输出容量和经过改善的效率。
为了使栅极外围和一种带有多个平行单元的晶体管相等,单一的单元需要在两个向度上进行伸展,以便它含有更多的指针。为了保持晶体管管芯的一种适当宽高比,指针也需要加长许多。
图2显示第三代设计的原理,其是一种已知的第三代射频功率LDMOS晶体管一部分布局的顶端视图。多对漏指针6被连接到一种共同的漏结合填充上(未显示),图2只显示其中的一对。多对栅极指针7在其各端和沿其长度预定的位置得到互连,其方法是使用若干片第一金属层,图2只显示该栅极指针对中的一对。图2显示此互连片8。源极/容积金属夹9也是用所述的第一金属层来制造的,其延伸至互连片之间的一对栅极指针7的上方。
依照上文的描述,第三代设计无可避免地与较长的指针相关。尤其在晶体管的栅极边上会发生这一问题。栅极指针通常由高度掺杂的多晶硅制成,其顶端可能具有一层金属硅化物,以便减少电阻率。然而,栅极指针的电阻根本不可忽略,而且在栅极指针长度的某些点上,将会对晶体管的功能产生负面影响。
这个问题在已知的第三代晶体管设计中已经得到解决,其方法是引入一种第二金属层。通过这种做法,人们能设计一种位于源极/容积夹9顶端的金属转轮10。通过一种电介质层(未在图2中显示)可以使金属转轮10隔离于夹9,而且该转轮被连接到该对栅极指针7,连接处位于经过互连片8、沿栅极指针7长度的预定位置上,同时也位于其各自的端点。金属转轮10的一端被连接到一种共同的栅极结合填充(未显示)。
因此,每个栅极指针的有效长度将等于两个栅极互连片之间距离的一半。
然而,晶体管设计中第二金属层的引入增加了设计过程和生产过程的复杂性。应该指出,在此连接中,如图2所示,漏指针6由两个金属层组成,即位于第一金属层顶端的第二金属层。在晶体管管芯的生产过程中,需要增加两种额外的屏蔽步骤,以及多个额外的过程步骤。
发明内容
本发明的目的在于生产一种第三代射频功率LDMOS晶体管,其与目前已知的晶体管相比,更易于生产。
通过依照本发明的晶体管可达到这一目的,主要通过仅使用一种金属层来实现,该金属层与较长的栅极指针进行中间接触。
附图说明
本发明将在以下参考附图得到更详细的说明。
其中,
图1显示一种传统射频功率LDMOS晶体管的布局;
图2显示一种已知的第三代射频功率LDMOS晶体管的布局;
图3显示了根据本发明的一种第三代射频功率LDMOS晶体管的布局;
图4是图3中根据本发明的晶体管沿线段A-A显示的截面视图。
具体实施方式
图3显示一种根据本发明的射频功率LDMOS晶体管的布局。
图2中已知的第三代晶体管包含两个金属层,与此不同的是,依照本发明的第三代晶体管只包含一个金属层。
在图3依照发明的晶体管中,每个栅极指针对的栅极指针11都通过金属层的各片在它们的各端和沿它们长度的预定位置上形成互连。图3显示了这种互连片12之一。
符合本发明的情况是,一种被连接到一种共同栅极结合填充的金属转轮13(未显示)被与针对对应栅极指针对的互连片12制成一个整体,用于每一对栅极指针11。
同样符合本发明的情况是,分离的源及极/容积金属夹14用与互连片12和金属转轮13相同的金属层生产而成,这些金属夹与每一对栅极指针中的每个栅极指针11相关。与各自对应的每一对栅极指针中的每个栅极指针11相关的金属夹14被一种槽15分开,该槽在每一对栅极指针中的平行栅极指针11之间延伸。
符合本发明的情况是,金属转轮13在金属夹14之间的槽15中制成。
多对漏指针16由与互连片12、金属转轮13以及金属夹14相同的金属层生产而成,其被连接到晶体管中一种共同的漏结合填充(未显示)。
图4是图3中依照本发明的晶体管的一种沿线段A-A的截面视图。在图4中,使用与图3相同的参考数字来指示同一组件。
在一种本身已知的方式中,晶体管被内置入一种p+基片17之内,其顶端具有一种p-epi18,并包含交替的n+漏区域19和n+源极区域20,其中n+漏区域19被通过一种n-漂移区域21从栅极11处分离出来。
一种p-型信道掺杂剂或p-井22被横向扩散在栅极11之下从其源极边出发的位置上。
一种深度的p+扩散或p+向下扩展23允许电流从n+源极区域20继续被传递到p+基片17,其电压降落是最小的,形成这种传递的方法是通过金属夹14造成这些区域彼此短路。
一种电介质层24将栅极指针11从金属夹14处分离出来,并将金属转轮13从p+向下扩展区域23处分离出来。
Claims (2)
1.一种射频功率LDMOS晶体管,其包含多对平行的栅极指针(11),每个栅极指针对的栅极指针(11)都位于一种相关的p+向下扩展(23)的对立边之上,而且提供金属夹(14)来造成p+向下扩展(23)和位于p+向下扩展(23)对立边上的n+源极区域(20)的短路,
其特征在于:
一种栅极指针对的每个栅极指针(11)都与分离的金属夹(14)相关,该金属夹造成n+源极区域(20)和与该特定的栅极指针(11)相关的p+向下扩展(23)的短路;
与每个栅极指针对相关的分离金属夹(14)被一种槽(15)分离,该槽在平行的栅极指针(11)之间延伸;
一种金属转轮(13)在分离的金属夹(14)之间的槽(15)中延伸,该槽与来自一种栅极填充的每个栅极指针对相关;且
一种栅极指针对的两个栅极指针(11)都在它们两者的各端以及沿它们长度的预定位置被连接到相关的金属转轮(13)。
2.根据权利要求1所述的晶体管,其特征在于金属转轮(13)被提供在一种位于p+向下扩展(23)顶端的电介质层(24)之上。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE01008044 | 2001-03-09 | ||
SE0100804A SE522576C2 (sv) | 2001-03-09 | 2001-03-09 | Effekt-LDMOS-transistor för radiofrekvens |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1524296A true CN1524296A (zh) | 2004-08-25 |
Family
ID=20283274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA028062507A Pending CN1524296A (zh) | 2001-03-09 | 2002-03-07 | 一种射频功率ldmos(横向扩散金属氧化物半导体)晶体管 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7095080B2 (zh) |
EP (1) | EP1366526A1 (zh) |
JP (1) | JP2004534382A (zh) |
KR (1) | KR20030082944A (zh) |
CN (1) | CN1524296A (zh) |
SE (1) | SE522576C2 (zh) |
TW (1) | TW512540B (zh) |
WO (1) | WO2002073701A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100438032C (zh) * | 2006-02-22 | 2008-11-26 | 崇贸科技股份有限公司 | 具有辐射结构和隔离效果的高电压和低导通电阻晶体管 |
CN103456734A (zh) * | 2012-05-28 | 2013-12-18 | 上海华虹Nec电子有限公司 | 一种非对称ldmos工艺偏差的监控结构及其制造方法 |
CN114497172A (zh) * | 2020-11-12 | 2022-05-13 | 苏州华太电子技术有限公司 | 用于射频放大的双重降低表面电场rfldmos器件 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1408552A1 (en) * | 2002-10-09 | 2004-04-14 | STMicroelectronics S.r.l. | Integrated MOS semiconductor device with high performance and process of manufacturing the same |
JP2004327919A (ja) * | 2003-04-28 | 2004-11-18 | Renesas Technology Corp | 半導体装置 |
KR101099931B1 (ko) * | 2009-10-07 | 2011-12-28 | 전북대학교산학협력단 | Ldmos 트랜지스터 |
US8212321B2 (en) * | 2009-10-30 | 2012-07-03 | Freescale Semiconductor, Inc. | Semiconductor device with feedback control |
US8941175B2 (en) | 2013-06-17 | 2015-01-27 | United Microelectronics Corp. | Power array with staggered arrangement for improving on-resistance and safe operating area |
CN106298927B (zh) * | 2015-06-11 | 2019-08-30 | 北大方正集团有限公司 | 射频横向双扩散金属氧化物半导体器件及其制作方法 |
US11011632B2 (en) | 2018-12-06 | 2021-05-18 | Globalfoundries Singapore Pte. Ltd. | High voltage devices and methods of forming the same |
US11282955B2 (en) | 2020-05-20 | 2022-03-22 | Silanna Asia Pte Ltd | LDMOS architecture and method for forming |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5369045A (en) * | 1993-07-01 | 1994-11-29 | Texas Instruments Incorporated | Method for forming a self-aligned lateral DMOS transistor |
US5681761A (en) * | 1995-12-28 | 1997-10-28 | Philips Electronics North America Corporation | Microwave power SOI-MOSFET with high conductivity metal gate |
JP3129223B2 (ja) * | 1997-02-28 | 2001-01-29 | 日本電気株式会社 | 半導体装置 |
JP2001094094A (ja) * | 1999-09-21 | 2001-04-06 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP4322414B2 (ja) * | 2000-09-19 | 2009-09-02 | 株式会社ルネサステクノロジ | 半導体装置 |
US6744117B2 (en) * | 2002-02-28 | 2004-06-01 | Motorola, Inc. | High frequency semiconductor device and method of manufacture |
-
2001
- 2001-03-09 SE SE0100804A patent/SE522576C2/sv not_active IP Right Cessation
- 2001-03-23 TW TW090106969A patent/TW512540B/zh not_active IP Right Cessation
-
2002
- 2002-03-07 WO PCT/SE2002/000414 patent/WO2002073701A1/en active Application Filing
- 2002-03-07 KR KR10-2003-7011373A patent/KR20030082944A/ko active IP Right Grant
- 2002-03-07 CN CNA028062507A patent/CN1524296A/zh active Pending
- 2002-03-07 EP EP02704004A patent/EP1366526A1/en not_active Withdrawn
- 2002-03-07 JP JP2002572645A patent/JP2004534382A/ja active Pending
-
2003
- 2003-09-09 US US10/658,137 patent/US7095080B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100438032C (zh) * | 2006-02-22 | 2008-11-26 | 崇贸科技股份有限公司 | 具有辐射结构和隔离效果的高电压和低导通电阻晶体管 |
CN103456734A (zh) * | 2012-05-28 | 2013-12-18 | 上海华虹Nec电子有限公司 | 一种非对称ldmos工艺偏差的监控结构及其制造方法 |
CN103456734B (zh) * | 2012-05-28 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | 一种非对称ldmos工艺偏差的监控结构及其制造方法 |
CN114497172A (zh) * | 2020-11-12 | 2022-05-13 | 苏州华太电子技术有限公司 | 用于射频放大的双重降低表面电场rfldmos器件 |
Also Published As
Publication number | Publication date |
---|---|
SE0100804L (sv) | 2002-09-10 |
WO2002073701A1 (en) | 2002-09-19 |
SE0100804D0 (sv) | 2001-03-09 |
US7095080B2 (en) | 2006-08-22 |
TW512540B (en) | 2002-12-01 |
US20040089897A1 (en) | 2004-05-13 |
SE522576C2 (sv) | 2004-02-17 |
EP1366526A1 (en) | 2003-12-03 |
JP2004534382A (ja) | 2004-11-11 |
KR20030082944A (ko) | 2003-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10748996B2 (en) | High power transistor with interior-fed gate fingers | |
US9640654B2 (en) | Semiconductor device | |
US6395593B1 (en) | Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration | |
JP4322414B2 (ja) | 半導体装置 | |
EP1683202B1 (en) | Trench gate field effect devices | |
US20030178672A1 (en) | High-breakdown-voltage semiconductor device | |
CN1586009A (zh) | 场效应晶体管半导体器件 | |
CN1738057A (zh) | 具有增强的屏蔽结构的金属氧化物半导体器件 | |
CN1842918A (zh) | 包括ldmos晶体管的电子器件 | |
CN110890426B (zh) | 高压半导体装置和制造方法 | |
EP1915783A2 (en) | Ldmos transistor | |
JP2009016686A (ja) | 高周波用トランジスタ | |
EP3821462A1 (en) | Improved drain and/or gate interconnect and finger structure | |
US11430874B2 (en) | Semiconductor device with a crossing region | |
CN1524296A (zh) | 一种射频功率ldmos(横向扩散金属氧化物半导体)晶体管 | |
CN1266750C (zh) | 在绝缘衬底上形成的场效应晶体管以及集成电路 | |
CN111009570B (zh) | 晶体管结构 | |
CN101707205A (zh) | 一种具有倾斜表面漂移区的横向功率晶体管 | |
KR20090028390A (ko) | 반도체 장치 | |
CN113410299A (zh) | 一种高耐压的n沟道LDMOS器件及其制备方法 | |
CN113410281B (zh) | 一种具有表面耐压结构的p沟道LDMOS器件及其制备方法 | |
KR20240057947A (ko) | 반도체 장치 | |
CN115332315A (zh) | 一种ldmosfet器件及其制备方法 | |
CN115799299A (zh) | 超级结ldmos器件 | |
CN114068696A (zh) | 包括多个沟槽的半导体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
AD01 | Patent right deemed abandoned | ||
C20 | Patent right or utility model deemed to be abandoned or is abandoned |