CN1524296A - 一种射频功率ldmos(横向扩散金属氧化物半导体)晶体管 - Google Patents

一种射频功率ldmos(横向扩散金属氧化物半导体)晶体管 Download PDF

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CN1524296A
CN1524296A CNA028062507A CN02806250A CN1524296A CN 1524296 A CN1524296 A CN 1524296A CN A028062507 A CNA028062507 A CN A028062507A CN 02806250 A CN02806250 A CN 02806250A CN 1524296 A CN1524296 A CN 1524296A
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J·约翰逊
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N·阿肯斯塔姆
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Abstract

在一种射频功率LDMOS晶体管中,其包含多对平行的栅极指针(11),其中栅极指针位于一种相关的p+向下扩展(23)的对立边之上,而且包含用于造成p+向下扩展短路的金属夹(14),每一对栅极指针(11)中的一种栅极指针与分离的金属夹(14)相关,该金属夹造成n+源极区域(20)的短路以及与特定的栅极指针(11)相关的p+向下扩展(23)的短路。与每个栅极指针对相关的分离金属夹(14)被一种槽(15)分开,该槽在平行的栅极指针(11)之间延伸,而且一种金属转轮(13)在分离的金属夹(14)之间的槽(15)中延伸,该夹与来自一种栅极填充的每个指针对相关。一种栅极指针对的两个栅极指针(11)都被连接到相关的金属转轮(13),连接处位于指针的两端以及沿其长度的预定位置。

Description

一种射频功率LDMOS(横向扩散金属氧化物半导体)晶体管
技术领域
本发明通常涉及射频功率LDMOS晶体管,更具体而言,涉及这种用于第三代无线通信系统的晶体管。
背景技术
离散的射频功率LDMOS晶体管主要用于建造在射频基站中所使用的功率放大器。
图1显示一种传统射频功率LDMOS晶体管的一部分布局的顶端视图。该晶体管包含多个平行LDMOS晶体管单元,图1显示其中的两个单元,其中这些单元是一种互相交叉的指针结构,包含多对漏指针1,多对栅极指针2和源极/容积金属夹3。漏指针1和栅极指针2分别连接到位于晶体管单元对立边上的一种漏馈电棒4和一种栅极馈电棒5上,如图1所示。传统的LDMOS功率晶体管包含许多平行单元。
然而,第三代(3G)无线系统对射频功率晶体管设定了新的要求。不但要求较高的频率(>2GHz),这本身就是一种挑战,而且在线性上的极高要求也迫使功率放大器的设计者们在远远低于额定最大输出功率时使用功率晶体管。晶体管必须在此后退输出功率水平上运行,即具有较高的增益和较好的效率。
这些新的要求迫使射频功率晶体管的设计者们脱离晶体管旧的″平行单元″布局,而转向一种微有不同的设计。该第三代设计仅使用一个互相交叉的晶体管单元,与较旧设计中的单元方向相比,该单元有90度的旋转。
这种新设计最大的优点是在每个有源晶体管区域中都极大地降低了晶体管外围,其因此产生较低的输出容量和经过改善的效率。
为了使栅极外围和一种带有多个平行单元的晶体管相等,单一的单元需要在两个向度上进行伸展,以便它含有更多的指针。为了保持晶体管管芯的一种适当宽高比,指针也需要加长许多。
图2显示第三代设计的原理,其是一种已知的第三代射频功率LDMOS晶体管一部分布局的顶端视图。多对漏指针6被连接到一种共同的漏结合填充上(未显示),图2只显示其中的一对。多对栅极指针7在其各端和沿其长度预定的位置得到互连,其方法是使用若干片第一金属层,图2只显示该栅极指针对中的一对。图2显示此互连片8。源极/容积金属夹9也是用所述的第一金属层来制造的,其延伸至互连片之间的一对栅极指针7的上方。
依照上文的描述,第三代设计无可避免地与较长的指针相关。尤其在晶体管的栅极边上会发生这一问题。栅极指针通常由高度掺杂的多晶硅制成,其顶端可能具有一层金属硅化物,以便减少电阻率。然而,栅极指针的电阻根本不可忽略,而且在栅极指针长度的某些点上,将会对晶体管的功能产生负面影响。
这个问题在已知的第三代晶体管设计中已经得到解决,其方法是引入一种第二金属层。通过这种做法,人们能设计一种位于源极/容积夹9顶端的金属转轮10。通过一种电介质层(未在图2中显示)可以使金属转轮10隔离于夹9,而且该转轮被连接到该对栅极指针7,连接处位于经过互连片8、沿栅极指针7长度的预定位置上,同时也位于其各自的端点。金属转轮10的一端被连接到一种共同的栅极结合填充(未显示)。
因此,每个栅极指针的有效长度将等于两个栅极互连片之间距离的一半。
然而,晶体管设计中第二金属层的引入增加了设计过程和生产过程的复杂性。应该指出,在此连接中,如图2所示,漏指针6由两个金属层组成,即位于第一金属层顶端的第二金属层。在晶体管管芯的生产过程中,需要增加两种额外的屏蔽步骤,以及多个额外的过程步骤。
发明内容
本发明的目的在于生产一种第三代射频功率LDMOS晶体管,其与目前已知的晶体管相比,更易于生产。
通过依照本发明的晶体管可达到这一目的,主要通过仅使用一种金属层来实现,该金属层与较长的栅极指针进行中间接触。
附图说明
本发明将在以下参考附图得到更详细的说明。
其中,
图1显示一种传统射频功率LDMOS晶体管的布局;
图2显示一种已知的第三代射频功率LDMOS晶体管的布局;
图3显示了根据本发明的一种第三代射频功率LDMOS晶体管的布局;
图4是图3中根据本发明的晶体管沿线段A-A显示的截面视图。
具体实施方式
图3显示一种根据本发明的射频功率LDMOS晶体管的布局。
图2中已知的第三代晶体管包含两个金属层,与此不同的是,依照本发明的第三代晶体管只包含一个金属层。
在图3依照发明的晶体管中,每个栅极指针对的栅极指针11都通过金属层的各片在它们的各端和沿它们长度的预定位置上形成互连。图3显示了这种互连片12之一。
符合本发明的情况是,一种被连接到一种共同栅极结合填充的金属转轮13(未显示)被与针对对应栅极指针对的互连片12制成一个整体,用于每一对栅极指针11。
同样符合本发明的情况是,分离的源及极/容积金属夹14用与互连片12和金属转轮13相同的金属层生产而成,这些金属夹与每一对栅极指针中的每个栅极指针11相关。与各自对应的每一对栅极指针中的每个栅极指针11相关的金属夹14被一种槽15分开,该槽在每一对栅极指针中的平行栅极指针11之间延伸。
符合本发明的情况是,金属转轮13在金属夹14之间的槽15中制成。
多对漏指针16由与互连片12、金属转轮13以及金属夹14相同的金属层生产而成,其被连接到晶体管中一种共同的漏结合填充(未显示)。
图4是图3中依照本发明的晶体管的一种沿线段A-A的截面视图。在图4中,使用与图3相同的参考数字来指示同一组件。
在一种本身已知的方式中,晶体管被内置入一种p+基片17之内,其顶端具有一种p-epi18,并包含交替的n+漏区域19和n+源极区域20,其中n+漏区域19被通过一种n-漂移区域21从栅极11处分离出来。
一种p-型信道掺杂剂或p-井22被横向扩散在栅极11之下从其源极边出发的位置上。
一种深度的p+扩散或p+向下扩展23允许电流从n+源极区域20继续被传递到p+基片17,其电压降落是最小的,形成这种传递的方法是通过金属夹14造成这些区域彼此短路。
一种电介质层24将栅极指针11从金属夹14处分离出来,并将金属转轮13从p+向下扩展区域23处分离出来。

Claims (2)

1.一种射频功率LDMOS晶体管,其包含多对平行的栅极指针(11),每个栅极指针对的栅极指针(11)都位于一种相关的p+向下扩展(23)的对立边之上,而且提供金属夹(14)来造成p+向下扩展(23)和位于p+向下扩展(23)对立边上的n+源极区域(20)的短路,
其特征在于:
一种栅极指针对的每个栅极指针(11)都与分离的金属夹(14)相关,该金属夹造成n+源极区域(20)和与该特定的栅极指针(11)相关的p+向下扩展(23)的短路;
与每个栅极指针对相关的分离金属夹(14)被一种槽(15)分离,该槽在平行的栅极指针(11)之间延伸;
一种金属转轮(13)在分离的金属夹(14)之间的槽(15)中延伸,该槽与来自一种栅极填充的每个栅极指针对相关;且
一种栅极指针对的两个栅极指针(11)都在它们两者的各端以及沿它们长度的预定位置被连接到相关的金属转轮(13)。
2.根据权利要求1所述的晶体管,其特征在于金属转轮(13)被提供在一种位于p+向下扩展(23)顶端的电介质层(24)之上。
CNA028062507A 2001-03-09 2002-03-07 一种射频功率ldmos(横向扩散金属氧化物半导体)晶体管 Pending CN1524296A (zh)

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SE01008044 2001-03-09
SE0100804A SE522576C2 (sv) 2001-03-09 2001-03-09 Effekt-LDMOS-transistor för radiofrekvens

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Cited By (3)

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CN100438032C (zh) * 2006-02-22 2008-11-26 崇贸科技股份有限公司 具有辐射结构和隔离效果的高电压和低导通电阻晶体管
CN103456734A (zh) * 2012-05-28 2013-12-18 上海华虹Nec电子有限公司 一种非对称ldmos工艺偏差的监控结构及其制造方法
CN114497172A (zh) * 2020-11-12 2022-05-13 苏州华太电子技术有限公司 用于射频放大的双重降低表面电场rfldmos器件

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EP1408552A1 (en) * 2002-10-09 2004-04-14 STMicroelectronics S.r.l. Integrated MOS semiconductor device with high performance and process of manufacturing the same
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KR101099931B1 (ko) * 2009-10-07 2011-12-28 전북대학교산학협력단 Ldmos 트랜지스터
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US7095080B2 (en) 2006-08-22
TW512540B (en) 2002-12-01
US20040089897A1 (en) 2004-05-13
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EP1366526A1 (en) 2003-12-03
JP2004534382A (ja) 2004-11-11
KR20030082944A (ko) 2003-10-23

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