TW490844B - Semiconductor device and method for making the same - Google Patents

Semiconductor device and method for making the same Download PDF

Info

Publication number
TW490844B
TW490844B TW089110702A TW89110702A TW490844B TW 490844 B TW490844 B TW 490844B TW 089110702 A TW089110702 A TW 089110702A TW 89110702 A TW89110702 A TW 89110702A TW 490844 B TW490844 B TW 490844B
Authority
TW
Taiwan
Prior art keywords
layer
wiring
aforementioned
pattern
film
Prior art date
Application number
TW089110702A
Other languages
English (en)
Chinese (zh)
Inventor
Shinichi Fukada
Kazuo Nojiri
Takashi Yunogami
Shoji Hotta
Hideo Aoki
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW490844B publication Critical patent/TW490844B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/0888—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures wherein via-level dielectrics are compositionally different than trench-level dielectrics

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW089110702A 1999-06-04 2000-06-01 Semiconductor device and method for making the same TW490844B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15875899A JP4094174B2 (ja) 1999-06-04 1999-06-04 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW490844B true TW490844B (en) 2002-06-11

Family

ID=15678711

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089110702A TW490844B (en) 1999-06-04 2000-06-01 Semiconductor device and method for making the same

Country Status (4)

Country Link
US (4) US6340632B1 (https=)
JP (1) JP4094174B2 (https=)
KR (3) KR100798166B1 (https=)
TW (1) TW490844B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100798166B1 (ko) * 1999-06-04 2008-01-24 가부시키가이샤 히타치세이사쿠쇼 반도체장치 및 그 제조방법

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170115B2 (en) * 2000-10-17 2007-01-30 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device and method of producing the same
JP2002222860A (ja) * 2001-01-29 2002-08-09 Sony Corp 半導体装置の作成方法
KR100441680B1 (ko) * 2001-02-07 2004-07-27 삼성전자주식회사 콘택의 설치 밀도를 높일 수 있는 반도체 장치 형성방법
JP2002252281A (ja) * 2001-02-27 2002-09-06 Sony Corp 半導体装置およびその製造方法
JP4523194B2 (ja) 2001-04-13 2010-08-11 富士通セミコンダクター株式会社 半導体装置とその製造方法
JP2002343770A (ja) * 2001-05-16 2002-11-29 Seiko Epson Corp エッチング方法、エッチング装置及び半導体装置の製造方法
JP2003051501A (ja) * 2001-05-30 2003-02-21 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP4948715B2 (ja) * 2001-06-29 2012-06-06 富士通セミコンダクター株式会社 半導体ウエハ装置およびその製造方法
US6890824B2 (en) * 2001-08-23 2005-05-10 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
US6949411B1 (en) * 2001-12-27 2005-09-27 Lam Research Corporation Method for post-etch and strip residue removal on coral films
KR100447977B1 (ko) * 2002-03-13 2004-09-10 주식회사 하이닉스반도체 듀얼 다마신 공정을 이용한 반도체 소자의 금속 배선 형성방법
US7138719B2 (en) * 2002-08-29 2006-11-21 Micron Technology, Inc. Trench interconnect structure and formation method
CN100352036C (zh) 2002-10-17 2007-11-28 株式会社瑞萨科技 半导体器件及其制造方法
JP4454242B2 (ja) 2003-03-25 2010-04-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US7387960B2 (en) * 2003-09-16 2008-06-17 Texas Instruments Incorporated Dual depth trench termination method for improving Cu-based interconnect integrity
US6960519B1 (en) 2004-06-25 2005-11-01 International Business Machines Corporation Interconnect structure improvements
JP4535845B2 (ja) * 2004-10-29 2010-09-01 富士通セミコンダクター株式会社 半導体装置
JP2006294771A (ja) * 2005-04-08 2006-10-26 Sony Corp 半導体装置の製造方法
US7842037B2 (en) * 2006-09-27 2010-11-30 Dupuy Products, Inc. Flexible bone fixation device
US7456030B1 (en) * 2007-10-11 2008-11-25 National Semiconductor Corporation Electroforming technique for the formation of high frequency performance ferromagnetic films
US7936072B2 (en) 2007-11-12 2011-05-03 Renesas Electronics Corporation Semiconductor device having dual damascene structure
KR100976796B1 (ko) * 2008-06-03 2010-08-20 주식회사 동부하이텍 비휘발성 반도체 메모리 소자 및 그의 제조방법
KR20110028506A (ko) * 2008-06-17 2011-03-18 가부시키가이샤 알박 다단형 기판의 제조 방법
JP4773543B2 (ja) * 2009-04-17 2011-09-14 昭和シェル石油株式会社 エッジスペースを備えた太陽電池モジュール
DE102009023251B4 (de) * 2009-05-29 2011-02-24 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung eines Kontaktelements mit großem Aspektverhältnis und mit einer günstigeren Form in einem Halbleiterbauelement zur Verbesserung der Abscheidung einer Beschichtung
US8404581B2 (en) * 2009-09-29 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an interconnect of a semiconductor device
US8790379B2 (en) 2010-06-23 2014-07-29 Zimmer, Inc. Flexible plate fixation of bone fractures
US8882815B2 (en) 2010-06-23 2014-11-11 Zimmer, Inc. Flexible plate fixation of bone fractures
US9295508B2 (en) 2012-02-03 2016-03-29 Zimmer, Inc. Bone plate for elastic osteosynthesis
US9006100B2 (en) * 2012-08-07 2015-04-14 Globalfoundries Inc. Middle-of-the-line constructs using diffusion contact structures
US20140342553A1 (en) * 2013-05-14 2014-11-20 United Microelectronics Corp. Method for Forming Semiconductor Structure Having Opening
US9385000B2 (en) * 2014-01-24 2016-07-05 United Microelectronics Corp. Method of performing etching process
US10515822B2 (en) 2016-06-20 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for preventing bottom layer wrinkling in a semiconductor device
KR102627459B1 (ko) * 2018-08-31 2024-01-22 삼성전자주식회사 다층 도선을 포함하는 집적 회로
US11324538B2 (en) 2019-12-04 2022-05-10 Biomet Manufacturing, Llc Active bone plate
JP2022048753A (ja) * 2020-09-15 2022-03-28 キオクシア株式会社 半導体製造システム、半導体装置の製造方法、及び半導体装置
US12557631B2 (en) * 2021-01-29 2026-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Low-resistance copper interconnects
US20220352018A1 (en) * 2021-04-30 2022-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Carbon-based liner to reduce contact resistance
CN114267587B (zh) * 2021-12-08 2025-09-23 合肥维信诺科技有限公司 显示面板的过孔控制方法和过孔刻蚀装置

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5279990A (en) 1990-03-02 1994-01-18 Motorola, Inc. Method of making a small geometry contact using sidewall spacers
US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
US5320981A (en) 1993-08-10 1994-06-14 Micron Semiconductor, Inc. High accuracy via formation for semiconductor devices
TW388083B (en) * 1995-02-20 2000-04-21 Hitachi Ltd Resist pattern-forming method using anti-reflective layer, resist pattern formed, and method of etching using resist pattern and product formed
US5684331A (en) 1995-06-07 1997-11-04 Lg Semicon Co., Ltd. Multilayered interconnection of semiconductor device
JPH09153545A (ja) * 1995-09-29 1997-06-10 Toshiba Corp 半導体装置及びその製造方法
JPH09306988A (ja) * 1996-03-13 1997-11-28 Sony Corp 多層配線の形成方法
US5741626A (en) * 1996-04-15 1998-04-21 Motorola, Inc. Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)
JP4384733B2 (ja) 1996-04-26 2009-12-16 テキサス インスツルメンツ インコーポレイテツド 導体を分離するシリコンナイトライド側壁と上表面層
US5663108A (en) 1996-06-13 1997-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Optimized metal pillar via process
JP3713869B2 (ja) 1997-02-17 2005-11-09 ソニー株式会社 半導体装置の製造方法
JPH10313006A (ja) * 1997-05-14 1998-11-24 Sony Corp 半導体装置の製造方法
TW408433B (en) 1997-06-30 2000-10-11 Hitachi Ltd Method for fabricating semiconductor integrated circuit
JPH1140765A (ja) 1997-07-16 1999-02-12 Toshiba Corp 半導体記憶装置及びその製造方法
US6040604A (en) 1997-07-21 2000-03-21 Motorola, Inc. Semiconductor component comprising an electrostatic-discharge protection device
US5891799A (en) * 1997-08-18 1999-04-06 Industrial Technology Research Institute Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates
EP0908945A3 (en) * 1997-09-29 2000-09-27 Siemens Aktiengesellschaft Dual damascene with self aligned via interconnects
US6166403A (en) 1997-11-12 2000-12-26 Lsi Logic Corporation Integrated circuit having embedded memory with electromagnetic shield
US6143649A (en) 1998-02-05 2000-11-07 Micron Technology, Inc. Method for making semiconductor devices having gradual slope contacts
US5959357A (en) 1998-02-17 1999-09-28 General Electric Company Fet array for operation at different power levels
US6100190A (en) * 1998-02-19 2000-08-08 Rohm Co., Ltd. Method of fabricating semiconductor device, and semiconductor device
US6197696B1 (en) 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
JP3718058B2 (ja) * 1998-06-17 2005-11-16 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6184142B1 (en) 1999-04-26 2001-02-06 United Microelectronics Corp. Process for low k organic dielectric film etch
JP4094174B2 (ja) * 1999-06-04 2008-06-04 株式会社ルネサステクノロジ 半導体装置の製造方法
US6133144A (en) * 1999-08-06 2000-10-17 Taiwan Semiconductor Manufacturing Company Self aligned dual damascene process and structure with low parasitic capacitance

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100798166B1 (ko) * 1999-06-04 2008-01-24 가부시키가이샤 히타치세이사쿠쇼 반도체장치 및 그 제조방법

Also Published As

Publication number Publication date
US6528400B2 (en) 2003-03-04
KR100773182B1 (ko) 2007-11-02
US6774020B2 (en) 2004-08-10
KR100798166B1 (ko) 2008-01-24
KR20010020946A (ko) 2001-03-15
US6555464B2 (en) 2003-04-29
KR20070103331A (ko) 2007-10-23
US20020076921A1 (en) 2002-06-20
JP2000349150A (ja) 2000-12-15
US6340632B1 (en) 2002-01-22
JP4094174B2 (ja) 2008-06-04
US20020127848A1 (en) 2002-09-12
US20030139031A1 (en) 2003-07-24
KR20070051812A (ko) 2007-05-18

Similar Documents

Publication Publication Date Title
TW490844B (en) Semiconductor device and method for making the same
US10714343B1 (en) Semiconductor structure and method for forming same
US10283407B2 (en) Two-dimensional self-aligned super via integration on self-aligned gate contact
TW531827B (en) Integrated circuits with multiple low dielectric-constant inter-metal dielectrics
US8952547B2 (en) Semiconductor device with contact structure with first/second contacts formed in first/second dielectric layers and method of forming same
TWI515826B (zh) 貫穿矽介層及其製造方法
CN109755126B (zh) 半导体器件的制造方法
TW201250920A (en) Interconnect structure with improved alignment for semiconductor devices
CN104241250B (zh) 用于形成接触件的掺杂保护层
TWI286819B (en) Semiconductor device
TW201126605A (en) Method to remove capping layer of insulation dielectric in interconnect structures
TW518719B (en) Manufacturing method of contact plug
US5081516A (en) Self-aligned, planarized contacts for semiconductor devices
TWI234280B (en) Semiconductor device with fuses
TW200924055A (en) Silicon carbide doped oxide hardmask for single and dual damascene integration
JP2015233069A (ja) 半導体装置及び半導体装置の製造方法
JPH02502417A (ja) 半導体素子の製造方法
JPH02502414A (ja) 半導体素子のための自己整列した相互接続
TW517377B (en) Semiconductor apparatus and its manufacturing method
US6413846B1 (en) Contact each methodology and integration scheme
CN102709192A (zh) 一种集成阻变存储器的mos晶体管结构的制造方法
CN105575805B (zh) 半导体结构的制造方法
TW531893B (en) Semiconductor device and manufacture method therefor
JP3245124B2 (ja) 垂直ゲート側壁を有する電界効果トランジスタおよびその製造方法
TWI887145B (zh) 半導體裝置的製造方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent