TW472382B - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
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- TW472382B TW472382B TW089106246A TW89106246A TW472382B TW 472382 B TW472382 B TW 472382B TW 089106246 A TW089106246 A TW 089106246A TW 89106246 A TW89106246 A TW 89106246A TW 472382 B TW472382 B TW 472382B
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- band
- band amplifier
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- amplifier
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims abstract description 8
- 230000002079 cooperative effect Effects 0.000 claims description 15
- 230000000875 corresponding effect Effects 0.000 claims description 6
- 230000010354 integration Effects 0.000 abstract description 11
- 238000004891 communication Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000006731 degradation reaction Methods 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 description 12
- 230000010355 oscillation Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 101100386719 Caenorhabditis elegans dcs-1 gene Proteins 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
- H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
- H03F3/187—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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Description
經濟部智慧財產局員工消費合作杜印製 472382 A7 _____ B7 五、發明説明(彳) (發明所屬之技術領域) 本發明有關於,主要係使用於高頻帶、及低頻帶之二 個頻帶域之無線系統之雙頻數無線通訊移動體終端機器中 ’將低噪音放大器之予以積化之雙頻帶送受信用半導體積 體電路。 (先前技術) 第4圖乃適用了以往之雙頻帶送受信用半導體積體電 路(下面稱爲「送受信I C」)之終端機器之構成例。這 是適用於二個不同頻帶之無線通訊系統之攜帶式終端機者 送受信I C 4 Ο 1乃由:適用於雙頻帶無線系統之高 頻帶受信混頻器4 0 3 a ,及低頻帶受信混頻器4 0 3 b ,及下序段之混頻器404,可變增益放大器405,解 調器4 0 6,調制器4 0 8,補償器P L L 4 0 9,及分 頻器4 0 7所構成。 在頻數變換所必要之局部振盪訊號係由合成器4 1 0 ,內藏之分頻器4 0 7所供給。連接於送受信I C之帶域 通過濾波器4 1 1乃用於除去帶域外之亂真(spurious )者 。高頻帶低噪音放大器4 0 2 a及低頻帶低噪音放大器 4 0 2 b乃做成I C外之附零件。以往,低噪音放大器乃 由於電晶體製程之f T限界,或電晶體基板間之容量之關 係而在於高頻帶域之增益或雜訊特性之不足所以內藏於 I C內乃屬於困難之事。惟由於最近之微細製程技術之提 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) I--------I------#------0 (請先閱讀背面之注意事項再填寫本頁) -4- 47238 〇 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(2 ) 高而克服了上述之問題,而內藏低噪音放大器已經成爲也 〇 適用於雙頻帶送受信I C之低噪音放大器之一例係揭 示於 Keng Leong Fong 「Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers for Wireless Applications」ISSCC 1 9 99,pp.224-225,p.463。這乃爲了 雙頻送受信I C而將二個低噪音放大器予以一晶片化,封 入於T S S 0 P 2 0腳位封裝體者,並非將送受信系體全 體予以內藏之構成,又訊號線及接地線與電極之對應方式 即不明。 再者內藏了低噪音放大器之送受信I c之一例係揭不 於 Michiel Steyaert et al. 「A single-Chip CMOS Transceiver for DCS 1 800 wireless Communications」ISSCC 1 9 9 8, pp.48-49,p.411。這是將送受信電路予以一晶片化 者惟不適用於雙頻帶,且訊號線及接地線等與電極之對應 方式不明,且使用之封裝體之方式也不明。 (發明所欲解決之課題) 本發明乃對於第4圖所示之雙頻帶用之送受信電路晶 片4 0, 1中斷的內藏了低噪音放大器4 0 2 a,及 4 0 2 b。此時在於封裝體上發現了腳位佈置之問題。本 發明中封裝體係採用了在於四邊配置有腳位之Q F P ( Quad 'Flat package)四邊偏平.封裝體。 第1課題係,將低噪音放大器採用,對於Q F p之導 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適:用中.國國家標準(CNS ) A4規格(210X297公釐) -5- 472382 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(3 ) 引腳位中之長的導引腳位以長的結合線來予以結合之佈置 時,即由於寄生電感所致之負回授量變大’使局頻增益及 噪音特性會劣化之問題。 第2課題係,由於I C之腳位間之變壓器結合或安裝 I. C之多層基板上之配線之交叉所致之變壓器結合而同樣 地會使I C之高頻特性之劣化之問題。 第3課題係由於在低噪音放大器之寄生容量及寄生電 感而有時會發生振盪之問題。 本發明之目的乃提供一種不會使內藏於雙頻送受信用 之I C電路上之低噪音放大器之高頻特性劣化之腳位佈置 者。 (發明之實施形態) 下面於第1圖表示本發明之實施例,圖中之標號 1 00係適用本發明之雙頻帶送受信I C之QFP。 1 2 3係相當於第4圖之高頻帶低噪音放大器者。1 2 1 相當於第4圖之低頻帶低噪音放大器4 0 2 b。1 1 8係 相當於第4圖之高頻帶受信混頻器4 0 3 a, 1 1 9相當 於第4圖之低頻帶受信混頻器4 0 3 b。 第1圖中,低頻帶低噪音放大器1 2 1及高頻帶低噪 音放大器1 2 3及由低頻帶低噪音放大器用偏壓電路 1 2 5,及高頻帶低噪音放大器用偏壓電路1 2 6而安定 的供給偏壓電流。由低頻帶低噪音放大器用偏壓電阻 1 2 2及高頻帶低噪音放大器用偏壓電阻1 2 4而將分別 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中周國家標準(CNS ) A4規格(210X297公釐) -6- 47238 2 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(4 ) 來自偏壓電路之偏壓電流乃變換爲偏壓電壓、供給於低噪 音放大器。1 0 3係低頻帶低噪音放大器之輸出腳位, 1 〇 4係低頻帶低噪音放大器之接地腳位,1 0 5係低頻 帶低噪音放大器之輸入腳位,1 0 6及1 0 8係高頻帶低 噪音放大器之接地腳位,1 0 7係高頻帶低噪音放大器之 輸出腳位,1 0 9係高頻帶低噪音放大器之輸入腳位, 1 2 9係送訊電路塊之電源腳位,1 3 0係送訊電路塊之 接地腳位,1 2 9及1 3 0係偏壓電路1 2 5及1 2 6之 電源,亦是接地。1 2 7乃雙頻帶受信混頻器部,乃由高 頻帶受信混頻器1 1 8及低頻帶受信混頻器1 1 9,及對 於兩受信混頻器供給局部振盪訊號之局部振盪訊號用放大 器1 2 0所構成。1 0 1, 1 0 2係高頻帶受信混頻器輸 入腳位,1 1 2係混頻器電路接地腳位,1 1 3係混頻器 電路電源腳位,114, 1 1 5係混頻器電路輸出腳位, 116, 1 1 7係局部振盪訊號輸入腳位,1 4 2係電源 ,介著腳位1 1 3及腳位1 2 9而對於受信混頻器,受信 電路供給電源電壓同時,介著輸出整合電路1 3 1對於低 噪音放大器,供給電源電壓。 下面說明本發明之腳位佈置方式之特徵。 第一之點乃在於從低噪音放大器之封裝體外腳位前端 到電極爲止之距離之成爲最短之位置設置低噪音放大器之 電路。如上地予以構成之結果,可以減少導入腳位與結合 線之寄生電感所致之負回授之效果,而可以防止增益、噪 音特性之劣化。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Λ4規格{ 21〇 X 297公釐) -7- 472382 A7 經濟部智慧財產局員工消費合作社印製 B7 ___ 五、發明説明(5 ) 本實施例中,配置於1 0 3乃至1 0 9之腳位乃是封 裝體外腳位前端到低噪音放大器之距離之成爲最短之案件 〇 再者,在此腳位之中,上述距離之最短者係腳位 1. 0 6,將連接形成低噪音放大器之雙極電晶體之射極。 第二之點係使複數之低噪音放大器之接地腳位與接地 腳位乃互相地使之不鄰接地予以配置。本實施例中,高頻 帶低噪音放大器1 2 3之接地腳位係二支,因此寄生電感 之負回授所致之效果得於減半,由而可以獲得高增益也。 第5圖表示予以接地之結合線及導入腳位之等效電路 。5 0 2係積體電路基板。5 0 3乃製作於其上方之積體 電路。本例係低噪音放大器。在於封裝體支撐構件5 0 1 之上方之導入腳位5 0 6係以結合線5 0 5而連接於低噪 音放大器之接地之電極5 0 4。此時之等效電路乃成爲 5 0 7所示之逆標號之變電路結合。一方之導入腳位上流 動之電流係具有使另一方之導入腳位之電流減少之作用。 因此使用鄰接之二支導入腳位時寄生電感乃不能成爲一半 ,而受變壓器之結合度之影響而成爲以單一之導入線比較 而成爲7 0 %程度。所以爲了寄生電感之減低起見,輸入 腳位與輸出腳位乃以不互相鄰接乃很重要。又輸入出高頻 訊號也不構成鄰接狀地於接地腳位爲間地予以插入。由而 可以避免與上述同樣之變壓器結合。由而可以防止流通於 一方之高頻訊號之電流之使相鄰之高頻訊號之電流而致使 增益之劣化之問題。本實施例中,從標號1 〇 6乃至 本紙張尺度適用中國國家標率(CNS ) A4规格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -8 - 47238 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明(6 ) 1 0 9所示之腳位佈値係相當於它者。自1 〇 3至1 0 5 之腳位佈置乃高頻訊號線之不互相鄰接之例子。 第三之點乃在於低頻帶受信混頻器1 1 9之輸入腳位 與低頻帶低噪音放大器1 2 1之輸入出腳位之間配置高頻 帶受信混頻器1 1 8之輸入腳位,而在於高頻帶受信混頻 器1 1 8之輸入腳位與高頻帶低噪音放大器1 2 3之輸入 出腳位之間,配置了低頻帶低噪音放大器1 2 1之輸入出 腳位,而低頻帶受信混頻器1 1 9之輸入腳位與低頻帶低 噪音放大器1 2 1之輸入腳位1 〇 5之間配置低頻帶低噪 音放大器1 2 1之輸出腳位1 〇 3,在於高頻帶受信混頻 器之輸入腳位與高頻帶低噪音放大器1 2 3之輸入腳位 1 0 9之間配置有高頻帶低噪音放大器1 2 3之輸出腳位 10 7° 由於將低噪音放大器之輸出腳位置於較輸入腳位更接 近於受信混頻器之位置,所以輸入線與輸出線乃不會交叉 。再者1 3 5及1 3 6係分別輸入於低噪音放大器1 2 1 及1 2 3之尚頻訊號之輸入點,係連接於天線。而以分別 附於各個之帶域通過之濾波器1 3 3來去除帶域外之亂真 (s p u η 〇 u s )訊號,而在於輸入整合電路1 3 2來採取5 0 Ω阻抗整合。對於各個之低噪音放大器1 2 1, 1 2 3輸 入高頻訊號。輸出係在於輸入整合電路1 3 1而使之阻抗 整合。接著以帶域通過濾波器1 3 4來去除帶域外亂真訊 號之後,以混頻器輸入整合電路用容量1 3 8, 1 4 1及 混頻器輸入整合用電感器1 3 7來產生差動訊號,而輸入 (請先閱讀背面之注意事項再填寫本頁) -裝 、-口 綉 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) -9- 472382 A7 B7 五、 發明説明 (7 ) 於 受 信 混 頻 器 1 1 8, 1 1 9 0 依 此 方 式 之 配 線 安 裝 時 即 在 於 以 虛 線 所圍繞之1 3 9 及 1 4 0 而 會 發 生 配 線 之 交 叉 , 惟 此 交 叉 係不同之頻 帶 之 訊 號 線 與 訊 號 線 所 交 叉 者 > 且 — 方 之 頻 市 在使用中另 一 方 之 頻 帶 係 不 使 用 > 因 此 不 會 發 生 互 相 之 干 涉之情形。 第 四 之 點係,分別 的 設 置 低 噪 音 放 大 器 之 接 地 腳 位 , 及低 噪 曰 放 大器之偏壓/ _路之接地腳位 又 偏 壓 電路之電源 腳 位 及 接 地 腳 位 乃 與 送 訊 塊 之 電 源 、 接 地 腳 位所共同使用 〇 第 2 圖 表示,包含 封 裝 體 之 寄 生 元 件 y 而 偏 壓 電 路 係 具 有 與 低 噪 音放大器共 同 之 接 地 結 點 時 之 電 路 例 〇 第 2 圖 之 上 段 係 表 示該電路也 0 標 號 2 0 1係低噪 ~jw* 放 大 器 用 電 晶 體 , 2 0 2 係 結 合 線 及 封 裝 體 之導入線( 引 線 ) 2 0 3 係 低 噪 放 大 器 之 偏 壓 1¾ 路 〇 2 0 5係電f 晶體 2 〕 L之集極偏厘 I霄 i位, 2 0 6 係 偏 壓電路之電 源 電 位 2 0 7 係 接 地 〇 第 2 圖 之 下 段 乃 上 段 之電路之等 效 電 路 〇 2 0 8 乃 做 爲 偏 壓 電 路 之 經 等 效 電 路 之 容量C 2 , 2 0 9 乃 電 晶 體 之 基 極 射 極 間 容 .濟 部 智 量 C 1 j 2 1 ◦係基極 射 極 間 電 位 ) 2 1 2 係 電 晶 體 之 互 慧 財 相 之 電 感 g m。2 1 1 係 結 合 線 與 封 裝 體 導 入 腳 位 之 等 效 局 資 電 路 之 電 感 L _來表示。 工 消 費 從 電 晶 體之輸入點 2 0 4 所 觀 視 之 阻 抗 Z i Π 乃 得 以 合 η 下 式 ( 1 ) 表示。 社 印 製 Z i η =g m L / ( 3 1 (1 - -ω 2 C 2 L ) ) + 本紙張尺度適间t國國豕樵準(CNS ) Α4規格(2ΙΟΧ297公酱) I 私衣 I 訂i I I 0 (請先閲讀背面之注意事項再填寫本頁} -10 - 47238 Ο A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(8 ) j (ω 2 L - 1 )/(ω C 1 ( 1 - ω 2 C 2 L )) 此時由於成爲1 <«2C 2 L ,因此(1 )式之實數部 成爲負,而阻抗成爲負性電阻抗由而有時會發生振盪,因 此將電源、接地予以分開以資去除發生振盪之原因之偏壓 電路之寄生容量。 本實施例乃舉雙頻帶之系統爲例來說明,而在於具有 複數之頻帶時仍以同樣之考察來得於實現者。 第3圖乃表示依本發明之腳位之佈置方式所構成之送 受信I C。標號3 0 0乃適用了本發明之送受信I c之晶 片。3 0 3係用於包封送受信I C之Q F P,相當於第1 圖之1 0 0。3 0 4係封裝體之晶片接著面3 〇 5之支撐 材。3 0 1係高頻帶及低頻帶之低噪音放大器之佈置。 302乃同樣二個頻帶之受信混頻器之佈置。 3 0 8係低頻帶低噪音放大器之輸出腳位,3 0 9係 低頻帶低噪音放大器之接地腳位,3 1 0係低頻帶低噪音 放大器之輸入腳位,3 1 1、3 1 3係高頻帶低噪音放大 器之接地腳位,3 1 2係高頻帶低噪音放大器之輸出腳位 ,3 1 4係高頻帶低噪音放大器之輸入腳位,3 2 3係送 訊電路塊電源腳位。,3 2 4係送訊電路塊接地腳位,分 別對應於第1圖之腳位1〇1〜1 〇 9及1 2 9 , 130 。又3 1 5,3 1 6係低頻帶受信混頻器輸入腳位, 3 1 7係混頻器電路接地腳位,3 ;L 8係混頻器電路電源 腳位,3 1 9,3 2 0係混頻器輸出腳位,3 2 1 , 3 2 .2係局部振擾訊號輸入腳位,各對應於第1圖之腳位 —---------裝— (請先閱讀背面之注意事項再填寫本頁) 訂 絲 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -11 - 47238; A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(9 ) 1 1 0〜1 1 7。標號3 2 5係由晶片上之各電極而附於 上述之導入腳位之結合線也。 爲了實施第1圖所示之腳位佈置,乃如第3圖所示下 述之點係非常重要者,即:在於自低噪音放大器之封裝體 外之腳位前端到電極爲止之距離之能成爲最短之位置上, 設置低噪音放大器之電路。又受信混頻器係如3 0 1與 3 0 2之關係一般地鄰接於低噪音放大器而予以配置。又 在於第1之受信混頻器之輸入腳位,其鄰處設第2之受信 混頻器之輸入腳位,再其鄰處設置連接於第1之受信混頻 器之低噪音放大器之輸入出腳位,而在其鄰處設置連接於 第2之受信混頻器之低噪音放大器之輸入出腳位地予以接 排配置也。 (發明之效果) 本發明乃,第1之點爲,在於自低噪音放大器之封裝 體外之腳位前端到電極爲止之距離之能成爲最短之位置上 ,設置低噪音放大器之電路由而提高了增益及噪音特性。 第二之點係,使二個低噪音放大器之接地腳位,高頻 訊號腳位配置使之不會相鄰接,以資減低腳位間之變壓器 結合。 第三之點係,藉由受信混頻器及低噪音放大器之多層 安裝基板而採取訊號配線之不交叉之腳位佈置以資減輕了 配線間之變壓器接合。 第四之點係,分開了低噪音放大器之電源與接腳位, (請先閱讀背面之注意事項再填寫本頁)
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T 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -12- 47238 2 Α7 Β7 五、發明説明(10 ) 以及偏壓電路之電源、接地腳位,以資減輕了振盪之發生 I---------裝-- (請先閲讀背面之注意事項再填寫本頁) Η式之簡單說明 第1圖係本發明之實施例。 第2圖係包含封裝體之寄生元件,而偏壓電路係備有 低噪音放大器之接地結點時之電路例。 第3圖係佈置之構成例。 第4圖係以往之移動體通訊之用之對應於雙頻帶受信 用半導體積體電路。 第5圖係,互鄰接之結合線,導入腳位之等效電路。 (標號說明) 訂
10 0……雙頻帶送受信I c之封裝體 I 1〇1、10 2……高頻帶受信混頻器輸入腳位 i 1 〇 3……低頻帶低噪音放大器、輸出腳位 | 1 〇 4……低頻帶低噪音放大器、接地腳位 絲 10 5……低頻帶低噪音放大器、輸入腳位 | 經濟部智慧財產局員工消費合作社印製
10 6……高頻帶低噪音放大器、接地腳位 I 1 〇 7……高頻帶低噪音放大器、輸出腳位 [ 10 8……高頻帶低噪音放大器、接地腳位 [ 1 0 9……高頻帶低噪音放大器、輸入腳位 |
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110、111……低頻帶受信混頻器輸入腳位 I 112……混頻器電路接地腳位 1 1 3……混頻器電路電源腳位 | 本紙張尺度適用中.國國家榡準(CNS ) Α4規格(210Χ297公釐〉 -13- 47238 2 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(11 ) 114、 115……混頻器電路輸出腳位 116、 117……局部振盪訊號輸入腳位 118……高頻帶受信混頻器 119……低頻帶受信混頻器. 12 0……局部振盪訊號用放大器 12 1……低頻帶低噪音放大器用電晶體 12 2……低頻帶低噪音放大器用偏壓電阻 12 3……高頻帶低噪音放大器用電晶體 12 4……高頻帶低噪音放大器用偏壓電阻 12 5……低頻帶低噪音放大器用偏壓電路 12 6……高頻帶低噪音放大器用偏壓電路 12 7……雙頻帶受信混頻器電路部 12 8……送訊電路塊 12 9……送訊電路塊電源腳位 13 0……送訊電路塊接地腳位 13 1……低噪音放大器用輸出整合電路 1 3 2……低噪音放大器用輸入整合電路 13 3……帶域通過濾波器 13 4……帶域通過濾波器 13 5……低頻帶輸入端子 1 3 6……高頻帶輸入端子 13 7……混頻器輸入整合電路用電感器 13 8、141……混頻器輸入整合電路用容量 13 9、 140……訊號線交叉線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標率(CNS ) A4規格(2丨OXW7公釐) -14- 472382 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(12 ) 2 0 1 ......低噪音放大器用電晶體 2〇2 ......做爲寄生元件之結合線及封裝體之導入線 2 0 3 ......偏壓電路 2 0 4……低噪音放大器輸入點 2 0 5 ......集極偏壓電位 2 0 6 ......電源電位 2 0 7……接地 2 0 8……做爲偏壓電路之等效電路之容量c 2 2 0 9……電晶體基極、射極間容量C 1 2 1 0……基極、射極電位 2 11……做爲結合線與封裝體導入線之等效電路之 電感L 2 12 ......相互電導gm 3 0 0……送受信I C晶片 3 0 1……高頻帶及低頻帶低噪音放大器之佈置 3 0 2……高頻帶及低頻帶受信混頻器電路之佈置 3 0 3……送受信1C之QFP 3 0 4·••…晶片接著面之支撐材 3 0 5……晶片接著面 3.06、3 0 7 ......高頻帶受信混頻器輸入腳位_ .3 0 8….···低頻帶低噪音放大器輸出腳位 3 0 9……低頻帶低噪音放大器接地腳位 3 10……低頻帶低噪音放大器輸入腳位 3 11 ......高頻帶低噪音放大器接地腳位 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中.國國家橾準(CNS ) A4規格(210X297公釐) -15- 11叫82 A7 B7 五、 發明説明(13 3 1 3 1 3 1 2 3 4 5、 7 - 8 .· 經濟部智慧財產局員工消費合作社印製 3 2 3 2 3 2 3 2 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 1 4 1 3 4 5 2 a 2 b 3 a 3 b 4… 5… 6… 7 ··· 8… 9… 0 3 3 高頻帶低噪音放大器輸出腳位 高頻帶低噪音放大器接地腳位 高頻帶低噪音放大器輸入腳位 16 ......低頻帶受信混頻器輸入腳位 混頻器電路接地腳位 混頻器電路電源腳位 2 0……混頻器電路輸出腳位 2 2……局部振盪訊號輸入腳位 送訊電路塊電源腳位 送訊電路塊接地腳位 結合線 包含高頻數部及中間頻數帶之 …高頻帶低噪音放大器 低頻帶低噪音放大器 高頻帶受信混頻器 …低頻帶受信混頻器 混頻器 可變增益放大器 解調器 分頻器 調制器 補償器 合成器 帶域通過濾波器 C電路 訂 n I 絲 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中.國國家標率(CNS) M規格(210X297公釐) -16- 47238 2 A7 B7 五、發明説明(14 ) 5 0 1……封裝體支撐構件 5 0 2……積體電路基板 5 0 3……積體電路 5 0 4 ......接地電極 5 0 5 ......結合用線 5 0 6……導入腳位 5 0 7……寄生變壓器 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中.國國家標準(CNS ) A4規格(210X297公釐) -17 -
Claims (1)
- 47238 〇 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製· 六、申請專利範圍 1 . 一種半導體積體電路,於一晶片上備有,被輸入 受信訊號之第1頻帶放大器,及該第1頻帶放大器之輸出 之被輸入之第1頻帶受信混頻器, 自封裝體而突出於外之腳位前端到連接於上述第1頻 帶放大器之電極爲止之距離係,與其他之引線腳位之前端 與,與它對應之電極爲止之距離相比較而爲最短之位置上 配設上述第1頻帶放大器,爲其特徵者。 2 .如申請專利範圍第1項所述之半導體積體電路, 其中 上述第1頻帶放大器係備有雙極電晶體,而該雙極電 晶體之射極之被連接之電極至對應於該電極之腳位之前端 '爲止之距離係最短者。 3 . —種半導體積體電路,於一晶片備有:受信訊號 之被輸入之第1頻帶放大器及第2頻帶放大器,及該第1 頻帶放大器及第2頻帶放大器之輸出之分別被輸出之第1 頻帶受信混頻器,及第2頻帶混頻器, 而在上述第1頻帶受信混頻器之輸入腳位,與上述第 1頻帶放大器之輸入出腳位之間配置了上述第2頻帶受信 混頻器之輸入腳位,在上述第2頻帶受信混頻器之輸入腳 位,與上述第2頻帶放大器之輸入出之間,配置上述第1 頻帶放大器之輸入出腳位,在上述第1頻帶受信混頻器之 輸入出腳位,與上述第1頻帶放大器之輸入腳位之間配置 上述第1頻帶放大器之輸出腳位,在上述第2頻帶受信混 頻器之輸入腳位,與上述第2頻帶放大器之輸入腳位之間 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) ---------------ΐτ------ (請先閱讀背面之注意事項再填寫本頁) -18 - 472382 Α8 Β8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 ,配置上述第2頻帶放大器之輸出腳位,爲其特徵者。 4 ·如申請專利範圍第3項所述之半導體積體電路, 其中 5亥i:述第1頻帶放大器之輸入出腳位,及上述第2頻 帶放大器之輸出入腳位係設置於形成封裝體之四邊之一邊 上者。 5.—種半導體積體電路,在於1晶片上,具有受信 訊號之被輸入之第1頻帶放大器及第2頻帶放大器, 及該第1頻帶放大器及第2頻帶放大器之輸出之分別 被輸入之第1頻帶受信混頻器及第2頻帶受信混頻器, 而自封裝體外突出之腳位前端至連接於上述第1頻帶 放大器或上述第2頻帶放大器之電極爲止之距離之,與其 他之引線腳位之前端與對應它之電極爲止之距離相比而可 成爲最短之位置上,設置上述第1頻帶放大器或上述第2 頻帶放大器之電路,爲其特徵者。 6 ·如申請專利範圍第5項所述之半導體積體電路, 其中 上述第1頻帶放大器及上述第2頻帶放大器係分別具 有雙極電晶體,而其中之一之雙極電晶體之射極之被連接 之電極至對應於該電極之腳位之前端爲止之距離係最短者 0 7 . —種送受信用半導體積體電路,係具有:被輸入 受信訊號之第1頻帶放大器及第2頻帶放大器;·連接上述 第1頻帶放大器的第1偏壓電路;連接上述第2頻帶放大 (請先閱讀背面之注意事項再填寫本頁) -9. 本紙張尺度適用中國國家標準(CNS ) A4規格(210χ297公釐) -19 - 472382 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 器的第2偏壓電路;上述第1頻帶放大器之輸出被輸入的 第1頻帶受信混頻器.;及上述第2頻帶放大器之輸出被輸 入的第2頻帶受信混頻器;分別設有上述第1頻帶放大器 之接地腳位,上述第2頻帶放大器之接地腳位,及上述偏 壓電路之接地腳位。 8 . —種送受信用半導體積體電路,係具有:被輸入 受信訊號之第1頻帶放大器及第2頻帶放大器;上述第1 頻帶放大器及第2頻帶放大器之輸出分別被輸入的第1頻 帶受信混頻器及第2頻帶受信混頻器;上述第1頻帶放大 器之接地腳位與上述第2頻帶放大器之接地腳位係配置於 互相不鄰接之位置。 9 · 一種半導體積體電路,係具有:被輸入受信訊號 之第1頻帶放大器;上述第1頻帶放大器之輸出被輸入的 第1頻帶受信混頻器;及連接上述第1頻帶放大器的輸入 腳位、輸出腳位及接地腳位;上述接地腳位係配置於上述 輸入腳位與上述輸出腳位之間。 1 0 ·如申請專利範圍第7至第9項中之任一項所述 之半導體積體電路,其中上述放大器係具有雙極電晶體, 該射極係連接於接地梢,該基極係連接於輸入梢,該集極 係連接於輸出梢者。 . ' 11.一種送受信用半導體積體電路,係具有:被輸 入受信訊號之第1頻帶放大器及第2頻帶放大器;連接上 述第1頻帶放大器的第1偏壓電路;連接上述第2頻帶放 大器的第2偏壓電路;上述第1頻帶放大器之輸出被輸入 ^-- (請先閱讀背面之注意事項再填寫本頁) 、1T 本紙張尺度適用t國國家摞準(CNS ) A4規格(210X297公釐) -20- 472382 A8 B8 C8 D8 六、申請專利範圍 的第1頻帶受信混頻器;上述第2頻帶放大器之輸出被輸 入的第2頻帶受信混頻器;及送信電路;分別設有上述第 1頻帶放大器之接地腳位,上述第2頻帶放大器之接地腳 位,及上述偏壓電路之接地腳位,上述送信電路係連接上 述偏壓電路之接地腳位。 I I I I I I I I I I 訂— I ――線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 一用 適 度 張 _一紙 本 準 標 家 國 國 " 公 7 9 2
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KR20150072846A (ko) * | 2013-12-20 | 2015-06-30 | 삼성전기주식회사 | 반도체 패키지 모듈 |
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TWI559449B (zh) * | 2015-10-19 | 2016-11-21 | 穩懋半導體股份有限公司 | 化合物半導體積體電路之電路佈局方法 |
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-
1999
- 1999-04-15 JP JP11107545A patent/JP2000299438A/ja active Pending
-
2000
- 2000-04-05 TW TW089106246A patent/TW472382B/zh not_active IP Right Cessation
- 2000-04-11 US US09/547,915 patent/US6407449B1/en not_active Expired - Fee Related
- 2000-04-14 EP EP00107931A patent/EP1045442A3/en not_active Withdrawn
- 2000-04-14 KR KR1020000019472A patent/KR100890677B1/ko not_active IP Right Cessation
-
2002
- 2002-02-27 US US10/083,547 patent/US6639310B2/en not_active Expired - Fee Related
-
2003
- 2003-08-01 US US10/631,793 patent/US6768192B2/en not_active Expired - Fee Related
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2004
- 2004-03-30 US US10/812,081 patent/US6847108B2/en not_active Expired - Fee Related
- 2004-12-16 US US11/012,120 patent/US7369817B2/en not_active Expired - Fee Related
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2007
- 2007-08-24 KR KR1020070085376A patent/KR100842994B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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EP1045442A2 (en) | 2000-10-18 |
JP2000299438A (ja) | 2000-10-24 |
US6768192B2 (en) | 2004-07-27 |
US7369817B2 (en) | 2008-05-06 |
US6847108B2 (en) | 2005-01-25 |
US20050101282A1 (en) | 2005-05-12 |
US20040178497A1 (en) | 2004-09-16 |
KR20010014729A (ko) | 2001-02-26 |
US20040021208A1 (en) | 2004-02-05 |
US6407449B1 (en) | 2002-06-18 |
KR20070089903A (ko) | 2007-09-04 |
KR100890677B1 (ko) | 2009-03-26 |
US6639310B2 (en) | 2003-10-28 |
US20020079569A1 (en) | 2002-06-27 |
KR100842994B1 (ko) | 2008-07-01 |
EP1045442A3 (en) | 2003-07-23 |
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