1283471 (1) 玖、發明說明 【發明所屬之技術領域】 本發明是關於半導體裝置及電子裝置，例如關於適用 於連結包含放大微弱的訊號之低雜訊放大器（LNA: Low Noise Amplifier)的高頻部類比訊號處理ic的高頻功率模 組（半導體裝置）以及無線通訊裝置（電子裝置）之有效技術 【先前技術】 攜帶電話機等的移動通訊機（移動終端）是像可對應複 數個通訊系統的構成。即用以在攜帶電話機的發送接收機 (前端，Front end)進行複數個通訊系統的發送接收而連結 有複數個電路系。例如使在通訊方式（系統）不同的攜帶電 話（例如行動電話機）間的通話爲可能的方式已知有雙帶 (Dual band)通訊方式。關於雙帶方式已知有例如發送頻帶 爲8 80〜915MHz的 GSM(移動通訊全球系統，Gi〇bai System for Mobile Communications)、利用發送頻帶爲 1710 〜1 78 5MHz 的 DCS- 1 800(數位蜂巢式系統，Digital Cellular System 1 800)的雙帶方式以及雙帶用高頻功率放 大器。1283471 (1) Field of the Invention The present invention relates to a semiconductor device and an electronic device, for example, a high frequency suitable for connecting a low noise amplifier (LNA) including a weakly amplified signal. An effective technique for processing a high-frequency power module (semiconductor device) and a wireless communication device (electronic device) of analog signal processing [Prior Art] A mobile communication device (mobile terminal) such as a portable telephone is like a plurality of communication systems. Composition. That is, a plurality of circuit systems are connected to a plurality of communication systems for transmitting and receiving at a transceiver (front end) of a mobile phone. For example, a dual band communication method is known in which a call between a portable telephone (e.g., a mobile phone) having a different communication method (system) is possible. Regarding the dual band method, for example, GSM (Gi〇bai System for Mobile Communications) having a transmission band of 880 to 915 MHz, and DCS-1800 using a transmission band of 1710 to 1 78 5 MHz (digital cellular type) are known. System, Digital Cellular System 1 800) dual band mode and dual band high frequency power amplifier.
而且，在日本特開平11-186921號（1997年7月9日公開 )揭示可利用於 PCN(個人通訊網路，Personal Communications Network:DCS - 1 800)、PCS(個人通訊服務 ，Personal Communications Service: DCS- 1 900)以及 GSM (2) 1283471 等的攜帶電話系統的多帶移動體通訊裝置。 而且，在攜帶電話機的前端可謀求GSM用的高頻部 類比訊號處理電路的模組化。例如有利用MOSFET(金氧 半導體場效電晶體，Metal Oxide Semiconductor Field-Effect-Transistor) 的 雙帶或 三帶的 GSM 用 RF(無線 電頻率 ，Radio Frequency)功率模組。 雙帶方式是處理 GSM以及 DCS(Digital Cellular System) 1800方式等的兩個通訊系的訊號，三帶方式是處 理GSM以及DCS 1 800以及PCS 1 900方式等的三個通訊系 的訊號。GSM連結有GSM900或GSM8 5 0。 而且，高頻模組連結有單片（Monolithic)積集LNA、 混頻器（Mixer)、PLL(鎖相迴路，Phase-Locked Loop)合成 器（Synthesizer)、附自動校準（Auto calibration)的 PGA(可 規劃程式的增益放大器，Programmable Gain Amplifier)、 IQ調變器/解調器、偏移 PLL、VCO(壓控振盪器， Voltage-Controlled Oscillator)等的單晶片的半導體元件 〇 又，特開平2002-7623 5號公報中揭示有雙帶方式送收 訊用半導體積體電路。內藏於此雙帶方式送收訊用半導體 積體電路的差動雜訊放大器（由輸入有彼此相位呈反相的 兩個單位放大器所構成）具有一對的輸入端子及一對的輸 出端子，差動放大器之成對的放大器的接地接腳會形成彼 此相鄰，且相同放大器的輸入接腳與接地接腳會形成彼此 相鄰。藉此，相鄰的接腳的訊號會呈反相’利用接腳間的 (3) 1283471 變壓器耦合來降低電晶體射極的阻抗，改善差動放大器的 增益。 另一方面，攜帶電話機爲了搬運方便起見被要求小型 、輕量化。其結果高頻功率模組等的電子零件也希望更小 型、輕量化。 半導體裝置依照其封裝的形態有各種，而其中之一已 知有使絕緣性樹脂的密封體（封裝）的背面（安裝面）露出在 導線（外部電極端子），不在密封體的側面使導線長長地突 出的非導線型（Non-lead)半導體裝置。 非導線型半導體裝置有沿著密封體的背面的對面的兩 邊，使導線露出的 SON(小外型非導線封裝，Small Outline Non-Leaded Package)或在密封體的背面的四邊側 使露出的 QFN(四邊扁平非導線封裝，Quad Flat Non-Leaded Package) 。 對於 小型不 發生導 線彎曲 的非導 線型半 導體裝置例如記載於日本特開2001-313363號公報。 記載於此文獻的樹脂密封型半導體裝置具有連接固定 半導體晶片的晶粒座（Die pad)與銲接線（Wire)的打線接合 (Wire bonding)部的銲墊（Island)，半導體晶片被固定於 晶粒座上’半導體晶片的各電極端子是連接於導線或銲墊 的打線接合部的構造。在晶粒座與打線接合部之間設有空 隙部’防止因熱應力造成的接合的銲接線的脫落或切斷。 這種構造藉由以銲接線連接半導體晶片的接地端子與銲墊 ’可將銲墊連接於作爲接地導線的印刷基板等。 曰本特開平II-2 5 1 494號公報記載以半導體元件搭載 (4) 1283471 部爲接地的攜帶電話機等所使用的導線構造爲鷗翼（Gull wing)型的高頻裝置（Device)。此技術除了以銲接線連接半 導體元件的電極與導線外，因以晶粒座爲接地電極而利用 ’故以銲接線連接半導體元件的電極與半導體元件搭載部 (朝下接合，Down bonding)。由於進行朝下接合，故半導 體元件搭載部比半導體元件大，而且在安裝狀態下成爲在 半導體元件的外側半導體元件搭載部的周緣部分突出，於 此部分連接有銲接線的構造。 【發明內容】 【發明所欲解決之課題】 本申請人檢討將高頻功率模組連結到非導線型半導體 裝置，且爲了接地電位的穩定化，經由銲接線電性連接構 V. 一一—______________________——一^^^ 成高頻功率模組的各電路部的接地端子於調整片的手法的 採用。藉由採用朝下接合可減少外部電極端子的數目，可 謀求封裝的小型化，最終可謀求半導體裝置的小型化。 ____、 -.....-^--------- 但是，在以無線通訊系（通訊系統）爲用途的高頻功率 模組判明發生如以下的問題。 在攜帶電話機的接收系以天線捕捉的訊號被低雜訊放 大器（LNA)放大，但是輸入訊號極爲微弱。因此，各電路 部特別是依照周期動作的振盪器的動作，共通端子的調整 片的電位即接地電位變動，起因於此變動在與一部分的電 路部之間發生串擾（Crosstalk)，輸出變動無法進行良好的 通§舌。 -9 - (5) 1283471 特別是因導線之間的串擾所造成的感應電流或接地電 位的變動所造成的訊號波形的失真由通訊系統輸出，此輸 出訊號進入使用中的通訊系統變成雜訊。 這種接地電位的變動以及容易接受串擾的影響的電路 部在低雜訊放大器（LNA)以外有處理高頻的RFVCO(高頻 電壓控制振盪器）等。 因此，本發明者企圖在低雜訊放大器或RFVCO，不 經由銲接線連接到半導體元件的電極端子之中接地端子爲 共通端子的調整片，而是經由銲接線連接於獨立的導線端 子（外部電極端子）減少在其他電路部的開關（ΟΝ/OFF)時等 的接地電位的變動的影響而完成本發明。 本發明的目的是提供在朝下接合構造的半導體裝置中 ，形成於半導體元件的電路之中特定的電路部中的接地電 位可很難受到剩餘的電路部的接地電位的影響的半導體裝 置。 本發明的其他目的是提供在高頻功率模組中低雜訊放 大器或RFVCO等的電路部很難受到其他電路部的接地電 位的變動所造成的串擾的影響的高頻功率模組。 本發明的其他目的是提供在無線通訊系統中，雜訊少 的良好的通話爲可能的無線通訊裝置。 本發明的其他目的是提供在具有複數個通訊系統的無 線通訊系統中，雜訊少的良好的通話爲可能的無線通訊裝 置。 另一方面，本發明者針對輸入彼此相位呈相反的訊號 -10- (6) 1283471 (互補訊號）之2輸入方式的低雜訊放大器（LNA:差動低雜 訊放大器）來進行分析檢討。圖34(a)及（b)分別爲含低雜訊 放大器 （LNA)IOO，高頻電壓控制振盪器 （RFVCO)lOl及 混頻器102的電路部分，圖34(a)是表示1輸入方式的LNA ，圖34(b)是表示2輸入方式的LNA。 在以混頻器1 02來混頻：處理來自天線的受訊訊號後 之低雜訊放大器1〇〇的輸出訊號，及來自局部振盪器 (RFVCO:高頻電壓控制振盪器）1〇1的訊號之電路構成中， 就圖34(a)所示之1輸入構成的低雜訊放大器而言，由於 RFVCO101的輸出頻率會與LNA100的輸出頻率相同，因此 若RFVCO101的輸出訊號洩漏至LNA輸入線，則會原封不 動地被放大於LNA100，而導致DC偏移會變大。 在此，如圖34(b)所示，以LNA100作爲差動低雜訊放 大器（差動放大器：LNA)，藉由輸入彼此相位呈反相的訊 號（互補訊號）之2輸入方式來縮小DC偏移。亦即，由於 差動放大器（差動放大電路）100是以相同構成的兩個單位 放大器來構成，輸入相位呈反相的兩個高頻訊號（互補訊 號）而差動放大，因此同相成分會被取消，所以可縮小D C 偏移値。 但，當發送頻帶形成更高時，只利用前述輸入互補訊 號的2輸入方式，是無法根本解決前述DC偏移的問題。 就輸入前述互補訊號的輸入配線路徑而言，大槪可分爲·· 以導線架來形成的導線部分，及供以連接前述導線部分與 半導體晶片的電極之銲接線部分。 -11 - (7) 1283471 例如，以銅等金屬的板材所形成的導線部分，由於厚 度及寬度較大，因此雖然在數毫米程度的微小導線長度時 所產生的電感差異小，但直徑爲20〜30 /z m程度的銲接線 部分會依其長度的不同而容易發生較大的電感差異。此銲 接線電感的差異會造成兩個互補輸入訊號的輸入時間差， 有損輸入訊號的對稱性。其結果，在高速通訊系統中會降 低增益。 因此，本發明的另一目的是在同時將互補訊號輸入差 動低雜訊放大器的電路部中，提高輸入訊號的對稱性。 又，本發明的另一目的是在於提高具有差動低雜訊放 大器的高頻功率模組的特性向（DC偏移小）。 本發明之前述及其他目的與新穎的特徴，可由本說明 書的記載及圖面來明確得知。 【用以解決課題之手段】 本發明的前述以及其他目的與新穎的特徵可由本說明 書的記述以及添付圖面而明瞭。 在本案中所揭示的發明之中，若簡單地說明代表的發 明槪要的話如以下所示。 (1 )、本發明的半導體裝置，包含： 由絕緣性樹脂構成的密封體； 沿著該密封體的周圍，遍及該密封體的內外配設的複 數條導線； 具有主面以及背面的調整片； -12- (8) 1283471 具有主面以及背面，在該主面上具有複數個電極端子 與分別由複數個半導體元件構成的複數個電路部的半導體 晶片；以及 連接該複數個電極端子與該導線的複數條導電性的銲 接線； 用以對該複數個電極端子供給第一電位，連接該複數 個電極端子與該調整片的主面的複數條導電性的銲接線（ 例如非導線型半導體裝置），其特徵爲： 該半導體晶片的背面被固定於該調整片的主面上， 該複數個電路部包含第一電路部（特定電路部）、第二 電路部， 該複數個電極端子具有用以對該第一電路部輸入外部 訊號的第一電極端子、用以對該第一電路部供給該第一電 位（接地電位）的第二電極端子、與該第二電路部連接的第 三電極端子以及用以對該第二電路部供給該第一電位的第 四電極端子， 該複數條導線包含第一導線（訊號用導線）、第二導線 (訊號用導線）、配置於該第一導線與第二導線之間的第三 導線（接地用導線）， 該第一電極端子是經由導電性的銲接線與該第一導線 連接， 該第二電極端子是經由導電性的銲接線與該第三導線 連接， 該第三電極端子是經由導電性的銲接線與該第二導線 -13- 1283471 Ο) 連接， 該第四電極端子是經由導電性的銲接線與成爲共通接 地的該調整片連接， 該第三導線與該調整片被電性分離， 構成該高頻模組。 該第一電路部是用以放大該第一導線以及經由該第一 電極端子而輸入的外部訊號的放大電路（低雜訊放大器 :；LAN)，無線訊號是用以放大經由天線而轉換的電氣訊號 的電路。 該第二電路部具有處理被第一電路部放大的訊號的功 能的至少一部分。 而且，在高頻功率模組令可對應複數個通訊方式而形 成有複數個通訊電路。這種高頻功率模組被連結到無線通 訊裝置。 如果依照前述（1)的手段，（a)、半導體元件的電極端 子除了經由銲接線連接於導線外，也被連接於成爲共通接 地的調整片（朝下接合）。放大微弱訊號的低雜訊放大器（ 特定電路部）的接地電極端子（半導體元件的電極端子）在 調整片不被連接，而是連接於獨立的導線端子（接地用導 線），故在與其他電路部之間接地電位變成獨立，在其他 電路部的電源的開關時接地電位變動也很難發生，伴隨著 接地電位的變動的低雜訊放大器的輸出變動或訊號波形的 失真也很難發生，若連結到無線通訊裝置的話，會使無輸 出變動或失真的良好的通話爲可能。 -14- (10) 1283471 (b) 、在具有複數個通訊電路的高頻功率模組中，利 用調整片的共通接地的情形伴隨著接地電位的變動在不使 用的通訊電路發生感應電流，發生起因於此感應電流的雜 訊進入使用中（動作中）的通訊電路的所謂的串擾，但是在 本發明的高頻功率模組因各通訊電路的低雜訊放大器與其 他電路部的接地分離，故可抑制低雜訊放大器的輸出的變 動或訊號波形的失真。其結果在具有複數個通訊電路的無 線通訊裝置中，也使無輸出變動或失真的良好的通話爲可 能。 (c) 、因由低雜訊放大器的電極端子經由銲接線到達 導線的訊號配線在其兩側配置有接地配線被電磁屏壁，故 可降低訊號配線之間的串擾。 (d) 、高頻功率模組爲朝下接合構造的非導線型半導 體裝置，可謀求小型、薄型、輕量化，並且因調整片露出 在密封體的背面，故散熱性良好，可穩定動作。因此，藉 由此高頻功率模組的連結，可提供通話性能良好的小型、 輕量的攜帶電話機。 【實施方式】 以下參照圖面詳細說明本發明的實施形態。此外，在 用以說明發明的實施形態的全圖中，對具有相同功能的構 件附加相同的符號，省略其重複說明。 (實施形態1) -15- (11) 1283471 圖1至圖13是與連結本發明的一實施形態（實施形態1) 之半導體裝置（高頻功率模組）及其高頻功率模組的無線通 訊裝置有關的圖。圖1至圖5是與高頻功率模組有關的圖， 圖6至圖1 1是與高頻功率模組的製造方法有關的圖，圖1 2 以及圖1 3是與無線通訊裝置有關的圖。 在本實施形態1說明關於在四角形狀的密封體（封裝） 的背面的安裝面適用本發明於露出調整片以及連接於此調 整片的調整片吊導線以及導線（外部電極端子）的QFN型的 半導體裝置的例子。半導體裝置1例如構成高頻功率模組 〇 QFN型的半導體裝置1如圖1以及圖2具有以扁平的四 角形狀的絕緣性樹脂形成密封體（封裝）2。在此密封體2的 內部埋入有四角形狀的半導體元件（半導體晶片：晶片）3。 前述半導體晶片3是藉由接著劑5固定於四角形狀的調整片 4的調整片表面（主面）（參照圖2)。如圖2所示，密封體2的 背面（底面）成爲被安裝的面側（安裝面）。 在密封體2的背面成爲露出調整片4以及支持調整片4 的調整片吊導線6以及導線（外部電極端子）7的一面（安裝 面7a)的構造。這些調整片4以及調整片吊導線6以及導線7 在半導體裝置1的製造中，以形成圖案（Patterning)的一片 金屬製（例如銅製）的導線架（Lead frame)形成，然後被切 斷而形成。 因此’在本實施形態1這些調整片4以及調整片吊導線 6以及導線7的厚度相同。但是，在導線7中因內端部分是 -16- (12) 1283471 鈾刻背面一定的深度而薄薄地形成，故在此薄的導線部分 的下側成爲構成密封體2的樹脂進入的構造。據此，導線7 很難由密封體2脫落。 調整片4其四角落被細的調整片吊導線6支持。這些調 整片吊導線6位於四角形狀的密封體2的對角線上，使外端 面臨四角形狀的密封體2的各角落部。密封體2爲扁平的四 角形體，角部（角落部）被實施倒角加工變成斜面2a(參照圖 1)。調整片吊導線6的外端在此倒角部分僅突出0.1mm以 下。此突出長度是由切斷導線架狀態的調整片吊導線時的 沖壓（P r e s s)機械的切斷模決定，例如可選擇0 . 1 m m以下。 而且，如圖1所示在調整片4的周邊使內端面對調整片 4的導線7是沿著四角形的密封體2的各邊，以預定間隔配 置複數個。調整片吊導線6以及導線7的外端是延伸到密封 體2的周緣。即導線7以及調整片吊導線6是遍及密封體2的 內外而延伸。由導線7的密封體2的突出長與前述調整片吊 導線6 —樣是由切斷導線架狀態的導線時的沖壓機械的切 斷模決定，例如僅突出0.1mm以下。 而且，密封體2的側面成爲傾斜面2b (參照圖2)。此傾 斜面2 b是在導線架的一面進行單面封膠（Μ ο 1 d )形成密封 體2後，當由封膠模具的模槽（Cavity)抽出密封體2時，爲 了使抽出容易起見，令模槽的側面爲傾斜面的結果所造成 者。此外，圖1是切去密封體2的上部而可見到調整片4、 調整片吊導線6、導線7以及半導體晶片3等的模式圖。 而且，如圖1以及圖4所示，在半導體晶片3的露出的 -17- (13) 1283471 主面配設有電極端子9。電極端子9在半導體晶片3的主面 中沿著四角形的各邊大致被配設成預定的間距（Pitch)。此 電極端子9經由導電性的銲接線1 〇連接於導線7的內端側。 調整片4與半導體晶片3比較大大地形成，在其主面的 中央具有半導體元件固定區域，並且在此半導體元件固定 區域的外側即調整片4的周緣部分具有銲接線連接區域。 而且半導體晶片3被固定在此半導體元件固定區域。而且 ，在銲接線連接區域連接有一端連接於半導體晶片3的電 極端子9的導電性的銲接線1 0的他端。特別是稱連接於調 整片4的銲接線10爲朝下接合銲接線10a。因藉由打線接合 裝置進行電極端子9與導線7之間的打線接合以及電極端子 9與調整片4之間的打線接合，故銲接線1 0與朝下接合銲接 線1 〇 a都是相同材質。 朝下接合構造的採用目的一般是利用調整片的半導體 晶片內的各電路部的接地電位的共通化。令調整片爲共通 的接地端子，藉由經由銲接線連接此調整片與成爲接地電 極端子的許多電極端子，可減少沿著密封體的周圍排列的 外部電極端子的導線（針腳，Pin)的數目’可謀求導線數 降低所造成的密封體的小型化。此與半導體裝置的小型化 有關。 而且，本實施形態1的半導體裝置1如圖3所不’在各 導線7與導線7之間以及導線7與調整片吊導線6之間存在在 形成密封體2時所產生的樹脂毛邊。此樹脂毛邊部分是在 半導體裝置1的製造中在導線架的一面進行單面封膠’形 -18- (14) 1283471 成密封體2時產生的。封膠後雖然切斷不要的導線架部分 ，惟因在此時的導線或調整片吊導線的切斷時樹脂毛邊也 同時被切斷，故樹脂毛邊的外緣變成與導線7的緣或調整 片吊導線6的緣一起，一部分的樹脂毛邊殘留於各導線7與 導線7之間以及導線7與調整片吊導線6之間。 而且，.在本實施形1是密封體2的背面比調整片4、調 整片吊導線6以及導線7的背面（安裝面）還凹入的構造。此 在傳送封膠（Transfer molding)中的單片封膠中，在封膠模 具的上下模間舖設樹脂製的薄片（Sheet)，使導線架的一面 接觸此薄片而進行封膠，因薄片在導線架的間隙咬入，故 密封體2的背面變成凹入形。 而且，在利用傳送封膠的單片封膠後，於導線架的表 面形成表面安裝用的電鍍膜。因此，露出在半導體裝置1 的密封體2的背面的調整片4、調整片吊導線6以及導線7的 表面雖然未圖示但是具有電鍍膜。 如此，在導線7或調整片吊導線6的背面之安裝面突出 ，密封體2的背面凹入的偏移構造具有在安裝基板等的銲 接線基板表面安裝半導體裝置1時，因銲錫的潤濕區域被 特定，故銲錫安裝良好的特長。 此處，對於本實施形態1的半導體裝置1的製造方法， 參照圖6至圖1 1來說明。如圖6的流程圖所示，半導體裝置 1是經過導線架準備（S 101)、晶片接合（S 102)、打線接合 (S 103)、密封（封膠：S 104)、電鍍處理（S 105)、切斷除去不 要的導線架（S 106)的各製程而製造。 -19- (15) 1283471 圖7是製造依照本實施形態1的QFN型的半導體裝置1 時所使用的矩陣構成的導線架1 3的模式的俯視圖。 此導線架13其單位導線架圖案I4沿著X方向配置20 行，沿著Y方向配置4列，可由一片導線架I3製造80個半 導體裝置1。在導線架1 3的兩側配設有導線架1 3的傳送或 定位等所使用的導孔（Guide hole) 15 a〜15c。 而且，澆道（Runner)在進行傳送封膠時位於各列的左 側。因此，因利用頂桿（Ejector pin)的突出由導線架13撕 下澆道硬化樹脂，故設有頂桿可貫通的頂桿孔1 6。而且， 因利用頂桿的突出由導線架1 3撕下由此澆道分歧，在流到 模槽的澆口（Gate)部分硬化的澆口硬化樹脂，故設有頂桿 可貫通的頂桿孔1 7。 圖8是顯示單位導線架圖案1 4的一部分的俯視圖。單 位導線架圖案1 4由於是實際製造的圖案，故有模式圖的圖 1或圖2等未必一致的部分。 單位導線架圖案1 4具有矩形框狀的框部1 8。調整片吊 導線6由此框部1 8的四角落延伸，成爲支持中央的調整片4 的圖案。複數條導線7由框部1 8的各邊的內側朝內方延伸 ，其內端接近調整片4的外周緣。在調整片4以及導線7的 主面配設有晶片接合或打線接合用的未圖示的電鍍膜。 而且，導線7其前端側背面被半蝕刻（Half-etching)而 變薄（參照圖2)。此外，導線7或調整片4等令其周緣爲像 主面的寬度比背面的寬度還寬的斜面，形成倒梯形剖面很 難由密封體2抽出的構造也可以。此也可藉由蝕刻或沖壓 -20- (16) 1283471 (Press)來製造。 而且，如圖8所示在調整片4的主面中，中央的四角形 區域成爲半導體元件搭載部4a(被二點鏈線框包圍的區域） ，其外側的區域成爲銲接線連接區域4b。 在準備這種導線架1 3後如圖8、9所示，藉由接著劑5 將半導體晶片3固定（晶片接合）於各單位導線架圖案14的 調整片4的半導體元件搭載部4a(S 102)。 其次如圖1 〇所示進行打線接合，以導電性的銲接線1 0 連接半導體晶片3的電極端子與導線7的前端，並且以導電 性的銲接線1 〇連接預定的電極端子與調整片4的銲接線連 接區域4b(Sl 03)。特別稱連接電極端子與調整片4的銲接 線連接區域4b的銲接線爲朝下接合銲接線1 0a。銲接線例 如使用金線。 接著，進行利用常用的傳送封膠的單片封膠，在導線 架13的主面形成利用絕緣性樹脂的密封體2(S 104)。密封 體2覆蓋導線架1 3的主面側的半導體晶片3、導線7等。在 圖8中以二點鏈線框表示的部分爲形成有密封體2的區域。 其次，未圖示進行電鍍處理（S 105)。其結果在導線架 1 3的背面形成有未圖示的電鍍膜。此電鍍膜是當作半導體 裝置1的表面安裝時的接合材使用，例如爲銲錫電鍍膜。 取代形成前述電鍍膜的製程，預先在導線架1 3的表面全面 使用被實施鍍Pd的物質也可以。而且，特別是當使用被 鍍Pd的導線架I3時可省略前述密封後的電鍍製程，使製 造製程簡略化，可削減製造成本。 -21 - (17) 1283471 其次，切斷除去不要的導線架部分（SI 06)，製造如圖 1所示的半導體裝置1。在圖8所示的二點鏈線框的密封體2 的稍外側，利用未圖示的沖壓機械的切斷模使導線7以及 調整片吊導線6被切斷。利用切斷模的構造在稍微脫離密 封體2的位置切斷導線7以及調整片吊導線6，而距此稍微 脫離的位置的密封體2的距離例如令成0.1mm以下。距導 線7以及調整片吊導線6的密封體2的突出長度由防止卡住 等的點，短的佳。此突出長度由沖壓機械的切斷模的變更 在0.1mm以上可自由選擇。 此處，舉半導體裝置1的各部的尺寸的一例。導線架（ 調整片4、調整片吊導線6、導線7)的厚度爲0.2mm，晶片3 的厚度爲0.28mm，半導體裝置1的厚度爲1.0mm，導線7的 寬度爲0.2mm，導線7的長度爲〇.5mm，調整片4的銲接線 連接位置（點）距所搭載的晶片3的端1.0mm，而且調整片4 與導線7的間隔爲0.2mm。 另一方面雖然此爲本發明的特徵之一，但是半導體晶 片3內的電路的一部分即特定電路部的接地當作接地電極 端子而取出，且經由銲接線連接於導線，與剩餘的電路部 的接地分離。剩餘的各電路部依照需要經由銲接線連接於 成爲共通接地的調整片，並且依照需要經由銲接線連接於 導線。而且，特定電路部的接地與其他剩餘的電路部的接 地雖然未圖示，但是在半導體晶片3內的配線中也藉由層 間絕緣膜（Interlayer dielectric insulating film)等絕緣隔 離0 22- (18) 1283471 在本實施形態1適用的高頻功率模組，若將形成於單 一半導體晶片內的各電路部全部接地共通化的話，如之前 所說明的，有因接地電位的變動使串擾發生，在各個電路 部的輸出變動或訊號波形的失真發生之虞。 而且，在具有雙帶或三帶等的複數個通訊電路的高頻 功率模組中，有在不使其動作於動作中的通訊電路發生感 應電流，此感應電流以雜訊進入動作中的通訊電路之虞。 因此，在本實施形態1特定電路部的接地用的電極端子（接 地電極端子）不連接於調整片，而是經由銲接線連接於獨 立的導線（接地導線）。 而且，有因輸入訊號配線彼此的串擾，使在各個電路 部的輸出變動或訊號波形的失真發生之虞，特別是在來自 輸入訊號小的天線的外部訊號輸入用導線中，需要極力避 開與接鄰的導線的串擾的影響。 在本實施形態1中因半導體裝置1爲攜帶電話機的三帶 用的高頻功率模組，故特定電路部爲低雜訊放大器（LNA) 。由於是三帶，故連接於天線的低雜訊放大器（LNA)也配 置三個。 單一的LNA成爲在本發明所謂的狹義的特定電路部 。即如圖5所示，來自各LN A的天線的輸入訊號配線爲兩 條。而且，爲了電磁屏壁此兩條訊號配線，兩條訊號用導 線與其他訊號用導線之間’最好在兩條訊號用導線的兩側 分別配置接地用導線。 若令輸入訊號配線爲兩條，令成差動輸入構成的話’ -23- (19) 1283471 在輸入訊號配線的兩條產生因同程度的串擾所造成的影響 ，可抵銷（消除）雜訊（串擾）。此外如圖5所示，令包圍三個 LNA的矩形框部分爲廣義的特定電路部丨〗。此特定電路 部1 1在半導體晶片中，在由其他電路部絕緣隔離的區域形 成有各LNA。而且各LNA的接地電位是共通。此乃因在 雙帶通訊系統、三帶通訊系統，在使用一個通訊系統（通 訊系）間，剩餘的通訊系統成爲空載（Idling)狀態，因對屬 於成爲空載狀態的通訊系統的LNA所造成的接地電位的 影響小，故即使使屬於個別的通訊系統的LNA彼此的接 地電極以及接地配線共通化，互相的不良影響也小。但是 ，若有需要對各LNA實施隔離（Isolation)，使各LNA的 接地電位獨立的構成也可以。 圖1 3是顯示本實施形態1的半導體裝置（高頻功率模組 )1的攜帶電話機中的安裝狀態的模式的剖面圖。 爲了在攜帶電話機的安裝基板（配線基板）80的主面搭 載半導體裝置1，配設有對應半導體裝置1的導線7以及調 整片4連接於配線的銲墊8 1以及調整片固定部82。因此， 令半導體裝置1的導線7以及調整片4與前述銲墊8 1以及固 定部82—致而重疊，以定位載置半導體裝置1。而且，在 此狀態下一時地熔融（迴銲，Reflow)預先形成於半導體裝 置1的導線7以及調整片4的背面的銲錫電鍍膜，以銲錫8 3 連接（安裝）導線7以及調整片4。 此處，參照圖1 2簡單地說明關於三帶構成的攜帶電話 機的電路構成（功能構成）。即此攜帶電話機可進行例如 -24- (20) 1283471 900MHz帶的GSM通訊方式與1 800MHz帶的DCS 1 8 00通 訊方式與1 900MHz帶的PCS 1 900通訊方式的訊號處理。 圖1 2的區塊圖顯示經由天線開關2 1連接於天線2 0的發 送系與接收系，發送系以及接收系都連接於基帶 (Baseband)晶片 22 。 接收系具有天線20、天線開關2 1、並聯連接於此天線 開關2 1的三個帶通濾波器23、分別連接於前述帶通濾波器 23的低雜訊放大器（LNA)24、連接於前述三個LNA24且並 聯連接的可變放大器25。在此兩個可變放大器25分別連接 有混頻器26、低通濾波器27、PGA28、低通濾波器29、 PGA30、低通濾波器3 1、PGA32、低通濾波器33、解調器 34 〇 PGA28、PGA30、PGA32 被 ADC/DAC&DC 偏移用控 制邏輯電路部35控制。而且，兩個混頻器26可藉由90度相 位轉換器40相位控制。 在圖12中由90相位轉換器40以及兩個混頻器26構成的 I/Q調變器爲了對應各頻帶區域，對應三個LNA分別配設 ，惟在圖12中爲了簡略化整理成一個而寫出。 在半導體晶片3訊號處理1C配設有由RF合成器41以 及IF(中間，Intermediate)合成器42構成的合成器。RF合 成器41經由緩衝器43連接於RFVC044，令RFVC044輸出 RF局部訊號而控制。在緩衝器43串聯連接有兩個局部訊 號用分頻器37、38，在各個輸出端連接有開關48、49。由 RFVCO 44出來的RF局部訊號藉由開關48的切換輸入到90 相位轉換器40。90相位轉換器40藉由此RF局部訊號控制 -25- (21) 1283471 混頻器26。 RFVC044的訊號輸出模式爲Rx模式的情形在GSM 爲 3 78 0 〜3 840MHz，在 DCS 爲 3 6 1 0〜3 7 60MHz，在 PCS 爲 3 8 60 〜3 98 0MHz。而且，T x 模式在 G S Μ 爲 3 8 4 0 〜3 9 8 0 ΜΗ z ，在 DCS 爲 3580 〜3730MHz，在 PCS 爲 3860 〜3980MHz。 IF合成器42經由分頻器46連接於IFVCO(中間波電壓 控制振盪器）45，令IFVC045輸出IF局部訊號而控制。利 用IF VC〇4 5的輸出訊號的頻率各通訊方式都爲640MHz。 而且，藉由RF合成器41以及IF合成器42控制VCXO(電 壓控制水晶振盪器）50，輸出基準訊號傳送到基帶晶片22 〇 在接收系利用合成器以及ADC/DAC&DC偏移用控制 邏輯電路部3 5控制IF訊號。利用解調器3 4轉換成基帶晶 片訊號（I，Q訊號）傳送到基帶晶片22。 發送系是由以自基帶晶片22輸出的I，Q訊號當作輸 入訊號的兩個混頻器6 1、控制此兩個混頻器6 1的相位的90 相位轉換器62、累加此兩個混頻器6 1的輸出的加法器63、 將加法器63的輸出都當作輸入的混頻器64以及DPD (數位 檢相器，Digital Phase Detector)65、將混頻器64以及 DPD65的輸出都當作輸入的環路濾波器（Loop filter)66、 將環路濾波器66的輸出都當作輸入的兩個TX VC 0(發送波 電壓控制發送器）67、將此兩個TXVC067的輸出都當作輸 入的功率模組68、天線開關21構成。環路濾波器66爲外加 零件。 -26- (22) 1283471 藉由混頻器61、90相位轉換器62以及加法器63構成直 交調變器。90相位轉換器62經由分頻器47連接於分頻器46 ，藉由自IF VC 045輸出的IF局部訊號控制。 兩個TXVC067的輸出利用耦合器（Couple〇70檢測電 流。此檢測訊號經由放大器7 1輸入到混頻器72。混頻器72 經由開關49輸入自RFVC 04 4輸出的RF局部訊號。混頻器 72的輸出訊號與加法器63的輸出訊號一起輸入到混頻器64 以及DPD65。由混頻器64與DPD65構成偏移PLL(Phase-Locked Loop)。由混頻器72產生的輸出訊號的頻率在各通 訊方式都爲80MHz。 兩個TXVC067之中的一個的TXVC067爲GSM通訊 方式用，輸出訊號的頻率爲880〜9 15MHz。而且，其他的 TXVC067爲DCS、PCS通訊方式用，輸出訊號的頻率爲 1710〜1 78 5 MHz或1 8 5 0〜19 10 MHz。功率模組68內裝低頻 用功率模組與高頻用功率模組，低頻用功率模組接受來自 輸出8 8 0〜9 15MHz的訊號的TXVC067的訊號而進行放大處 理，高頻用功率模組接受來自輸出1710〜1 7 8 5 MHz或 1 8 5 0〜1910 MHz的訊號的TXVC067的訊號而進行放大處 理，傳送到天線開關2 1。 邏輯電路60也單片地形成在本實施形態1的半導體裝 置1，將輸出訊號傳送到基帶晶片22。 本實施形態1的半導體裝置（高頻功率模組）1在圖1 2中 以粗線包圍的部分的各電路部是單片地形成。而且，三個 LNA24的部分成爲本實施形態1中的特定電路部1 1(參照圖 -27- (23) 1283471 4、圖5)。雖然模式地顯示一部分這些各電路部，但是爲 圖4以及圖5的半導體晶片3的區塊俯視圖。 以天線2〇接收的無線訊號（電波）被轉換成電氣訊號， 在接收系的各零件依次被處理，傳送到基帶晶片22。而且 ，由基帶晶片22輸出的電氣訊號在發送系的各零件依次被 處理，被由天線20以電波發射。 圖4是顯示半導體晶片3中的各電路部的配置的模式的 佈局圖。在半導體晶片3的主面沿著邊配置有電極端子（銲 墊）9。而且，在這些電極端子9的內側區分區域配置有各 電路部。如圖4所示在半導體晶片3中央配置有 ADC/DAC&DC偏移用控制邏輯電路部35，在其左側排列 混頻器26、64與三個 LNA24，RFVC044位於上彻1，在右 側由上到下排列RF合成器41、VCXO50、IF合成器42、 IFVC045，TXVC067位於下側。 在圖5顯示各電路部（第一電路部以及第二電路部）與 其電極端子9的關係，電極端子9與導線7的銲接線1 0所造 成的接線狀態。銲接線10顯示連接電極端子9與導線7的銲 接線10與連接電極端子9與調整片4的朝下接合銲接線10a 〇 若著眼於特定電路部11(第一電路部）的三個LNA24的 話，與外加零件的帶通濾波器23連接的預定的導線7、即 記載於左側的Signal的導線7與LNA24的訊號電極端子9 經由銲接線1 〇連接。由電極端子9經由銲接線1 〇到達導線7 的訊號配線配設兩條，此兩條訊號配線的兩側，特定電路 -28- (24) 1283471 部1 1的LNA24的接地電極端子9經由銲接線10連接於接地 導線7(圖中記載於左側的GND的導線7)，形成有接地配 線。 據此，其他電路部至少各VCO的接地與LNA24的接 地被絕緣隔離’且接鄰的其他電路部的導線與L N A 2 4的 導線之間被接地導線7電磁屏蔽。而且，接鄰的LNA24彼 此也被接地導線7電磁屏蔽。 與放大由天線進入的微弱訊號的LNA24比較，在處 理由基帶晶片22輸出的電氣訊號的發送系的各電路部（例 如偏移PLL、TXVCO67等）中，因該電氣訊號比前述微弱 訊號大，故具有因接地電位的變動或串擾所造成的雜訊強 的特性。因此，對發送系的電路部的接地電位的供給藉由 經由各VCO等與調整片4使其共通，可減少導線7的數目 ，可使半導體裝置小型化。 LNA爲了防止因在形成於半導體晶片3主面上的配線 間的串擾所造成的訊號的劣化，比較例如P G A等、處理 被前述LNA放大的訊號的電路或發送系的電路等，使前 述配線的長度變短而配置於更接近電極端子9較佳。 如果依照本實施形態1，具有以下的功效。 (1 )、在半導體裝置1即高頻功率模組1中，半導體元 件（半導體晶片）3的電極端子9除了經由銲接線10連接於導 線7外，也連接於調整片4(朝下接合）。而且，此朝下接合 因調整片4成爲共通接地，故特定電路部1 1的低雜訊放大 器24的接地電極端子（半導體元件的電極端子）不連接於調 -29- (25) 1283471 整片4，而是連接於獨立的導線端子（接地導線）。因低雜 訊放大器24放大微弱的訊號，接地電位的變動變成低雜訊 放大器24的輸出的變動，並且訊號波形也失真，但是因低 雜訊放大器24的接地與其他電路部的接地分離，故可抑制 低雜訊放大器24的輸出的變動或訊號波形的失真。其結果 藉由連結到無線通訊裝置使無輸出變動或失真的良好的通 化爲可能。 (2) 、在具有複數個通訊電路的高頻功率模組中，利 用調整片4的共通接地的情形伴隨著接地電位的變動在不 使用的通訊電路發生感應電流，發生起因於此感應電流的 雜訊進入使用中（動作中）的通訊電路的所謂的串擾，但是 在本發明的高頻功率模組1因各通訊電路的低雜訊放大器 24與其他電路部的接地分離，故可抑制低雜訊放大器24的 輸出的變動或訊號波形的失真。其結果在具有複數個通訊 電路的無線通訊裝置中，也使無輸出變動或失真的良好的 通話爲可能。 (3) 、在高頻功率模組1中，因由低雜訊放大器24的電 極端子9經由銲接線1 0到達導線7的訊號配線在其兩側配置 有接地配線被電磁屏壁，故訊號配線很難受到串擾。 (4) 、在高頻功率模組1中，因調整片4露出在密封體2 的背面，故可有效地將在半導體晶片3產生的熱散發到安 裝基板8 0。因此，連結此高頻功率模組1的無線通訊裝置 可穩定動作。 (5) 、因高頻功率模組1爲調整片4以及導線7露出在密 -30- (26) 1283471 封體2的背面的非導線型半導體裝置，故高頻功率模組1的 小型、薄型化爲可能，也可謀求輕量化。因此，連結此高 頻功率模組1的無線通訊裝置的小型、輕量化也可能。 (6)、因高頻功率模組1成爲經由銲接線10連接半導體 晶片3的電極端子9與導線（針腳）7，並且以朝下接合銲接 線l〇a連接成爲接地電位的調整片4與半導體晶片3的電極 端子（接地電極端子）9的朝下接合構造，故可減少成爲外 部電極端子7的接地導線，使藉由降低針腳數的密封體2的 小型化爲可能，可達成高頻功率模組1的小型化。 (實施形態2) 圖14是切去本發明的其他實施形態（實施形態2)之高 頻功率模組的密封體的一部分的模式的俯視圖。 本實施形態2除了在實施形態1中特定電路部1 1具有三 個低雜訊放大器（LNA)24的電路部外，VCO之中處理高頻 的 RFVC044也是當作特定電路部1 1。因此，RFVC044的 所有的接地電極端子9經由銲接線1 0連接於導線（接地導線 )7，而不經由銲接線連接於調整片4。 在由半導體晶片3的電極端子9經由銲接線1 0到達導線 7的配線中，在RFVCCM4的兩條訊號配線的兩側配置有接 地配線，進行訊號配線的電磁屏蔽。 據此，藉由處理高頻訊號的特定電路部11的接地電位 由其他電路部的接地電位絕緣隔離’故串擾不發生。 -31 - (27) 1283471 (實施形態3) 圖1 5是切去本發明的其他實施形態（實施形態3)之高 頻功率模組的密封體的一部分的模式的俯視圖。 在本實施形態3令RFVC〇44爲外加零件，爲在半導體 晶片3單片地形成的例子。此雙帶通訊方式是單片地形成 低雜訊放大器、混頻器、VCO、合成器、IQ調變器/解調 器、分頻器、直交調變器等各電路部。 接收系的兩個混頻器分別被分頻器控制，而且此分頻 器是用以將由外加零件的RFVCO輸出的高頻訊號轉換成 更低頻的訊號的頻率轉換電路。 因此，在本實施形態3如圖15所示在半導體裝置1的外 側存在RFVC044，RFVC044的訊號配線連接於兩條半導 體裝置1的導線7。而且，由連接於RFVC 044的兩條導線7 經由銲接線1 〇到達半導體晶片3的電極端子9的兩條訊號配 線的兩側的電極端子9與導線7經由銲接線1 0連接。此兩條 訊號配線的兩側的電極端子9爲接地電極端子，經由銲接 線1 〇連接於此接地電極端子的導線7也變成接地導線。據 此，與實施形態2的情形一樣，處理高頻訊號的訊號配線 也被電磁屏蔽，並且與半導體晶片3中的其他電路部接地 電位爲獨立的構成。 在本實施形態3中也與實施形態2—樣，不發生伴隨著 RFVC 044的接地電位的變動的障礙。 (實施形態4) -32- (28) 1283471 圖16以及圖17是與本發明的其他實施形態（實施形態 4)之高頻功率模組有關的圖，圖16是切去高頻功率模組的 密封體的一部分的模式的俯視圖，圖1 7是高頻功率模組的 模式的剖面圖。 本實施形態4是藉由導電性的銲接線1 〇b電性連接成 爲共通的接地端子的調整片4與被製作成接地電位的導線7 ，也令導線7爲接地外部電極端子。在本實施形態4的半導 體裝置1因調整片4的背面由密封體2的背面（安裝面）露出 ，故可以調整片4當作接地用外部電極端子使用，並且經 由銲接線1 〇b連接於調整片4的導線7也能當作接地用外部 電極端子使用。 圖1 8爲本實施形態4的變形例。即在此變形例因半鈾 刻調整片4的背面側而變薄，故在單片封膠時樹脂也繞入 調整片4的背面側，故如圖1 8所示調整片4其背面也不由密 封體露出，完全埋沒於密封體2內。這種構造的情形因調 整片4經由銲接線1 Ob連接於導線7，可令此導線7當作接 地用外部電極端子使用。此外，使調整片埋沒到密封體內 的其他構造爲在調整片吊導線的途中更折彎成高階梯狀的 構造也可以。 在圖1 8所記載的構成中與經由銲接線1 Oa連接於調整 片4的接地電位供給用的電極端子9的數目比較，藉由減少 經由銲接線1 Ob與調整片連接的導線7的數目，因可減少 沿著密封體2的周圍排列的導線7的條數且可使裝置小型化 ，並且調整片4的背面被密封體2覆蓋，故當安裝本實施例 -33- (29) 1283471 中的半導體裝置1於配線基板上時，有半導體裝置1之下的 區域也可當作配置配線基板上的配線用的區域而利用的優 點。因此，在本實施例中有與半導體裝置1的小型化一起 可提高配線基板上的安裝密度的優點。 (實施形態5) 圖19〜圖30是表示本發明之其他實施形態（實施形態 5)的高頻功率模組（半導體裝置）。本實施形態5的高頻功 率模組，基本上與實施形態1的高頻功率模組相同。 本實施形態5的高頻功率模組1，如圖3 0所示，爲組裝 於雙帶構成（GSM通訊，DCS通訊及 PCS通訊）的無線 通訊裝置（行動電話機等的攜帶用無線機器）來使用。圖 30是大致對應於圖12，顯示由天線20至基帶晶片22的送· 受訊系的電路構成。在本實施形態5中，一對相位呈反相 的互補訊號會從連接於天線開關2 1 (連接天線20 )的帶通 濾波器23輸出，且此互補訊號會被輸入2輸入· 2輸出構成 的低雜訊放大器 （LNA)24，LNA24的輸出訊號會依次在 各電路部被處理，而傳至基帶晶片22或送 受訊系切換開 關36 〇 基本上圖3 0與圖12的不同點是在於圖30中，爲了顯示 訊號爲根據互補訊號處理者，而將連結各電路部的結線形 成2條，以及從90度移相轉換器40至混頻器26的輸出訊號 線亦形成2條。 本實施形態5的高頻功率模組1，如圖1 9〜圖22所示， -34- (30) 1283471 是在密封體（樹脂密封體）2的背面露出導線7的一面（下面 :安裝面7a)之無導線型半導體裝置，且形成由四角形狀的 4邊分別使導線7突出的QFN構造。晶片搭載部（調整片 )4，調整片吊導線6及導線7，是藉由沖壓或蝕刻等來對具 有一定厚度（例如〇.2mm左右）的一片金屬板（例如銅板）進 行圖案形成而成者。並且，導線7或調整片吊導線6的下面 (背面）會被部分地蝕刻一定厚度（例如〇. 1 mm左右）而形成 較薄。而且，導線的寬度，在第1部分 7c例如形成0.2腿 程度，在第2部分7d例如形成0.15 nun程度。其結果，搭載 半導體晶片3的晶片搭載部4的上面，導線7的上面及調整 片吊導線6的上面會形成位於同一平面上的構造，且晶片 搭載部4的下面會露出於樹脂密封體2的下面，導線7及調 整片吊導線6的一部份會露出。 樹脂密封體2是形成具有上面，及對向於該上面的背 面（下面），以及夾在前述上面及背面的側面之偏平矩形 的構造。又，具有沿著樹脂密封體2的周圍而設於樹脂密 封體2的内外之複數條的導線7。高頻功率模組1的外形尺 寸是與實施形態1相同。 如圖22所示，晶片搭載部4是位於複數條導線7所圍繞 的領域，且在此晶片搭載部4的上面，藉由接著劑5而固定 有半導體晶片3。半導體晶片3的平面形狀是形成四角形狀 ，且在其主面上具有複數個電極端子9，及分別藉由複數 個半導體元件而構成的複數個電路部。 半導體晶片3是被固定於沿著晶片搭載部（調整片）4 -35- (31) 1283471 的周邊而設置的細縫3 7所圍繞的四角形狀的領域上。晶片 搭載部4是被固定於接地電位。並且，晶片搭載部4與半導 體晶片3的預定電極端子9(接地電位用電極端子）是以導電 性的銲接線1 〇來予以連接，但此銲接線1 〇，亦即朝下接 合銲接線l〇a會被連接於細縫37外側的晶片搭載部分。由 於在細縫3 7外側的晶片搭載部分連接有朝下接合銲接線 1 〇a，因此細縫3 7外側的晶片搭載部分不會被流出的接著 劑5所汚染，而使得朝下接合銲接線1 〇a的連接性會變佳 。而且，藉由細縫3 7的存在，形成樹脂密封體2的樹脂會 進入細縫3 7内，而使得晶片搭載部4與樹脂密封體2的接合 強度也會提高，進而提升封裝性。又，藉由細縫3 7的存在 ，可提高安裝加熱時的耐熱性，以及防止朝下接合之調整 片接合部的銲接線剥離。 半導體晶片3的複數個電路部包含具有一對輸入的差 動放大器（差動放大電路部）。如圖25所示，此差動放大 電路會構成低雜訊放大器 （LNA)24。如圖25所示，圍繞3 個LNA的特定電路部11是在半導體晶片中，自其他電路 部絕緣分離的領域中形成各LNA。並且，各LNA的接地 電位會形成共通。此部分的構成是與實施形態1相同。 LNA24是供以放大攜帶用無線機器中經由天線而被轉 換的電氣訊號之電路部。由於構成本實施形態5的各個 LNA24是構成差動放大器，因此具有2個輸入配線用的電 極端子9。爲了維持差動放大電路部之輸入訊號的對稱性 ，連接於2個電極端子9的銲接線1 0長度是形成相同長度。 -36- (32) 1283471 並且，在連接2個電極端子9與對應的導線7之銲接線10的 兩側配置有接地用的銲接線1 0，且對訊號線施以電磁屏壁 ，而使能夠不產生串擾。 其次，針對差動放大電路部的輸入配線（訊號線）來 進行說明（更包含導線7的圖案等）。半導體晶片3的複數 個電極端子9，如圖23(a)所示，是包含對應於差動放大電 路部的一對輸入之第1電極端子9a及第 2電極端子9b。此 第1電極端子9a及第2電極端子9b是沿著半導體晶片3的一 邊而彼此隣接配置。並且，在第1電極端子9a及第2電極 端子9b中會被輸入一對相位不同（形成反相）的互補訊號。 爲了取得輸入訊號（互補訊號）的同時輸入性（對稱性）， 而使連接於第1電極端子9a及第2電極端子9b的銲接線10 的長度形成相同。 爲了使銲接線1 〇的長度形成相同，而改變導線7的平 面圖案，使與預定的電極端子9的距離形成相同。 在此，針對晶片搭載部4，導線7及調整片吊導線6的 関係來進行説明。如圖1 9所示，複數條導線7是由：在樹 脂密封體2的背面露出背面（下面）的第1部分7c，及從第1 部分7c往晶片搭載部4延伸至内側的第2部分7d所構成， 且第2部分7d的下面會藉由鈾刻而去除一定厚度。其結果 ，導線7的第2部分7d與第1部分7c相較之下，厚度會形成 較薄，且第2部分7d的全體會被覆蓋於樹脂密封體2内。 並且，因爲調整片吊導線6的途中部分的下面也會與前述 第2部分7d同樣地被蝕刻成預定厚度，所以在傳遞模塑法 -37- (33) 1283471 時所被鈾刻的部份樹脂會進入，因此在樹脂密封體2的背 面，調整片吊導線6只會部份地露出。並且，導線7的第1 部分7c會以能夠自樹脂密封體2的側面（周面）露出之方 式來突出於樹脂密封體2的周圍。此突出長度爲0.1mm程 度以下。 由於導線7的第2部分7d會埋入樹脂密封體2内，且第 2部分7d的端部（銲接線連接部）與晶片搭載部4的外周部 之間介在絕緣性樹脂，因此可使第2部分7d的端接近晶片 搭載部4。 亦即，由於導線7的第2部分7d不會露出於樹脂密封 體2的背面，而是形成延伸於樹脂密封體 2内的構造，因 此如圖29所示，在將高頻功率模組1安裝於安裝基板80時 ，經由銲錫83來將導線7及晶片搭載部4固定於安裝基板80 的銲墊81或固定部82時，由於可不考量固定導線7及銲墊 81的銲錫83與在固定部82固定晶片搭載部4的銲錫 83會 接触或接近（產生電氣短路的程度），因此可使第2部分 7d的端部接近晶片搭載部4的外周部。 如此一來，可藉由使導線7的第2部分7d埋入樹脂密 封體2内，來獨立決定前述第2部分7d的圖案，亦即有別 於形成外部電極的部分（第1部分7c)的形狀。 因此，爲了取得輸入訊號（互補訊號）的對稱性，可 以連接於第1電極端子9a及第2電極端子9b的銲接線10長 度能夠形成相同之方式來決定導線7(第1部分7c及第2部分 7 d)的圖案。就本實施形態5而言，第1電極端子9 a是比第2 -38- (34) 1283471 電極端子9b還要靠近半導體晶片3的一個角部，且電性連 接於第1電極端子9a的導線7的第2部分7d的端部是比電性 連接於第2電極端子9b的導線7的第2部分7d的端部還要延 伸至接近半導體晶片3的一邊（參照圖2 3 ( a))。並且，連 接第1電極端子9a與導線7的第2部份7d之導電性銲接線1〇 的長度與連接第2電極端子9b及導線7的第2部份7d之導電 性銲接線1 〇的長度會形成L 0，幾乎形成相同的長度。 另一方面，在未具有第2部分7d之圖23(b)所示的導線 7時，由於連接電極端子9a，9b (與導線7隣接）的導電性 銲接線1 〇的長度會分別形成L 1，L 2，亦即比前述L 0還 要長，因此電感會變大，而造成高頻特性會劣化。 又，由於LI與L2的長度不同，因此電感的差異會變 大，而造成輸入訊號的對稱性會劣化。 例如，銲接線爲使用直径25微米的Au銲接線時，若 動作頻帶爲GHz，則銲接線長只要差異〇.5mm，便會產生 0.5 nH的電感差異，這將會明顯地影響互補輸入訊號的對 稱性。 又，就QFN的外形規格而言，由於配置於樹脂密封 體2的背面周圍的導線7會形成外部電極端子，因此必須以 預定的間距來平行配置。 又，就本實施形態5的情況而言，如圖23 (a)所示’由 於導線7是由：在樹脂密封體2的背面露出下面的第上部分 7c，及由此第1部分7c延伸，且於埋入樹脂密封體2内的 狀態下延伸的第2部分7d所構成，因此可使第2部分7d延 -39- (35) 1283471 伸於自由的方向，且可使隣接的導線彼此分別延伸於所期 望的方向，在與導線7隣接的電極端子9間，亦可使銲接線 1 〇的長度大致形成相同（L 0)。其結果，可使連接第1電極 端子9 a與導線7之銲接線1 0的長度和連接第2電極端子9b 與導線7之銲接線1 0的長度形成相同，進而能夠使各銲接 線1 0的電感形成相同。 又，如前述，由於導線7的第2部分7d是位於樹脂密 封體2的内部，而不露出於樹脂密封體2的背面，因此可使 延伸於自由的方向。亦即，如圖24(a)所示，由於可使第2 部分7 d的延伸方向與銲接線1 0的延伸方向一致，且使銲 接線10位於導線7前端的寬度内，因此可使銲接線1〇的連 接部分的長度形成較長（圖示f)。 圖24(b)是表示僅以第1部分7c來形成導線7時的情況 。由於第1部分7c是在樹脂密封體2的背面構成外部電極 端子，因此各外部電極端子會以預定的間隔來平行配列。 其結果，如圖24(b )所示，對外部電極端子之銲接線的交 差角度Θ會隨著外部電極端子靠近四角形狀樹脂密封體2 的角落而變大，而使得銲接線1 〇會偏離導線 7的幅員， 形成交叉於導線7的側縁之形狀，因此對銲接線1 〇的導線7 之連接長度會形成h，亦即形成比連接長度f還要短。 又，如本實施形態5所示，亦即如圖24(a)所示，可藉 由使第2部分7d的延伸方向與銲接線10的拉伸方向一致， 來拉長導線7與銲接線10的連接長度（f)，進而能夠提高銲 接線的連接強度及銲接線的連接（打線接合）信頼性。 -40- (36) 1283471 又’輸入訊號的對稱性在處理高頻訊號的RF VC 044 中也是同樣重要的。就本實施形態5而言，如圖2 5所示， 延伸於兩個RFVC 044之間的訊號線，亦即兩條的銲接線 1 0也會形成相同的銲接線長度。並且，兩條的訊號線也會 藉由兩側的接地配線來形成電磁屏壁，而使不會產生串擾 〇 圖2 6是表示高頻功率模組的製造部份平面圖，亦即以 焊接線1 0來連接固定於導線架1 3的半導體晶片1 3的電極端 子9與導電7的狀態之一部份的導線架。由於本實施形態5 的高頻功率模組1的製造方法與實施形態1相同，因此省略 其説明。 就本實施形態5而言，如圖2 7的模式擴大剖面圖所示 ，在晶片搭載部4的上面，會藉由接著劑5而搭載有半導體 晶片3。半導體晶片3具有：第1半導體基板8 5，及形成於 第1半導體基板8 5表面的絕緣層8 6，以及形成於絕緣層8 6 上的第2半導體基板87，且複數個電極端子9會被形成於第 2半導體基板87的主面，複數個電路部會被形成於第2半導 體基板87，半導體晶片3的第1半導體基板85的背面會經由 導電性的接著劑5來電性連接於晶片搭載部4。 第1半導體基板85爲P型矽基板，第2半導體基板8 7爲 N型矽基板，兩者是形成以絕緣層86而貼合的 SOI構造 (silicon on insulator)。並且，半導體晶片3上面的複數個 電極端子9是分別構成訊號用電極端子，電源電位用電極 端子，及基準電源電位用電極端子。又，連接晶片搭載部 -41 - (37) 1283471 4與半導體晶片3的電極端子9之銲接線10爲朝下接合銲接 線l〇a，供以將晶片搭載部4固定於接地電位或負電位。在 將晶片搭載部4固定於負電位時，第1半導體基板8 5會被固 定於負電位，其結果，空乏層會延伸至第1半導體基板85 因此，可減少形成於第2半導體基板87的複數個電路 部中所被附加的寄生電容，進而具有謀求電路高速化的效 果。 並且，在第2半導體基板87中設有多數個下底會到達 絕緣層8 6的隔離溝。而且，在此隔離溝中充塡有絕緣體8 9 ，且由隔離溝所圍繞的領域會形成電性獨立的島。此外， 在各隔離溝所圍繞的第2半導體基板87的全體表面或一部 份形成有預定雜質濃度的N型及P型的半導體層（N，P)， 以及形成有含預定的pn接合的半導體元件。另外，在含 各半導體元件的第2半導體基板的表面上依次形成有氧化 矽膜等的絕緣層INS 1，INS2或氧化鋁或銅等的金屬配線 層，以及連接上下配線層的導體Ml〜M4，且如圖27所示 ，以最上層的配線M4來形成複數個電極端子9。 圖2 8是表示圖27所示之晶片的詳細構造模式剖面圖。 就半導體元件而言，由左而右，分別表示NPN縱型電晶 體（NPN Trs)，PNP縱型電晶體（V-PNP Trs)，P通道型 MOS電晶體（PMOS)，N通道型MOS電晶體（NM0S)，MOS 電容，電阻（多晶矽電阻）。並且，可藉由組合複數個如此 的半導體元件來形成圖30所示的高頻功率模組（半導體裝 -42- (38) 1283471 置）1。 此外，在製造如此的高頻功率模組1時，是在準備第1 半導體基板之後，隔著絕緣層86來貼合第2半導體基板87 ，然後，在使第2半導體基板87形成預定的厚度之後，以 預定的厚度來選擇性地蝕刻除去第2半導體基板87，而選 擇性地重複形成所望的半導體層，形成各半導體元件，且 形成隔離溝與絕緣體8 9，而形成配線構造，最後縱橫切斷 第1半導體基板8 5，而形成半導體晶片3。 本實施形態5的高頻功率模組1是處理高頻訊號的低雜 訊放大器（LNA)24及RFVC044爲形成2輸入2輸出構成，且 爲了維持2輸入訊號的對稱性，而使2輸入的銲接線1 〇的長 度形成相同。並且，構成訊號線的銲接線1 〇的長度可藉由 連接於半導體晶片3的電極端子9與導線7的第2部分7d的 端部分來縮短銲接線的長度，進而縮小銲接線電感。藉此 ，可提升高頻特性（DC偏移小）。 換言之，在本實施形態5中，GSM DCS PCS通訊 用的3個低雜訊放大器（LNA)24是以圖33(b)所示2輸入方式 的差動低雜訊放大器（差動放大器）來構成。亦即，實施 形態5的各低雜訊放大器（LNA)24是由輸入彼此相位呈反 相的訊號（互補訊號）之兩個的單位放大器所構成。因此 ，即使90度移相轉換器40的輸出訊號洩漏至LNA輸入線 ，還是會因爲輸入互補訊號，所以同相成分會被消除，而 不會在LNA24被放大，可縮小DC偏移。其結果，在發送 頻帶較高的通訊方式中，具有防止DC偏移特性劣化的効 -43- (39) 1283471 果。 又，本實施形態5的高頻功率模組1具有DC偏移小， 且可防止增益降低的効果。 (實施形態6) 圖3 1是表示本發明的其他實施形態（實施形態6)，亦 即支持半導體晶片的調整片比半導體晶片還要小的構成（ 小調整片構成）之尚頻功率模組的模式剖面圖。圖3 2是表 示使用於本實施形態6的高頻功率模組的製造之小調整片 構成的導線架的部份模式平面圖。 本實施形態6的高頻功率模組1是在實施形態5的高頻 功率模組1中，使晶片搭載部4比半導體晶片3還要小，亦 即形成小調整片構成，且使未圖示晶片搭載部4的調整片 吊導線6在途中部分彎曲成一段階梯狀，而使晶片搭載部4 的下面要比導線7的第1部分7c的下面來得高，形成埋入 樹脂封密封體2内的構造。亦即，本實施形態6的特徴晶片 搭載部4與導線7的第1部分7c附有段差，晶片搭載部4是 位於樹脂密封體2内。藉此，當銲接線接合部的正下方未 錫銲而搭載於安裝基板時，不會受到來自基板的應力影響 (溫度變化時），具有提高連接可靠度的效果。 如圖3 1所示，在連接半導體晶片3與導線7的銲接線1 0 中，如兩點虛線所示，與銲接線1 0的導線7連接的位置， 並非是連接於導線7的第1部分7c，而是藉由連接於導線7 的第2部分7d的端部分來縮短銲接線的長度，亦即可縮短 -44- (40) 1283471 圖示k的部份。 又’本實施形態6的高頻功率模組1亦具備實施形態1 所具有的一部份効果。如圖32所示，可藉由使調整片（晶 片搭載部）4形成比半導體晶片3還要小的構造來提高導線 架的泛用性，進而能夠降低高頻功率模組1的製造成本。 圖3 3是表示小調整片構成的其他幾個變形例之高頻功 率模組的模式剖面圖。圖33(a)是表示由導線7的第1部分 7c彎曲後延伸第2部分7d，而使第2部分7d位於樹脂密封 體2内的構造。這是在導線架形成的階段中，藉由使導線7 及調整片吊導線6在途中部分彎曲成一段階梯狀而形成者 ，在導線7中可藉此彎曲處理來形成由第1部分7 c彎曲而 延伸的第2部分7d，且可藉由調整片吊導線6的彎曲來使晶 片搭載部4埋入樹脂密封體2内。由於此構造不必對導線或 晶片搭載部4及調整片吊導線6進行選擇性的蝕刻處理，因 此可降低高頻功率模組1的製造成本。 圖3 3(b)是表示不使調整片吊導線6彎曲’而僅使導線 7彎曲，而具有由第1部分7c彎曲延伸的第2部分7d之構造 者。就此例而言，由於是形成使晶片搭載部4露出於樹脂 密封體2的下面之構造，因此來自晶片搭載部4下面的放熱 効果會増大。藉此，搭載於晶片搭載部4的半導體兀件 的放熱性佳，可進行安定的動作。 圖3 3(c)是表示在實施形態5的高頻功率模組1中，使 晶片搭載部4形成比半導體晶片3還要小的調整片構造，可 提高導線架的泛用性，進而能夠降低高頻功率模組1的製 -45 - (41) 1283471 造成本。 圖3 3 (d)是表示在實施形態5的高頻功率模組1中，使 晶片搭蔵部4形成比半導體晶片3還要小的調整片，且與導 線7的第2部分7d同樣地對晶片搭載部4的下面進行蝕刻’ 而使形成較薄之一例。 由於爲小調整片構成，因此可提高製造中所使用之導 線架的泛用性，進而能夠降低高頻功率模組1的製造成本 〇 以上根據發明的實施形態具體地說明了由本發明者所 創作的發明，惟本發明並非限定於前述發明的實施形態， 當然在不脫離其要旨的範圍可進行種種的變更。 在前述實施形態對於共通化或分離的電源電位雖然僅 記載關於接地電位，惟本發明的適用範圍並非僅限於接地 電位及與接地電位相關的構成，在適用本發明上著眼於適 當的電源電位（第一電位）例如藉由進行電極的共通化可減 少導線7的數目的電源電位，對供給該電源電位用的電極 端子9或導線7的構成，適用本發明也可以。 在前述實施形態雖然說明關於適用本發明於QFN型 的半導體裝置的製造的例子，但是對於例如SON型半導 體裝置的製造也同樣可適用本發明，可具有同樣的功效。 再者，本發明不限定於非導線型半導體裝置，例如對於沿 著密封體2的周圍折彎成鷗翼形狀的導線突出的稱爲QFP( 四邊扁平封裝，Quad Flat Package)或SOP(小外型封裝， Small Outline Package)的半導體裝置也一樣可適用，惟與 -46- (42) 1283471 前述Q F P或S Ο P比較，採用密封體2的周圍中的導線的突 出量小的QFN型的構造在達成裝置的小型化上更佳。 【發明效果】 如果簡單地說明藉由在本案中所揭示的發明之中代表 的發明所獲得的功效的話，如以下所示。 (1 )、可提供不易引起串擾的朝下接合構造的半導體 裝置。 (2) 、可提供低雜訊放大器或RFVCO等的特定電路部 中的接地電位不易受到剩餘的電路部的接地電位的影響， 連結單片地形成低雜訊放大器、混頻器、VC0、合成器、 IQ調變器/解調器、分頻器、直交調變器等各電路部的半 導體元件的高頻功率模組。 (3) 、可提供低雜訊放大器或RFVCO等的特定電路部 中的接地電位不易受到剩餘的電路部的接地電位的影響， 連結單片地形成低雜訊放大器、混頻器、VC0、合成器、 IQ調變器/解調器、分頻器、直交調變器等各電路部的半 導體元件的朝下接合構造且非導線型的高頻功率模組。 (4) 、可提供低雜訊放大器或RFVCO等的特定電路部 中的接地電位不易受到剩餘的電路部的接地電位的影響， 連結單片地形成低雜訊放大器、混頻器、VCO、合成器、 IQ調變器/解調器、分頻器、直交調變器等各電路部的半 導體元件的小型 '輕量化的高頻功率模組。 (5) 、可提供雜訊少的良好的通話爲可能的無線通訊 -47- (43) 1283471 裝置。 (6) 、可提供雜訊少的良好的通話爲可能的可應付複 數個通訊方式的無線通訊裝置。 (7) 如以上所述，本發明的半導體裝置可使用於行動 電話機等的無線通訊裝置。特別是在通訊系統爲複數系統 的行動電話中，並非是將處理低雜訊放大器之類的輸入訊 號爲極微弱的訊號之電路部的接地電極端子連接於形成共 通接地電位的調整片，而是連接於完全獨立的導線，因此 在一系統的通訊系統使用中，不會在與其他系統的通訊系 統之間產生串擾，而能夠提供一種通話良好的高頻功率模 組。 (8) 由於可以構成外部電極端子的第1部分及延伸於樹 脂密封體内的第2部份來形成導線，而使能夠自由地選擇 第2部分的圖案，因此可選擇儘可能縮短連接半導體晶片 的電極端子與導線之銲接線的長度之導線圖案。藉此，將 能夠謀求銲接線電感的降低。 (9) 在具有差動放大電路部等的2輸入構成電路部的半 導體裝置中，可使連接於2輸入用電極端子的銲接線的長 度形成同樣的長度，而取得輸入訊號的對稱性。因此，當 無線通訊裝置的低雜訊放大器 （LNA)或RFVCO爲2輸入 構成電路部時，可在各個的電路部中取得輸入訊號的對稱 性，進而能夠提高頻特性及防止增益降低。 【圖式簡單說明】 -48- (44) 1283471 圖1是切去本發明的一實施形態（實施形態1)之高頻功 率模組的密封體的一部分的模式的俯視圖。 圖2是本實施形態1的高頻功率模組的剖面圖。 圖3是本實施形態1的高頻功率模組的模式的俯視圖。 圖4是區塊地顯示連結到本實施形態1的高頻功率模組 的半導體晶片中的電路構成的模式的俯視圖。 圖5是顯示本實施形態1的高頻功率模組中的外部電極 端子與半導體晶片的低雜訊放大器或合成器等的各電路部 的接線狀態的模式的俯視圖。 圖6是顯示本實施形態1的高頻功率模組的製造方法的 流程圖。 圖7是在本實施形態1的高頻功率模組的製造中所使用 的導線架的俯視圖。 圖8是顯示前述導線架中的單位導線架圖案的模式的 俯視圖。 圖9是搭載半導體晶片的前述導線架的模式的剖面圖 〇 圖1 〇是顯示打線接合終了的前述導線架的模式的剖面 圖。 圖1 1是顯示形成有密封體的前述導線架的模式的剖面 圖。 圖1 2是顯示連結有本實施形態1的高頻功率模組的攜 帶電話機的電路構成的區塊圖。 圖1 3是顯示本實施形態1的高頻功率模組的攜帶電話 -49- (45) 1283471 機中的安裝狀態的模式的剖面圖。 圖1 4是切去本發明的其他實施形態（實施形態2)之高 頻功率模組的密封體的一部分的模式的俯視圖。 圖1 5是切去本發明的其他實施形態（實施形態3)之高 頻功率模組的密封體的一部分的模式的俯視圖。 圖16是切去本發明的其他實施形態（實施形態4)之高 頻功率模組的密封體的一部分的模式的俯視圖。 圖1 7是本實施形態4的高頻功率模組的模式的剖面圖 〇 圖1 8是顯示本實施形態4的高頻功率模組的變形例的 模式的剖面圖。 圖19是顯示本發明的其他實施形態（實施形態5)之高 頻功率模組的模式的剖面圖。 圖2 0是顯示本實施形態5之高頻功率模組的俯視圖。 圖2 1是顯示本實施形態5之高頻功率模組的底面圖。 圖2 2是切去本實施形態5之高頻功率模組的密封體的 一部分的模式的俯視圖。 圖23是顯示使高頻功率模組的差動放大電路部之一對 的輸入部的銲接線電感一致之本實施形態5的導線及銲接 線的圖案例，及銲接線電感未一致之導線及銲接線的圖案 例的模式圖。 圖24是在於說明圖23所示之導線圖案的不同而造成銲 接線的連接可靠度不同的模式圖。 圖2 5是顯示本實施形態5之高頻功率模組的外部電極 -50- (46) 1283471 端子與半導體晶片的低雜訊放大器或合成器等的各電路部 的結線狀態的模式的俯視圖。 圖2 6是顯示在本實施形態5之高頻功率模組的製造中 ，以銲接線來連接固定於導線架之半導體晶片的電極與導 線的狀態的一部份的導線架的俯視圖。 圖2 7是顯示本實施形態5之高頻功率模組的半導體晶 片內部構成及導線的連接狀態的模式的擴大剖面圖。 圖2 8是顯示本實施形態5之高頻功率模組的半導體晶 片內部構成的模式的擴大剖面圖。 圖2 9是顯示本實施形態5之高頻功率模組的安裝狀態 的模式的剖面圖。 圖3 0是顯示裝入本實施形態5之高頻功率模組的行動 電話的電路構成的區塊圖。 圖3 1是顯示本發明的其他實施形態（實施形態6)之支 持半導體晶片的調整片比半導體晶片還要小的構成（小調 整片構成）之高頻功率模組的模式的剖面圖。 圖3 2是顯示使用於本實施形態6之高頻功率模組的製 造之小調整片構成的導線架的一部份之模式的俯視圖。 圖3 3是顯示上述小調整片構成的其他幾個變形例之高 頻功率模組的模式的剖面圖。 圖34是顯示行動電話之含2輸入差動放大電路部 (LNA)的區塊圖，及含1輸入差動放大電路部（LNA)的區塊 圖。 -51 - (47) (47)1283471 【符號說明】 1：半導體裝置（高頻功率模組） 2:密封體（樹脂封裝體） 2a :斜面 2 b :傾斜面 3 :半導體晶片 4：調整片（晶片搭載部） 5 :接著劑 6 :調整片吊導線 7 :導線 7a:安裝面 7c:第1部份 7d:第2部份 9 :電極端子 9 a :第1電極端子 9b:第2電極端子 1 0 :銲接線 l〇a:朝下接合銲接線 1 0 b :銲接線 11:特定電路部 1 3 :導線架 1 4 :單位導線架圖案 1 5 a〜1 5 c :導孔 1 6 :頂桿孔 -52- (48) (48)1283471 1 7 :頂桿孔 1 8 :框部 2 0 :天線 2 1 :天線開關 22:基帶晶片 23:帶通濾波器 24:低雜訊放大器 25:可變放大器 2 6 :混頻器Further, it is disclosed in Japanese Patent Laid-Open No. Hei 11-186921 (published on July 9, 1997), which is incorporated in PCN (Personal Communication Network: Personal Communication Network: DCS-1800), PCS (Personal Communication Service, Personal Communications Service: DCS). - 1 900) and multi-band mobile communication devices for mobile telephone systems such as GSM (2) 1283471. Further, the front end of the portable telephone can be modularized in the high-frequency analog signal processing circuit for GSM. For example, there are two- or three-band RF (Radio Frequency) power modules for GSM using a MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor). The dual-band mode is to process signals from two communication systems, such as GSM and DCS (Digital Cellular System) 1800. The three-band mode is to process signals from three communication systems, such as GSM, DCS 1 800, and PCS 1 900. The GSM link has GSM900 or GSM8 50. Moreover, the high-frequency module is connected with a monolithic integrated LNA, a mixer, a PLL (Phase-Locked Loop) synthesizer, and a PGA with auto calibration. Planning a program's gain amplifier, Programmable Gain Amplifier), IQ modulator/demodulator, offset PLL, VCO (Voltage Controlled Oscillator), and other single-chip semiconductor components. Japanese Patent Publication No. 7623 discloses a semiconductor integrated circuit for receiving and receiving a dual band system. A differential noise amplifier (consisting of two unit amplifiers having phases inverted in phase with each other) provided in the dual-band transmission semiconductor integrated circuit has a pair of input terminals and a pair of output terminals The ground pins of the pair of amplifiers of the differential amplifier are formed adjacent to each other, and the input pins and the ground pins of the same amplifier are formed adjacent to each other. As a result, the signals of adjacent pins are inverted, using the (3) 1283471 transformer coupling between the pins to reduce the impedance of the transistor emitter and improve the gain of the differential amplifier. On the other hand, portable telephones are required to be small and lightweight for the convenience of transportation. As a result, electronic components such as high-frequency power modules are also expected to be smaller and lighter. The semiconductor device has various forms depending on the package, and one of them is known in which the back surface (mounting surface) of the sealing body (package) of the insulating resin is exposed to the lead wire (external electrode terminal), and the wire length is not formed on the side surface of the sealing body. A long-lead non-lead semiconductor device. The non-conducting type semiconductor device has two sides on the opposite side of the back surface of the sealing body, and the SON (Small Outline Non-Leaded Package) which exposes the wires or the exposed QFN on the four sides of the back surface of the sealing body (Quad Flat Non-Leaded Package). A non-conducting type semiconductor device that does not cause wire bending is described in Japanese Laid-Open Patent Publication No. 2001-313363. The resin-sealed semiconductor device described in this document has a bonding pad (Island) that is connected to a wire bonding portion of a die pad and a wire of a semiconductor wafer, and the semiconductor wafer is fixed to the crystal. Each electrode terminal of the semiconductor wafer on the pellet is a structure that is connected to a wire bonding portion of a wire or a pad. A gap portion is provided between the die pad and the wire bonding portion to prevent the wire from being detached or cut off due to thermal stress. This configuration can connect the pad to a printed substrate or the like as a ground lead by connecting the ground terminal of the semiconductor wafer and the pad by a bonding wire. Japanese Laid-Open Patent Publication No. Hei. No. Hei. No. Hei. No. Hei. No. 5, No. 5, No. 494 discloses a gull-wing type high-frequency device (Device) used for a cellular phone in which a semiconductor device is mounted (4) 1283471 is grounded. In this technique, the electrode of the semiconductor element and the semiconductor element mounting portion (down bonding) are connected by a bonding wire, except that the electrode and the wire of the semiconductor element are connected by a bonding wire. Since the semiconductor element mounting portion is larger than the semiconductor element, the semiconductor element mounting portion protrudes in the peripheral portion of the outer semiconductor element mounting portion of the semiconductor element in the mounted state, and the bonding wire is connected to the portion. SUMMARY OF THE INVENTION [Problems to be Solved by the Invention] The present applicant reviewed the connection of a high-frequency power module to a non-conducting type semiconductor device, and electrically connected via a bonding wire in order to stabilize the ground potential. One--______________________ - One ^^^ The grounding terminal of each circuit part of the high-frequency power module is used in the method of the adjustment piece. By using the downward bonding, the number of external electrode terminals can be reduced, and the size of the package can be reduced, and finally, the size of the semiconductor device can be reduced. ____, -. . . . . -^--------- However, the following problems have been identified in high-frequency power modules for wireless communication systems (communication systems). The signal captured by the antenna at the receiving end of the portable telephone is amplified by a low noise amplifier (LNA), but the input signal is extremely weak. Therefore, in particular, each circuit unit changes the ground potential of the potential of the tab of the common terminal in accordance with the operation of the oscillator that operates periodically, and as a result of this, crosstalk occurs between a part of the circuit unit and the output fluctuation cannot be performed. Good tongue. -9 - (5) 1283471 In particular, the distortion of the signal waveform caused by the variation of the induced current or the ground potential caused by the crosstalk between the wires is output by the communication system, and the output signal enters the in-use communication system to become noise. The circuit portion where the fluctuation of the ground potential and the influence of the crosstalk are easily received is a high-frequency RFVCO (high-frequency voltage-controlled oscillator) or the like other than the low noise amplifier (LNA). Therefore, the inventors of the present invention have attempted to connect a low-noise amplifier or an RFVCO to a tab of a common terminal among the electrode terminals of the semiconductor element without a bonding wire, but to connect to a separate lead terminal (external electrode) via a bonding wire. The terminal) reduces the influence of variations in the ground potential at the time of switching (ΟΝ/OFF) of another circuit unit, and completes the present invention. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a ground potential of a specific circuit portion formed in a circuit of a semiconductor element can be hardly affected by a ground potential of a remaining circuit portion in a semiconductor device having a downward bonding structure. Another object of the present invention is to provide a high-frequency power module in which a low-frequency amplifier or a circuit unit such as RFVCO is hardly affected by crosstalk caused by fluctuations in ground potentials of other circuit units in a high-frequency power module. Another object of the present invention is to provide a wireless communication device in which a good communication with less noise is possible in a wireless communication system. Another object of the present invention is to provide a wireless communication device in which a good communication with less noise is possible in a wireless communication system having a plurality of communication systems. On the other hand, the inventors conducted an analysis and review on a low noise amplifier (LNA: Differential Low Noise Amplifier) which inputs a two-input mode of a signal -10- (6) 1283471 (complementary signal) having opposite phases. 34(a) and (b) are circuit portions including a low noise amplifier (LNA) 100, a high frequency voltage controlled oscillator (RFVCO) 101, and a mixer 102, respectively, and FIG. 34(a) shows an input mode. The LNA, Fig. 34(b) is an LNA showing a 2-input method. Mixing with the mixer 102: processing the output signal of the low noise amplifier 1〇〇 after receiving the signal from the antenna, and the local oscillator (RFVCO: high frequency voltage controlled oscillator) 1〇1 In the circuit configuration of the signal, for the low noise amplifier composed of one input shown in Fig. 34(a), since the output frequency of the RFVCO101 is the same as the output frequency of the LNA100, if the output signal of the RFVCO101 leaks to the LNA input line It will be magnified to the LNA100 as it is, causing the DC offset to become larger. Here, as shown in FIG. 34(b), the LNA 100 is used as a differential low noise amplifier (differential amplifier: LNA), and the DC is reduced by inputting a signal (complementary signal) in which the phases are inverted in phase. Offset. That is, since the differential amplifier (differential amplifying circuit) 100 is constituted by two unit amplifiers having the same configuration, the input phase is inverted by two high-frequency signals (complementary signals) and differentially amplified, so the in-phase components are Canceled, so the DC offset can be reduced. However, when the transmission band is formed higher, the problem of the aforementioned DC offset cannot be fundamentally solved by using only the two-input method of inputting the complementary signal. In the case of the input wiring path for inputting the aforementioned complementary signal, the large-sized wire can be divided into a wire portion formed by a lead frame, and a welded wire portion to which the wire portion and the electrode of the semiconductor wafer are connected. -11 - (7) 1283471 For example, a wire portion formed of a metal plate such as copper has a large thickness and a width, and although the inductance difference is small when the length of the minute wire is several millimeters, the diameter is 20 A portion of the weld line of ~30 / zm is likely to have a large inductance difference depending on its length. This difference in the inductance of the soldering wiring results in a difference in the input time of the two complementary input signals, which detracts from the symmetry of the input signal. As a result, the gain is reduced in a high speed communication system. Therefore, another object of the present invention is to improve the symmetry of the input signal by simultaneously inputting the complementary signal into the circuit portion of the differential low noise amplifier. Further, another object of the present invention is to improve the characteristic direction (small DC offset) of a high frequency power module having a differential low noise amplifier. The above and other objects and novel features of the present invention will be apparent from the description and drawings. [Means for Solving the Problems] The foregoing and other objects and novel features of the present invention will be apparent from the description and appended claims. Among the inventions disclosed in the present invention, the following is a brief description of the representative invention. (1) The semiconductor device of the present invention, comprising: a sealing body made of an insulating resin; a plurality of wires disposed around the inside and the outside of the sealing body along the periphery of the sealing body; and a regulating piece having a main surface and a back surface -12- (8) 1283471 having a main surface and a back surface, the semiconductor wafer having a plurality of electrode terminals and a plurality of circuit portions each composed of a plurality of semiconductor elements; and connecting the plurality of electrode terminals a plurality of electrically conductive solder wires of the wire; a plurality of conductive solder wires (eg, non-conducting semiconductors) for supplying a plurality of electrode terminals to the plurality of electrode terminals and connecting the plurality of electrode terminals to the main surface of the tab The device is characterized in that: the back surface of the semiconductor wafer is fixed to the main surface of the tab, and the plurality of circuit portions include a first circuit portion (specific circuit portion) and a second circuit portion, and the plurality of electrode terminals have a first electrode terminal for inputting an external signal to the first circuit portion, and a first electrode for supplying the first potential (ground potential) to the first circuit portion An electrode terminal, a third electrode terminal connected to the second circuit portion, and a fourth electrode terminal for supplying the first potential to the second circuit portion, the plurality of wires including the first wire (signal wire), a second wire (signal wire), a third wire (grounding wire) disposed between the first wire and the second wire, wherein the first electrode terminal is connected to the first wire via a conductive bonding wire, The second electrode terminal is connected to the third wire via a conductive bonding wire, and the third electrode terminal is connected to the second wire 13-1283471 Ο) via a conductive bonding wire, and the fourth electrode terminal is via The conductive bonding wire is connected to the regulating piece that is commonly grounded, and the third wire is electrically separated from the adjusting piece to constitute the high frequency module. The first circuit portion is an amplifying circuit (low noise amplifier: LAN) for amplifying the first wire and an external signal input through the first electrode terminal, and the wireless signal is used to amplify the electrical converted via the antenna Signal circuit. The second circuit portion has at least a portion of a function of processing a signal amplified by the first circuit portion. Moreover, the high frequency power module allows a plurality of communication circuits to be formed corresponding to a plurality of communication methods. This high frequency power module is connected to the wireless communication device. According to the means of the above (1), (a), the electrode terminal of the semiconductor element is connected to the regulating piece (downward bonding) which is a common ground, in addition to being connected to the wire via the bonding wire. The ground electrode terminal (electrode terminal of the semiconductor element) of the low noise amplifier (specific circuit unit) that amplifies the weak signal is connected to the independent lead terminal (grounding conductor) without being connected to the tab, so it is connected to other circuits. The ground potential between the parts becomes independent, and the ground potential fluctuation is hard to occur when the power supply of the other circuit unit is switched. The output fluctuation of the low noise amplifier or the distortion of the signal waveform is hard to occur with fluctuations in the ground potential. Connecting to a wireless communication device makes it possible to have a good call with no output changes or distortion. -14- (10) 1283471 (b) In a high-frequency power module having a plurality of communication circuits, the common grounding of the tabs is accompanied by a change in the ground potential, and an induced current occurs in the unused communication circuit. The noise caused by the induced current enters the so-called crosstalk of the communication circuit in use (in operation), but in the high frequency power module of the present invention, since the low noise amplifier of each communication circuit is separated from the ground of other circuit parts, Therefore, it is possible to suppress variations in the output of the low noise amplifier or distortion of the signal waveform. As a result, in a wireless communication device having a plurality of communication circuits, it is also possible to make a good call with no output fluctuation or distortion. (c) Since the signal wiring from the electrode terminal of the low noise amplifier to the conductor via the bonding wire is provided with the ground wiring on both sides of the wiring, the crosstalk between the signal wiring can be reduced. (d) The high-frequency power module is a non-conducting type semiconductor device with a downward-facing structure, which is small, thin, and lightweight. Since the tab is exposed on the back surface of the sealing body, heat dissipation is good and stable operation is possible. Therefore, by connecting the high-frequency power modules, it is possible to provide a small, lightweight portable telephone with good call performance. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the entire drawings for explaining the embodiments of the invention, the same reference numerals will be given to the components having the same functions, and the repeated description thereof will be omitted. (Embodiment 1) -15- (11) 1283471 FIGS. 1 to 13 show a wireless connection between a semiconductor device (high-frequency power module) and a high-frequency power module according to an embodiment (Embodiment 1) of the present invention. A diagram related to the communication device. 1 to 5 are diagrams related to a high frequency power module, and FIGS. 6 to 11 are diagrams related to a method of manufacturing a high frequency power module, and FIGS. 12 and 13 are related to a wireless communication device. Figure. In the first embodiment, the QFN type in which the present invention is applied to the exposed tab and the tab suspension wire and the lead wire (external electrode terminal) connected to the tab is applied to the mounting surface of the back surface of the rectangular sealing body (package). An example of a semiconductor device. The semiconductor device 1 constitutes, for example, a high-frequency power module. The semiconductor device 1 of the QFN type has a sealing body (package) 2 formed of a flat rectangular insulating resin as shown in Figs. 1 and 2 . A semiconductor element (semiconductor wafer: wafer) 3 having a quadrangular shape is embedded in the inside of the sealing body 2. The semiconductor wafer 3 is fixed to the surface (main surface) of the tab of the quadrangular tab 4 by the adhesive 5 (see Fig. 2). As shown in Fig. 2, the back surface (bottom surface) of the sealing body 2 serves as a surface side (mounting surface) to be mounted. The back surface of the sealing body 2 has a structure in which the regulating piece 4 and the one side (mounting surface 7a) of the regulating piece hanging wire 6 and the lead wire (external electrode terminal) 7 of the regulating piece 4 are exposed. These tabs 4 and the tab suspension wires 6 and the wires 7 are formed in a lead frame of a metal (for example, copper) formed in a pattern by the semiconductor device 1, and then cut to form a lead frame. . Therefore, in the first embodiment, the thickness of the tab 4 and the tab suspension wires 6 and the wires 7 are the same. However, in the wire 7, since the inner end portion is formed to have a certain depth on the back surface of the -16-(12) 1283471 uranium, the lower side of the thin wire portion becomes a structure in which the resin constituting the sealing body 2 enters. Accordingly, the wire 7 is hard to be detached from the sealing body 2. The four corners of the tab 4 are supported by the thin tab suspension wires 6. These adjustment piece suspension wires 6 are located on the diagonal line of the square-shaped sealing body 2 such that the outer ends face the corner portions of the square-shaped sealing body 2. The sealing body 2 is a flat quadrangular body, and the corner portion (corner portion) is chamfered into a sloped surface 2a (see Fig. 1). The outer end of the adjustment piece suspension wire 6 protrudes only in this chamfered portion. Below 1mm. This protruding length is determined by the cutting mode of the punch (P r e s s) when the wire is cut off in the state of the lead frame, for example, 0 can be selected. Below 1 m m. Further, as shown in Fig. 1, at the periphery of the tab 4, the inner end surface of the pair of wires 7 of the tab 4 is arranged along the sides of the square-shaped sealing body 2 at a predetermined interval. The outer ends of the tab suspension wires 6 and the wires 7 extend to the periphery of the sealing body 2. That is, the wire 7 and the tab suspension wire 6 extend over the inside and outside of the sealing body 2. The projection length of the sealing body 2 of the wire 7 is determined by the cutting mode of the press machine when the wire of the lead frame is cut as in the case of the above-mentioned tab suspension wire 6, for example, only 0. 1mm or less. Further, the side surface of the sealing body 2 is an inclined surface 2b (see Fig. 2). The inclined surface 2 b is formed by one-side sealing on one side of the lead frame (Μ 1 1 d ) to form the sealing body 2, and when the sealing body 2 is taken out from the cavity of the sealing mold, the extraction is easy. See, the result is that the side of the cavity is the result of the inclined surface. In addition, FIG. 1 is a schematic view in which the upper portion of the sealing body 2 is cut off, and the regulating piece 4, the regulating piece hanging wire 6, the wire 7, the semiconductor wafer 3, and the like are seen. Further, as shown in Figs. 1 and 4, the electrode terminal 9 is disposed on the main surface of the exposed -17-(13) 1283471 of the semiconductor wafer 3. The electrode terminal 9 is substantially arranged at a predetermined pitch along each of the sides of the square in the main surface of the semiconductor wafer 3. This electrode terminal 9 is connected to the inner end side of the wire 7 via a conductive bonding wire 1 。. The tab 4 is formed substantially larger than the semiconductor wafer 3, has a semiconductor element fixing region at the center of its main surface, and has a bonding wire connection region on the outer side of the semiconductor element fixing region, that is, the peripheral portion of the tab 4. Further, the semiconductor wafer 3 is fixed to the semiconductor element fixing region. Further, a other end of the conductive bonding wire 10 connected to the electrode terminal 9 of the semiconductor wafer 3 is connected to the bonding wire connection region. In particular, the weld line 10 connected to the adjustment sheet 4 is referred to as a downward bonding weld line 10a. Since the wire bonding between the electrode terminal 9 and the wire 7 and the wire bonding between the electrode terminal 9 and the tab 4 are performed by the wire bonding device, the bonding wire 10 and the downward bonding bonding wire 1 〇a are the same material. . The purpose of the downward bonding structure is generally to achieve the commonality of the ground potential of each circuit portion in the semiconductor wafer by the tab. By making the tab a common ground terminal, by connecting the tab and a plurality of electrode terminals serving as the ground electrode terminal via the bonding wire, the number of wires (pins) of the external electrode terminals arranged along the circumference of the sealing body can be reduced. 'The size of the sealing body caused by the reduction in the number of wires can be reduced. This is related to the miniaturization of semiconductor devices. Further, in the semiconductor device 1 of the first embodiment, as shown in Fig. 3, between the respective wires 7 and the wires 7, and between the wires 7 and the tab suspension wires 6, there is a resin burr generated when the sealing body 2 is formed. This resin burr portion is produced in the manufacture of the semiconductor device 1 when one side of the lead frame is formed as a single-face seal '--18-(14) 1283471 into the sealed body 2. Although the unnecessary lead frame portion is cut after sealing, the resin burrs are also cut at the same time due to the cutting of the wire or the tab suspension wire at this time, so the outer edge of the resin burr becomes the edge or adjustment of the wire 7. Along with the edges of the sheet suspension wires 6, a portion of the resin burrs remain between the respective wires 7 and the wires 7 and between the wires 7 and the tab suspension wires 6. and,. In the first embodiment, the back surface of the sealing body 2 is recessed from the regulating piece 4, the regulating piece hanging wire 6, and the back surface (mounting surface) of the wire 7. In the single-piece sealant in the transfer molding, a resin sheet is placed between the upper and lower molds of the seal mold, and one side of the lead frame is contacted with the sheet to seal the sheet. The gap of the lead frame bites in, so that the back surface of the sealing body 2 becomes concave. Further, after the single-piece sealant of the transfer sealant is used, a plating film for surface mounting is formed on the surface of the lead frame. Therefore, the surface of the tab 4, the tab suspension wire 6, and the lead wire exposed on the back surface of the sealing body 2 of the semiconductor device 1 has a plating film although not shown. As described above, the mounting surface of the back surface of the wire 7 or the tab suspension wire 6 protrudes, and the offset structure of the back surface of the sealing body 2 is recessed by soldering when the semiconductor device 1 is mounted on the surface of the bonding wire substrate such as a mounting substrate. The area is specified, so the solder is well installed. Here, a method of manufacturing the semiconductor device 1 of the first embodiment will be described with reference to FIGS. 6 to 11. As shown in the flowchart of FIG. 6, the semiconductor device 1 is subjected to lead frame preparation (S101), wafer bonding (S102), wire bonding (S103), sealing (sealing: S104), plating treatment (S105). ), manufactured by cutting off each process of removing the unnecessary lead frame (S 106). -19- (15) 1283471 FIG. 7 is a plan view showing a mode of the lead frame 13 formed of a matrix used in the QFN type semiconductor device 1 according to the first embodiment. This lead frame 13 has its unit lead frame pattern I4 arranged in 20 rows in the X direction and four columns in the Y direction, and 80 semiconductor devices 1 can be manufactured from one lead frame I3. Guide holes 15a to 15c used for the conveyance or positioning of the lead frame 13 are disposed on both sides of the lead frame 13. Moreover, the runner is located on the left side of each column as it is being transferred. Therefore, since the runner hardening resin is torn off by the lead frame 13 by the protrusion of the Ejector pin, the jack hole 16 through which the ejector rod can pass is provided. Moreover, since the protrusion of the ejector rod is torn off by the lead frame 13 and the runner is diverged, the gate hardened by the gate which flows to the gate of the cavity hardens the resin, so that the ejector rod through which the ejector rod can pass is provided Hole 1 7. FIG. 8 is a plan view showing a part of the unit lead frame pattern 14. Since the unit lead frame pattern 14 is a pattern actually manufactured, there is a portion of the pattern diagram which is not necessarily identical to Fig. 1 or Fig. 2 and the like. The unit lead frame pattern 14 has a frame portion 18 having a rectangular frame shape. The tab suspension wire 6 is extended by the four corners of the frame portion 18 to form a pattern supporting the central tab 4. The plurality of wires 7 extend inwardly from the inner side of each side of the frame portion 18, and the inner ends thereof are close to the outer periphery of the tab 4. A plating film (not shown) for wafer bonding or wire bonding is disposed on the main surfaces of the tab 4 and the wires 7. Further, the front end side of the lead wire 7 is thinned by half-etching (see Fig. 2). Further, the lead wire 7 or the regulating piece 4 or the like may have a peripheral surface whose slope is wider than the width of the back surface, and the inverted trapezoidal cross section may be difficult to be extracted by the sealing body 2. This can also be fabricated by etching or stamping -20- (16) 1283471 (Press). Further, as shown in Fig. 8, in the main surface of the tab 4, the central quadrangular region becomes the semiconductor element mounting portion 4a (the region surrounded by the two-point chain frame), and the outer region thereof becomes the bonding wire connection region 4b. After preparing the lead frame 13 as shown in FIGS. 8 and 9, the semiconductor wafer 3 is fixed (wafer bonded) to the semiconductor element mounting portion 4a of the tab 4 of each unit lead frame pattern 14 by the adhesive 5 (S). 102). Next, wire bonding is performed as shown in FIG. 1A, and the electrode terminal of the semiconductor wafer 3 and the leading end of the wire 7 are connected by the conductive bonding wire 10, and the predetermined electrode terminal and the tab 4 are connected by the conductive bonding wire 1 〇. The weld line is connected to the area 4b (S103). Specifically, the welding line connecting the electrode terminal and the bonding wire connection region 4b of the tab 4 is bonded to the bonding wire 10a downward. For the welding line, for example, a gold wire is used. Next, a single-piece sealant using a conventional transfer sealer is formed, and a sealing body 2 made of an insulating resin is formed on the main surface of the lead frame 13 (S104). The sealing body 2 covers the semiconductor wafer 3, the wires 7, and the like on the main surface side of the lead frame 13. The portion indicated by the two-dot chain line frame in Fig. 8 is a region in which the sealing body 2 is formed. Next, the plating process is not shown (S105). As a result, a plating film (not shown) is formed on the back surface of the lead frame 13. This plating film is used as a bonding material for surface mounting of the semiconductor device 1, and is, for example, a solder plating film. Instead of the process for forming the plating film, a substance to which Pd plating is applied may be used in advance on the surface of the lead frame 13 in total. Further, in particular, when the lead frame I3 to which the Pd is plated is used, the plating process after the sealing can be omitted, the manufacturing process can be simplified, and the manufacturing cost can be reduced. -21 - (17) 1283471 Next, the unnecessary lead frame portion (SI 06) was cut and removed, and the semiconductor device 1 shown in Fig. 1 was fabricated. On the outside of the sealing body 2 of the two-point chain frame shown in Fig. 8, the wire 7 and the regulating piece hanging wire 6 are cut by a cutting die of a press machine (not shown). With the configuration of the cutting die, the wire 7 is cut and the wire hanger wire 6 is adjusted at a position slightly apart from the sealing body 2, and the distance of the sealing body 2 at a position slightly separated therefrom is, for example, 0. 1mm or less. The protruding length of the sealing body 2 from the wire 7 and the tab suspension wire 6 is short, preferably from a point of preventing jamming or the like. This protruding length is changed by the cutting die of the stamping machine at 0. More than 1mm can be freely chosen. Here, an example of the size of each part of the semiconductor device 1 is mentioned. The thickness of the lead frame (adjustment piece 4, adjusting piece hanging wire 6, wire 7) is 0. 2mm, the thickness of the wafer 3 is 0. 28mm, the thickness of the semiconductor device 1 is 1. 0mm, the width of the wire 7 is 0. 2mm, the length of the wire 7 is 〇. 5mm, the welding wire of the tab 4 is connected to the end of the wafer 3 at the connection position (dot). 0mm, and the interval between the tab 4 and the wire 7 is 0. 2mm. On the other hand, although this is one of the features of the present invention, a part of the circuit in the semiconductor wafer 3, that is, the ground of the specific circuit portion is taken out as a ground electrode terminal, and is connected to the wire via the bonding wire, and the remaining circuit portion Ground separation. The remaining circuit portions are connected to the common-adjusting tab via a bonding wire as needed, and are connected to the wires via a bonding wire as needed. Further, although the ground of the specific circuit portion and the ground of the other remaining circuit portions are not shown, the wiring in the semiconductor wafer 3 is also insulated by an interlayer insulating film or the like (0) - (18) 1283471 In the high-frequency power module according to the first embodiment, when all the circuit portions formed in a single semiconductor wafer are grounded and common, as described above, crosstalk occurs due to fluctuations in the ground potential. The output variation of the circuit section or the distortion of the signal waveform occurs. Further, in a high-frequency power module having a plurality of communication circuits such as a double band or a triple band, there is an induced current that is generated in a communication circuit that does not operate, and the induced current enters an action communication by noise. The top of the circuit. Therefore, the electrode terminal (ground electrode terminal) for grounding of the specific circuit portion of the first embodiment is not connected to the regulating piece, but is connected to an independent wire (grounding wire) via a bonding wire. In addition, there is a crosstalk between the input signal lines, so that the output fluctuation of each circuit portion or the distortion of the signal waveform occurs, especially in the external signal input wire from the antenna with a small input signal, it is necessary to avoid the The effect of crosstalk on adjacent wires. In the first embodiment, since the semiconductor device 1 is a three-band high-frequency power module for a cellular phone, the specific circuit portion is a low noise amplifier (LNA). Since it is a three-band, three low-noise amplifiers (LNAs) connected to the antenna are also configured. A single LNA becomes a specific circuit portion in the narrow sense of the present invention. That is, as shown in Fig. 5, the input signal wirings from the antennas of the respective LN A are two. Moreover, for the two signal wirings on the electromagnetic screen wall, between the two signal conductors and the other signal conductors, it is preferable to arrange the grounding conductors on both sides of the two signal conductors. If the input signal is wired to two, so that the differential input is formed, '-23- (19) 1283471 can offset (eliminate) noise by causing the same degree of crosstalk in the input signal wiring. (crosstalk). Further, as shown in Fig. 5, the rectangular frame portion surrounding the three LNAs is made into a generalized specific circuit portion. This specific circuit portion 1 1 is formed in a semiconductor wafer in which LNAs are formed in a region insulated and isolated by other circuit portions. Moreover, the ground potential of each LNA is common. This is because in the dual-band communication system and the three-band communication system, when a communication system (communication system) is used, the remaining communication system becomes an idle state because of the LNA belonging to the communication system that becomes a no-load state. Since the influence of the ground potential is small, even if the ground electrodes and the ground wirings of the LNAs belonging to the individual communication systems are shared, the adverse effects are small. However, if it is necessary to isolate each LNA, the ground potential of each LNA may be independent. Fig. 13 is a cross-sectional view showing a mode in which the portable device of the semiconductor device (high-frequency power module) 1 of the first embodiment is mounted. In order to mount the semiconductor device 1 on the main surface of the mounting substrate (wiring substrate) 80 of the portable telephone, the lead wire 7 corresponding to the semiconductor device 1 and the bonding pad 8 1 and the tab fixing portion 82 to which the regulating sheet 4 is connected to the wiring are disposed. Therefore, the wires 7 and the tabs 4 of the semiconductor device 1 are overlapped with the pads 8 1 and the fixing portions 82 to position the semiconductor device 1 to be positioned. Then, in this state, the solder plating film which is formed in advance on the lead wires 7 of the semiconductor device 1 and the back surface of the tab 4 is soldered (reflow), and the wires 7 and the tabs 4 are connected (mounted) by the solder 8 3 . Here, the circuit configuration (functional configuration) of the portable telephone having the three-band configuration will be briefly described with reference to Fig. 12 . That is, the portable telephone can perform signal processing such as the GSM communication method of the -24-(20) 1283471 900 MHz band and the DCS 1 800 communication mode of the 1 800 MHz band and the PCS 1 900 communication mode of the 1 900 MHz band. The block diagram of Fig. 12 shows the transmission system and the reception system connected to the antenna 20 via the antenna switch 21, and the transmission system and the reception system are both connected to the baseband wafer 22. The receiving system has an antenna 20, an antenna switch 21, three band pass filters 23 connected in parallel to the antenna switch 21, and a low noise amplifier (LNA) 24 connected to the band pass filter 23, respectively, connected to the foregoing Three LNAs 24 and variable amplifiers 25 connected in parallel. The two variable amplifiers 25 are respectively connected with a mixer 26, a low pass filter 27, a PGA 28, a low pass filter 29, a PGA 30, a low pass filter 31, a PGA 32, a low pass filter 33, and a demodulator. 34 〇 PGA 28, PGA 30, and PGA 32 are controlled by the ADC/DAC & DC offset control logic circuit unit 35. Moreover, the two mixers 26 can be phase controlled by a 90 degree phase converter 40. In Fig. 12, an I/Q modulator composed of a 90-phase converter 40 and two mixers 26 is provided corresponding to each of the three LNAs in order to correspond to the respective band regions, but is simplified in Fig. 12 for the sake of simplicity. And write it out. A synthesizer composed of an RF synthesizer 41 and an IF (Intermediate) synthesizer 42 is disposed in the semiconductor wafer 3 signal processing 1C. The RF synthesizer 41 is connected to the RFVC 044 via the buffer 43, and the RFVC 044 outputs an RF local signal for control. Two local signal frequency dividers 37, 38 are connected in series to the buffer 43, and switches 48, 49 are connected to the respective output terminals. The RF local signal from the RFVCO 44 is input to the 90 phase converter 40 by switching of the switch 48. The 90 phase converter 40 controls the -25-(21) 1283471 mixer 26 by means of the RF local signal. The signal output mode of RFVC044 is Rx mode in the case of GSM of 3 78 0 to 3 840 MHz, DCS of 3 6 1 0 to 3 7 60 MHz, and PCS of 3 8 60 to 3 98 0 MHz. Moreover, the T x mode is 3 8 4 0 to 3 9 8 ΜΗ z in G S , , 3580 to 3730 MHz in DCS, and 3860 to 3980 MHz in PCS. The IF synthesizer 42 is connected to the IFVCO (Intermediate Wave Voltage Control Oscillator) 45 via the frequency divider 46 to cause the IFVC 045 to output an IF local signal for control. The frequency of the output signals of the IF VC〇4 5 is 640 MHz. Moreover, the VCXO (Voltage Controlled Crystal Oscillator) 50 is controlled by the RF synthesizer 41 and the IF synthesizer 42, and the output reference signal is transmitted to the baseband chip 22, and the synthesizer and the ADC/DAC & DC offset control logic are used in the receiving system. The circuit unit 35 controls the IF signal. The baseband chip 22 is converted into a baseband chip signal (I, Q signal) by the demodulator 34. The transmitting system is a two-phase mixer 61 that uses the I, Q signals output from the baseband chip 22 as input signals, a 90-phase converter 62 that controls the phases of the two mixers 61, and the two are added. The adder 63 of the output of the mixer 61, the mixer 64 which takes the output of the adder 63 as the input, and the DPD (Digital Phase Detector) 65, the output of the mixer 64 and the DPD 65 Loop filter 66, which is regarded as input, two TX VC 0 (transmission wave voltage control transmitter) 67 which takes the output of loop filter 66 as input, and outputs of these two TXVC067 Both of the power module 68 and the antenna switch 21 are used as inputs. Loop filter 66 is an add-on component. -26- (22) 1283471 The mixer 61, the 90 phase converter 62, and the adder 63 constitute a quadrature modulator. The 90 phase converter 62 is connected to the frequency divider 46 via a frequency divider 47, and is controlled by an IF local signal output from the IF VC 045. The outputs of the two TXVCs 067 are sensed by a coupler (Couple 〇 70. This detection signal is input to the mixer 72 via the amplifier 71. The mixer 72 inputs the RF local signal output from the RFVC 04 4 via the switch 49. Mixer The output signal of 72 is input to the mixer 64 and the DPD 65 together with the output signal of the adder 63. The mixer 64 and the DPD 65 form an offset PLL (Phase-Locked Loop). The frequency of the output signal generated by the mixer 72. The communication mode is 80MHz. The TXVC067 of one of the two TXVC067 is used for the GSM communication mode, and the output signal frequency is 880~9 15MHz. Moreover, the other TXVC067 is used for the DCS and PCS communication modes, and the frequency of the output signal is used. It is 1710~1 78 5 MHz or 1 8 5 0~19 10 MHz. Power module 68 contains low frequency power module and high frequency power module, low frequency power module accepts output from 8 8 0~9 15MHz The signal of the TXVC067 signal is amplified, and the high-frequency power module receives the signal from the TXVC067 that outputs the signal of 1710~1 7 5 5 MHz or 1 8 5 0~1910 MHz, and amplifies the signal to the antenna switch. 2 1. Logic electricity 60 is also formed monolithically in the semiconductor device 1 of the first embodiment, and the output signal is transmitted to the baseband wafer 22. The semiconductor device (high-frequency power module) 1 of the first embodiment is surrounded by a thick line in FIG. A part of each of the circuit portions is formed in a single piece. Further, the portions of the three LNAs 24 are the specific circuit portion 11 in the first embodiment (see FIG. 27-(23) 1283471 4, FIG. 5). Some of these circuit parts are block diagrams of the semiconductor wafer 3 of Fig. 4 and Fig. 5. The wireless signals (electric waves) received by the antenna 2 are converted into electrical signals, and the components of the receiving system are sequentially processed and transmitted. The baseband wafer 22 is supplied. The electrical signals outputted from the baseband wafer 22 are sequentially processed in the components of the transmission system, and are transmitted by the antenna 20 by radio waves. Fig. 4 is a view showing a mode of arrangement of each circuit portion in the semiconductor wafer 3. In the layout diagram, electrode terminals (pads) 9 are arranged along the main surface of the semiconductor wafer 3. Further, circuit portions are disposed in the inner division regions of the electrode terminals 9. As shown in Fig. 4, the semiconductor crystals are arranged. 3 is centrally configured with an ADC/DAC & DC offset control logic circuit portion 35, on the left side of which the mixers 26, 64 and three LNAs 24 are arranged, RFVC 044 is located on top 1, and RF synthesizer 41 is arranged on the right side from top to bottom. The VCXO 50, the IF synthesizer 42, the IFVC 045, and the TXVC 067 are located on the lower side. The relationship between each circuit portion (the first circuit portion and the second circuit portion) and the electrode terminal 9 thereof, and the welding line 1 of the electrode terminal 9 and the wire 7 are shown in FIG. 0 caused by the wiring status. The bonding wire 10 shows the bonding wire 10 connecting the electrode terminal 9 and the wire 7 and the downward bonding bonding wire 10a connecting the electrode terminal 9 and the tab 4, and focusing on the three LNAs 24 of the specific circuit portion 11 (first circuit portion). The predetermined wire 7 connected to the band pass filter 23 of the external component, that is, the signal wire 7 of the Signal described on the left side is connected to the signal electrode terminal 9 of the LNA 24 via the bonding wire 1 。. Two signal wires are arranged from the electrode terminal 9 to the wire 7 via the bonding wire 1 ,, and the ground electrode terminal 9 of the LNA 24 of the specific circuit -28- (24) 1283471 portion 11 is soldered on both sides of the two signal wires. The wire 10 is connected to the ground wire 7 (the wire 7 shown in the GND on the left side), and the ground wire is formed. Accordingly, at least the ground of the VCOs of the other circuit portions is insulated from the ground of the LNA 24, and the wires of the other circuit portions adjacent to each other and the wires of the L N A 2 4 are electromagnetically shielded by the ground wires 7. Moreover, the adjacent LNAs 24 are also electromagnetically shielded by the ground conductors 7. In comparison with the LNA 24 that amplifies the weak signal entering by the antenna, in the circuit sections (for example, the offset PLL, the TXVCO 67, and the like) that process the transmission signal of the electrical signal output from the baseband chip 22, since the electrical signal is larger than the aforementioned weak signal, Therefore, there is a strong noise characteristic due to fluctuations in ground potential or crosstalk. Therefore, the supply of the ground potential to the circuit portion of the transmission system is common to the tabs 4 via the VCOs and the like, and the number of the wires 7 can be reduced, and the semiconductor device can be downsized. In order to prevent deterioration of a signal due to crosstalk between wirings formed on the main surface of the semiconductor wafer 3, the LNA compares, for example, a PGA or the like, a circuit for processing a signal amplified by the LNA, or a transmission system, etc., to make the wiring It is preferable that the length is shortened and disposed closer to the electrode terminal 9. According to the first embodiment, the following effects are obtained. (1) In the high-frequency power module 1 of the semiconductor device 1, the electrode terminal 9 of the semiconductor element (semiconductor wafer) 3 is connected to the tab 7 in addition to the lead wire 7 via the bonding wire 10 (downward bonding) . Further, since the adjustment piece 4 is connected to the ground in this downward direction, the ground electrode terminal (electrode terminal of the semiconductor element) of the low noise amplifier 24 of the specific circuit unit 11 is not connected to the entire -29-(25) 1283471 piece. 4, but connected to a separate wire terminal (grounding wire). Since the low noise amplifier 24 amplifies the weak signal, the fluctuation of the ground potential becomes a change in the output of the low noise amplifier 24, and the signal waveform is also distorted, but since the ground of the low noise amplifier 24 is separated from the ground of other circuit parts, The variation of the output of the low noise amplifier 24 or the distortion of the signal waveform can be suppressed. As a result, it is possible to connect to the wireless communication device to make good communication without distortion or distortion of the output. (2) In the high-frequency power module having a plurality of communication circuits, the common grounding of the tabs 4 is accompanied by a change in the ground potential, and an induced current is generated in the unused communication circuit, resulting in the induced current. The noise enters the so-called crosstalk of the communication circuit in use (in operation), but the high frequency power module 1 of the present invention can be suppressed from being low because the low noise amplifier 24 of each communication circuit is separated from the ground of the other circuit portion. The variation of the output of the noise amplifier 24 or the distortion of the signal waveform. As a result, in a wireless communication device having a plurality of communication circuits, a good call with no output fluctuation or distortion is also possible. (3) In the high-frequency power module 1, the signal wiring from the electrode terminal 9 of the low noise amplifier 24 to the wire 7 via the bonding wire 10 is disposed on both sides of the ground wiring by the electromagnetic screen wall, so that the signal wiring It is difficult to get crosstalk. (4) In the high-frequency power module 1, since the tab 4 is exposed on the back surface of the sealing body 2, heat generated in the semiconductor wafer 3 can be efficiently dissipated to the mounting substrate 80. Therefore, the wireless communication device connected to the high-frequency power module 1 can be stably operated. (5) Since the high-frequency power module 1 is a non-conducting type semiconductor device in which the tab 4 and the lead wire 7 are exposed on the back surface of the compact 30-(26) 1283471 enclosure 2, the high-frequency power module 1 is small, It is possible to reduce the thickness and to reduce the weight. Therefore, it is also possible to reduce the size and weight of the wireless communication device to which the high-frequency power module 1 is connected. (6) The high-frequency power module 1 is connected to the electrode terminal 9 of the semiconductor wafer 3 via the bonding wire 10 and the lead wire (pin) 7, and is connected to the grounding potential by the bonding wire 10a facing downward. Since the electrode terminal (ground electrode terminal) 9 of the semiconductor wafer 3 has a downward bonding structure, the ground lead wire serving as the external electrode terminal 7 can be reduced, and the size of the sealing body 2 which reduces the number of stitches can be reduced, and a high frequency can be achieved. The power module 1 is miniaturized. (Embodiment 2) FIG. 14 is a plan view showing a mode in which a part of a sealing body of a high-frequency power module according to another embodiment (Embodiment 2) of the present invention is cut out. In the second embodiment, in addition to the circuit portion in which the specific circuit portion 11 has three low noise amplifiers (LNA) 24 in the first embodiment, the RFVC 044 which processes the high frequency among the VCOs also serves as the specific circuit portion 11. Therefore, all the ground electrode terminals 9 of the RFVC 044 are connected to the wires (ground wires) 7 via the bonding wires 10, and are not connected to the tabs 4 via the bonding wires. In the wiring from the electrode terminal 9 of the semiconductor wafer 3 to the wire 7 via the bonding wire 10, ground wiring is disposed on both sides of the two signal wirings of the RFVCCM 4, and electromagnetic shielding of the signal wiring is performed. Accordingly, the ground potential of the specific circuit portion 11 for processing the high-frequency signal is insulated from the ground potential of the other circuit portion, so that crosstalk does not occur. -31 - (27) 1283471 (Embodiment 3) FIG. 15 is a plan view showing a mode in which a part of a sealing body of a high-frequency power module according to another embodiment (Embodiment 3) of the present invention is cut out. In the third embodiment, the RFVC 〇 44 is an additional component, and is an example in which the semiconductor wafer 3 is formed in a single piece. This dual-band communication method forms a low-noise amplifier, a mixer, a VCO, a synthesizer, an IQ modulator/demodulator, a frequency divider, a quadrature modulator, and the like in a single chip. The two mixers of the receiving system are respectively controlled by a frequency divider, and this frequency divider is a frequency conversion circuit for converting the high frequency signal outputted by the RFVCO of the external part into a signal of a lower frequency. Therefore, in the third embodiment, RFVC 044 is present on the outer side of the semiconductor device 1 as shown in Fig. 15, and the signal wiring of the RFVC 044 is connected to the wires 7 of the two semiconductor devices 1. Further, the electrode terminals 9 on both sides of the two signal wirings which are connected to the electrode terminals 9 of the semiconductor wafer 3 via the bonding wires 1 through the two wires 7 connected to the RFVC 044 are connected to the wires 7 via the bonding wires 10. The electrode terminals 9 on both sides of the two signal wirings are ground electrode terminals, and the wires 7 connected to the ground electrode terminals via the bonding wires 1 are also grounded wires. Accordingly, as in the case of the second embodiment, the signal wiring for processing the high-frequency signal is also electromagnetically shielded, and is configured to be independent of the ground potential of the other circuit portion in the semiconductor wafer 3. Also in the third embodiment, as in the second embodiment, the obstacle accompanying the fluctuation of the ground potential of the RFVC 044 does not occur. (Embodiment 4) -32- (28) 1283471 FIGS. 16 and 17 are diagrams related to a high-frequency power module according to another embodiment (Embodiment 4) of the present invention, and FIG. 16 is a cut-off high-frequency power module. A top view of a mode of a portion of the sealing body, and FIG. 17 is a cross-sectional view of a mode of the high frequency power module. In the fourth embodiment, the regulating piece 4 which is a common grounding terminal and the wire 7 which is formed to have a ground potential are electrically connected by the conductive bonding wire 1 〇b, and the wire 7 is a grounding external electrode terminal. In the semiconductor device 1 of the fourth embodiment, since the back surface of the bonding sheet 4 is exposed by the back surface (mounting surface) of the sealing body 2, the adjustment sheet 4 can be used as a grounding external electrode terminal and connected to the grounding wire 1 〇b via the bonding wire 1 〇b. The wire 7 of the tab 4 can also be used as a grounding external electrode terminal. Fig. 18 is a modification of the fourth embodiment. That is, since the modification is thinned by the back side of the semi-uranium engraving sheet 4, the resin is also wound around the back side of the tab 4 during the single-pack sealing, so that the back surface of the sheet 4 is also adjusted as shown in Fig. 18. It is not exposed by the sealing body and is completely buried in the sealing body 2. In the case of such a configuration, since the regulating piece 4 is connected to the wire 7 via the bonding wire 1 Ob, the wire 7 can be used as a grounding external electrode terminal. Further, the other structure in which the tab is buried in the sealing body may be a structure in which the tab suspension wire is bent more into a high step shape. In the configuration shown in FIG. 18, the number of the wires 7 connected to the tab via the bonding wire 1 Ob is reduced by comparison with the number of electrode terminals 9 for ground potential supply connected to the tab 4 via the bonding wire 10 Oa. Since the number of the wires 7 arranged along the circumference of the sealing body 2 can be reduced and the apparatus can be miniaturized, and the back surface of the tab 4 is covered by the sealing body 2, when this embodiment-33-(29) 1283471 is mounted When the semiconductor device 1 is mounted on the wiring substrate, the region under the semiconductor device 1 can be used as an area for wiring on the wiring substrate. Therefore, in the present embodiment, there is an advantage that the mounting density on the wiring substrate can be improved together with the miniaturization of the semiconductor device 1. (Embodiment 5) Figs. 19 to 30 show a high frequency power module (semiconductor device) according to another embodiment (Embodiment 5) of the present invention. The high-frequency power module of the fifth embodiment is basically the same as the high-frequency power module of the first embodiment. As shown in FIG. 30, the high-frequency power module 1 of the fifth embodiment is a wireless communication device (a portable wireless device such as a mobile phone) that is incorporated in a dual-band configuration (GSM communication, DCS communication, and PCS communication). use. Fig. 30 is a view schematically showing the circuit configuration of the transmission/reception system from the antenna 20 to the baseband wafer 22, substantially corresponding to Fig. 12; In the fifth embodiment, a pair of complementary signals whose phases are inverted will be output from the band pass filter 23 connected to the antenna switch 2 1 (connected to the antenna 20), and the complementary signal will be input by the input 2 input · 2 output. The low noise amplifier (LNA) 24, the output signal of the LNA 24 will be processed in each circuit portion in turn, and transmitted to the baseband chip 22 or the transmit and receive system switch switch 36. Basically, the difference between FIG. 30 and FIG. 12 lies in In Fig. 30, in order to display the signal according to the complementary signal processor, two connection lines are formed to connect the respective circuit portions, and two output signal lines from the 90-degree phase shift converter 40 to the mixer 26 are also formed. In the high-frequency power module 1 of the fifth embodiment, as shown in FIGS. 19 to 22, -34-(30) 1283471 is a surface on which the lead wire 7 is exposed on the back surface of the sealing body (resin sealing body) 2 (bottom: mounting) The non-conducting type semiconductor device of the surface 7a) has a QFN structure in which the wires 7 are respectively protruded from the four sides of the quadrangular shape. The wafer mounting portion (adjusting sheet) 4, the sheet hanging wire 6 and the wire 7 are fixed by a stamping or etching method (for example, 〇. A piece of metal plate (for example, a copper plate) of about 2 mm is formed into a pattern. Also, the underside (back) of the wire 7 or the tab suspension wire 6 is partially etched to a certain thickness (for example, 〇. It is thinner by about 1 mm. Moreover, the width of the wire is, for example, 0 in the first portion 7c. The degree of 2 legs, for example, forms 0 in the second part 7d. 15 nun degree. As a result, the upper surface of the wafer mounting portion 4 on which the semiconductor wafer 3 is mounted, the upper surface of the lead wire 7 and the upper surface of the tab suspension wire 6 are formed on the same plane, and the lower surface of the wafer mounting portion 4 is exposed to the resin sealing body 2. Below the wire 7 and a portion of the tab suspension wire 6 are exposed. The resin sealing body 2 has a structure in which a flat rectangular shape having an upper surface, a back surface facing the upper surface (lower surface), and a side surface sandwiching the upper surface and the back surface is formed. Further, a plurality of wires 7 provided inside and outside the resin sealing body 2 along the periphery of the resin sealing body 2 are provided. The outer size of the high-frequency power module 1 is the same as that of the first embodiment. As shown in Fig. 22, the wafer mounting portion 4 is in a field surrounded by a plurality of wires 7, and a semiconductor wafer 3 is fixed to the upper surface of the wafer mounting portion 4 by an adhesive 5. The planar shape of the semiconductor wafer 3 is a quadrangular shape, and has a plurality of electrode terminals 9 on its main surface, and a plurality of circuit portions each composed of a plurality of semiconductor elements. The semiconductor wafer 3 is fixed in a quadrangular shape surrounded by a slit 3 7 provided along the periphery of the wafer mounting portion (adjacent sheet) 4 - 35 - (31) 1283471. The wafer mounting portion 4 is fixed to the ground potential. Further, the wafer mounting portion 4 and the predetermined electrode terminal 9 (electrode potential electrode terminal) of the semiconductor wafer 3 are connected by a conductive bonding wire 1 ,, but the bonding wire 1 〇, that is, the bonding wire 1 is bonded downward. 〇a is connected to the wafer mounting portion outside the slit 37. Since the wafer mounting portion outside the slits 37 is connected with the downward bonding bonding wires 1a, the wafer mounting portion outside the slits 37 is not contaminated by the flowing adhesive 5, so that the bonding wires are bonded downward. 1 〇a's connectivity will be better. Further, by the presence of the slits 7, the resin forming the resin sealing body 2 enters the slits 37, and the bonding strength between the wafer mounting portion 4 and the resin sealing body 2 is also improved, thereby improving the encapsulation property. Further, by the presence of the slits 37, the heat resistance at the time of mounting heating can be improved, and the weld line peeling of the tab joint portion which is joined downward can be prevented. The plurality of circuit portions of the semiconductor wafer 3 include a differential amplifier (differential amplification circuit portion) having a pair of inputs. As shown in Figure 25, the differential amplifier circuit forms a low noise amplifier (LNA) 24. As shown in Fig. 25, the specific circuit portion 11 surrounding the three LNAs is formed in the semiconductor wafer, and each LNA is formed in a field in which the other circuit portions are insulated and separated. Also, the ground potentials of the LNAs are common. The configuration of this portion is the same as that of the first embodiment. The LNA 24 is a circuit unit for amplifying an electric signal that is converted via an antenna in a portable wireless device. Since each of the LNAs 24 constituting the fifth embodiment constitutes a differential amplifier, it has two electrode terminals 9 for input wiring. In order to maintain the symmetry of the input signal of the differential amplifying circuit portion, the length of the bonding wire 10 connected to the two electrode terminals 9 is formed to have the same length. -36- (32) 1283471 Further, a grounding bonding wire 10 is disposed on both sides of the bonding wire 10 connecting the two electrode terminals 9 and the corresponding wires 7, and an electromagnetic screen wall is applied to the signal wires. Can not generate crosstalk. Next, the input wiring (signal line) of the differential amplifier circuit unit will be described (including the pattern of the wires 7 and the like). As shown in Fig. 23 (a), the plurality of electrode terminals 9 of the semiconductor wafer 3 are a first electrode terminal 9a and a second electrode terminal 9b including a pair of inputs corresponding to the differential amplifying circuit portion. The first electrode terminal 9a and the second electrode terminal 9b are arranged adjacent to each other along one side of the semiconductor wafer 3. Further, a pair of complementary signals having different phases (inversion) are input to the first electrode terminal 9a and the second electrode terminal 9b. In order to obtain the simultaneous input (symmetry) of the input signal (complementary signal), the lengths of the bonding wires 10 connected to the first electrode terminal 9a and the second electrode terminal 9b are formed to be the same. In order to make the lengths of the bonding wires 1 形成 the same, the plane pattern of the wires 7 is changed so that the distance from the predetermined electrode terminals 9 is made the same. Here, the relationship between the lead wire 7 and the tab suspension wire 6 will be described with respect to the wafer mounting portion 4. As shown in Fig. 19, the plurality of wires 7 are: a first portion 7c that exposes the back surface (lower surface) on the back surface of the resin sealing body 2, and a second portion that extends from the first portion 7c to the wafer mounting portion 4 to the inside. 7d is formed, and the lower portion of the second portion 7d is removed by uranium engraving to a certain thickness. As a result, the second portion 7d of the wire 7 is thinner than the first portion 7c, and the entire second portion 7d is covered in the resin sealing body 2. Further, since the lower portion of the intermediate portion of the tab suspension wire 6 is etched to a predetermined thickness in the same manner as the second portion 7d described above, the portion which is engraved by the uranium at the transfer molding method -37-(33) 1283471 The resin enters, so on the back side of the resin sealing body 2, the tab suspension wire 6 is only partially exposed. Further, the first portion 7c of the wire 7 protrudes from the side surface (peripheral surface) of the resin sealing body 2 so as to protrude around the resin sealing body 2. This protruding length is 0. Less than 1mm. Since the second portion 7d of the wire 7 is embedded in the resin sealing body 2, and the insulating resin is interposed between the end portion (welding wire connecting portion) of the second portion 7d and the outer peripheral portion of the wafer mounting portion 4, the The end of the two portions 7d is close to the wafer mounting portion 4. In other words, since the second portion 7d of the wire 7 is not exposed on the back surface of the resin sealing body 2, but is formed to extend in the resin sealing body 2, the high-frequency power module 1 is shown in FIG. When the mounting substrate 80 is mounted, when the lead wire 7 and the wafer mounting portion 4 are fixed to the pad 81 or the fixing portion 82 of the mounting substrate 80 via the solder 83, the solder 83 of the fixing wire 7 and the pad 81 can be fixed and fixed. Since the solder 83 of the fixed wafer mounting portion 4 of the portion 82 is in contact with or close to each other (to the extent of electrical short-circuiting), the end portion of the second portion 7d can be brought close to the outer peripheral portion of the wafer mounting portion 4. In this manner, the pattern of the second portion 7d can be independently determined by embedding the second portion 7d of the wire 7 in the resin sealing body 2, that is, the portion (the first portion 7c) that forms the external electrode. shape. Therefore, in order to obtain the symmetry of the input signal (complementary signal), the length of the bonding wire 10 connected to the first electrode terminal 9a and the second electrode terminal 9b can be determined in the same manner to determine the wire 7 (the first portion 7c and the second portion). Part 7 d) pattern. In the fifth embodiment, the first electrode terminal 9a is closer to the corner of the semiconductor wafer 3 than the second -38-(34) 1283471 electrode terminal 9b, and is electrically connected to the first electrode terminal 9a. The end of the second portion 7d of the wire 7 extends to the side closer to the semiconductor wafer 3 than the end of the second portion 7d of the wire 7 electrically connected to the second electrode terminal 9b (refer to Fig. 23 (a) ). Further, the length of the conductive bonding wire 1A connecting the first electrode terminal 9a and the second portion 7d of the wire 7 and the conductive bonding wire 1 of the second electrode terminal 9b and the second portion 7d of the wire 7 are connected. The length will form L 0 and will form almost the same length. On the other hand, when the wire 7 shown in Fig. 23(b) of the second portion 7d is not provided, the length of the conductive bonding wire 1 连接 connecting the electrode terminals 9a, 9b (adjacent to the wire 7) respectively forms L. 1, L 2 , that is, longer than the aforementioned L 0 , so that the inductance becomes large, and the high frequency characteristics are deteriorated. Moreover, since the lengths of LI and L2 are different, the difference in inductance becomes large, and the symmetry of the input signal is deteriorated. For example, when the welding line is an Au soldering wire with a diameter of 25 μm, if the operating frequency band is GHz, the welding line length is only different. 5mm will produce 0. 5 nH inductance difference, which will significantly affect the symmetry of the complementary input signal. Further, in the external specifications of the QFN, since the lead wires 7 disposed around the back surface of the resin sealing body 2 form external electrode terminals, they must be arranged in parallel at a predetermined pitch. Further, in the case of the fifth embodiment, as shown in Fig. 23 (a), the lead wire 7 is formed by exposing the lower first portion 7c to the back surface of the resin sealing body 2, and thereby extending the first portion 7c. And the second portion 7d extending in a state of being embedded in the resin sealing body 2 is formed, so that the second portion 7d can be extended -39-(35) 1283471 in a free direction, and adjacent wires can be made to each other. The lengths of the bonding wires 1 〇 may be substantially the same (L 0) between the electrode terminals 9 adjacent to the wires 7 extending in the desired direction. As a result, the length of the bonding wire 10 connecting the first electrode terminal 9a and the wire 7 and the length of the bonding wire 10 connecting the second electrode terminal 9b and the wire 7 can be made the same, and each bonding wire 10 can be made. The inductance is formed the same. Further, as described above, since the second portion 7d of the wire 7 is located inside the resin sealing body 2 and is not exposed on the back surface of the resin sealing body 2, it can be extended in a free direction. That is, as shown in Fig. 24(a), since the extending direction of the second portion 7d can be made to coincide with the extending direction of the bonding wire 10, and the bonding wire 10 is positioned within the width of the leading end of the wire 7, the welding can be performed. The length of the connecting portion of the wire 1〇 is formed long (figure f). Fig. 24 (b) shows a case where the wire 7 is formed only by the first portion 7c. Since the first portion 7c constitutes the external electrode terminal on the back surface of the resin sealing body 2, the respective external electrode terminals are arranged in parallel at predetermined intervals. As a result, as shown in Fig. 24(b), the intersection angle Θ of the bonding wires to the external electrode terminals becomes larger as the external electrode terminals are closer to the corners of the square-shaped resin sealing body 2, so that the bonding wires 1 〇 are deviated. The width of the wire 7 forms a shape that intersects the side turns of the wire 7, so that the length of the connection of the wire 7 of the bonding wire 1 会 forms h, that is, it is formed shorter than the connection length f. Further, as shown in the fifth embodiment, as shown in Fig. 24 (a), the wire 7 and the bonding wire can be elongated by matching the extending direction of the second portion 7d with the stretching direction of the bonding wire 10. The connection length (f) of 10 can further improve the connection strength of the bonding wire and the connection (wire bonding) reliability of the bonding wire. -40- (36) 1283471 The symmetry of the input signal is equally important in RF VC 044, which processes high frequency signals. In the fifth embodiment, as shown in Fig. 25, the signal lines extending between the two RFVCs 044, that is, the two welding lines 10, also form the same welding line length. Moreover, the two signal lines also form the electromagnetic screen wall by the grounding wiring on both sides, so that no crosstalk is generated. FIG. 26 is a partial plan view showing the manufacturing part of the high-frequency power module, that is, the welding line. The lead frame of the semiconductor terminal 13 of the semiconductor wafer 13 fixed to the lead frame 13 and a portion of the state of the conductive 7 is connected. Since the method of manufacturing the high-frequency power module 1 of the fifth embodiment is the same as that of the first embodiment, the description thereof will be omitted. In the fifth embodiment, as shown in the enlarged mode sectional view of Fig. 27, the semiconductor wafer 3 is mounted on the upper surface of the wafer mounting portion 4 by the adhesive 5. The semiconductor wafer 3 includes a first semiconductor substrate 85, an insulating layer 86 formed on the surface of the first semiconductor substrate 85, and a second semiconductor substrate 87 formed on the insulating layer 86, and a plurality of electrode terminals 9 The plurality of circuit portions are formed on the main surface of the second semiconductor substrate 87, and the plurality of circuit portions are formed on the second semiconductor substrate 87. The back surface of the first semiconductor substrate 85 of the semiconductor wafer 3 is electrically connected to the wafer via the conductive adhesive 5. Mounting section 4. The first semiconductor substrate 85 is a P-type germanium substrate, and the second semiconductor substrate 878 is an N-type germanium substrate, and both of them are formed of an SOI structure (silicon on insulator) bonded together by an insulating layer 86. Further, the plurality of electrode terminals 9 on the upper surface of the semiconductor wafer 3 constitute a signal electrode terminal, a power source potential electrode terminal, and a reference power source potential electrode terminal. Further, the bonding wire 10 to which the wafer mounting portion -41 - (37) 1283471 4 and the electrode terminal 9 of the semiconductor wafer 3 are bonded is bonded to the bonding wire 10a downward, and the wafer mounting portion 4 is fixed to the ground potential or the negative potential. . When the wafer mounting portion 4 is fixed to a negative potential, the first semiconductor substrate 85 is fixed at a negative potential. As a result, the depletion layer extends to the first semiconductor substrate 85, so that the second semiconductor substrate 87 can be reduced. The parasitic capacitance added to the plurality of circuit portions has an effect of increasing the speed of the circuit. Further, in the second semiconductor substrate 87, a plurality of isolation grooves in which the lower bottom reaches the insulating layer 86 are provided. Moreover, the isolation trenches are filled with insulators 89, and the areas surrounded by the isolation trenches form electrically independent islands. Further, N-type and P-type semiconductor layers (N, P) having a predetermined impurity concentration are formed on the entire surface or a part of the second semiconductor substrate 87 surrounded by the isolation trenches, and a predetermined pn junction is formed. Semiconductor component. Further, on the surface of the second semiconductor substrate including each semiconductor element, an insulating layer INS 1, INS 2 such as a hafnium oxide film or a metal wiring layer such as alumina or copper, and conductors M1 to M4 to which the upper and lower wiring layers are connected are sequentially formed. As shown in FIG. 27, a plurality of electrode terminals 9 are formed by the uppermost wiring M4. Fig. 28 is a cross-sectional view showing a detailed structure of the wafer shown in Fig. 27. For semiconductor components, from left to right, respectively, NPN vertical transistor (NPN Trs), PNP vertical transistor (V-PNP Trs), P-channel MOS transistor (PMOS), N-channel MOS Crystal (NM0S), MOS capacitor, resistor (polysilicon resistor). Further, the high-frequency power module (semiconductor package - 42 - (38) 1283471) 1 shown in Fig. 30 can be formed by combining a plurality of such semiconductor elements. Further, when the high-frequency power module 1 is manufactured, after the first semiconductor substrate is prepared, the second semiconductor substrate 87 is bonded via the insulating layer 86, and then the second semiconductor substrate 87 is formed to have a predetermined thickness. Thereafter, the second semiconductor substrate 87 is selectively etched and removed by a predetermined thickness, and the desired semiconductor layer is selectively formed repeatedly to form respective semiconductor elements, and the isolation trench and the insulator 849 are formed to form a wiring structure, and finally the vertical and horizontal The semiconductor wafer 3 is formed by cutting the first semiconductor substrate 85. The high-frequency power module 1 of the fifth embodiment is configured to form a 2-input and 2-output low-noise amplifier (LNA) 24 and RFVC 044 for processing high-frequency signals, and to make 2-input in order to maintain the symmetry of the 2-input signal. The length of the weld line 1 形成 is the same. Further, the length of the bonding wire 1 构成 constituting the signal line can be shortened by the length of the bonding wire by connecting the electrode terminal 9 of the semiconductor wafer 3 and the end portion of the second portion 7d of the wire 7 to further reduce the inductance of the bonding wire. Thereby, high frequency characteristics (small DC offset) can be improved. In other words, in the fifth embodiment, three low noise amplifiers (LNAs) 24 for GSM DCS PCS communication are differential low noise amplifiers (differential amplifiers) of the two input type shown in Fig. 33 (b). Composition. That is, each of the low noise amplifiers (LNAs) 24 of the fifth embodiment is constituted by a unit amplifier that inputs two signals (complementary signals) whose phases are opposite to each other. Therefore, even if the output signal of the 90-degree phase shift converter 40 leaks to the LNA input line, the in-phase component will be eliminated because the complementary signal is input, and will not be amplified at the LNA 24, and the DC offset can be reduced. As a result, in the communication method in which the transmission band is high, there is an effect of preventing the deterioration of the DC offset characteristic -43-(39) 1283471. Further, the high-frequency power module 1 of the fifth embodiment has an effect that the DC offset is small and the gain can be prevented from being lowered. (Embodiment 6) FIG. 31 is a diagram showing another embodiment (Embodiment 6) of the present invention, that is, a configuration of a frequency-capped power module in which a tab for supporting a semiconductor wafer is smaller than a semiconductor wafer (small tab structure) Profile section view. Fig. 3 is a partial schematic plan view showing a lead frame formed by a small tab used in the manufacture of the high-frequency power module of the sixth embodiment. In the high-frequency power module 1 of the sixth embodiment, in the high-frequency power module 1 of the fifth embodiment, the wafer mounting portion 4 is made smaller than the semiconductor wafer 3, that is, a small tab is formed, and The tab suspension wire 6 of the wafer mounting portion 4 is partially curved in a stepwise manner, and the lower surface of the wafer mounting portion 4 is made higher than the lower surface of the first portion 7c of the lead wire 7 to form the embedded resin sealing body 2 The internal structure. In other words, the special wafer mounting portion 4 of the sixth embodiment has a step difference with the first portion 7c of the lead wire 7, and the wafer mounting portion 4 is located inside the resin sealing body 2. Therefore, when the soldering wire bonding portion is not soldered and mounted on the mounting substrate, it is not affected by the stress from the substrate (at the time of temperature change), and the connection reliability is improved. As shown in FIG. 31, in the bonding wire 10 connecting the semiconductor wafer 3 and the wire 7, as shown by the two-dotted line, the position of the wire 7 connected to the bonding wire 10 is not the first connection to the wire 7. In part 7c, the length of the bonding wire is shortened by connecting the end portion of the second portion 7d of the wire 7, and the portion of the -78-(40) 1283471 k is shortened. Further, the high-frequency power module 1 of the sixth embodiment also has a part of the effects of the first embodiment. As shown in Fig. 32, the tab (the wafer mounting portion) 4 can be formed to have a smaller structure than the semiconductor wafer 3, thereby improving the versatility of the lead frame and further reducing the manufacturing cost of the high-frequency power module 1. Fig. 3 is a schematic cross-sectional view showing a high frequency power module of another modification of the configuration of the small tab. Fig. 33 (a) shows a structure in which the second portion 7d is bent by bending the first portion 7c of the wire 7, and the second portion 7d is placed in the resin sealing body 2. This is formed by bending the wire 7 and the tab suspension wire 6 in a stepwise manner in the stage of forming the lead frame, and the wire 7 can be bent by this to form the first portion 7 c. The second portion 7d that is bent and extended, and the wafer mounting portion 4 can be embedded in the resin sealing body 2 by adjusting the bending of the sheet hanging wire 6. Since it is not necessary to selectively etch the wire or the wafer mounting portion 4 and the tab suspension wire 6 in this configuration, the manufacturing cost of the high-frequency power module 1 can be reduced. Fig. 3 (b) shows the structure of the second portion 7d which is bent by the first portion 7c and which is formed by bending only the wire 6 without bending the tab wire 6. In this example, since the wafer mounting portion 4 is exposed to the lower surface of the resin sealing body 2, the heat radiation effect from the lower surface of the wafer mounting portion 4 is increased. As a result, the semiconductor element mounted on the wafer mounting portion 4 has a good heat dissipation property and can perform a stable operation. In the high-frequency power module 1 of the fifth embodiment, the wafer mounting portion 4 is formed with a smaller tab structure than the semiconductor wafer 3, and the versatility of the lead frame can be improved. Reduce the high frequency power module 1 system -45 - (41) 1283471 caused this. In the high-frequency power module 1 of the fifth embodiment, the wafer tab portion 4 is formed with a smaller adjustment piece than the semiconductor wafer 3, and is similar to the second portion 7d of the lead wire 7. An example in which the lower surface of the wafer mounting portion 4 is etched is formed to be thin. Since it is a small tab structure, the versatility of the lead frame used for manufacturing can be improved, and the manufacturing cost of the high-frequency power module 1 can be reduced. The above embodiment of the invention is specifically described by the inventors. The invention is not limited to the embodiments of the invention described above, and various modifications may be made without departing from the spirit and scope of the invention. In the above-described embodiment, the power supply potential that is common or separated is only described with respect to the ground potential. However, the scope of application of the present invention is not limited to the ground potential and the ground potential. In the application of the present invention, attention is paid to an appropriate power supply potential ( The first potential) can reduce the power supply potential of the number of the wires 7 by performing commonalization of the electrodes, and the present invention can be applied to the configuration of the electrode terminal 9 or the wire 7 for supplying the power supply potential. In the above-described embodiment, an example in which the semiconductor device of the QFN type of the present invention is applied is described. However, the present invention is also applicable to the manufacture of, for example, a SON-type semiconductor device, and has the same effects. Furthermore, the present invention is not limited to the non-conducting type semiconductor device, and is, for example, a QFP (Quad Flat Package) or SOP (small outer package) which protrudes along a circumference of the sealing body 2 and is bent into a gull-wing shape. The semiconductor device of the Small Outline Package is also applicable, but a QFN type structure in which the amount of protrusion of the wire in the periphery of the sealing body 2 is small is compared with the above-mentioned QFP or S Ο P of -46-(42) 1283471. It is better to achieve miniaturization of the device. [Effect of the Invention] The effects obtained by the invention represented by the invention disclosed in the present invention will be briefly described as follows. (1) A semiconductor device having a downward bonding structure which is less likely to cause crosstalk can be provided. (2) The ground potential in a specific circuit unit such as a low noise amplifier or RFVCO is not easily affected by the ground potential of the remaining circuit unit, and a low noise amplifier, a mixer, a VC0, and a composite are formed in a single piece. High-frequency power module for semiconductor components of each circuit unit such as a modulator, an IQ modulator/demodulator, a frequency divider, and a quadrature modulator. (3) The ground potential in a specific circuit unit such as a low noise amplifier or RFVCO is not easily affected by the ground potential of the remaining circuit unit, and a low noise amplifier, a mixer, a VC0, and a composite are formed in a single piece. A non-conducting type high frequency power module having a downwardly bonded structure of semiconductor elements of each circuit portion such as an IQ modulator/demodulator, a frequency divider, and a quadrature modulator. (4) The ground potential in a specific circuit unit such as a low noise amplifier or RFVCO is not easily affected by the ground potential of the remaining circuit unit, and a low noise amplifier, a mixer, a VCO, and a composite are formed in a single piece. Small, lightweight high-frequency power module for semiconductor components in various circuit sections such as IQ, IQ modulator/demodulator, frequency divider, and quadrature modulator. (5), can provide good communication with less noise for possible wireless communication -47- (43) 1283471 device. (6) A good communication with less noise can be provided as a possible wireless communication device that can cope with multiple communication methods. (7) As described above, the semiconductor device of the present invention can be used for a wireless communication device such as a mobile phone. In particular, in a mobile phone in which the communication system is a complex system, the ground electrode terminal of the circuit portion that processes the input signal having a very weak signal such as a low noise amplifier is connected to the tab that forms the common ground potential, but It is connected to a completely independent wire, so in the use of a system communication system, crosstalk is not generated between the communication system of other systems, and a high-frequency power module with good communication can be provided. (8) Since the first portion of the external electrode terminal and the second portion extending in the resin sealing body can be formed to form the lead wire, and the pattern of the second portion can be freely selected, it is possible to select the semiconductor wafer to be connected as short as possible. The wire pattern of the length of the electrode terminal and the wire of the wire. Thereby, it is possible to reduce the inductance of the welding wire. (9) In the semiconductor device having the two-input circuit portion having the differential amplifier circuit portion or the like, the length of the bonding wire connected to the two-input electrode terminal can be formed to have the same length, and the symmetry of the input signal can be obtained. Therefore, when the low noise amplifier (LNA) or RFVCO of the wireless communication device is a two-input circuit unit, the symmetry of the input signal can be obtained in each circuit unit, and the frequency characteristics can be improved and the gain can be prevented from being lowered. [Brief Description of the Drawings] -48- (44) 1283471 Fig. 1 is a plan view showing a mode in which a part of a sealing body of a high-frequency power module according to an embodiment (Embodiment 1) of the present invention is cut away. Fig. 2 is a cross-sectional view showing the high frequency power module of the first embodiment. Fig. 3 is a plan view showing a mode of the high-frequency power module of the first embodiment. Fig. 4 is a plan view showing a mode in which the circuit configuration of the semiconductor wafer connected to the high-frequency power module of the first embodiment is displayed in blocks. Fig. 5 is a plan view showing a mode in which the external electrode terminals of the high-frequency power module of the first embodiment are connected to respective circuit portions of a low noise amplifier or a synthesizer of a semiconductor wafer. Fig. 6 is a flow chart showing a method of manufacturing the high-frequency power module according to the first embodiment. Fig. 7 is a plan view showing a lead frame used in the manufacture of the high-frequency power module of the first embodiment. Fig. 8 is a plan view showing a mode of a unit lead frame pattern in the aforementioned lead frame. Fig. 9 is a cross-sectional view showing a mode of the lead frame on which a semiconductor wafer is mounted. Fig. 1A is a cross-sectional view showing a mode of the lead frame in which wire bonding is completed. Fig. 11 is a cross-sectional view showing a mode of the above-described lead frame in which a sealing body is formed. Fig. 12 is a block diagram showing the circuit configuration of a portable telephone to which the high-frequency power module of the first embodiment is connected. Fig. 13 is a cross-sectional view showing a mode in which the mobile phone of the high-frequency power module of the first embodiment is mounted in a -49-(45) 1283471 machine. Fig. 14 is a plan view showing a mode in which a part of a sealing body of a high-frequency power module according to another embodiment (Embodiment 2) of the present invention is cut away. Fig. 15 is a plan view showing a mode in which a part of a sealing body of a high-frequency power module according to another embodiment (Embodiment 3) of the present invention is cut away. Fig. 16 is a plan view showing a mode in which a part of a sealing body of a high-frequency power module according to another embodiment (Embodiment 4) of the present invention is cut away. Fig. 17 is a cross-sectional view showing a mode of a high frequency power module according to a fourth embodiment of the present invention. Fig. 18 is a cross-sectional view showing a mode of a modification of the high frequency power module according to the fourth embodiment. Fig. 19 is a cross-sectional view showing a mode of a high-frequency power module according to another embodiment (Embodiment 5) of the present invention. Fig. 20 is a plan view showing the high frequency power module of the fifth embodiment. Fig. 21 is a bottom plan view showing the high frequency power module of the fifth embodiment. Fig. 2 is a plan view showing a mode in which a part of the sealing body of the high-frequency power module of the fifth embodiment is cut out. 23 is a diagram showing an example of a pattern of a lead wire and a bonding wire according to the fifth embodiment in which the welding line inductance of the input portion of one pair of the differential amplifying circuit portions of the high-frequency power module is matched, and a lead wire in which the welding wire inductance is not uniform and A pattern diagram of a pattern example of a weld line. Fig. 24 is a schematic view showing a difference in connection reliability of the bonding wires in order to explain the difference in the pattern of the wires shown in Fig. 23. Fig. 25 is a plan view showing a mode in which the external electrode -50-(46) 1283471 terminal of the high-frequency power module of the fifth embodiment is connected to each circuit portion of a low noise amplifier or a synthesizer of a semiconductor wafer. Fig. 26 is a plan view showing a lead frame which is a part of a state in which electrodes and wires of a semiconductor wafer fixed to a lead frame are connected by a bonding wire in the manufacture of the high-frequency power module of the fifth embodiment. Fig. 27 is an enlarged cross-sectional view showing a mode in which the internal structure of the semiconductor wafer and the connection state of the wires of the high-frequency power module of the fifth embodiment are connected. Fig. 28 is an enlarged cross-sectional view showing the internal structure of the semiconductor wafer of the high-frequency power module of the fifth embodiment. Fig. 29 is a cross-sectional view showing a mode in which the high-frequency power module of the fifth embodiment is mounted. Fig. 30 is a block diagram showing the circuit configuration of a mobile phone incorporating the high-frequency power module of the fifth embodiment. Fig. 31 is a cross-sectional view showing a mode of a high-frequency power module in which a configuration of a semiconductor wafer supporting a semiconductor wafer is smaller than that of a semiconductor wafer (a small-sized configuration) according to another embodiment (Embodiment 6) of the present invention. Fig. 3 is a plan view showing a mode of a part of a lead frame constructed using a small tab for manufacturing the high-frequency power module of the sixth embodiment. Fig. 3 is a cross-sectional view showing a mode of a high frequency power module of another modification of the small tab. Fig. 34 is a block diagram showing a 2-input differential amplifier circuit unit (LNA) for a mobile phone, and a block diagram including a 1-input differential amplifier circuit unit (LNA). -51 - (47) (47)1283471 [Description of Symbols] 1: Semiconductor device (high-frequency power module) 2: Sealed body (resin package) 2a: Bevel 2 b: Inclined surface 3: Semiconductor wafer 4: Tab (wafer mounting portion) 5: adhesive 6: tab suspension wire 7: wire 7a: mounting surface 7c: first portion 7d: second portion 9: electrode terminal 9a: first electrode terminal 9b: second electrode Terminal 1 0 : welding line l〇a: bonding welding line 1 0 b downward: welding line 11: specific circuit portion 1 3 : lead frame 1 4 : unit lead frame pattern 1 5 a to 1 5 c : guide hole 1 6 :Pole hole -52- (48) (48)1283471 1 7 :Pole hole 1 8 :Frame 2 0 : Antenna 2 1 : Antenna switch 22 : Baseband chip 23 : Band pass filter 24 : Low noise amplifier 25: Variable Amplifier 2 6 : Mixer
2 7、2 9、3 1、3 3 :低通濾波器 28、30、32: PGA 3 4 :解調器 35: ADC/DAC&DC偏移用控制邏輯電路部 3 6 :送•收訊系切換開關 3 7 :細縫 4 0 : 9 0度相位轉換器 41 : RF合成器 42: IF合成器 43:緩衝器 44: RFVCO 45: IFVCO 4 6' 47:分頻器 4 8 :開關 4 9 :開關 -53- (49) (49)12834712 7, 2 9, 3 1 , 3 3 : Low-pass filter 28, 30, 32: PGA 3 4 : Demodulator 35: ADC/DAC & DC offset control logic circuit unit 3 6: Send/receive System switch 3 7 : Slit 4 0 : 9 0 degree phase converter 41 : RF synthesizer 42 : IF synthesizer 43 : Buffer 44 : RFVCO 45 : IFVCO 4 6 ' 47 : Divider 4 8 : Switch 4 9 : Switch -53- (49) (49)1283471
50: VCXO 60:邏輯電路 6 1 :混頻器 62: 90度相位轉換器 6 3 :加法器 64:混頻器50: VCXO 60: Logic Circuit 6 1 : Mixer 62: 90 degree phase converter 6 3 : Adder 64: Mixer
65: DPD65: DPD
6 6 :迴圈濾波器 67: TXVCO 6 8 :功率模組 70:耦合器 7 1 :放大器 72:混頻器 8 0 :安裝基板 8 1 :銲墊 8 2 :固定部 8 3 :婷錫 85 :第1半導體基板 8 6 :絕緣層 87 :第2半導體基板 8 9 :絕緣層 100 :低雜訊放大器（LNA) 101 :高頻電壓控制振盪器（RFVCO) 1 〇 2 :混頻器 -54-6 6 : Loop filter 67: TXVCO 6 8 : Power module 70: Coupler 7 1 : Amplifier 72: Mixer 8 0 : Mounting substrate 8 1 : Pad 8 2 : Fixing part 8 3 : Ting tin 85 : 1st semiconductor substrate 8 6 : insulating layer 87 : 2nd semiconductor substrate 8 9 : insulating layer 100 : low noise amplifier (LNA) 101 : high frequency voltage controlled oscillator (RFVCO) 1 〇 2 : mixer - 54 -