WO2013051599A1 - Semiconductor device and production method for same - Google Patents

Semiconductor device and production method for same Download PDF

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Publication number
WO2013051599A1
WO2013051599A1 PCT/JP2012/075632 JP2012075632W WO2013051599A1 WO 2013051599 A1 WO2013051599 A1 WO 2013051599A1 JP 2012075632 W JP2012075632 W JP 2012075632W WO 2013051599 A1 WO2013051599 A1 WO 2013051599A1
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Prior art keywords
region
drain
pad
wires
pad electrode
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PCT/JP2012/075632
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French (fr)
Japanese (ja)
Inventor
智明 下石
亮太 佐藤
靜城 中島
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株式会社村田製作所
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Publication of WO2013051599A1 publication Critical patent/WO2013051599A1/en

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    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which a wire is connected to a pad of a semiconductor chip having an amplifying element and a technique effective when applied to the manufacturing thereof.
  • GSM registered trademark
  • PCS PCS method
  • PDC method PDC method
  • CDMA Code Division Multiple Access
  • this type of mobile communication device includes an antenna that emits and receives radio waves, a high-frequency power amplifier (RF power module) that amplifies a power-modulated high-frequency signal and supplies the signal to the antenna, and a high-frequency signal received by the antenna.
  • RF power module high-frequency power amplifier
  • a receiving unit that performs signal processing, a control unit that performs these controls, and a battery (battery) that supplies a power supply voltage thereto are configured.
  • Patent Document 1 describes a technique in which a bond pad has a probe region and a wire bond region that do not substantially overlap each other.
  • Patent Document 2 describes a technique in which a contact pad has a probe inspection region and a bonding region.
  • a semiconductor device such as a power amplification module is manufactured by mounting a semiconductor chip on a wiring board and electrically connecting pad electrodes of the semiconductor chip and terminals of the wiring board with wires.
  • a surface protective film and a pad electrode
  • a probe inspection is performed in the wafer state.
  • a probe probe
  • the semiconductor wafer is cut into individual pieces (chips) by dicing, and the obtained semiconductor chip is mounted on the wiring board, and wire bonding is performed between the pad electrode of the semiconductor chip and the terminal of the wiring board.
  • a probe mark which is a mark pressed by the probe, is formed on the pad electrode to which the probe for inspection is pressed.
  • wire bonding is performed after the semiconductor chip is mounted on the wiring board, if the wire is connected to the probe trace of the pad electrode, the wire is connected to an area where the flatness is lowered. Connection strength may be reduced. The reduction in the connection strength of the wires reduces the reliability of the manufactured semiconductor device.
  • the pad electrode it is also conceivable to divide the wire connection region and the region where the probe is pressed in the probe inspection process (probe mark).
  • the area of the semiconductor chip is increased by increasing the size of the pad electrode simply by separating the wire connection area and the area where the probe is pressed in the probe inspection process (probe marks). There is a risk of inviting.
  • An increase in the area of the semiconductor chip leads to an increase in manufacturing cost and is disadvantageous for downsizing of the semiconductor device.
  • An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.
  • an object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.
  • a semiconductor device is a semiconductor device including a semiconductor chip having a plurality of pad electrodes, and a plurality of wires connected to the plurality of pad electrodes.
  • This semiconductor chip has a first pad electrode connected to the output of the semiconductor element constituting the power amplifier circuit, and a plurality of first wires are connected to the first pad electrode.
  • Probe marks are formed between the connection regions of the plurality of first wires.
  • a plurality of pad electrodes of the semiconductor chip and a plurality of terminals of the wiring board are connected via a plurality of wires. Connect electrically.
  • This semiconductor chip has a first pad electrode connected to the output of the semiconductor element constituting the power amplifier circuit, and a plurality of first wires are connected to the first pad electrode in the wire bonding step. In the first pad electrode, a position where the probe is applied in the probe inspection process is located between positions where the plurality of first wires are connected in the Y bonding process.
  • the reliability of the semiconductor device can be improved.
  • the semiconductor device can be miniaturized.
  • FIG. 2 is a circuit block diagram schematically showing a configuration example of a power amplification module used in the digital mobile phone shown in FIG. 1. It is a top view which shows the power amplification module of one embodiment of this invention. It is a bottom view which shows the power amplification module of one embodiment of this invention. It is a plane perspective view which shows the power amplification module of one embodiment of this invention. It is sectional drawing which shows the power amplification module of one embodiment of this invention. It is a side view which shows the state which mounted the power amplification module of one embodiment of this invention on the mounting board
  • FIG. 10 is a cross-sectional view of the power amplification module during a manufacturing step following that of FIG. 9; It is sectional drawing in the manufacturing process of the power amplification module following FIG.
  • FIG. 12 is a cross-sectional view of the power amplification module during a manufacturing step following that of FIG. 11;
  • FIG. 13 is a cross-sectional view of the power amplification module during a manufacturing step following that of FIG. 12;
  • FIG. 6 is a partially enlarged plan view of FIG. 5.
  • FIG. 4 is an explanatory diagram showing probe marks formed on a drain pad of a semiconductor chip according to an embodiment of the present invention, and a wire connection region in the drain pad 3.
  • FIG. 4 is an explanatory diagram showing probe marks formed on a drain pad of a semiconductor chip according to an embodiment of the present invention, and a wire connection region in the drain pad 3.
  • FIG. It is sectional drawing which shows a mode that the probe for a test
  • hatching may be omitted even in a cross-sectional view in order to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.
  • a power amplification module such as a radio frequency (RF) power module
  • RF radio frequency
  • a digital mobile phone mobile communication device
  • a network such as the GSM system ( A semiconductor device) and a semiconductor chip (semiconductor device) used (mounted).
  • GSM Global System for Mobile Communication
  • GSM Global System for Mobile Communication
  • GSM900 Global System for Mobile Communication
  • GSM1800 the 1800 MHz band (1710 to 1910 MHz)
  • DCS Digital Cellular System
  • GSM1900 the 1900 MHz band
  • GSM1900 is mainly used in North America.
  • GSM850 in the 850 MHz band may also be used.
  • the power amplification module PA1 of the present embodiment is a power amplification module used in these frequency bands (high frequency bands), for example.
  • FIG. 1 is a block diagram (an explanatory diagram) showing an example of a standard digital cellular phone (digital cellular phone system, mobile communication device) DPS.
  • a signal received from an antenna ANT is amplified by a low noise amplifier LNA through an antenna switch ANT-SW, and an IF frequency of about 150 to 250 MHz by a reception mixer RX-MIX ( (Intermediate frequency), and further frequency converted by the IF circuit IFC, guided to the baseband unit BBP as a second IF frequency of about 455 kHz, and demodulated by the demodulation circuit DMDL.
  • code COD1 is an audio CODEC (codec)
  • code SP is a speaker
  • code MIC is a microphone
  • code COD2 is a channel CODEC (codec)
  • code MDL is a modulation circuit.
  • the digitalized signal is DA-converted (digital-analog conversion) by the D / A conversion circuit DAC of the baseband unit BBP, and is guided to the RF block unit RFBP as an I / Q signal, and is a quadrature modulator.
  • the digitalized signal After being modulated to an IF frequency by QMD and converted to a transmission signal by transmission mixer TX-MIX, it is amplified by power amplification module PA1 and transmitted from antenna ANT through antenna switch ANT-SW.
  • a local signal is supplied to the reception mixer RX-MIX and the transmission mixer TX-MIX from a synthesizer composed of an oscillator and a PLL (phase synchronization circuit).
  • a synthesizer composed of an oscillator and a PLL (phase synchronization circuit).
  • AGCAMP is an AGC (Automatic Gain Control) amplifier
  • symbol FPL1 is an RF-PLL (RF frequency phase synchronization circuit)
  • symbol FPL2 is an IF-PLL (IF frequency phase synchronization circuit).
  • the digital cellular phone DPS also includes a display / control unit CDP configured by a liquid crystal display LCD, a microcomputer MCN, a memory MRY, and the like.
  • FIG. 2 shows a power amplification module (semiconductor device, electronic device, power amplifier, high output amplifier, high frequency power amplifier, high frequency power amplification device) used in a mobile communication device such as the digital cellular phone DPS shown in FIG.
  • FIG. 2 is a circuit block diagram (explanatory diagram) schematically showing a configuration example of a power amplifier module, RF power module) PA1.
  • two frequency bands of GSM900 and DCS1800 can be used (dual band system), and GMSK (Gaussian filtered Minimum Shift Keying) modulation system and EDGE (Enhanced Data GSM Environment) modulation system in each frequency band.
  • the circuit block diagram (amplifier circuit) of the power amplification module which can use two communication systems is shown.
  • the GMSK modulation method is a method used for communication of audio signals, and is a method of shifting the phase of a carrier wave according to transmission data.
  • the EDGE modulation method is a method used for data communication and is a method in which an amplitude shift is further added to the phase shift of GMSK modulation.
  • the circuit configuration of the power amplifying module PA1 includes two power amplifying circuits (high frequency power amplifying circuits) LDML and LDMH, a peripheral circuit 103, matching circuits 105A, 105B, 107A, and 107B.
  • Low-pass filters (low-pass filter circuits) 108A and 108B and switch circuits 109A and 109B are provided.
  • the power amplifier circuit LDML is a power amplifier circuit for GSM900, and has a multi-stage configuration in which a plurality of amplifier stages (amplifier circuits), here, three amplifier stages (amplifier circuits) LDML1, LDML2, and LDML3 are connected in multistage.
  • the power amplifying circuit LDMH is a power amplifying circuit for DCS1800, and has a multi-stage configuration in which a plurality of amplifying stages (amplifying circuits), here, three amplifying stages (amplifying circuits) LDMH1, LDMH2, and LDMH3 are connected in multistage. Yes.
  • the matching circuit (input matching circuit) 105A is provided between the input terminal 104a for GSM900 and the power amplification circuit LDML (first amplification stage LDML1), and the matching circuit (input matching circuit) 105B is an input for DCS1800. It is provided between terminal 104b and power amplification circuit LDMH (first amplification stage LDMH1).
  • the matching circuit (output matching circuit) 107A is provided between the switch circuit 109A for GSM900 and the power amplifier circuit LDML (third amplifier stage LDML3), and the matching circuit (output matching circuit) 107B is a switch for DCS1800. It is provided between circuit 109B and power amplifier circuit LDMH (third amplifier stage LDMH3).
  • the low-pass filter 108A for GSM900 is provided between the matching circuit 107A and the switch circuit 109A for GSM900, and the output of the power amplifier circuit LDML is input via the matching circuit 107A.
  • the low pass filter 108B for DCS1800 is provided between the matching circuit 107B and the switch circuit 109B for DCS1800, and the output of the power amplifier circuit LDMH is input through the matching circuit 107B.
  • an interstage matching circuit 102AM1 is provided between the amplification stage LDML1 and the amplification stage LDML2 of the power amplification circuit LDML for GSM900, and an interstage matching circuit 102AM2 is provided between the amplification stage LDML2 and the amplification stage LDML3.
  • An interstage matching circuit 102BM1 is provided between the amplification stage LDMH1 and the amplification stage LDMH2 of the power amplification circuit LDMH for the DCS 1800, and an interstage matching circuit 102BM2 is provided between the amplification stage LDMH2 and the amplification stage LDMH3.
  • Each matching circuit is a circuit that performs impedance matching, and the low-pass filters 108A and 108B are circuits that attenuate harmonics (harmonic components generated by the power amplifier circuits LDML and LDMH).
  • the power amplification circuit LDML (amplification stages LDML1 to LDML3) for GSM900, the power amplification circuit LDMH for DCS1800 (amplification stages LDMH1 to LDMH3), and the peripheral circuit 103 are one semiconductor chip (semiconductor amplification element chip). , High frequency power amplifying element chip, semiconductor device) 2.
  • the amplification stages LDML1 to LDML3 constituting the power amplification circuit LDML and the amplification stages LDMH1 to LDMH3 constituting the power amplification circuit LDMH are formed in the semiconductor chip CP1, but the matching circuits 102AM1, 102AM2 for the stages are used.
  • 102BM1, 102BM2 may be formed inside the semiconductor chip CP1 or outside the semiconductor chip CP1.
  • the peripheral circuit 103 is a circuit for controlling and assisting the amplification operation of the power amplifier circuits LDML and LDMH, or controlling the switch circuits 109A and 109B, and the control circuits 103A and 103C, and the amplification stages LDML1 to LDML3 and LDMH1 to LDMH3. And a bias circuit 103B for applying a bias voltage to the.
  • the control circuit 103A is a circuit that generates a desired voltage to be applied to the power amplification circuits LDML and LDMH, and includes a power supply control circuit 103A1 and a bias voltage generation circuit 103A2.
  • the power supply control circuit 103A1 is a circuit that generates a first power supply voltage to be applied to the drain terminals of the output amplifying elements (in this case, LDMOSFETs) of the amplification stages LDML1 to LDML3 and LDMH1 to LDMH3.
  • the bias voltage generation circuit 103A2 is a circuit that generates a first control voltage for controlling the bias circuit 103B.
  • the bias voltage generation circuit 103A2 is generated by the power supply control circuit 103A1.
  • the first control voltage is generated based on the power supply voltage.
  • the baseband circuit is a circuit that generates the output level designation signal.
  • This output level designation signal is a signal that designates the output level of the power amplifier circuits LDML and LDMH, and is generated based on the distance between the mobile phone and the base station, that is, the output level corresponding to the strength of the radio wave. It is like that.
  • the control circuit 103C is a circuit that controls the switch circuits 109A and 109B.
  • the switch circuit 109A for transmission / reception switching of the GSM900 connects the terminal (output terminal) 106 to the output side of the low-pass filter 108A when transmitting the GSM900 and connects the terminal 106 when receiving the GSM900.
  • terminal 110a The switch circuit 109B for transmission / reception switching of the DCS 1800 connects the terminal 106 to the output side of the low-pass filter 108B during transmission of the DCS 1800, and connects the terminal 106 to the terminal 110b during reception of the DCS 1800 according to the switching signal from the control circuit 103C. Connect to.
  • the RF input signal input to the GSM900 input terminal 104a of the power amplifier module PA1 is input to the semiconductor chip CP1 via the matching circuit 105A, and the power amplifier circuit LDML in the semiconductor chip CP1, that is, the three amplification stages LDML1 to LDML3. And output as an RF signal (GSM900 RF signal) amplified from the semiconductor chip CP1.
  • the RF signal of GSM900 amplified and output from the semiconductor chip CP1 is input to the switch circuit 109A through the matching circuit 107A and the low-pass filter 108A.
  • the switch circuit 109A When the switch circuit 109A is switched so as to connect the terminal 106 to the output side of the low-pass filter 108A, the RF signal input to the switch circuit 109A via the low-pass filter 108A is output as an RF output signal of the GSM900 from the terminal 106. And transmitted from the antenna ANT.
  • the RF input signal input to the DCS 1800 input terminal 104b of the power amplifier module PA1 is input to the semiconductor chip CP1 through the matching circuit 105B, and the power amplifier circuit LDMH in the semiconductor chip CP1, that is, the three amplification stages LDMH1. Amplified by LDMH3 and output from the semiconductor chip CP1 as an RF signal (DCS1800 RF signal).
  • the RF signal of DCS 1800 amplified and output from the semiconductor chip CP1 is input to the switch circuit 109B through the matching circuit 107B and the low-pass filter 108B.
  • the switch circuit 109B switches so that the terminal 106 is connected to the output side of the low-pass filter 108B, the RF signal input to the switch circuit 109B via the low-pass filter 108B is output from the terminal 106 as the RF output signal of the DCS 1800. And transmitted from the antenna ANT.
  • an input signal (for example, a control signal) input to the input terminal 104c of the power amplification module PA1 is input to the peripheral circuit 103, and based on this, the peripheral circuit 103 controls the power amplification circuits LDML and LDMH.
  • the switch circuits 109A and 109B can be controlled.
  • the switch circuits 109A and 109B correspond to the antenna switch ANT-SW in FIG. 1, and the power amplification module PA1 shown in FIG. 2 is the same as the antenna switch ANT-SW in FIG. This corresponds to the case where it is built in PA1.
  • the antenna switch ANT-SW can be provided outside the power amplification module PA1, and in this case, the switch circuits 109A and 109B are provided outside the power amplification module PA1.
  • the low-pass filters (low-pass filter circuits) 108A and 108B can be provided outside the power amplification module PA1.
  • Each of the power amplifier circuits LDML and LDMH is composed of three n-channel LDMOSFETs (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor, lateral diffusion MOSFET) ) Are sequentially connected in cascade (multi-stage connection). That is, each amplification stage LDML1, LDML2, LDML3, LDMH1, LDMH2, and LDMH3 are formed by n-channel LDMOSFET elements.
  • n-channel LDMOSFETs that is, an n-channel LDMOSFET constituting the amplification stage LDML1, an n-channel LDMOSFET constituting the amplification stage LDML2, and an n-channel LDMOSFET constituting the amplification stage LDML3 are sequentially connected (multistage connection). ) To form a power amplifier circuit LDML.
  • the input terminal 104a for GSM900 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDML1 via the matching circuit 105A, and the n-channel LDMOSFET constituting the amplification stage LDML1 is electrically connected.
  • the drain is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDML2 through the matching circuit 102AM1.
  • the drain of the n-channel LDMOSFET constituting the amplification stage LDML2 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDML3 via the matching circuit 102AM2, and the n-channel constituting the amplification stage LDML3.
  • the drain of the type LDMOSFET is electrically connected to the low-pass filter 108A through the matching circuit 107A.
  • n-channel LDMOSFETs that is, an n-channel LDMOSFET constituting the amplification stage LDMH1, an n-channel LDMOSFET constituting the amplification stage LDMH2, and an n-channel LDMOSFET constituting the amplification stage LDMH3 are sequentially connected (multi-stage connection). ) To form a power amplifier circuit LDMH.
  • the input terminal 104b for DCS1800 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDMH1 via the matching circuit 105B, and the n-channel LDMOSFET constituting the amplification stage LDMH1 is connected.
  • the drain is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDMH2 through the matching circuit 102BM1.
  • the drain of the n-channel LDMOSFET constituting the amplification stage LDMH2 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDMH3 via the matching circuit 102BM2, and the n-channel constituting the amplification stage LDMH3.
  • the drain of the type LDMOSFET is electrically connected to the low-pass filter 108B through the matching circuit 107B.
  • each power amplifier circuit LDML, LDMH is subordinate to two or four or more n-channel LDMOSFETs. Connected circuit configuration.
  • FIG. 3 is a top view (plan view) of the power amplification module PA1 of the present embodiment
  • FIG. 4 is a bottom view of the power amplification module PA1
  • FIG. 5 is a plan perspective view of the power amplification module PA1.
  • FIG. 6 is a cross-sectional view (side cross-sectional view) of power amplification module PA1 of the present embodiment. 6 corresponds to a cross-sectional view
  • FIG. 5 corresponds to a plan view, both of which show a conceptual structure of the power amplification module PA1.
  • FIG. 6 is a cross-sectional view of the structure of FIG. Is not completely consistent with the cross-sectional view.
  • a power amplification module PA1 of the present embodiment shown in FIGS. 3 to 6 includes a wiring board (multilayer board, multilayer wiring board, module board) 11 and a semiconductor chip (semiconductor) mounted (mounted) on the wiring board 11.
  • a resin (sealing portion, sealing resin portion) 13 The semiconductor chip CP1 and the passive component 12 are electrically connected to the conductor layer (transmission line) of the wiring board 11.
  • the power amplification module PA1 can also be mounted on, for example, an external circuit board (not shown) or a motherboard.
  • the power amplification module PA1 can be regarded as a semiconductor device because it includes the semiconductor chip CP1, but can also be regarded as an electronic device.
  • the wiring board 11 is, for example, a multilayer wiring board (multilayer board) in which a plurality of insulator layers (dielectric layers) 14 and a plurality of conductor layers (wiring layers) are stacked and integrated.
  • the five insulating layers 14 are laminated to form the wiring board 11.
  • the number of the insulating layers 14 to be laminated is not limited to this and can be variously changed.
  • Each conductor layer (wiring layer) 15 constituting the wiring board 11 is electrically connected through a conductor (conductor film) in a via hole (through hole) 16 formed in the insulator layer 14 as necessary.
  • the wiring board 11 As a material for forming the insulator layer 14 of the wiring substrate 11, a ceramic material such as alumina (aluminum oxide, Al 2 O 3 ) can be used.
  • the wiring board 11 is a ceramic multilayer board.
  • the material of the insulator layer 14 of the wiring board 11 is not limited to a ceramic material and can be variously changed. For example, a glass epoxy resin may be used.
  • a conductor layer (wiring layer, wiring pattern, conductor pattern) 15 for wiring formation is formed on the upper surface (front surface) 11a and the lower surface (back surface) 11b of the wiring substrate 11 and between the insulator layers 14.
  • a conductor-side board (terminal, electrode) TE made of a conductor and a chip mounting conductor pattern 15 c are formed on the upper surface 11 a of the wiring board 11 by the uppermost conductor layer 15 of the wiring board 11, and the lowermost layer of the wiring board 11.
  • the conductor layer 15 forms an external connection terminal (terminal, electrode, module electrode) 15 a made of a conductor and a reference potential supply terminal 15 b on the lower surface 11 b of the wiring board 11.
  • the external connection terminal 15 a includes terminals corresponding to the input terminals 104 a, 104 b, and 104 c and terminals corresponding to the terminals (output terminals) 106.
  • a conductor layer (wiring layer, wiring pattern, conductor pattern) 15 is also formed in the wiring substrate 11, that is, between the insulator layers 14.
  • the wiring pattern for supplying the reference potential (for example, the reference potential supplying terminal 15 b on the lower surface 11 b of the wiring substrate 11) is the wiring of the insulator layer 14.
  • the wiring pattern for the transmission line can be formed as a band-shaped pattern, with a rectangular pattern covering most of the formation surface.
  • the semiconductor chip CP1 is formed by forming a semiconductor integrated circuit on a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like, and then grinding the back surface of the semiconductor substrate as necessary, and then dicing or the like to each semiconductor chip CP1. It is separated.
  • a plurality of pad electrodes (electrodes, bonding pads) PD are formed on the surface (upper surface) of the semiconductor chip CP1, and each pad electrode PD is electrically connected to a semiconductor element or a semiconductor integrated circuit formed in the semiconductor chip CP1. Connected.
  • the configuration of the semiconductor chip CP1 will be described in detail later.
  • the principal surface on the side where the pad electrode PD is formed is referred to as the surface of the semiconductor chip CP1
  • the principal surface on the side where the pad electrode PD is formed is referred to as the surface of the semiconductor chip CP1
  • the principal surface on the side where the pad electrode PD is formed is referred to as the back surface of the semiconductor chip CP1.
  • the semiconductor chip CP1 is die-bonded (bonded) to the chip mounting conductor pattern 15c on the upper surface 11a of the wiring substrate 11 with a bonding material (adhesive material) such as solder 18 face up.
  • a bonding material such as solder 18 face up.
  • a conductive paste adhesive such as silver paste can be used.
  • the pad electrode PD formed on the surface (upper surface) of the semiconductor chip CP1 is electrically connected to the substrate-side terminal TE on the upper surface 11a of the wiring substrate 11 through a conductive wire (bonding wire) WA.
  • a back electrode BE1 is formed on the entire back surface of the semiconductor chip CP1, and the back electrode BE1 of the semiconductor chip CP1 is electrically conductive such as solder 18 on the chip mounting conductor pattern 15c on the top surface 11a of the wiring substrate 11. Bonded by a bonding material and electrically connected, and further electrically connected to a reference potential supply terminal 15b on the lower surface 11b of the wiring substrate 11 via a conductor in the via hole 16 (16a).
  • the via hole 16a provided below the semiconductor chip CP1 can also function as a thermal via for conducting heat generated in the semiconductor chip CP1 to the lower surface 11b side of the wiring substrate 11.
  • the passive component 12 is composed of a passive element such as a resistive element (for example, a chip resistor), a capacitive element (for example, a chip capacitor), or an inductor element (for example, a chip inductor), for example, a chip component.
  • the passive component 12 is a passive component that constitutes the matching circuits 105A, 105B, 107A, 107B, 102AM1, 102AM2, 102BM1, and 102BM2, for example.
  • the electrodes of the passive component 12 are joined and electrically connected to the board-side terminal TE on the upper surface 11a of the wiring board 11 by a conductive joining material such as solder 18.
  • the board-side terminal TE on the upper surface 11a of the wiring board 11 to which the semiconductor chip CP1 or the passive component 12 is electrically connected is connected to the upper surface 11a of the wiring board 11 or an internal conductor layer (wiring layer) 15 or via hole 16 as necessary.
  • the wiring is connected via an internal conductor or the like, and is electrically connected to the external connection terminal 15a or the reference potential supply terminal 15b on the lower surface 11b of the wiring board 11 as necessary.
  • solder resist layer (not shown) is formed on the upper surface 11a and the lower surface of the wiring substrate 11.
  • the terminal TE is exposed from the opening of the solder resist layer.
  • the external connection terminal 15 a and the reference potential supply terminal 15 b are exposed from the solder resist layer.
  • the sealing resin 13 is formed on the upper surface 11a of the wiring board 11 so as to cover the semiconductor chip CP1, the passive component 12, and the wire WA.
  • the sealing resin 13 is made of, for example, a resin material such as an epoxy resin or a silicone resin, and can contain a filler or the like.
  • FIG. 7 is a side view schematically showing a state in which the power amplification module PA1 of the present embodiment is mounted on a mounting board (wiring board, motherboard, external circuit board) 21.
  • FIG. 7 is a side view schematically showing a state in which the power amplification module PA1 of the present embodiment is mounted on a mounting board (wiring board, motherboard, external circuit board) 21.
  • FIG. 7 is a side view schematically showing a state in which the power amplification module PA1 of the present embodiment is mounted on a mounting board (wiring board, motherboard, external circuit board) 21.
  • the power amplification module PA1 and other components 22 are mounted on the upper surface 21a of the mounting substrate 21.
  • the external connection terminal 15a of the power amplification module PA1 is joined and electrically connected to the terminal 23a of the mounting substrate 21 via a conductive joining material such as solder 24, and the reference of the power amplification module PA1.
  • the potential supply terminal 15b is joined to and electrically connected to a terminal (reference potential supply terminal) 23b of the mounting substrate 21 via a conductive joining material such as solder 24.
  • the electrodes of the component 22 are joined and electrically connected to the terminals 23 c of the mounting substrate 21 via a conductive joining material such as solder 24. Therefore, a reference potential (ground potential, ground potential) is supplied from the terminal (reference potential supply terminal) 23b of the mounting substrate 21 to the power amplification module PA1 via the solder 24 and the reference potential supply terminal 15b. it can.
  • FIG. 8 is a process flow diagram showing the manufacturing process of the power amplification module PA1.
  • 9 to 13 are cross-sectional views of the power amplification module PA1 according to the present embodiment during the manufacturing process.
  • the power amplification module PA1 of the present embodiment can be manufactured, for example, as follows.
  • a wiring board base (wiring board) 25 is prepared as a wiring board (step S1 in FIG. 8).
  • the wiring board base body 25 becomes the wiring board 11 after a cutting process described later, and can be manufactured using, for example, a printing method, a sheet lamination method, a build-up method, or the like. Further, the upper surface 25a of the wiring board base body 25 becomes the upper surface 11a of the wiring board 11 after a cutting process described later.
  • the semiconductor chip CP1 is prepared (Step S2 in FIG. 8).
  • the step of preparing the semiconductor chip CP1 in step S2 may be performed before, after, or simultaneously with the step of preparing the wiring board base 25 in step S1.
  • the preparation process of the semiconductor chip CP1 in step S2 includes steps S11, S12, and S13 described later.
  • the chip mounting conductor pattern 15c on which the semiconductor chip CP1 is to be mounted and the board-side terminal TE on which the passive component 12 is to be mounted are connected to solder or the like.
  • the bonding material is printed or applied as necessary.
  • the semiconductor chip CP1 and the passive component 12 are mounted (arranged) on the upper surface 25a of the wiring board mother body 25 (step S3 in FIG. 8).
  • the wiring board is arranged such that the back side (back side electrode BE1 side) faces downward (wiring board base 25 side) and the front side (pad electrode PD side) faces upward (face-up bonding).
  • the semiconductor chip CP1 and the passive component 12 are fixed (bonded, connected, fixed) to the wiring board base 25 via a bonding material such as solder 18 (step S4 in FIG. 8).
  • the solder melted and solidified by the solder reflow becomes the solder 18.
  • the mounting process of the passive component 12 on the wiring board base 25 and the mounting process of the semiconductor chip CP1 on the wiring board 25 can be performed separately.
  • the wiring board base 25 After the passive component 12 is mounted and fixed with a bonding material such as solder, the semiconductor chip CP1 can be mounted on the wiring board base 25 and fixed with a bonding material (such as solder or a conductive paste adhesive). .
  • a wire bonding step is performed to connect a plurality of pad electrodes PD on the surface of the semiconductor chip CP1 and a plurality of substrate-side terminals TE on the upper surface 25a of the wiring board base 25 to a plurality of wires ( Bonding wires) are electrically connected via WA (step S5 in FIG. 8).
  • the sealing resin (sealing part, sealing resin part) 13 is formed on the upper surface 25a of the wiring board base 25 so as to cover the semiconductor chip CP1, the passive component 12, and the wire WA.
  • the sealing resin 13 can be formed using, for example, a printing method or a mold for molding (for example, transfer mold) (step S6 in FIG. 8).
  • the power amplification module PA1 can be manufactured by cutting the wiring board base 25 and the sealing resin 13 by dicing or the like (step S7 in FIG. 8).
  • the wiring board matrix 25 after cutting becomes the wiring board 11.
  • FIG. 14 is a partially enlarged plan view of FIG. 5 and shows an enlarged view of the semiconductor chip CP1 mounted on the wiring board 11 and its peripheral region.
  • FIG. 15 is a plan view in which the wire WA and the substrate-side terminal TE are omitted from FIG. 14, and corresponds to a plan view (planar layout diagram) of the semiconductor chip CP1.
  • a region in which the LDMOSFET element constituting the first amplification stage LDML1 for GSM900 is formed is denoted as a LDMOSFET formation region REGL1 with a reference sign REGL1, and the region for GSM900 is used.
  • a region in which the LDMOSFET elements constituting the second amplification stage LDML2 are formed is denoted by a reference sign REGL2 and is indicated as an LDMOSFET formation region REGL2.
  • a region in which the LDMOSFET elements constituting the third (final) amplification stage LDML3 for GSM900 are formed is denoted by the reference numeral REGL3 and indicated as an LDMOSFET formation region REGL3.
  • the region where the LDMOSFET element constituting the first amplification stage LDMH1 for DCS1800 is formed is denoted by the reference numeral REGH1, and is indicated as LDMOSFET formation region REGH1, and the second amplification stage LDMH2 for DCS1800 is constituted.
  • a region where the LDMOSFET element is formed is indicated as a LDMOSFET formation region REGH2 with a reference sign REGH2.
  • a region in which the LDMOSFET elements constituting the third (final) amplification stage LDMH3 for DCS1800 are formed is denoted by reference numeral REGH3 and is indicated as an LDMOSFET formation region REGH3.
  • the semiconductor chip CP1 also has a region in which elements constituting the peripheral circuit 103 such as a capacitor element, a resistance element, or a control MOSFET are formed. This region is illustrated in FIGS. Is omitted.
  • a plurality of pad electrodes PD are formed on the surface of the semiconductor chip CP1.
  • the pad electrodes PD are drain pads (drain pad electrodes) PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 which are drain pad electrodes PD and gate pads (gate pad electrodes) PDG1, which are gate pad electrodes PD.
  • PDG2, PDG3, PDG4, PDG5, PDG6 are included.
  • the pad electrode PD includes a pad electrode PD1 for use in inputting a control signal, outputting a detection signal, and the like.
  • the gate pad PDG1 is an input pad electrode (pad electrode for inputting an RF signal through the matching circuit 105A) electrically connected to the gate electrode of the LDMOSFET formation region REGL1.
  • the drain pad PDD1 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGL1) electrically connected to the drain of the LDMOSFET formation region REGL1.
  • the gate pad PDG2 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit 102AM1) electrically connected to the gate electrode of the LDMOSFET formation region REGL2.
  • the drain pad PDD2 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGL2) electrically connected to the drain of the LDMOSFET formation region REGL2.
  • the gate pad PDG3 is an input pad electrode (pad electrode for inputting an RF signal through the matching circuit 102AM2) electrically connected to the gate electrode of the LDMOSFET formation region REGL3.
  • the drain pad PDD3 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGL3) electrically connected to the drain of the LDMOSFET formation region REGL3.
  • the gate pad PDG4 is an input pad electrode (pad electrode for inputting an RF signal through the matching circuit 105B) electrically connected to the gate electrode of the LDMOSFET formation region REGH1.
  • the drain pad PDD4 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGH1) electrically connected to the drain of the LDMOSFET formation region REGH1.
  • the gate pad PDG5 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit 102BM1) electrically connected to the gate electrode of the LDMOSFET formation region REGH2.
  • the drain pad PDD5 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGH2) electrically connected to the drain of the LDMOSFET formation region REGH2.
  • the gate pad PDG6 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit 102BM2) electrically connected to the gate electrode of the LDMOSFET formation region REGH3.
  • the drain pad PDD6 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGH3) electrically connected to the drain of the LDMOSFET formation region REGH3.
  • the regions where the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, and REGH3 are formed and the regions where the elements for the control circuit are formed are buried oxides formed between the regions. Each element is electrically isolated from other regions by element isolation regions (corresponding to element isolation regions 32 described later) made of a film or the like. Further, the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, REGH3 and the region where the elements for the control circuit are formed, and between them and the pad electrode PD, the inside of the semiconductor chip CP1 as necessary. It is electrically connected by wiring.
  • the semiconductor chip CP1 has a rectangular planar shape having the four sides (chip sides) SD1, SD2, SD3, and SD4.
  • the side SD1 and the side SD3 are parallel to and face each other, and the side SD2 And the side SD4 are parallel to each other and face each other, the side SD1 and the side SD2 are orthogonal, the side SD1 and the side SD4 are orthogonal, the side SD3 and the side SD2 are orthogonal, and the side SD3 and the side SD4 are orthogonal is doing.
  • the plurality of pad electrodes PD are arranged on the periphery of the surface of the semiconductor chip CP1.
  • the drain pad PDD3, the gate pad PDG3, the drain pad PDD2, the gate pad PDG2, the drain pad PDD1, and the gate pad PDG1 are arranged along the side SD1 in this order.
  • the drain pad PDD6, the gate pad PDG6, the drain pad PDD5, the gate pad PDG5, the drain pad PDD4, and the gate pad PDG4 are arranged along the side SD3 in this order.
  • the LDMOSFET formation regions REGL3, REGL2, and REGL1 are disposed on the side SD1 side, and the LDMOSFET formation regions REGH3, REGH2, and REGH1 are disposed on the side SD3 side.
  • the drain pad PDD3 is located between the LDMOSFET formation region REGL3 and the side SD1
  • the drain pad PDD2 is located between the LDMOSFET formation region REGL2 and the side SD1
  • a drain pad PDD1 is located between the two.
  • the drain pad PDD6 is located between the LDMOSFET formation region REGH3 and the side SD3
  • the drain pad PDD5 is located between the LDMOSFET formation region REGH2 and the side SD3
  • a drain pad PDD4 is located between SD3 and SD3.
  • FIG. 16 is a cross-sectional view of a main part of the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, and REGH3 in the semiconductor chip CP1.
  • 17 shows a cross-sectional position different from that in FIG. 16, and corresponds to a cross-sectional view of a region where the gate electrode 35 is pulled up to the gate wirings M1G and M2G on the element isolation region 32.
  • FIG. 18 shows a cross-sectional position different from that in FIGS.
  • FIG. 16 and 17 shows cross-sectional positions different from those in FIGS. 16 to 18, and corresponds to a cross-sectional view of a region where the gate pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6 are formed.
  • FIG. 20 shows a cross-sectional position different from that in FIGS. 16 to 19 and corresponds to a cross-sectional view of a region where the drain pads PDD3 and PDD6 are formed.
  • a semiconductor substrate (hereinafter simply referred to as a substrate) 31 constituting the semiconductor chip CP1 includes a substrate body (semiconductor substrate, semiconductor wafer) 31a made of p + -type single crystal silicon, and the like. And an epitaxial layer (semiconductor layer) 31b made of, for example, p ⁇ type single crystal silicon, formed on the main surface of the substrate body 31a. For this reason, the substrate 31 is a so-called epitaxial wafer.
  • the epitaxial layer 31b is a semiconductor layer
  • the impurity concentration of the epitaxial layer 31b is lower than the impurity concentration of the substrate body 31a
  • the resistivity of the epitaxial layer 31b is higher than the resistivity of the substrate body 31a.
  • An element isolation region 32 made of an insulator is formed in the epitaxial layer 31b. 16 corresponds to a cross-sectional view crossing an active region (corresponding to an active region AR1 described later) surrounded by the element isolation region 32, the element isolation region 32 is not shown in FIG. 17 to 20 correspond to cross-sectional views across the element isolation region 32 surrounding the active region, so that the element isolation region 32 is shown in FIGS. 17 to 20.
  • the element isolation region 32 is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method.
  • the element isolation region 32 defines an active region AR1 described later on the main surface of the substrate body 31a (main surface of the epitaxial layer 31b), and a plurality of LDMOSFET cells (unit LDMOSFET elements) are formed in the active region AR1.
  • the active region AR1 is surrounded by the element isolation region 32.
  • a p-type well 33 that functions as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET is formed on a part of the main surface of the epitaxial layer 31b.
  • a gate electrode 35 of the LDMOSFET is formed via a gate insulating film 34 made of silicon oxide or the like.
  • the gate electrode 35 is made of, for example, a single film of an n-type polycrystalline silicon film or a laminated film of an n-type polycrystalline silicon film and a metal silicide film, and a side wall made of silicon oxide or the like is formed on the side wall of the gate electrode 35.
  • a wall spacer (side wall insulating film) 36 is formed.
  • the source and drain of the LDMOSFET are formed in regions separated from each other across the channel formation region (region immediately below the gate electrode 35) inside the epitaxial layer 31b. Drain first n in contact with the channel forming region - -type drain region 37, the first n - -type drain region 38 - -type drain region in contact with the second n which is spaced apart from the channel forming region And an n + type drain region (drain high concentration region, high concentration n type drain region) 39 formed in contact with the second n ⁇ type drain region and further away from the channel formation region.
  • the first n ⁇ -type drain region 37 closest to the gate electrode 35 has the highest impurity concentration.
  • the n + -type drain region 39 which is low and is most distant from the gate electrode 35 has the highest impurity concentration.
  • the junction depth of the second n ⁇ -type drain region 38 is substantially the same as the junction depth of the first n ⁇ -type drain region 37, but the n + -type drain region 39 has the second n ⁇ -type drain. It is formed shallower than the drain region 38 and the first n ⁇ -type drain region 37.
  • the first n ⁇ -type drain region (first low-concentration n-type drain region, first n-type LDD region) 37 is formed in a self-aligned manner with respect to the gate electrode 35, and its end is a channel formation region It terminates at the bottom of the side wall of the gate electrode 35 so as to come into contact.
  • the second n ⁇ -type drain region (second low-concentration n-type drain region, second n-type LDD region) 38 is formed with respect to the side wall spacer 36 formed on the side wall on the drain side of the gate electrode 35. Therefore, it is formed so as to be separated from the gate electrode 35 by an amount corresponding to the film thickness of the sidewall spacer 36 along the gate length direction.
  • the source of the LDMOSFET is n ⁇ -type source region 40 in contact with the channel formation region, and is in contact with the n ⁇ -type source region 40, spaced apart from the channel formation region, and has an impurity concentration higher than that of the n ⁇ -type source region 40. And a + type source region 41.
  • the n ⁇ -type source region 40 is formed in a self-aligned manner with respect to the gate electrode 35, and terminates at the lower portion of the side wall of the gate electrode 35 so that the end thereof is in contact with the channel formation region.
  • a p-type halo region (not shown) can be formed below the n ⁇ -type source region 40, and this p-type halo region is not necessarily formed, but when formed, The spread of impurities from the source to the channel formation region is further suppressed, and the short channel effect is further suppressed, so that the threshold voltage can be further prevented from decreasing.
  • the n + type source region 41 is formed in a self-aligned manner with respect to the side wall spacer 36 formed on the source side wall of the gate electrode 35, the n + type source region 41 is an n ⁇ type source region. 40, and is spaced apart from the channel formation region by an amount corresponding to the film thickness of the sidewall spacer 36 along the gate length direction.
  • the position of the bottom of the n + -type source region 41 is deeper than the position of the bottom of the n ⁇ -type source region 40.
  • the lightly doped n-type drain region (n-type LDD region) interposed between the gate electrode 35 and the n + -type drain region 39 has a double structure, and the first n ⁇ -type closest to the gate electrode 35 is formed.
  • the impurity concentration of the drain region 37 is relatively low, and the impurity concentration of the second n ⁇ -type drain region 38 spaced from the gate electrode 35 is relatively high.
  • a depletion layer spreads between the gate electrode 35 and the drain.
  • the feedback capacitance (Cgd) formed between the gate electrode 35 and the first n ⁇ -type drain region 37 in the vicinity thereof is reduced. Get smaller.
  • the impurity concentration of the second n ⁇ -type drain region 38 is high, the on-resistance (Ron) is also reduced. Since the second n ⁇ -type drain region 38 is formed at a position separated from the gate electrode 35, the influence on the feedback capacitance (Cgd) is small. For this reason, since both the on-resistance (Ron) and the feedback capacitance (Cgd) can be reduced, the power added efficiency of the amplifier circuit can be improved.
  • the MOSFET or LDMOSFET is not only a MISFET using an oxide film (silicon oxide film) as a gate insulating film, but also a MISFET using an insulating film other than an oxide film (silicon oxide film) as a gate insulating film. Shall also be included.
  • the LDMOSFET is a MISFET (Metal-Insulator-Semiconductor-Field-Effect-Transistor) element, and is a MISFET element having the following characteristics (first to third characteristics).
  • MISFET Metal-Insulator-Semiconductor-Field-Effect-Transistor
  • the LDMOSFET has an LDD (Lightly doped drain) region formed on the drain side of the gate electrode 35 in order to enable a high voltage operation with a short channel length. That is, the drain of the LDMOSFET has a high impurity concentration n + -type region (here, n + -type drain region 39) and a lower impurity concentration LDD region (here, the first n ⁇ -type drain region 37 and the first n - type drain region 37). 2 n ⁇ -type drain region 38), and the n + -type region (n + -type drain region 39) is separated from the gate electrode 35 (or the channel formation region below the gate electrode 35) via the LDD region. Is formed.
  • LDD Lightly doped drain
  • Charge amount (impurity concentration) in the LDD region on the drain side, and distance along the plane (main surface of the epitaxial layer 31b) between the end of the gate electrode 35 and the n + -type drain region (drain high concentration region) 39 must be optimized to maximize the breakdown voltage of the LDMOSFET.
  • the LDMOSFET has a p-type well (p-type base region) for punch-through stoppers in a source-side source formation region (n ⁇ -type source region 40 and n + -type source region 41) and a channel formation region. ) 33 is formed.
  • the p-type well 33 is not formed, or is formed only in contact with a part of the drain formation region closer to the channel region.
  • the LDMOSFET has a source (here, a source region composed of an n ⁇ type source region 40 and an n + type source region 41) and a drain (here, a first n ⁇ type drain region 37, a second n ⁇ type source region 41).
  • the drain region composed of the ⁇ type drain region 38 and the n + type drain region 39) has an asymmetric structure with respect to the gate electrode 35.
  • the p-type punching layer 44 is a conductive layer for electrically connecting the source of the LDMOSFET and the substrate body 31a, and is formed of, for example, a p-type polycrystalline silicon film embedded in a groove formed in the epitaxial layer 31b.
  • the tip (bottom) of the p-type punching layer 44 reaches the substrate body 31a.
  • the p-type punching layer 44 can also be formed by a metal layer embedded in a groove formed in the substrate 31.
  • An insulating film (interlayer insulating film) 46 is formed on the main surface of the epitaxial layer 31b so as to cover the gate electrode 35 and the sidewall spacers 36.
  • the insulating film 46 is made of, for example, a laminated film of a thin silicon nitride film and a thick silicon oxide film thereon. The upper surface of the insulating film 46 is planarized.
  • a contact hole (opening, through hole, through hole) 47 is formed in the insulating film 46, and a plug (a buried conductor for connection) 48 mainly composed of a tungsten (W) film is embedded in the contact hole 47. It is.
  • the contact hole 47 and the plug 48 filling the contact hole 47 are formed of a p-type punch layer 44 (p + -type semiconductor region 45), a source (n + -type source region 41), a drain (n + -type drain region 39), and a gate electrode 35. It is formed at the top of each.
  • a wiring (first layer wiring) M1 made of a conductor film (tungsten film) mainly composed of tungsten (W) or the like is formed on the insulating film 46 in which the plug 48 is embedded.
  • the wiring M1 is formed by patterning a conductor film (tungsten film) formed on the insulating film 46 in which the plug 48 is embedded.
  • the wiring M1 is not limited to the tungsten wiring, and may be a wiring using another metal material such as an aluminum wiring.
  • the wiring M1 includes a source wiring (source electrode) M1S electrically connected to both the n + -type source region 41 and the p + -type semiconductor region 45 through the plug 48, and an n + -type drain region 39 through the plug 48.
  • a through hole (opening, through hole) 50 exposing a part of the wiring M1 at the bottom is formed.
  • a wiring M2 made of a conductor film mainly composed of aluminum (Al) or an aluminum alloy is formed on the insulating film 49 including the inside of the through hole 50.
  • the wiring M2 includes a barrier conductor film (for example, a laminated film of a titanium film and a titanium nitride film), an aluminum film (or an aluminum alloy film), and a barrier conductor film (for example, a titanium film) on the insulating film 49 including the inside of the through hole 50. And a titanium nitride film) is formed by patterning the conductor film.
  • the upper and lower barrier conductor films are thinner than the aluminum film as the main conductor film.
  • the barrier conductor film below the aluminum film in the laminated film has a function of suppressing a reaction between the aluminum film and the lower wiring M1, a function of improving the adhesion between the wiring M2 and the insulating film 49, and the like. Yes.
  • the barrier conductor film on the upper side of the aluminum film in the laminated film has a function of improving the adhesion between the wiring M2 and the insulating film (surface protective film) 52 and a function as an antireflection film at the time of exposure in the photolithography process. Etc.
  • the wiring M2 extends on the insulating film 49, partially fills the through hole 50, and is electrically connected to the wiring M1 at the bottom of the through hole 50. Therefore, the wiring M2 is integrally formed with a wiring portion extending on the insulating film 49 and a via portion (connecting portion) filling the through hole 50.
  • the wiring M2 is electrically connected to the drain wiring M2D that is electrically connected to the drain wiring M1D via the via portion (the portion that fills the through hole 50) and to the gate wiring M1G via the via portion (the portion that fills the through hole 50). And a source wiring M2S electrically connected to the source wiring M1S through a via portion (a portion filling the through hole 50).
  • a plug similar to the plug 48 is embedded in the through hole 50, a conductor film for forming the wiring M2 is formed on the insulating film 49 in which the plug is embedded, and the conductor film is patterned.
  • the wiring M2 can be formed.
  • the wiring M2 is electrically connected to the wiring M1 through a plug filling the through hole 50.
  • An insulating film (surface protective film) 52 is formed on the insulating film 49 so as to cover the wiring M2.
  • the insulating film 52 is made of, for example, a laminated film of a silicon oxide film and a silicon nitride film thereon, and can function as a protective film on the outermost surface of the semiconductor chip CP1.
  • An opening (through hole, through hole) 53 for a pad electrode is formed in the insulating film 52, and the wiring M ⁇ b> 2 is exposed at the bottom of the opening 53. That is, an opening 53 is formed on the wiring M2, and a part of the wiring M2 is exposed from the opening 53.
  • the wiring M2 exposed from the opening 53 corresponds to the pad electrode PD. That is, the pad electrode PD is formed by the wiring M2 exposed from the opening 53.
  • the opening 53 formed on the drain wiring M2D and exposing a part of the drain wiring M2D is referred to as a drain pad opening 53D.
  • the opening 53 is formed on the gate wiring M2G and is a part of the gate wiring M2G.
  • the opening that exposes is referred to as a gate pad opening 53G.
  • the drain wiring M2D exposed from the drain pad opening 53D corresponds to the drain pads PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6, and the gate wiring M2G exposed from the gate pad opening 53G is the gate. It corresponds to pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6.
  • the drain pad PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6 are formed by the drain wiring M2D exposed from the drain pad opening 53D, and the gate wiring M2G exposed from the gate pad opening 53G forms the gate.
  • Pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6 are formed.
  • the wire WA is connected to the wiring M2 exposed from the opening 53 (that is, the pad electrode PD) after the semiconductor chip CP1 is mounted on the wiring substrate 11 (wiring substrate base 25).
  • the wiring M2 has a pattern with a larger area than the opening 53. .
  • the wiring M2 is formed by patterning a conductor film made of a laminated film of a barrier conductor film, an aluminum film, and a barrier conductor film, an opening 53 is formed in the insulating film 52.
  • the uppermost barrier conductor film can also be removed by dry etching.
  • a portion of the wiring M2 exposed from the opening 53 (that is, a portion that becomes the pad electrode PD) is formed of a laminated film of a barrier conductor film and an aluminum film thereon, and the wiring M2 ( The surface of the aluminum film (or aluminum alloy film) constituting the pad electrode PD) is exposed, while the portion of the wiring M2 covered with the insulating film 52 includes a barrier conductor film, an aluminum film thereon, and It consists of a laminated film with the upper barrier conductor film.
  • a source back electrode (back electrode) 54 is formed on the back surface of the substrate 31 (the main surface opposite to the main surface on which the epitaxial layer 31b is formed).
  • the source back electrode (back electrode) 54 is formed on the entire back surface of the substrate 31 constituting the semiconductor chip CP1 (that is, the entire back surface of the substrate body 31a), and corresponds to the back electrode BE1.
  • the source (n ⁇ type source region 40 and n + type source region 41) of the LDMOSFET formed in the epitaxial layer 31b is a plug 48 (plug 48 disposed on the n + type source region 41), source wiring M1S, plug 48 (plug 48 disposed on p + type semiconductor region 45), p + type semiconductor region 45, p type punching layer 44, and substrate 31 are electrically connected to source back electrode 54 (ie, back electrode BE1). It is connected.
  • a metal silicide layer (for example, a cobalt silicide layer or a nickel silicide layer, not shown) is further formed on the surface (upper part) of the n + type source region 41 and the p + type semiconductor region 45, and this metal silicide is formed.
  • the n + -type source region 41 and the p + -type semiconductor region 45 can also be electrically connected through the layer, which can further reduce the source resistance.
  • the drain (first n ⁇ type drain region 37, second n ⁇ type drain region 38 and n + type drain region 39) of the LDMOSFET formed in the epitaxial layer 31b is connected to the plug 48 (on the n + type drain region 39).
  • a drain pad any one of drain pads PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6 via a drain wiring M1D and a drain wiring M2D.
  • the gate electrode 35 of the LDMOSFET formed on the epitaxial layer 31b is connected to the gate pad (gate pads PDG1, PDG2, PDG3) via the plug 48 (plug 48 disposed on the gate electrode 35), the gate wiring M1G, and the gate wiring M2G. , PDG4, PDG5, PDG6).
  • FIG. 21 is a process flowchart showing the manufacturing process of the semiconductor chip CP1.
  • the epitaxial layer (semiconductor layer) 31b is formed on the main surface of the substrate body (semiconductor substrate, semiconductor wafer) 31a by using the epitaxial growth method, whereby the substrate body 31a and the substrate body are formed.
  • a substrate (semiconductor substrate) 31 composed of the epitaxial layer 31b on 31a is formed.
  • the substrate 31 at this stage is in a state of a substantially disk-shaped semiconductor wafer because a dicing process described later is not performed.
  • a part of the epitaxial layer 31b is etched using a photolithography technique and a dry etching technique to form a groove reaching the substrate body 31a, and then a CVD method or the like is formed on the epitaxial layer 31b including the inside of the groove.
  • the p-type polycrystalline silicon film is deposited using the p-type, the p-type polycrystalline silicon film outside the trench is removed by an etch back method or the like, thereby forming a p-type polycrystalline silicon film embedded in the trench.
  • a stamping layer 44 is formed.
  • the element isolation region 32 is formed in the epitaxial layer 31b by STI (Shallow Trench Isolation) method or LOCOS (Local Oxidization of Silicon) method.
  • a p-type well 33 is formed by ion-implanting p-type impurities into a part of the epitaxial layer 31b. Then, a gate insulating film 34 is formed on the surface of the epitaxial layer 31b, and a gate electrode 35 is formed on the gate insulating film 34.
  • a first n ⁇ -type drain region 37 is formed by ion-implanting an n-type impurity into a part of the epitaxial layer 31b. Then, an n ⁇ type source region 40 is formed by ion implantation of an n type impurity into a part of the p type well 33.
  • sidewall spacers 36 are formed on the side walls of the gate electrode 35.
  • a second n ⁇ type drain region 38 is formed by ion implantation of n type impurities.
  • an n + type drain region 39 and an n + type source region 41 are formed by ion implantation of an n type impurity.
  • a p + type semiconductor region 45 is formed by ion implantation of p type impurities.
  • an insulating film (interlayer insulating film) 46 is formed on the substrate 31 using a CVD method or the like, and the surface thereof is planarized using a CMP (Chemical Mechanical Polishing) method or the like as necessary. To do. Then, a contact hole 47 is formed in the insulating film 46 by using a photolithography technique and a dry etching technique, and then a plug 48 mainly composed of a tungsten (W) film is formed in the contact hole 47.
  • CMP Chemical Mechanical Polishing
  • the conductor film is patterned by using a photolithography technique and a dry etching technique to form the wiring M1.
  • an insulating film 49 is formed on the insulating film 46 so as to cover the wiring M1. Then, a through hole 50 is formed in the insulating film 49 using a photolithography technique and a dry etching technique.
  • a conductor film is formed on the insulating film 49 so as to fill the through hole 50, and then the conductor film is patterned by using a photolithography technique and a dry etching technique, so that the wiring M2 is formed. Form.
  • an insulating film (surface protective film) 52 is formed on the insulating film 49 so as to cover the wiring M2, and then an opening 53 is formed in the insulating film 49 using a photolithography technique and a dry etching technique. .
  • the wiring M2 is exposed from the opening 53, thereby forming the pad electrode PD including the drain pads PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 and the gate pads PDG1, PDG2, PDG3, PDG4, PDG5, PDG6. Is done.
  • the back surface of the substrate 31 (the main surface opposite to the side on which the epitaxial layer 31b is formed) is polished as necessary, and then the source back electrode 54 is formed on the entire back surface of the substrate 31 by sputtering or the like. To do.
  • the wafer process for the semiconductor wafer (substrate 31) is completed through the steps so far (step S11 in FIG. 21).
  • the wafer process is also called a pre-process, and generally, various elements (in this case, LDMOSFETs) and wiring layers are formed on the main surface of the semiconductor wafer (substrate 31), and a surface protective film (and a pad)
  • LDMOSFETs low-mobility metal-oxidation-oxide
  • a probe inspection process is performed on the semiconductor wafer (substrate 31) (step S12 in FIG. 21).
  • a probe probe
  • a probe is applied (pressed) to the pad electrode PD of each chip region (ie, semiconductor chip CP1) of the semiconductor wafer (substrate 31), and each chip region (ie, semiconductor) of the semiconductor wafer (ie, semiconductor chip CP1).
  • the electrical characteristics of the chip CP1) are inspected (tested).
  • the electrical characteristics of each chip region (that is, the semiconductor chip CP1) of the semiconductor wafer can be inspected.
  • the chip region determined to be defective in the probe inspection process is not used as the semiconductor chip CP1 after dicing, and is determined to be a non-defective product in the probe inspection process.
  • the chip area is used as the semiconductor chip CP1 after dicing.
  • step S13 can also be regarded as a process of obtaining the semiconductor chip CP1 by cutting the semiconductor wafer (substrate 31).
  • the preparation process of the semiconductor chip CP1 in step S2 includes these steps S11, S12, and S13.
  • the separated semiconductor chip CP1 is picked up in step S3 and mounted (mounted, die-bonded) on the wiring board base 25 (wiring board 11) as shown in FIG.
  • 22 to 24 are plan views of main parts of the semiconductor chip CP1, and plan views of the LDMOSFET formation region REGL3 in the semiconductor chip CP1 are shown. 22 to 24 show plan views of the same region, FIG. 22 shows a plan layout of the active region AR1, and FIG. 23 shows a wiring M1 (that is, a source wiring M1S and a drain wiring). A planar layout of M1D and gate wiring M1G) is shown, and FIG. 24 shows a planar layout of wiring M2 (that is, source wiring M2S, drain wiring M2D, and gate wiring M2G). 22 to 24, the drain pad opening 53D and the gate pad opening 53G are indicated by dotted lines in order to make it easy to compare the planar positions of FIGS.
  • FIG. 22 is a plan view, but in order to make the drawing easier to see, in FIG. 22, the active region AR1 is hatched.
  • the sectional view taken along the line A3-A3 in FIG. 24 substantially corresponds to FIG. 18, the sectional view taken along the line A4-A4 in FIG. 24 substantially corresponds to FIG. 19, and the sectional view taken along the line A5-A5 in FIG. Substantially corresponds to FIG.
  • FIG. 25 to 28 are main part plan views of the semiconductor chip CP1, and are enlarged views of a region 55 surrounded by a one-dot chain line in FIG. 25 to 28 show plan views of the same region (that is, the region 55 in FIG. 22).
  • FIG. 25 shows a plan layout of the active region AR1
  • FIG. The planar layout of the n + -type drain region 39, the n + -type source region 41 and the p-type punching layer 44 is shown.
  • 27 shows a planar layout of the wiring M1 (that is, the source wiring M1S, the drain wiring M1D, and the gate wiring M1G)
  • FIG. 28 shows the wiring M2 (that is, the source wiring M2S, the drain wiring M2D, and the gate wiring M2G).
  • Planar layout is shown.
  • the gate electrode 35 is indicated by a dotted line in order to make it easy to compare the planar positions of FIGS. 27 also shows the position of the contact hole 47 located below the wiring M1 (that is, the source wiring M1S, the drain wiring M1D, and the gate wiring M1G), and FIG. 28 shows the wiring M2 (that is, the source wiring M2S and the drain wiring).
  • the position of the through hole 50 located below M2D and the gate wiring M2G) is also illustrated.
  • 25 to 28 are plan views. To make the drawing easier to see, in FIG. 25, the active region AR1 is hatched with dots, and in FIG. 26, the gate electrode 35 is hatched with dots. Is attached.
  • the wiring M1 that is, the source wiring M1S, the drain wiring M1D, and the gate wiring M1G
  • the wiring M2 that is, the source wiring M2S, the drain wiring M2D, and the gate wiring. M2G
  • M2G is hatched with dots.
  • the sectional view taken along line A1-A1 in FIG. 25 substantially corresponds to FIG. 16
  • the sectional view taken along line A2-A2 in FIG. 28 substantially corresponds to FIG.
  • the X direction shown in the plan views of FIGS. 22 to 28 is a direction parallel to the side (chip side) SD1 on the side where the LDMOSFET formation region REGL3 and the drain pad PDD3 are formed in the semiconductor chip CP1.
  • the Y direction shown in the plan views of FIGS. 22 to 28 is a direction intersecting the X direction, and preferably a direction orthogonal to the X direction.
  • the element isolation region 32 defines an active region AR1 as shown in FIG. 22 and FIG. 25, and the active region AR1 is surrounded by the element isolation region 32.
  • the drain region of the LDMOSFET first n ⁇ type drain region 37, second n ⁇ type drain region 38 and n + type drain region 39
  • source region n ⁇ type source region 40 and n + type
  • a source region 41 is formed, and a gate electrode 35 is formed via a gate insulating film 34.
  • the gate electrode 35 of the LDMOSFET extends in the Y direction.
  • the drain region of the LDMOSFET (the first n ⁇ -type drain region 37, the second n ⁇ -type drain region 38 and the n + -type drain region 39) is a region between the adjacent gate electrodes 35 in the active region AR1. Formed in the Y direction.
  • the source region (n ⁇ type source region 40 and n + type source region 41) of the LDMOSFET is formed in a region between the other adjacent gate electrodes 35 in the active region AR1 and extends in the Y direction. Yes.
  • the p-type punching layer 44 is formed in a region between the n + type source regions 41 of adjacent LDMOSFETs.
  • One unit cell 60 forms two unit LDMOSFETs (unit LDMOSFET element, LDMOSFET cell, unit MISFET element) 60a. That is, the unit of repetition is the unit cell 60, but each unit cell 60 is configured by two unit LDMOSFETs 60a having a common n + -type drain region 39 and symmetrical in the X direction. Since the LDMOSFET is a MISFET element, the unit LDMOSFET 60a can be regarded as a unit MISFET element.
  • the structure (layout) of the unit cell 60 is repeated in the X direction, so that a large number (a plurality of) unit LDMOSFETs 60a are formed (arranged), and the large number (a plurality of) unit LDMOSFETs 60a are connected in parallel.
  • the unit LDMOSFETs 60a are repeatedly arranged in the X direction, and the plurality of unit LDMOSFETs 60a arranged in the LDMOSFET formation region REGL3 are connected in parallel.
  • the gate electrodes 35 of the plurality of unit LDMOSFETs 60a in the LDMOSFET formation region REGL3 are connected to each other via the plug 48 and the gate wirings M1G and M2G.
  • the drain regions (n + -type drain regions 39) are electrically connected to each other via the plug 48 and the drain wirings M1D and M2D.
  • the source regions are connected to each other by the plug 48, the source wiring M1S, M2S, the p + type semiconductor region 45, p.
  • the die punching layer 44, the substrate 31 and the source back electrode 54 are electrically connected to each other.
  • the LDMOSFET formation region REGL3 corresponds to a region in which the MISFET elements constituting the amplification stage LDML3 are formed, and a plurality of unit LDMOSFETs 60a formed in the LDMOSFET formation region REGL3 are connected in parallel to form the amplification stage LDML3. Is configured. Therefore, the MISFET element constituting the amplification stage LDML3 is configured by connecting a plurality of unit LDMOSFETs 60a in parallel.
  • the drain wiring M1D is formed on the drain region (n + -type drain region 39) of the LDMOSFET formed in the active region AR1, and the plug 48 disposed on the n + -type drain region 39 is interposed.
  • the drain wiring M1D and the drain region (n + -type drain region 39) of the LDMOSFET thereunder are electrically connected.
  • the drain wiring M1D also extends in the Y direction on the active region AR1, but on the element isolation region 32 between the active regions AR1.
  • the drain wiring M1D is not formed.
  • the drain wiring M1D is an isolated pattern formed only on each active region AR1, the upper portion of the drain wiring M1D extends in the Y direction as shown in FIGS.
  • the drain wiring M2D of the uppermost layer is electrically connected to the drain wiring M2D via a via portion (a portion filling the through hole 50).
  • the uppermost drain wiring M2D is a wiring portion (drain wiring) extending in the Y direction across a plurality of active regions AR1 (drain regions) arranged in the Y direction. Part) M2D1, and a connecting wiring part (drain wiring part) M2D2 that extends in the X direction and connects one ends of the plurality of wiring parts M2D1.
  • the plurality of wiring parts M2D1 and the connection wiring part M2D2 are integrally formed to constitute the drain wiring M2D. Accordingly, the drain wiring M2D has a so-called comb-like pattern.
  • Each wiring portion M2D1 extends in the Y direction so as to be positioned on each drain region of the plurality of unit LDMOSFETs 60a formed in the LDMOSFET formation region REGL3, and a plurality of unit LDMOSFETs 60a are connected via the drain wiring M1D and the plug 48. Are electrically connected to each drain region.
  • a drain pad opening 53D is formed above the connection wiring portion M2D2 of the drain wiring M2D, and the drain pad opening 53D is connected to the connection wiring portion M2D2 in a plane (in a plan view).
  • the wiring portion M2D2 has a larger area pattern than the drain pad opening 53D.
  • the drain pad PDD3 is formed by the drain wiring M2D exposed from the drain pad opening 53D, that is, the connection wiring M2D2 exposed from the drain pad opening 53D.
  • the drain region (n + -type drain region 39) of each unit cell 60 is pulled up to the wiring portion M2D1 of the uppermost drain wiring M2D through the plug 48 and the drain wiring M1D.
  • the drain wiring M2D is electrically connected to each other by the connecting wiring portion M2D2.
  • the drain pad PDD3 is formed by exposing a part of the drain wiring M2D (connection wiring portion M2D2) from the drain pad opening 53D.
  • the source region of LDMOSFET formed in the active region AR1 (n + -type source region 41) electrically connected to have been the source wiring M1S is, the source region (n + -type source region of the active region AR1 41) and the p + type semiconductor region 45.
  • the source wiring M1S since the source region extends in the Y direction, the source wiring M1S also extends in the Y direction on the active region AR1, but in the element isolation region 32 between the active regions AR1, The source wiring M1S is not formed. Therefore, the source line M1S is an isolated pattern formed only on each active region AR1, but as shown in FIGS. 16, 27, 28, etc., the upper part of the source line M1S extends in the Y direction.
  • the uppermost source wiring M2S is electrically connected to the source wiring M2S via a via portion (a portion filling the through hole 50).
  • the uppermost source line M2S extends in the Y direction across a plurality of active regions AR1 (source regions) arranged in the Y direction.
  • the source lines M2S are not connected to each other.
  • the pad electrode PD is not connected to the source wiring M2S because the source of the LDMOSFET is drawn from the source back electrode 54 on the back surface of the substrate 31 through the p-type punching layer 44 and the like. It is.
  • the gate electrode 35 extends in the Y direction and is buried in the contact hole 47 at a portion located on the element isolation region 32 around or between the active regions AR1.
  • the gate wiring M1G is electrically connected through the plug 48.
  • the gate wiring M1G extends in the X direction and the Y direction on the element isolation region 32 around and between the active regions AR1.
  • each gate electrode 35 extending in the Y direction is electrically connected to a portion extending in the X direction of the gate wiring M1G via a plug 48, and extends in the X direction of the gate wiring M1G.
  • the gate electrode 35 is electrically connected to each other via the gate wiring M1G by integrally connecting the portion to be extended and the portion extending in the Y direction.
  • the gate wiring M1G is a wiring in the same layer as the drain wiring M1D and the source wiring M1S. However, as shown in FIGS. 23 and 27, the drain wiring M1D and the source wiring M1S are formed on the element isolation region 32 between the active regions AR1. Is not formed, and the gate wiring M1G extends in the X direction. Therefore, the drain wiring M1D and the source wiring M1S extending in the Y direction are arranged between the portions of the gate wiring M1G extending in the X direction.
  • the gate wiring M1G is located on the opposite side of the drain wiring M2D from the connection wiring portion M2D2 (the side far from the connection wiring portion M2D2) and extends in the X direction.
  • the gate wiring M2G extending in the X direction on the element isolation region 32 is electrically connected to the via portion of the gate wiring M2G (the portion filling the through hole 50). That is, at least a portion of the gate wiring M2G extending in the X direction overlaps with the portion of the gate wiring M1G extending in the X direction in a plane, and the via portion (through hole) of the gate wiring M2G in the overlapping region. 50), the upper gate wiring M2G and the lower gate wiring M1G are electrically connected.
  • the gate electrode 35 of each unit LDMOSFET 60a is pulled up to the gate wiring M1G via the plug 48, and this gate wiring M1G is pulled up to the uppermost gate wiring.
  • the gate wiring M2G is connected to M2G, extends to the gate pad opening 53G, and a part of the gate wiring M2G is exposed from the gate pad opening 53G, thereby forming the gate pad PDG3.
  • FIG. 29 is a plan view of an essential part of the semiconductor chip CP1, and shows the same regions as those in FIGS. However, FIG. 29 shows the layout (arrangement) of the LDMOSFET formation region REGL3, the connection wiring portion M2D2 of the drain wiring M2D, the drain pad opening 53D, the gate wiring M2G, and the gate pad opening 53G, and other components. Is omitted. Accordingly, the source wiring M2S and the wiring portion M2D1 of the drain wiring M2D shown in FIG. 24 are not shown in FIG. Note that FIG.
  • FIG. 29 is a plan view, but the LDMOSFET formation region REGL3, the gate wiring M2G, and the connection wiring portion M2D2 of the drain wiring M2D are hatched for easy understanding of the drawing.
  • the gate pad opening 53G and the drain pad opening 53D are indicated by dotted lines, and the portion of the gate wiring M2G exposed from the gate pad opening 53G is the gate pad PDG3.
  • a portion of the drain wiring M2D (connection wiring portion M2D2) exposed from the opening 53D is the drain pad PDD3.
  • 30 and 31 are main part plan views of the power amplification module PA1 during the manufacturing process.
  • FIG. 30 shows a step after mounting the semiconductor chip CP1 on the wiring board matrix 25 (wiring board 11).
  • FIG. 31 shows the stage immediately after the wire bonding process (wire WA connection process) in step S5.
  • FIG. 32 is a perspective view (bird's eye view) of a main part during the manufacturing process of the power amplification module PA1, and a stage immediately after performing the wire bonding process (connection process of the wire WA) of step S5 to the semiconductor chip CP1 (that is, FIG. 31). The same stage) is shown.
  • 30 and 31 show a region corresponding to the region 56 surrounded by the two-dot chain line in FIG. 15, and FIG. 32 shows a part of FIG.
  • FIG. 33 is a plan view of the main part of the semiconductor chip CP101 of the first comparative example, and corresponds to FIG. 29 of the present embodiment.
  • the LDMOSFET formation region REGL103, the drain wiring M2D101, the drain pad opening 153D, the gate wiring M2G101, and the gate pad opening 153G are respectively the LDMOSFET formation region REGL3 and the drain wiring in this embodiment. This corresponds to M2D, drain pad opening 53D, gate wiring M2G, and gate pad opening 53G.
  • FIG. 34 and FIG. 35 are main part plan views during the manufacturing process of the power amplifying module of the first comparative example, and correspond to FIG. 30 and FIG. 31 of the present embodiment, respectively.
  • FIG. 34 shows a stage after mounting the semiconductor chip CP101 of the first comparative example on the wiring board base 25 and immediately before performing the wire bonding process (connection process of the wire WA101).
  • the stage immediately after performing the wire bonding process (connection process of the wire WA101) is shown.
  • FIG. 36 is a perspective view (bird's eye view) of the main part during the manufacturing process of the power amplifying module of the first comparative example, and corresponds to FIG. 32 of the present embodiment.
  • FIG. 36 shows a stage immediately after the wire bonding process (connection process of the wire WA101) to the semiconductor chip CP101 of the first comparative example (that is, the same stage as FIG. 35).
  • the gate pads PDG101, PDG102, PDG103, the drain pads PDD101, PDD102, PDD103, and the wire WA (bonding wire) 101 shown in FIGS. 34 to 36 are the gate pads PDG1, PDG2, PDG3 in the present embodiment, respectively. This corresponds to the drain pads PDD1, PDD2, PDD3 and the wire WA.
  • a plurality of are formed on the drain wiring M2D101 electrically connected to the drain of the LDMOSFET formed in the LDMOSFET formation region REGL103.
  • seven drain pad openings 153D are provided, and the drain pad PDD103 is formed by the drain wiring M2D101 exposed from each drain pad opening 153D. That is, in the semiconductor chip CP101 of the first comparative example, seven drain pads PDD103 are formed with respect to the LDMOSFET formation region REGL103, and these seven drain pads PDD103 are arranged in the X direction with a predetermined interval. Is arranged in.
  • one wire WA101 is connected to each of the seven drain pads PDD103. That is, the number of wires WA connected to one drain pad PDD103 is one. Therefore, in the semiconductor chip CP101 of the first comparative example, seven drain pads PDD103 are provided for the LDMOSFET formation region REGL103, and a total of seven wires WA101 are connected to these seven drain pads PDD103.
  • a probe inspection is performed after the wafer process.
  • a probe (probe) for inspection is pressed against the pad electrode in each chip area of the semiconductor wafer.
  • the pad electrode in each chip region becomes the pad electrode of each semiconductor chip after dicing of the semiconductor wafer.
  • the pad electrode is deformed in the area where the probe is pressed (contacted). Therefore, the probe is pressed against the pad electrode where the probe is pressed in the probe inspection.
  • Probe marks are formed (contacted) marks.
  • drain pads PDD103 are formed in the LDMOSFET formation region REGL103, and the wire WA101 is connected to each drain pad PDD103.
  • a probe mark PRB101 is formed on any of the seven drain pads PDD103 by pressing the probe in the probe inspection process.
  • FIG. 37 is an explanatory diagram (plan view) showing the probe mark PRB101 formed on the drain pad PDD103 of the semiconductor chip CP101 of the first comparative example and the connection region RGW101 of the wire WA101 on the drain pad PDD103.
  • FIG. 37 shows the drain pad PDD103 before the probe test, and (b) shows a probe (probe for inspection) on two drain pads PDD103 of the seven drain pads PDD103 in the probe test. A state in which the probe mark PRB101 is formed by pressing the needle) is schematically shown.
  • (c) shows a connection region RGW101 of the wire WA101 when the wire WA101 is connected to the drain pad PDD103 in the wire bonding step.
  • the first bonding is performed in the wire bonding process.
  • the bonding is performed on the pad electrodes (PDD3 and PDD103) of the chips CP1 and CP101, and the second bonding is performed on the substrate-side terminal TE.
  • ball bonding is preferably used for the wire bonding. For this reason, at the time of wire bonding, a metal ball at the tip of the wire (a gold ball when the wire is a gold wire) is connected to each pad electrode (PDD3, PDD103) of the semiconductor chips CP1, CP101 (specifically, , Crushed and connected or crimped).
  • a connection area RGW101 of the wire WA101, a connection area RGW201 of the wire WA101, which will be described later, and a connection area RGW of the wire WA are areas to which the metal balls (gold balls when the wires are gold wires) are connected.
  • the wires WA and WA101 are preferably wires (gold wires) made of gold, but when the gold wires (WA and WA101) are connected to the pad electrodes (PDD3 and PDD103) mainly made of aluminum (Al).
  • the gold ball at the tip of the wire (WA, WA101) is alloyed with the aluminum of the pad electrode (PDD3, PDD103), so that the wire (the gold ball at the tip thereof) is connected to the pad electrode (PDD3, PDD103).
  • the pad electrode (PDD3, PDD103) when connecting the wire (the metal ball at the tip of the wire) to the pad electrode (PDD3, PDD103), it is important that the surface state of the pad electrode (PDD3, PDD103) serving as the base is uniform. It is preferable that the pad electrode (PDD3, PDD103) to be formed has high flatness. If the wire (the metal ball at the tip thereof) is connected to the flat surface of the pad electrode, the connection strength of the wire to the pad electrode can be increased. However, since the semiconductor chips (CP1 and CP101) are used only for the production of a semiconductor device such as a power amplification module, contact of the probe to the pad electrodes (PDD3 and PDD103) by probe inspection is avoided. Therefore, probe marks (PRB, PRB101) are generated on the pad electrodes (PDD3, PDD103) to be wire-bonded.
  • connection region RGW101 of the wire WA101 overlaps the probe mark PRB101 as shown in FIG.
  • the connection strength between the PDD 103 and the wire WA101 is reduced.
  • the connection region RGW101 of the wire WA101 overlaps the probe mark PRB101 at two drain pads PDD103 of the seven drain pads PDD103, and the connection strength of the wire WA101 decreases at the two drain pads PDD103.
  • the connection region RGW101 of the wire WA101 becomes the probe mark PRB101 during wire bonding. This is because the wire (the metal ball at the tip thereof) is connected to a non-flat region due to the probe mark, and the connection strength of the wire WA101 is reduced. The decrease in the connection strength of the wire WA101 decreases the reliability of the manufactured power amplification module.
  • An example of the area of the probe mark PRB101 is, for example, about 40% of the area of the connection region RGW101 of the wire WA101.
  • FIG. 38 is an explanatory diagram (plan view) showing the probe mark PRB201 formed on the drain pad PDD203 of the semiconductor chip of the second comparative example and the connection region RGW201 of the wire WA101 in the drain pad PDD203.
  • FIG. 38 shows the drain pad PDD 203 before the probe test, and (b) shows a probe (probe for inspection) on two drain pads PDD 203 of the seven drain pads PDD 203 in the probe test.
  • a state in which the probe mark PRB201 is formed by pressing the needle) is schematically shown.
  • FIG. 38 is an explanatory diagram (plan view) showing the probe mark PRB201 formed on the drain pad PDD203 of the semiconductor chip of the second comparative example and the connection region RGW201 of the wire WA101 in the drain pad PDD203.
  • (c) shows a connection region RGW201 of the wire WA101 when the wire WA101 is connected to the drain pad PDD203 in the wire bonding step.
  • the drain pad PDD203 of the semiconductor chip of the second comparative example of FIG. 38 corresponds to the drain pad PDD103 of the semiconductor chip CP101 of the first comparative example of FIG.
  • the drain pad PDD203 of the semiconductor chip of the second comparative example shown in FIG. 38 has a larger dimension in the Y direction than the drain pad PDD103 of the semiconductor chip CP101 of the first comparative example. For this reason, in the semiconductor chip of the second comparative example, even if the wire WA101 is connected to the drain pad PDD203 to which the probe is pressed in the probe inspection in the wire bonding process, as shown in FIG. 38, the connection of the wire WA101 is performed.
  • the region RGW201 and the probe mark PRB201 can be shifted in the Y direction so that the connection region RGW201 of the wire WA101 and the probe mark PRB201 do not overlap.
  • the drain pad PDD203 of the semiconductor chip of the second comparative example shown in FIG. 38 is used to shift the position of the connection region RGW201 of the wire WA101 and the probe mark PRB201 in the drain pad PDD203 in the Y direction. It is necessary to enlarge the dimension in the Y direction. Therefore, the area required for the LDMOSFET formation region REGL103 and the drain pad PDD203 and the gate pad connected thereto is larger than that of the semiconductor chip CP101 of the first comparative example because the size of the drain pad PDD203 in the Y direction is larger. The semiconductor chip of the second comparative example to which the PDD 203 is applied becomes larger.
  • the semiconductor chip of the second comparative example to which the drain pad PDD203 is applied has a larger chip size (particularly the dimension in the Y direction) than the semiconductor chip CP101 of the first comparative example because the dimension of the drain pad PDD203 in the Y direction is larger. End up. This reduces the number of semiconductor chips that can be obtained from a single wafer, leading to an increase in manufacturing cost, and miniaturization of semiconductor devices (here, power amplification modules) on which semiconductor chips are mounted (planar dimensions). (Reduction) is disadvantageous.
  • a drain pad provided for the LDMOSFET formation region REGL3 that is, a drain pad electrically connected to the drain of the LDMOSFET formed in the LDMOSFET formation region REGL3.
  • a drain pad PDD3 having a larger dimension in the X direction than a dimension in the Y direction is formed.
  • the dimension in the X direction of the drain pad PDD3 is at least twice the dimension in the Y direction of the drain pad PDD3, and the drain pad PDD3 has a substantially rectangular planar shape (however, the rectangular corners are rounded). Can also be held).
  • One of the main features of the present embodiment is that a plurality of wires WA are connected to the one drain pad PDD3.
  • the drain pad PDD3 has a rectangular planar shape, and the long side direction (X direction) of the rectangle is the side (chip side) on the surface of the semiconductor chip CP1 where the drain pad PDD3 is disposed.
  • the direction is preferably parallel to SD1. That is, of the four sides (chip sides) SD1, SD2, SD3, and SD4 of the semiconductor chip CP1, the drain pad PDD3 is aligned in a direction parallel to the chip side (here, the side SD1) located closest to the drain pad PDD3. It is preferable to set the long side direction.
  • the drain pads PDD1, PDD2, and PDD3 and the gate pads PDG1, PDG2, and PDG3 are arranged along the side SD2 instead of the side SD1, and the LDMOSFET formation regions REGL1, REGL2, and REGL3 are When arranged on the side SD2 side instead of the SD1 side, the long side direction (X direction) of the drain pad PDD3 is parallel to the side SD2.
  • the drain pad PDD3 in FIGS. 29 to 32 is connected to the seven drain pads PDD103 arranged in the X direction in FIGS. It corresponds to. That is, in FIGS. 33 to 36, seven drain pads PDD103 and a region between drain pads PDD103 adjacent in the X direction are added to form one drain pad as a whole. It corresponds to PDD3.
  • FIG. 39 is an explanatory view (plan view) showing the probe mark PRB formed on the drain pad PDD3 of the semiconductor chip CP1 of this embodiment and the connection region RGW of the wire WA in the drain pad PDD3.
  • FIG. 39 shows the drain pad PDD3 before the probe test, and (b) shows a probe (probe for inspection) at two locations on the drain pad PDD3 in the probe test (corresponding to step S12). A state in which the probe mark PRB is formed by pressing the needle) is schematically shown.
  • (c) shows a connection region RGW of the wire WA when the wire WA is connected to the drain pad PDD3 in the wire bonding step (corresponding to step S5).
  • FIG. 40 is an explanatory diagram showing the probe mark PRB formed on the drain pad PDD3 of the semiconductor chip CP1 of this embodiment and the connection region RGW of the wire WA in the drain pad PDD3. ) Shows an enlarged view of a region 57 surrounded by a two-dot chain line in FIG. 39, and FIG. 40 (b) shows a cross-sectional view taken along line B1-B1 of FIG. 40 (a).
  • FIG. 40A is a plan view, but the probe mark PRB and the connection region RGW of the wire WA are hatched for easy viewing of the drawing.
  • FIG. 41 is a cross-sectional view showing a state in which the probe (probe) 58 for inspection is pressed against the drain pad PDD3 in the probe inspection (corresponding to step S12 above), and FIG. 42 shows the probe 58 in FIG.
  • FIG. 19 is a cross-sectional view showing a state in which a probe mark PRB is formed on the drain pad PDD3 by being pressed against the drain pad PDD3, and each shows a cross-section corresponding to FIG.
  • the surface (upper surface) of the drain pad PDD3 is substantially flat before the probe test.
  • FIG. 41 when the probe 58 is pressed against the drain pad PDD3 in the probe test (step S12), as shown in FIG.
  • the conductor film constituting the M2S is deformed to form a depression (concave part), and in some cases, a convex part is formed together with the depression (concave part).
  • a probe mark PRB is formed by a portion where the flatness is lost (a portion where a recess is formed or a portion where a recess and a projection are formed).
  • a plurality of wires WA are connected to the drain pad PDD3 and, as can be seen from FIGS. 39 and 40, a plurality of wires WA are connected in the drain pad PDD3.
  • the probe mark PRB is formed between the regions RGW. That is, in the pad electrode PDD3, a plurality of (here, seven) positions where the probe is applied (contacted) in the probe inspection in step S12 (that is, the position where the probe mark PRB is formed) are formed in the wire bonding step in step S5. ) Between the positions where the wire WA is connected. That is, in the drain pad PDD3, the region where the probe is pressed in the probe inspection (that is, the probe mark PRB) is located between the connection region RGW of a certain wire WA and the connection region RGW of the adjacent wire WA. is there.
  • the dimension in the X direction of the drain pad PDD3 is larger than the dimension in the Y direction of the drain pad PDD3, and a plurality of (in this case, seven) wires WA are connected to the drain pad PDD3.
  • the connection regions RGW of the wires WA in the drain pad PDD3 are aligned (arranged) in the X direction.
  • the connection regions RGW of the wires WA are adjacent to each other in the X direction, and probe traces are connected between the connection regions RGW adjacent in the X direction.
  • the PRB that is, the position where the probe is applied in the probe inspection in step S12
  • the connection region RGW of the adjacent wires WA and the probe mark PRB between the connection regions RGW of the adjacent wires WA are arranged in the X direction.
  • a plurality of wires WA are connected to the drain pad PDD3, and a region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) is located between the connection regions RGW of the plurality of wires WA in the drain pad PDD3.
  • the region where the probe is pressed by the probe inspection (that is, the probe mark PRB) is located between the connection regions RGW of the adjacent wires WA, so that the connection of the wire WA is performed in the drain pad PDD3.
  • the overlap between the region RGW and the probe mark PRB can be reduced, and preferably, the connection region RGW of the wire WA and the probe mark PRB can be prevented from overlapping (not overlapping in plan view).
  • the wire WA can be connected to the flat portion of the drain pad PDD3 (the portion where the probe mark PRB is not formed), so that the connection strength between the drain pad PDD3 and the wire WA can be improved. For this reason, the reliability of manufactured power amplification module PA1 can be improved.
  • a region where the probe is pressed in the probe inspection (that is, the probe mark PRB) is positioned between the connection regions RGW of the adjacent wires WA.
  • the planar area for securing does not contribute to an increase in the chip size of the semiconductor chip CP1, and is advantageous in terms of reducing the planar dimension (planar area) of the semiconductor chip CP1.
  • an empty space between the connection regions RGW of the adjacent wires WA is assigned to a region where the probe is pressed in the probe inspection (that is, a region where the probe mark PRB is formed). That is, in the semiconductor chip CP101 of the first comparative example of FIGS. 33 to 37, the region between the adjacent drain pads PDD103 (the region where the insulating film 52 as the surface protective film is formed) In the semiconductor chip CP1 of the present embodiment shown in FIGS.
  • a part of the drain pad PDD3 is used, and this is a region where the probe is pressed in the probe inspection (that is, the region where the probe mark PRB is formed).
  • a region that is not used as a pad electrode or a circuit region that is, a region between adjacent drain pads PDD103
  • FIGS. 32, 39 and 40 it is used as a region where the probe is pressed in the probe inspection (that is, a region where the probe mark PRB is formed).
  • the connection region RGW201 of the wire WA101 and the probe mark PRB201 are shifted in the Y direction. It is necessary to enlarge the probe mark PRB201.
  • the semiconductor chip CP1 of the present embodiment since the probe mark PRB is arranged between the connection regions RGW of the wires WA101 adjacent in the X direction, the dimension of the drain pad PDD3 in the Y direction is the same as that of the wire WA101. It is only necessary to set a dimension that can secure the connection region RGW, and it is not necessary to increase the dimension in the Y direction of the drain pad PDD3 in consideration of the area of the probe mark PRB.
  • the dimension in the Y direction of the drain pad PDD3 of the semiconductor chip CP1 of the present embodiment can be approximately the same as the dimension in the Y direction of the drain pad PDD103 in the semiconductor chip CP101 of the first comparative example. It can be made smaller than the dimension in the Y direction of the drain pad PDD203 in the semiconductor chip of the second comparative example. Therefore, in the present embodiment, the planar dimension (planar area) of the semiconductor chip CP1 can be reduced compared with the case where the drain pad PDD203 of FIG. 38 is applied, and the manufacturing cost can be reduced and the semiconductor chip CP1 can be manufactured.
  • the mounted semiconductor device here, power amplification module PA1 can be reduced in size (reduction in planar dimensions).
  • the connection strength between the drain pad PDD3 and the wire WA can be improved, and the manufactured power amplification The reliability of the module PA1 can be improved.
  • the planar dimension (planar area) of the semiconductor chip CP1 can be reduced. The manufacturing cost can be reduced, and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted can be downsized (planar dimensions can be reduced).
  • the drain pad PDD3 has a long planar shape along the chip side (here, the side SD1) on the side where the drain pad PDD3 is disposed, the dimension of the drain pad PDD3 in the short side direction (Y direction) (
  • the length L1 depends on the size of the metal ball at the tip of the wire WA to be connected, but can be, for example, about 65 ⁇ m (the dimension L1 is shown in FIG. 40).
  • the connection pitch (connection interval) P1 of the wires WA in the drain pad PDD3 (the connection pitch P1 is shown in FIG. 40) is set to 1 of the dimension L1 in the short side direction of the drain pad PDD3 in consideration of the arrangement of the probe marks PRB.
  • the diameter L2 (diameter L2 is a figure of the connection region RGW of the wire WA from the viewpoint of area saving). 40) is set to be 60% or more of the dimension L1 in the short side direction of the drain pad PDD3 (that is, L2 ⁇ L1 ⁇ 0.6), and the dimension L1 in the short side direction of the drain pad PDD3 is set. It is preferable.
  • the thickness of the conductor film (corresponding to the source line M2S) constituting the drain pad PDD3 can be set to, for example, about 0.3 to 3 ⁇ m.
  • the probe mark PRB is arranged between the connection regions RGW of the wires WA adjacent in the X direction, the probe mark PRB is partially overlapped with the connection region RGW of the wire WA. Even if it exists, since the overlapping area of the probe mark PRB and the connection region RGW of the wire WA can be reduced, the effect of improving the connection strength of the wire WA to the drain pad PDD3 can be obtained.
  • the probe mark PRB is arranged between the connection regions RGW of the wires WA adjacent in the X direction, but the probe mark PRB overlaps with the connection region RGW of the wire WA. It is more preferable that they are not overlapped (in a plan view).
  • the plurality of wires WA are connected to the drain pad PDD3 at a position that does not overlap the probe mark PRB in plan view. Since the probe mark PRB and the connection region RGW of the wire WA do not overlap (does not overlap in plan view), the wire WA is connected to the drain pad PDD3 in a flat portion where the probe mark PRB is not formed.
  • the connection strength of the wire WA to the drain pad PDD3 can be improved more accurately, and the reliability of the power amplification module PA1 can be improved more accurately.
  • connection regions RGW of the plurality of wires WA in the drain pad PDD3 are arranged in a line (on a straight line). That is, in the wire bonding process of step S5, it is preferable that the positions where the plurality of wires WA are connected in the drain pad PDD3 are arranged in a line (on a straight line). More specifically, the connection regions RGW of the plurality of wires WA in the drain pad PDD3 are preferably arranged in a line (on a straight line) along the long side direction (X direction) of the drain pad PDD3.
  • connection region RGW of the wires WA is not arranged in a so-called staggered arrangement (without shifting in the Y direction), as shown in FIGS.
  • the connection regions RGW of the plurality of wires WA are arranged in a line (on a straight line) in the X direction (that is, the long side direction of the drain pad PDD3).
  • planar dimension (planar area) of the semiconductor chip CP1 can be reduced, the manufacturing cost can be reduced, and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted is reduced (the planar dimension is reduced). ).
  • FIG. 31 In FIG. 31, FIG. 32 and FIG. 39, seven wires WA are connected to the drain pad PDD3.
  • the number of wires WA connected to the drain pad PDD3 is not limited to seven. Or more).
  • the number of regions in which the probe is pressed against the drain pad PDD3 in the probe inspection process that is, the number of probe marks PRB formed on the drain pad PDD3, or the number of probes pressed against the drain pad PDD3 in the probe inspection process).
  • FIG. 39 the number of regions in which the probe is pressed against the drain pad PDD3 in the probe inspection process (that is, the number of probe marks PRB formed on the drain pad PDD3, or the number of probes pressed against the drain pad PDD3 in the probe inspection process). ) Is two (two places), but is not limited to this, and may be one or more (one or
  • the region between the connection regions RGW of the wires WA in the drain pad PDD3 includes a region where the probe mark PRB is arranged and a region where the probe mark PRB is not arranged.
  • the region where the probe mark PRB is arranged there are six locations between the seven connection regions RGW.
  • a region where the probe is pressed in the probe inspection ie, the probe mark PRB
  • the other ends of the plurality of wires WA whose one ends are connected to the drain pad PDD3 are connected to one terminal TE of the wiring substrate 11.
  • One end of the WA may be connected to the drain pad PDD3, and the other ends of the plurality of wires may be connected to the plurality of terminals TE, respectively.
  • the resistance component due to the wires WA can be further reduced as compared with the case of two wires WA (that is, the power loss reduction effect can be further increased).
  • the number of regions where the probe is pressed against the drain pad PDD3 in the probe inspection process that is, the number of probe marks PRB formed on the drain pad PDD3
  • the reliability of the probe inspection is further improved than the case of one. Can be improved.
  • the drain pad PDD3 electrically connected to the drain of the LDMOSFET formation region REGL3 is connected to the connection region RGW of the wire WA and the region where the probe is pressed in the probe inspection (that is, the probe mark PRB).
  • connection strength between the drain pad PDD6 and the wire WA can be improved, and the reliability of the power amplification module PA1 can be improved.
  • chip size of the semiconductor chip CP1 can be suppressed, so that the manufacturing cost can be reduced and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted can be downsized (planar dimensions are reduced). it can.
  • the semiconductor chip CP1 has a plurality of power amplifier circuits (in this case, the amplifier stages LDML1, LDML2, and LDML3 and the amplifier stages LDMH1, LDMH2, and LDMH3) connected in multiple stages.
  • the pad electrodes PD connected to the outputs of the semiconductor elements (here, LDMOSFETs) constituting the amplification stages (LDML3, LDMH3) are drain pads PDD3, PDD6.
  • the pad electrode (drain pad PDD3, PDD6) connected to the output of the semiconductor element (here LDMOSFET) constituting the final stage power amplification circuit (here amplification stage LDML3, LDMH3) has a large output current
  • the number of wires WA to be connected to be plural (increase) the effect of reducing the resistance component by the wires WA and reducing the power loss is extremely great. Therefore, like the drain pad PDD3 in FIGS. 39 and 40, a plurality of wires WA are connected to the pad electrode PD, and a probe inspection is performed between the connection regions RGW of the plurality of wires WA in the pad electrode PD.
  • the above-described feature of locating the region where the is pressed is particularly effective when applied to the pad electrodes (here, drain pads PDD3 and PDD6) connected to the output of the power amplifier circuit in the final stage. .
  • the pad electrodes (drain pads PDD3 and PDD6) connected to the output are rectangular. Even if a plurality of wires WA are connected to the pad electrode, it is difficult to increase the area of the semiconductor chip CP1.
  • pad electrodes PD (here, drain pads PDD1, PDD2) connected to the outputs of the semiconductor elements (here, LDMOSFETs) constituting the amplification stages LDML1, LDML2, LDMH1, and LDMH2 prior to the last amplification stages LDML3 and LDMH3.
  • PDD4, PDD5 when connecting a plurality of wires WA to the pad electrode PD, the features of the drain pad PDD3 of FIGS. 39 and 40 can be applied. That is, also in the pad electrode PD, the region where the probe is pressed in the probe inspection (that is, the probe mark PRB) can be positioned between the connection regions RGW of the plurality of wires WA. For example, as shown in FIGS.
  • a plurality (two in the case of FIG. 14) of wires WA are connected to the drain pad PDD2, and also in this drain pad PDD2, like the drain pad PDD3 in FIG. Between the connection regions RGW of the plurality of wires WA, a region where the probe is pressed in the probe inspection (that is, the probe mark PRB) can be positioned. Further, as shown in FIGS. 14 and 15, a plurality (two in the case of FIG. 14) of wires WA are connected to the drain pad PDD5, and also in this drain pad PDD5, as in the drain pad PDD3 of FIG. Between the connection regions RGW of the plurality of wires WA, a region where the probe is pressed in the probe inspection (that is, the probe mark PRB) can be positioned.
  • the pad electrode PD (here, drain pad) connected to the output of the semiconductor element (here, LDMOSFET) constituting the power amplifier circuit.
  • a plurality of wires WA are connected to any one of PDD1, PDD2, PDD3, PDD4, PDD5 and PDD6).
  • region (namely, probe mark PRB) which pressed the probe by the probe test
  • FIG. 43 is an explanatory diagram of the first modified example and corresponds to FIG. 39 described above.
  • (a) shows the drain pad PDD3 before the probe inspection
  • (b) shows the probe (probing for inspection) at two locations on the drain pad PDD3 in the probe inspection (corresponding to step S12).
  • a state in which the probe mark PRB is formed by pressing the needle) is schematically shown.
  • (c) shows a connection region RGW of the wire WA when the wire WA is connected to the drain pad PDD3 in the wire bonding step (corresponding to step S5).
  • three or more wires WA are connected to the drain pad PDD3 and are connected at equal intervals. That is, in the drain pad PDD3, a plurality of wires WA are connected at an equal pitch (equal interval), and an interval (a distance in the X direction) between the connection region RGW of the wire WA and the connection region RGW of the adjacent wire WA.
  • the pitch P1) is the same for any wire WA connected to the drain pad PDD3. This is because in the wire bonding step of step S5, three or more wires WA are connected to the drain pad PDD3, and these three or more wires WA are connected to the drain pad PDD3 at equal pitches (equal intervals). is there.
  • a region where the probe mark PRB is arranged and a region where the probe mark PRB is not arranged are mixed.
  • the plurality of wires WA are not connected at an equal pitch (equal interval). That is, in the drain pad PDD3, the interval (pitch, distance) P5 between the connection regions RGW between which the probe marks PRB are disposed is the interval (pitch, distance) between the connection regions RGW between which the probe marks PRB are not disposed. Distance) is larger than P6 (that is, P5> P6).
  • intervals P5 and P6 are shown in FIG. 43, and the interval P5 indicates a plurality of wires WA connected to the drain pad PDD3 in the connection region RGW of adjacent wires WA with the probe mark PRB interposed therebetween. It corresponds to the interval (pitch, distance).
  • the interval P6 corresponds to the interval (pitch, distance) between the connection regions RGW of adjacent wires WA without interposing the probe mark PRB between the plurality of wires WA connected to the drain pad PDD3.
  • the interval between the connection regions RGW of the wires WA is set to a wire bonding apparatus (bonding tool).
  • Bonding tool can be set to the minimum interval (pitch) that needs to be set, and the number of wires WA connected to the pad electrode PD (here, the drain pad PDD3) can be efficiently increased.
  • the resistance component by wire WA can be reduced efficiently and a power loss can be reduced efficiently.
  • the dimension of the pad electrode PD in the long side direction can be suppressed, and the chip size of the semiconductor chip CP1 can be reduced.
  • the interval P5 between the connection regions RGW of the wires WA between which the probe traces PRB are arranged is arranged, and the probe trace PRB is arranged therebetween.
  • P5> P6 the distance between the connection areas RGW of the unwired wires WA is larger (P5> P6), the following advantages can be obtained. That is, if the interval P5 is too small, the connection region RGW of the wire WA and the probe mark PRB overlap with each other, and the connection strength of the wire WA tends to decrease.
  • the connection region RGW of the wire WA and the probe mark PRB do not overlap with each other, and the connection strength of the wire WA does not decrease.
  • the pad electrode PD Here, the number of wires WA that can be connected to the drain pad PDD3) decreases, or the size of the pad electrode PD (here, the drain pad PDD3) in the long side direction (here, the X direction) increases. For this reason, by making the interval P5 larger than the interval P6 (P5> P6), the connection region RGW of the wire WA and the probe trace PRB are more accurately suppressed or prevented and the connection strength of the wire WA is improved.
  • the number of wires WA that can be connected to the pad electrode PD can be increased, and the dimension of the pad electrode PD in the long side direction can also be increased. Can be suppressed.
  • the number of wires WA that can be connected to the pad electrode PD (here, the drain pad PDD3) is increased while the overlapping of the connection region RGW of the wire WA and the probe mark PRB is more accurately suppressed or prevented.
  • the resistance component due to the wire WA can be efficiently reduced, the power loss can be efficiently reduced, and the size of the pad electrode PD in the long side direction is also suppressed, so that the chip size of the semiconductor chip CP1 can be reduced. Reduction is also possible.
  • FIG. 44 is a plan perspective view of the power amplification module PA1 using the semiconductor chip CP1a of the second modified example instead of the semiconductor chip CP1, and shows a state where the sealing resin 13 is seen through.
  • FIG. 45 is a partially enlarged plan view of FIG. 44, in which the semiconductor chip CP1a mounted on the wiring board 11 and its peripheral region are enlarged.
  • FIG. 46 is a plan view in which the wires WA and the substrate-side terminals TE are omitted from FIG. 45, and corresponds to a plan view (planar layout diagram) of the semiconductor chip CP1a.
  • the semiconductor chip CP1 has two systems of power amplification circuits LDML and LDMH.
  • the semiconductor chip CP1a of the second modified example has two systems of power amplification in addition to the two systems of power amplification circuits LDML and LDMH.
  • a circuit is added, and a total of four power amplifier circuits are provided. That is, the semiconductor chip CP1a has four-system power amplifier circuits corresponding to the four frequency bands, and the power amplifier module PA1 of FIG. 44 using the semiconductor chip CP1a corresponds to the four frequency bands.
  • the semiconductor chip CP1a has LDMOSFET formation regions REGM1, REGM2, REGN1, and REGN2 in addition to the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, and REGH3.
  • the first power amplifier circuit LDML is formed by the LDMOSFETs formed in the LDMOSFET formation regions REGL1, REGL2, and REGL3, respectively
  • the second system is formed by the LDMOSFETs formed in the LDMOSFET formation regions REGH1, REGH2, and REGH3, respectively.
  • the semiconductor chip CP1a is the same as the semiconductor chip CP1 in that the power amplifier circuit LDMH is formed.
  • the first amplification stage constituted by the LDMOSFET formed in the LDMOSFET formation region REGM1 and the second amplification stage constituted by the LDMOSFET formed in the LDMOSFET formation region REGM2 are connected.
  • a third system power amplifier circuit is formed.
  • the first stage amplification stage configured by the LDMOSFET formed in the LDMOSFET formation region REGN1 and the second stage amplification stage configured by the LDMOSFET formed in the LDMOSFET formation region REGN2 are connected, and the fourth system power is connected.
  • An amplifier circuit is formed.
  • the semiconductor chip CP1a has, as the pad electrode PD, in addition to the drain pads PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 and the gate pads PDG1, PDG2, PDG3, PDG4, PDG5, PDG6, and further drain pads PDD7, PDD8, PDD9, PDD10 and gate pads PDG7, PDG8, PDG9, PDG10 are also provided.
  • the gate pad PDG7 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGM1
  • the drain pad PDD7 is an output pad electrically connected to the drain of the LDMOSFET formation region REGM1.
  • the pad electrode is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGM1
  • the drain pad PDD7 is an output pad electrically connected to the drain of the LDMOSFET formation region REGM1.
  • the gate pad PDG8 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGM2, and the drain pad PDD8 is electrically connected to the drain of the LDMOSFET formation region REGM2.
  • This is a pad electrode for output.
  • the gate pad PDG9 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGN1
  • the drain pad PDD9 is an output pad electrically connected to the drain of the LDMOSFET formation region REGN1. It is a pad electrode.
  • the gate pad PDG10 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGN2, and the drain pad PDD10 is an output pad electrically connected to the drain of the LDMOSFET formation region REGN2. It is a pad electrode.
  • the semiconductor chip CP1a When the semiconductor chip CP1a is used instead of the semiconductor chip CP1, not only the drain pads PDD1, PDD2, PDD3, PDD4, PDD5 and PDD6 but also one or more of the drain pads PDD7, PDD8, PDD9 and PDD10.
  • the relationship between the pad electrode, the connection region RGW of the wire WA, and the probe mark PRB described with reference to FIGS. 29 to 32 and 39 can also be applied. That is, in FIG. 44 to FIG. 46, a plurality of wires WA are connected to the drain pad PDD7. However, similarly to the drain pad PDD3 in FIG. A region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned between the regions RGW.
  • a plurality of wires WA are connected to the drain pad PDD8.
  • a plurality of wires WA are connected to the drain pad PDD8.
  • a region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned between the regions RGW.
  • a plurality of wires WA are connected to the drain pad PDD9.
  • the drain pad PDD9 similarly to the drain pad PDD3 in FIG. 39 or 43, the drain pad PDD9 also has a connection region RGW of the plurality of wires WA.
  • the region where the probe is pressed in the probe inspection process that is, the probe mark PRB
  • a plurality of wires WA are connected to the drain pad PDD10. However, similarly to the drain pad PDD3 in FIG. 39 or 43, a plurality of wires WA are connected to the drain pad PDD7.
  • a region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned between the regions RGW.
  • the power amplification module has been described as a preferred application example of the present invention.
  • various semiconductor devices in which wires are connected to pad electrodes of a semiconductor chip having an amplification element, and manufacturing methods thereof Can be applied to.
  • the present invention is effective when applied to a semiconductor device and its manufacturing technology.

Abstract

The purpose is to improve the reliability of a semiconductor device, as well as achieving smaller scale of the semiconductor device. A passive component and a semiconductor chip are mounted on a circuit board, a plurality of pad electrodes of the semiconductor chip are electrically connected by wires to a plurality of terminals of the circuit board, and the assembly is resin-encapsulated to manufacture a power amplification module. The semiconductor chip has a drain pad (PDD3) connected to the drain of an LDMOASFET constituting the power amplification circuit, and a plurality of wires are connected to the drain pad (PDD3). In the drain pad (PDD3), a probe mark (PRB) formed by probe inspection is positioned between the connection regions (RGW) of the plurality of wires.

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置およびその製造方法に関し、特に、増幅素子を有する半導体チップのパッドにワイヤを接続した半導体装置およびその製造に適用して有効な技術に関する。 The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which a wire is connected to a pad of a semiconductor chip having an amplifying element and a technique effective when applied to the manufacturing thereof.
　近年、ＧＳＭ（登録商標）方式、ＰＣＳ方式、ＰＤＣ方式、ＣＤＭＡ方式といった通信方式に代表される移動体通信装置（いわゆる携帯電話）が世界的に普及している。 In recent years, mobile communication devices (so-called mobile phones) represented by communication methods such as GSM (registered trademark) method, PCS method, PDC method, and CDMA method have become widespread worldwide.
　一般に、この種の移動体通信装置は、電波の放射と受信をするアンテナ、電力変調された高周波信号を増幅してアンテナへ供給する高周波電力増幅器（ＲＦパワーモジュール）、アンテナで受信した高周波信号を信号処理する受信部、これらの制御を行う制御部、そしてこれらに電源電圧を供給する電池（バッテリー）で構成される。 In general, this type of mobile communication device includes an antenna that emits and receives radio waves, a high-frequency power amplifier (RF power module) that amplifies a power-modulated high-frequency signal and supplies the signal to the antenna, and a high-frequency signal received by the antenna. A receiving unit that performs signal processing, a control unit that performs these controls, and a battery (battery) that supplies a power supply voltage thereto are configured.
　特開２００８－２１８４４２号公報（特許文献１）には、ボンドパッドが実質的に重なりのないプローブ領域およびワイヤボンド領域を有する技術が記載されている。 Japanese Patent Application Laid-Open No. 2008-218442 (Patent Document 1) describes a technique in which a bond pad has a probe region and a wire bond region that do not substantially overlap each other.
　特開２０１１－４０７５９号公報（特許文献２）には、コンタクトパッドがプローブ検査領域とボンディング領域とを有する技術が記載されている。 Japanese Patent Application Laid-Open No. 2011-40759 (Patent Document 2) describes a technique in which a contact pad has a probe inspection region and a bonding region.
特開２００８－２１８４４２号公報JP 2008-218442 A 特開２０１１－４０７５９号公報JP 2011-40759 A
　本発明者の検討によれば、次のことが分かった。 According to the study of the present inventor, the following has been found.
　半導体チップを配線基板に搭載しかつ半導体チップのパッド電極と配線基板の端子とをワイヤで電気的に接続することで、電力増幅モジュールなどの半導体装置が製造される。 A semiconductor device such as a power amplification module is manufactured by mounting a semiconductor chip on a wiring board and electrically connecting pad electrodes of the semiconductor chip and terminals of the wiring board with wires.
　半導体チップを製造するには、半導体ウエハの主面上に種々の素子や配線層を形成し、表面保護膜（およびパッド電極）を形成した後、ウエハ状態でプローブ検査を行う。プローブ検査工程では、半導体ウエハの各チップ領域のパッド電極にプローブ（探針）を当てて、半導体ウエハの各チップ領域の電気的特性を検査する。その後、ダイシングにより半導体ウエハを切断して個片化（チップ化）し、取得された半導体チップは配線基板に搭載され、半導体チップのパッド電極と配線基板の端子との間がワイヤボンディングされる。 To manufacture a semiconductor chip, various elements and wiring layers are formed on the main surface of a semiconductor wafer, a surface protective film (and a pad electrode) is formed, and then a probe inspection is performed in the wafer state. In the probe inspection process, a probe (probe) is applied to the pad electrode of each chip region of the semiconductor wafer to inspect the electrical characteristics of each chip region of the semiconductor wafer. Thereafter, the semiconductor wafer is cut into individual pieces (chips) by dicing, and the obtained semiconductor chip is mounted on the wiring board, and wire bonding is performed between the pad electrode of the semiconductor chip and the terminal of the wiring board.
　プローブ検査の際に、検査用のプローブが押し当てられたパッド電極には、プローブが押し当てられた痕であるプローブ痕が形成される。配線基板に半導体チップを搭載した後に行うワイヤボンディングの際に、パッド電極のプローブ痕上にワイヤを接続しようとすると、平坦性が低下している領域にワイヤを接続することになるため、ワイヤの接続強度が低下する虞がある。ワイヤの接続強度の低下は、製造された半導体装置の信頼性を低下させる。 During probe inspection, a probe mark, which is a mark pressed by the probe, is formed on the pad electrode to which the probe for inspection is pressed. When wire bonding is performed after the semiconductor chip is mounted on the wiring board, if the wire is connected to the probe trace of the pad electrode, the wire is connected to an area where the flatness is lowered. Connection strength may be reduced. The reduction in the connection strength of the wires reduces the reliability of the manufactured semiconductor device.
　一方、パッド電極において、ワイヤの接続領域とプローブ検査工程でプローブを押し当てる領域（プローブ痕）とを分けることも考えられる。しかしながら、パッド電極において、ワイヤの接続領域とプローブ検査工程でプローブを押し当てる領域（プローブ痕）とを単に分ける（別々の領域にする）だけでは、パッド電極の寸法増大により半導体チップの面積の増大を招く虞がある。半導体チップの面積の増大は、製造コストの増大を招き、また、半導体装置の小型化に不利となる。 On the other hand, in the pad electrode, it is also conceivable to divide the wire connection region and the region where the probe is pressed in the probe inspection process (probe mark). However, in the pad electrode, the area of the semiconductor chip is increased by increasing the size of the pad electrode simply by separating the wire connection area and the area where the probe is pressed in the probe inspection process (probe marks). There is a risk of inviting. An increase in the area of the semiconductor chip leads to an increase in manufacturing cost and is disadvantageous for downsizing of the semiconductor device.
　このため、ワイヤの接続強度の向上とチップサイズの抑制とを考慮した総合的な設計が望まれる。 For this reason, a comprehensive design that takes into account improvements in wire connection strength and chip size reduction is desired.
　本発明の目的は、半導体装置の信頼性を向上できる技術を提供することにある。 An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.
　また、本発明の目的は、半導体装置の小型化を図ることができる技術を提供することにある。 Also, an object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.
　本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
　代表的な実施の形態による半導体装置は、複数のパッド電極を有する半導体チップを備え、前記複数のパッド電極に複数のワイヤが接続された半導体装置である。この半導体チップは、電力増幅回路を構成する半導体素子の出力に接続された第１パッド電極を有し、この第１パッド電極に複数の第１ワイヤが接続されており、第１パッド電極において、複数の第１ワイヤの接続領域の間にプローブ痕が形成されている。 A semiconductor device according to a typical embodiment is a semiconductor device including a semiconductor chip having a plurality of pad electrodes, and a plurality of wires connected to the plurality of pad electrodes. This semiconductor chip has a first pad electrode connected to the output of the semiconductor element constituting the power amplifier circuit, and a plurality of first wires are connected to the first pad electrode. In the first pad electrode, Probe marks are formed between the connection regions of the plurality of first wires.
　また、代表的な実施の形態による半導体装置の製造方法は、半導体チップを配線基板上に搭載してから、半導体チップの複数のパッド電極と配線基板の複数の端子とを複数のワイヤを介して電気的に接続する。この半導体チップは、電力増幅回路を構成する半導体素子の出力に接続された第１パッド電極を有しており、ワイヤボンディング工程において、この第１パッド電極には複数の第１ワイヤを接続する。第１パッド電極において、プローブ検査工程でプローブが当てられる位置は、ワイボンディング工程で複数の第１ワイヤを接続する位置の間に位置する。 Further, in a method for manufacturing a semiconductor device according to a representative embodiment, after mounting a semiconductor chip on a wiring board, a plurality of pad electrodes of the semiconductor chip and a plurality of terminals of the wiring board are connected via a plurality of wires. Connect electrically. This semiconductor chip has a first pad electrode connected to the output of the semiconductor element constituting the power amplifier circuit, and a plurality of first wires are connected to the first pad electrode in the wire bonding step. In the first pad electrode, a position where the probe is applied in the probe inspection process is located between positions where the plurality of first wires are connected in the Y bonding process.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
　代表的な実施の形態によれば、半導体装置の信頼性を向上させることができる。 According to the representative embodiment, the reliability of the semiconductor device can be improved.
　また、半導体装置の小型化を図ることができる。 Also, the semiconductor device can be miniaturized.
標準的なデジタル携帯電話機の一例を示すブロック図である。It is a block diagram which shows an example of a standard digital mobile telephone. 図１に示されるデジタル携帯電話機に用いられている電力増幅モジュールの構成例を模式的に示した回路ブロック図である。FIG. 2 is a circuit block diagram schematically showing a configuration example of a power amplification module used in the digital mobile phone shown in FIG. 1. 本発明の一実施の形態の電力増幅モジュールを示す上面図である。It is a top view which shows the power amplification module of one embodiment of this invention. 本発明の一実施の形態の電力増幅モジュールを示す下面図である。It is a bottom view which shows the power amplification module of one embodiment of this invention. 本発明の一実施の形態の電力増幅モジュールを示す平面透視図である。It is a plane perspective view which shows the power amplification module of one embodiment of this invention. 本発明の一実施の形態の電力増幅モジュールを示す断面図である。It is sectional drawing which shows the power amplification module of one embodiment of this invention. 本発明の一実施の形態の電力増幅モジュールを実装基板に実装した状態を示す側面図である。It is a side view which shows the state which mounted the power amplification module of one embodiment of this invention on the mounting board | substrate. 本発明の一実施の形態の電力増幅モジュールの製造工程を示す工程フロー図である。It is a process flow figure showing a manufacturing process of a power amplification module of one embodiment of the present invention. 本発明の一実施の形態の電力増幅モジュールの製造工程中の断面図である。It is sectional drawing in the manufacturing process of the power amplification module of one embodiment of this invention. 図９に続く電力増幅モジュールの製造工程中の断面図である。FIG. 10 is a cross-sectional view of the power amplification module during a manufacturing step following that of FIG. 9; 図１０に続く電力増幅モジュールの製造工程中の断面図である。It is sectional drawing in the manufacturing process of the power amplification module following FIG. 図１１に続く電力増幅モジュールの製造工程中の断面図である。FIG. 12 is a cross-sectional view of the power amplification module during a manufacturing step following that of FIG. 11; 図１２に続く電力増幅モジュールの製造工程中の断面図である。FIG. 13 is a cross-sectional view of the power amplification module during a manufacturing step following that of FIG. 12; 図５の部分拡大平面図である。FIG. 6 is a partially enlarged plan view of FIG. 5. 本発明の一実施の形態の半導体チップの平面図である。It is a top view of the semiconductor chip of one embodiment of the present invention. 本発明の一実施の形態の半導体チップの要部断面図である。It is principal part sectional drawing of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部断面図である。It is principal part sectional drawing of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部断面図である。It is principal part sectional drawing of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部断面図である。It is principal part sectional drawing of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部断面図である。It is principal part sectional drawing of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの製造工程を示す工程フロー図である。It is a process flow figure showing a manufacturing process of a semiconductor chip of a 1 embodiment of the present invention. 本発明の一実施の形態の半導体チップの要部平面図である。It is a principal part top view of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部平面図である。It is a principal part top view of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部平面図である。It is a principal part top view of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部平面図である。It is a principal part top view of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部平面図である。It is a principal part top view of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部平面図である。It is a principal part top view of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部平面図である。It is a principal part top view of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の半導体チップの要部平面図である。It is a principal part top view of the semiconductor chip of one embodiment of this invention. 本発明の一実施の形態の電力増幅モジュールの製造工程中の要部平面図である。It is a principal part top view in the manufacturing process of the power amplification module of one embodiment of this invention. 本発明の一実施の形態の電力増幅モジュールの製造工程中の要部平面図である。It is a principal part top view in the manufacturing process of the power amplification module of one embodiment of this invention. 本発明の一実施の形態の電力増幅モジュールの製造工程中の要部斜視図である。It is a principal part perspective view in the manufacturing process of the power amplification module of one embodiment of this invention. 第１の比較例の半導体チップの要部平面図である。It is a principal part top view of the semiconductor chip of the 1st comparative example. 第１の比較例の電力増幅モジュールの製造工程中の要部平面図である。It is a principal part top view in the manufacturing process of the power amplification module of a 1st comparative example. 第１の比較例の電力増幅モジュールの製造工程中の要部平面図である。It is a principal part top view in the manufacturing process of the power amplification module of a 1st comparative example. 第１の比較例の電力増幅モジュールの製造工程中の要部斜視図である。It is a principal part perspective view in the manufacturing process of the power amplification module of a 1st comparative example. 第１の比較例の半導体チップのドレインパッドに形成されたプローブ痕と、ドレインパッドにおけるワイヤの接続領域とを示す説明図である。It is explanatory drawing which shows the probe trace formed in the drain pad of the semiconductor chip of a 1st comparative example, and the connection area | region of the wire in a drain pad. 第２の比較例の半導体チップのドレインパッドに形成されたプローブ痕とドレインパッドにおけるワイヤの接続領域とを示す説明図である。It is explanatory drawing which shows the probe trace formed in the drain pad of the semiconductor chip of the 2nd comparative example, and the connection area | region of the wire in a drain pad. 本発明の一実施の形態の半導体チップのドレインパッドに形成されたプローブ痕と、ドレインパッド３におけるワイヤの接続領域とを示す説明図である。4 is an explanatory diagram showing probe marks formed on a drain pad of a semiconductor chip according to an embodiment of the present invention, and a wire connection region in the drain pad 3. FIG. 本発明の一実施の形態の半導体チップのドレインパッドに形成されたプローブ痕と、ドレインパッド３におけるワイヤの接続領域とを示す説明図である。4 is an explanatory diagram showing probe marks formed on a drain pad of a semiconductor chip according to an embodiment of the present invention, and a wire connection region in the drain pad 3. FIG. プローブ検査工程でドレインパッドに検査用のプローブを押し当てる様子を示す断面図である。It is sectional drawing which shows a mode that the probe for a test | inspection is pressed against a drain pad at a probe test process. プローブ検査工程でプローブをドレインパッドに押し当てたことで、ドレインパッドにプローブ痕が形成された状態を示す断面図である。It is sectional drawing which shows the state by which the probe trace was formed in the drain pad by pressing the probe on the drain pad at the probe test process. 第１の変形例の説明図である。It is explanatory drawing of the 1st modification. 第２の変形例の説明図である。It is explanatory drawing of the 2nd modification. 第２の変形例の説明図である。It is explanatory drawing of the 2nd modification. 第２の変形例の説明図である。It is explanatory drawing of the 2nd modification.
　以下の実施の形態においては便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。 In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.
　また、実施の形態で用いる図面においては、断面図であっても図面を見易くするためにハッチングを省略する場合もある。また、平面図であっても図面を見易くするためにハッチングを付す場合もある。 In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view in order to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.
　本実施の形態は、例えば、ＧＳＭ方式などのネットワークを利用して情報を伝送するデジタル携帯電話（移動体通信装置）に使用（搭載）されるＲＦ（Radio Frequency）パワーモジュールなどの電力増幅モジュール（半導体装置）およびそれに使用（搭載）される半導体チップ（半導体装置）である。 In the present embodiment, for example, a power amplification module (such as a radio frequency (RF) power module) used (mounted) in a digital mobile phone (mobile communication device) that transmits information using a network such as the GSM system ( A semiconductor device) and a semiconductor chip (semiconductor device) used (mounted).
　ここで、ＧＳＭ（Global System for Mobile Communication）は、デジタル携帯電話に使用されている無線通信方式の１つまたは規格をいう。ＧＳＭには、使用する電波の周波数帯が３つある。このうち、９００ＭＨｚ帯（８２４～９１５ＭＨｚ）をＧＳＭ９００または単にＧＳＭ、１８００ＭＨｚ帯（１７１０～１９１０ＭＨｚ）をＧＳＭ１８００またはＤＣＳ（Digital Cellular System）１８００若しくはＰＣＮ、１９００ＭＨｚ帯をＧＳＭ１９００またはＤＣＳ１９００若しくはＰＣＳ（Personal Communication Services）という。なお、ＧＳＭ１９００は主に北米で使用されている。北米ではその他に８５０ＭＨｚ帯のＧＳＭ８５０を使用する場合もある。本実施の形態の電力増幅モジュールＰＡ１は、例えば、これらの周波数帯（高周波帯）で使用される電力増幅モジュールである。 Here, GSM (Global System for Mobile Communication) is one of radio communication systems or standards used for digital mobile phones. GSM has three frequency bands of radio waves to use. Of these, the 900 MHz band (824 to 915 MHz) is referred to as GSM900 or simply GSM, the 1800 MHz band (1710 to 1910 MHz) is referred to as GSM1800 or DCS (Digital Cellular System) 1800 or PCN, and the 1900 MHz band is referred to as GSM1900 or DCS1900 or PCS (Personal Communication Services). . GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may also be used. The power amplification module PA1 of the present embodiment is a power amplification module used in these frequency bands (high frequency bands), for example.
　＜デジタル携帯電話機の構成について＞
　図１は、標準的なデジタル携帯電話機（デジタル携帯電話機システム、移動体通信装置）ＤＰＳの一例を示すブロック図（説明図）である。 <About the configuration of digital mobile phones>
FIG. 1 is a block diagram (an explanatory diagram) showing an example of a standard digital cellular phone (digital cellular phone system, mobile communication device) DPS.
　図1に示されるデジタル携帯電話機ＤＰＳにおいては、アンテナＡＮＴより受信した信号は、アンテナスイッチＡＮＴ－ＳＷを通って低雑音アンプＬＮＡにより増幅され、受信ミクサＲＸ－ＭＩＸにより１５０～２５０ＭＨｚ程度のＩＦ周波数（中間周波数）に変換された後、ＩＦ回路ＩＦＣで更に周波数変換され、４５５ｋＨｚ程度の第２ＩＦ周波数としてベースバンド部ＢＢＰへ導かれて復調回路ＤＭＤＬで復調される。なお、図１において、符号ＣＯＤ１は音声ＣＯＤＥＣ（コーデック）、符号ＳＰはスピーカ、符号ＭＩＣはマイク、符号ＣＯＤ２はチャネルＣＯＤＥＣ（コーデック）、符号ＭＤＬは変調回路である。 In the digital cellular phone DPS shown in FIG. 1, a signal received from an antenna ANT is amplified by a low noise amplifier LNA through an antenna switch ANT-SW, and an IF frequency of about 150 to 250 MHz by a reception mixer RX-MIX ( (Intermediate frequency), and further frequency converted by the IF circuit IFC, guided to the baseband unit BBP as a second IF frequency of about 455 kHz, and demodulated by the demodulation circuit DMDL. In FIG. 1, code COD1 is an audio CODEC (codec), code SP is a speaker, code MIC is a microphone, code COD2 is a channel CODEC (codec), and code MDL is a modulation circuit.
　また、音声をデジタル化した信号は、ベースバンド部ＢＢＰのＤ／Ａ変換回路ＤＡＣでＤ－Ａ変換（デジタル－アナログ変換）され、Ｉ／Ｑ信号としてＲＦブロック部ＲＦＢＰへ導かれ、直交変調器ＱＭＤによりＩＦ周波数へ変調され、送信ミクサＴＸ－ＭＩＸにより送信信号に変換された後、電力増幅モジュールＰＡ１で増幅され、アンテナスイッチＡＮＴ－ＳＷを通してアンテナＡＮＴから送信される。受信ミクサＲＸ－ＭＩＸおよび送信ミクサＴＸ－ＭＩＸへは、発振器とＰＬＬ（位相同期回路）により構成されたシンセサイザよりローカル信号が供給されている。なお、図１において、符号ＡＧＣＡＭＰはＡＧＣ（Automatic Gain Control）アンプ、符号ＦＰＬ１はＲＦ－ＰＬＬ（ＲＦ周波数位相同期回路）、符号ＦＰＬ２はＩＦ－ＰＬＬ（ＩＦ周波数位相同期回路）である。また、デジタル携帯電話機ＤＰＳは、液晶表示部ＬＣＤ、マイコンＭＣＮおよびメモリＭＲＹなどで構成された表示・制御部ＣＤＰも備えている。 Also, the digitalized signal is DA-converted (digital-analog conversion) by the D / A conversion circuit DAC of the baseband unit BBP, and is guided to the RF block unit RFBP as an I / Q signal, and is a quadrature modulator. After being modulated to an IF frequency by QMD and converted to a transmission signal by transmission mixer TX-MIX, it is amplified by power amplification module PA1 and transmitted from antenna ANT through antenna switch ANT-SW. A local signal is supplied to the reception mixer RX-MIX and the transmission mixer TX-MIX from a synthesizer composed of an oscillator and a PLL (phase synchronization circuit). In FIG. 1, symbol AGCAMP is an AGC (Automatic Gain Control) amplifier, symbol FPL1 is an RF-PLL (RF frequency phase synchronization circuit), and symbol FPL2 is an IF-PLL (IF frequency phase synchronization circuit). The digital cellular phone DPS also includes a display / control unit CDP configured by a liquid crystal display LCD, a microcomputer MCN, a memory MRY, and the like.
　＜電力増幅モジュールの回路構成について＞
　図２は、図１に示されるデジタル携帯電話機ＤＰＳのような移動体通信装置に用いられている電力増幅モジュール（半導体装置、電子装置、電力増幅器、高出力増幅器、高周波電力増幅器、高周波電力増幅装置、電力増幅器モジュール、ＲＦパワーモジュール）ＰＡ１の構成例を模式的に示した回路ブロック図（説明図）である。この図には、例えばＧＳＭ９００とＤＣＳ１８００との２つの周波数帯が使用可能（デュアルバンド方式）で、それぞれの周波数帯でＧＭＳＫ（Gaussian filtered Minimum Shift Keying）変調方式とＥＤＧＥ（Enhanced Data GSM Environment）変調方式との２つの通信方式を使用可能な電力増幅モジュールの回路ブロック図（増幅回路）が示されている。なお、ＧＭＳＫ変調方式は、音声信号の通信に用いる方式で搬送波の位相を送信データに応じて位相シフトする方式である。また、ＥＤＧＥ変調方式は、データ通信に用いる方式でＧＭＳＫ変調の位相シフトにさらに振幅シフトを加えた方式である。 <About the circuit configuration of the power amplification module>
FIG. 2 shows a power amplification module (semiconductor device, electronic device, power amplifier, high output amplifier, high frequency power amplifier, high frequency power amplification device) used in a mobile communication device such as the digital cellular phone DPS shown in FIG. FIG. 2 is a circuit block diagram (explanatory diagram) schematically showing a configuration example of a power amplifier module, RF power module) PA1. In this figure, for example, two frequency bands of GSM900 and DCS1800 can be used (dual band system), and GMSK (Gaussian filtered Minimum Shift Keying) modulation system and EDGE (Enhanced Data GSM Environment) modulation system in each frequency band. The circuit block diagram (amplifier circuit) of the power amplification module which can use two communication systems is shown. Note that the GMSK modulation method is a method used for communication of audio signals, and is a method of shifting the phase of a carrier wave according to transmission data. The EDGE modulation method is a method used for data communication and is a method in which an amplitude shift is further added to the phase shift of GMSK modulation.
　図２に示されるように、電力増幅モジュールＰＡ１の回路構成は、２系統の電力増幅回路（高周波電力増幅回路）ＬＤＭＬ，ＬＤＭＨと、周辺回路１０３と、整合回路１０５Ａ，１０５Ｂ，１０７Ａ，１０７Ｂと、ローパスフィルタ（ローパスフィルタ回路）１０８Ａ，１０８Ｂと、スイッチ回路１０９Ａ，１０９Ｂとを有している。 As shown in FIG. 2, the circuit configuration of the power amplifying module PA1 includes two power amplifying circuits (high frequency power amplifying circuits) LDML and LDMH, a peripheral circuit 103, matching circuits 105A, 105B, 107A, and 107B. Low-pass filters (low-pass filter circuits) 108A and 108B and switch circuits 109A and 109B are provided.
　電力増幅回路ＬＤＭＬは、ＧＳＭ９００用の電力増幅回路であり、複数の増幅段（増幅回路）、ここでは３つの増幅段（増幅回路）ＬＤＭＬ１，ＬＤＭＬ２，ＬＤＭＬ３、を多段接続した多段構成を有している。電力増幅回路ＬＤＭＨは、ＤＣＳ１８００用の電力増幅回路であり、複数の増幅段（増幅回路）、ここでは３つの増幅段（増幅回路）ＬＤＭＨ１，ＬＤＭＨ２，ＬＤＭＨ３、を多段接続した多段構成を有している。 The power amplifier circuit LDML is a power amplifier circuit for GSM900, and has a multi-stage configuration in which a plurality of amplifier stages (amplifier circuits), here, three amplifier stages (amplifier circuits) LDML1, LDML2, and LDML3 are connected in multistage. Yes. The power amplifying circuit LDMH is a power amplifying circuit for DCS1800, and has a multi-stage configuration in which a plurality of amplifying stages (amplifying circuits), here, three amplifying stages (amplifying circuits) LDMH1, LDMH2, and LDMH3 are connected in multistage. Yes.
　整合回路（入力整合回路）１０５Ａは、ＧＳＭ９００用の入力端子１０４ａと電力増幅回路ＬＤＭＬ（１段目の増幅段ＬＤＭＬ１）の間に設けられ、整合回路（入力整合回路）１０５Ｂは、ＤＣＳ１８００用の入力端子１０４ｂと電力増幅回路ＬＤＭＨ（１段目の増幅段ＬＤＭＨ１）の間に設けられている。整合回路（出力整合回路）１０７Ａは、ＧＳＭ９００用のスイッチ回路１０９Ａと電力増幅回路ＬＤＭＬ（３段目の増幅段ＬＤＭＬ３）の間に設けられ、整合回路（出力整合回路）１０７Ｂは、ＤＣＳ１８００用のスイッチ回路１０９Ｂと電力増幅回路ＬＤＭＨ（３段目の増幅段ＬＤＭＨ３）の間に設けられている。 The matching circuit (input matching circuit) 105A is provided between the input terminal 104a for GSM900 and the power amplification circuit LDML (first amplification stage LDML1), and the matching circuit (input matching circuit) 105B is an input for DCS1800. It is provided between terminal 104b and power amplification circuit LDMH (first amplification stage LDMH1). The matching circuit (output matching circuit) 107A is provided between the switch circuit 109A for GSM900 and the power amplifier circuit LDML (third amplifier stage LDML3), and the matching circuit (output matching circuit) 107B is a switch for DCS1800. It is provided between circuit 109B and power amplifier circuit LDMH (third amplifier stage LDMH3).
　ＧＳＭ９００用のローパスフィルタ１０８Ａは、整合回路１０７ＡとＧＳＭ９００用のスイッチ回路１０９Ａの間に設けられ、電力増幅回路ＬＤＭＬの出力が整合回路１０７Ａを経て入力されるようになっている。ＤＣＳ１８００用のローパスフィルタ１０８Ｂは、整合回路１０７ＢとＤＣＳ１８００用のスイッチ回路１０９Ｂの間に設けられ、電力増幅回路ＬＤＭＨの出力が整合回路１０７Ｂを経て入力されるようになっている。 The low-pass filter 108A for GSM900 is provided between the matching circuit 107A and the switch circuit 109A for GSM900, and the output of the power amplifier circuit LDML is input via the matching circuit 107A. The low pass filter 108B for DCS1800 is provided between the matching circuit 107B and the switch circuit 109B for DCS1800, and the output of the power amplifier circuit LDMH is input through the matching circuit 107B.
　また、ＧＳＭ９００用の電力増幅回路ＬＤＭＬの増幅段ＬＤＭＬ１と増幅段ＬＤＭＬ２の間には段間用の整合回路１０２ＡＭ１が設けられ、増幅段ＬＤＭＬ２と増幅段ＬＤＭＬ３の間には段間用の整合回路１０２ＡＭ２が設けられている。また、ＤＣＳ１８００用の電力増幅回路ＬＤＭＨの増幅段ＬＤＭＨ１と増幅段ＬＤＭＨ２の間には段間用の整合回路１０２ＢＭ１が設けられ、増幅段ＬＤＭＨ２と増幅段ＬＤＭＨ３の間には段間用の整合回路１０２ＢＭ２が設けられている。各整合回路はインピーダンスの整合を行う回路であり、ローパスフィルタ１０８Ａ，１０８Ｂは高調波（電力増幅回路ＬＤＭＬ，ＬＤＭＨで発生した高調波成分）を減衰させる回路である。 In addition, an interstage matching circuit 102AM1 is provided between the amplification stage LDML1 and the amplification stage LDML2 of the power amplification circuit LDML for GSM900, and an interstage matching circuit 102AM2 is provided between the amplification stage LDML2 and the amplification stage LDML3. Is provided. An interstage matching circuit 102BM1 is provided between the amplification stage LDMH1 and the amplification stage LDMH2 of the power amplification circuit LDMH for the DCS 1800, and an interstage matching circuit 102BM2 is provided between the amplification stage LDMH2 and the amplification stage LDMH3. Is provided. Each matching circuit is a circuit that performs impedance matching, and the low- pass filters 108A and 108B are circuits that attenuate harmonics (harmonic components generated by the power amplifier circuits LDML and LDMH).
　このうち、ＧＳＭ９００用の電力増幅回路ＬＤＭＬ（増幅段ＬＤＭＬ１～ＬＤＭＬ３）と、ＤＣＳ１８００用の電力増幅回路ＬＤＭＨ（増幅段ＬＤＭＨ１～ＬＤＭＨ３）と、周辺回路１０３とは、１つの半導体チップ（半導体増幅素子チップ、高周波用電力増幅素子チップ、半導体装置）２内に形成されている。なお、電力増幅回路ＬＤＭＬを構成する増幅段ＬＤＭＬ１～ＬＤＭＬ３と、電力増幅回路ＬＤＭＨを構成する増幅段ＬＤＭＨ１～ＬＤＭＨ３とは、半導体チップＣＰ１内に形成されるが、段間用の整合回路１０２ＡＭ１，１０２ＡＭ２，１０２ＢＭ１，１０２ＢＭ２は、半導体チップＣＰ１内に形成しても、半導体チップＣＰ１外に形成してもよい。 Among these, the power amplification circuit LDML (amplification stages LDML1 to LDML3) for GSM900, the power amplification circuit LDMH for DCS1800 (amplification stages LDMH1 to LDMH3), and the peripheral circuit 103 are one semiconductor chip (semiconductor amplification element chip). , High frequency power amplifying element chip, semiconductor device) 2. The amplification stages LDML1 to LDML3 constituting the power amplification circuit LDML and the amplification stages LDMH1 to LDMH3 constituting the power amplification circuit LDMH are formed in the semiconductor chip CP1, but the matching circuits 102AM1, 102AM2 for the stages are used. , 102BM1, 102BM2 may be formed inside the semiconductor chip CP1 or outside the semiconductor chip CP1.
　周辺回路１０３は、電力増幅回路ＬＤＭＬ，ＬＤＭＨの増幅動作の制御や補佐あるいはスイッチ回路１０９Ａ，１０９Ｂの制御などを行う回路であり、制御回路１０３Ａ，１０３Ｃと、上記増幅段ＬＤＭＬ１～ＬＤＭＬ３，ＬＤＭＨ１～ＬＤＭＨ３にバイアス電圧を印加するバイアス回路１０３Ｂなどを有している。 The peripheral circuit 103 is a circuit for controlling and assisting the amplification operation of the power amplifier circuits LDML and LDMH, or controlling the switch circuits 109A and 109B, and the control circuits 103A and 103C, and the amplification stages LDML1 to LDML3 and LDMH1 to LDMH3. And a bias circuit 103B for applying a bias voltage to the.
　制御回路１０３Ａは、上記電力増幅回路ＬＤＭＬ，ＬＤＭＨに印加する所望の電圧を発生する回路であり、電源制御回路１０３Ａ１およびバイアス電圧生成回路１０３Ａ２を有している。電源制御回路１０３Ａ１は、上記増幅段ＬＤＭＬ１～ＬＤＭＬ３，ＬＤＭＨ１～ＬＤＭＨ３の各々の出力用の増幅素子（ここではＬＤＭＯＳＦＥＴ）のドレイン端子に印加される第１電源電圧を生成する回路である。また、上記バイアス電圧生成回路１０３Ａ２は、上記バイアス回路１０３Ｂを制御するための第１制御電圧を生成する回路である。ここでは、電源制御回路１０３Ａ１が外部のベースバンド回路から供給される出力レベル指定信号に基づいて上記第１電源電圧を生成すると、バイアス電圧生成回路１０３Ａ２が電源制御回路１０３Ａ１で生成された上記第１電源電圧に基づいて、上記第１制御電圧を生成するようになっている。上記ベースバンド回路は、上記出力レベル指定信号を生成する回路である。この出力レベル指定信号は、電力増幅回路ＬＤＭＬ、ＬＤＭＨの出力レベルを指定する信号で、携帯電話機と基地局との間の距離、すなわち、電波の強弱に応じた出力レベルに基づいて生成されているようになっている。 The control circuit 103A is a circuit that generates a desired voltage to be applied to the power amplification circuits LDML and LDMH, and includes a power supply control circuit 103A1 and a bias voltage generation circuit 103A2. The power supply control circuit 103A1 is a circuit that generates a first power supply voltage to be applied to the drain terminals of the output amplifying elements (in this case, LDMOSFETs) of the amplification stages LDML1 to LDML3 and LDMH1 to LDMH3. The bias voltage generation circuit 103A2 is a circuit that generates a first control voltage for controlling the bias circuit 103B. Here, when the power supply control circuit 103A1 generates the first power supply voltage based on the output level designation signal supplied from the external baseband circuit, the bias voltage generation circuit 103A2 is generated by the power supply control circuit 103A1. The first control voltage is generated based on the power supply voltage. The baseband circuit is a circuit that generates the output level designation signal. This output level designation signal is a signal that designates the output level of the power amplifier circuits LDML and LDMH, and is generated based on the distance between the mobile phone and the base station, that is, the output level corresponding to the strength of the radio wave. It is like that.
　制御回路１０３Ｃは、スイッチ回路１０９Ａ，１０９Ｂの制御を行う回路である。ＧＳＭ９００の送受信切り換え用のスイッチ回路１０９Ａは、制御回路１０３Ｃからの切換信号に応じて、ＧＳＭ９００の送信時には端子（出力端子）１０６をローパスフィルタ１０８Ａの出力側に接続し、ＧＳＭ９００の受信時には端子１０６を端子１１０ａに接続する。また、ＤＣＳ１８００の送受信切り換え用のスイッチ回路１０９Ｂは、制御回路１０３Ｃからの切換信号に応じて、ＤＣＳ１８００の送信時には端子１０６をローパスフィルタ１０８Ｂの出力側に接続し、ＤＣＳ１８００の受信時には端子１０６を端子１１０ｂに接続する。 The control circuit 103C is a circuit that controls the switch circuits 109A and 109B. In response to the switching signal from the control circuit 103C, the switch circuit 109A for transmission / reception switching of the GSM900 connects the terminal (output terminal) 106 to the output side of the low-pass filter 108A when transmitting the GSM900 and connects the terminal 106 when receiving the GSM900. Connect to terminal 110a. The switch circuit 109B for transmission / reception switching of the DCS 1800 connects the terminal 106 to the output side of the low-pass filter 108B during transmission of the DCS 1800, and connects the terminal 106 to the terminal 110b during reception of the DCS 1800 according to the switching signal from the control circuit 103C. Connect to.
　電力増幅モジュールＰＡ１のＧＳＭ９００用の入力端子１０４ａに入力されたＲＦ入力信号は、整合回路１０５Ａを経て半導体チップＣＰ１に入力され、半導体チップＣＰ１内の電力増幅回路ＬＤＭＬ、すなわち３つの増幅段ＬＤＭＬ１～ＬＤＭＬ３で増幅されて半導体チップＣＰ１から増幅されたＲＦ信号（ＧＳＭ９００のＲＦ信号）として出力される。この増幅されて半導体チップＣＰ１から出力されたＧＳＭ９００のＲＦ信号は、整合回路１０７Ａおよびローパスフィルタ１０８Ａを経てスイッチ回路１０９Ａに入力される。スイッチ回路１０９Ａが、端子１０６をローパスフィルタ１０８Ａの出力側に接続するように切り換えていると、ローパスフィルタ１０８Ａを経てスイッチ回路１０９Ａに入力されたＲＦ信号は、端子１０６からＧＳＭ９００のＲＦ出力信号として出力され、上記アンテナＡＮＴから送信される。 The RF input signal input to the GSM900 input terminal 104a of the power amplifier module PA1 is input to the semiconductor chip CP1 via the matching circuit 105A, and the power amplifier circuit LDML in the semiconductor chip CP1, that is, the three amplification stages LDML1 to LDML3. And output as an RF signal (GSM900 RF signal) amplified from the semiconductor chip CP1. The RF signal of GSM900 amplified and output from the semiconductor chip CP1 is input to the switch circuit 109A through the matching circuit 107A and the low-pass filter 108A. When the switch circuit 109A is switched so as to connect the terminal 106 to the output side of the low-pass filter 108A, the RF signal input to the switch circuit 109A via the low-pass filter 108A is output as an RF output signal of the GSM900 from the terminal 106. And transmitted from the antenna ANT.
　また、電力増幅モジュールＰＡ１のＤＣＳ１８００用の入力端子１０４ｂに入力されたＲＦ入力信号は、整合回路１０５Ｂを経て半導体チップＣＰ１に入力され、半導体チップＣＰ１内の電力増幅回路ＬＤＭＨ、すなわち３つの増幅段ＬＤＭＨ１～ＬＤＭＨ３で増幅されて半導体チップＣＰ１から増幅されたＲＦ信号（ＤＣＳ１８００のＲＦ信号）として出力される。この増幅されて半導体チップＣＰ１から出力されたＤＣＳ１８００のＲＦ信号は、整合回路１０７Ｂおよびローパスフィルタ１０８Ｂを経てスイッチ回路１０９Ｂに入力される。スイッチ回路１０９Ｂが、端子１０６をローパスフィルタ１０８Ｂの出力側に接続するように切り換えていると、ローパスフィルタ１０８Ｂを経てスイッチ回路１０９Ｂに入力されたＲＦ信号は、端子１０６からＤＣＳ１８００のＲＦ出力信号として出力され、上記アンテナＡＮＴから送信される。 The RF input signal input to the DCS 1800 input terminal 104b of the power amplifier module PA1 is input to the semiconductor chip CP1 through the matching circuit 105B, and the power amplifier circuit LDMH in the semiconductor chip CP1, that is, the three amplification stages LDMH1. Amplified by LDMH3 and output from the semiconductor chip CP1 as an RF signal (DCS1800 RF signal). The RF signal of DCS 1800 amplified and output from the semiconductor chip CP1 is input to the switch circuit 109B through the matching circuit 107B and the low-pass filter 108B. When the switch circuit 109B switches so that the terminal 106 is connected to the output side of the low-pass filter 108B, the RF signal input to the switch circuit 109B via the low-pass filter 108B is output from the terminal 106 as the RF output signal of the DCS 1800. And transmitted from the antenna ANT.
　また、電力増幅モジュールＰＡ１の入力端子１０４ｃに入力された入力信号（例えば制御用信号など）が周辺回路１０３に入力され、これに基づいて、周辺回路１０３は、電力増幅回路ＬＤＭＬ，ＬＤＭＨの制御やスイッチ回路１０９Ａ，１０９Ｂの制御などを行うことができる。 Further, an input signal (for example, a control signal) input to the input terminal 104c of the power amplification module PA1 is input to the peripheral circuit 103, and based on this, the peripheral circuit 103 controls the power amplification circuits LDML and LDMH. The switch circuits 109A and 109B can be controlled.
　スイッチ回路１０９Ａ，１０９Ｂは、上記図１の上記アンテナスイッチＡＮＴ－ＳＷに対応するものであり、図２に示される電力増幅モジュールＰＡ１は、上記図１の上記アンテナスイッチＡＮＴ－ＳＷも、電力増幅モジュールＰＡ１に内蔵させた場合に対応する。他の形態として、上記アンテナスイッチＡＮＴ－ＳＷを、電力増幅モジュールＰＡ１の外部に設けることもでき、この場合、スイッチ回路１０９Ａ，１０９Ｂは電力増幅モジュールＰＡ１の外部に設けられることになる。また、更に、上記ローパスフィルタ（ローパスフィルタ回路）１０８Ａ，１０８Ｂを、電力増幅モジュールＰＡ１の外部に設けることもできる。 The switch circuits 109A and 109B correspond to the antenna switch ANT-SW in FIG. 1, and the power amplification module PA1 shown in FIG. 2 is the same as the antenna switch ANT-SW in FIG. This corresponds to the case where it is built in PA1. As another form, the antenna switch ANT-SW can be provided outside the power amplification module PA1, and in this case, the switch circuits 109A and 109B are provided outside the power amplification module PA1. Furthermore, the low-pass filters (low-pass filter circuits) 108A and 108B can be provided outside the power amplification module PA1.
　上記電力増幅回路ＬＤＭＬ，ＬＤＭＨのそれぞれは、上記３段の増幅段ＬＤＭＬ１～ＬＤＭＬ３，ＬＤＭＨ１～ＬＤＭＨ３として、３個のｎチャネル型のＬＤＭＯＳＦＥＴ（Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor、横方向拡散ＭＯＳＦＥＴ)を順次従属接続（多段接続）した回路構成を有している。すなわち、各増幅段ＬＤＭＬ１，ＬＤＭＬ２，ＬＤＭＬ３，ＬＤＭＨ１，ＬＤＭＨ２，ＬＤＭＨ３がｎチャネル型のＬＤＭＯＳＦＥＴ素子により形成されている。 Each of the power amplifier circuits LDML and LDMH is composed of three n-channel LDMOSFETs (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor, lateral diffusion MOSFET) ) Are sequentially connected in cascade (multi-stage connection). That is, each amplification stage LDML1, LDML2, LDML3, LDMH1, LDMH2, and LDMH3 are formed by n-channel LDMOSFET elements.
　そして、３個のｎチャネル型ＬＤＭＯＳＦＥＴ（すなわち増幅段ＬＤＭＬ１を構成するｎチャネル型ＬＤＭＯＳＦＥＴと増幅段ＬＤＭＬ２を構成するｎチャネル型ＬＤＭＯＳＦＥＴと増幅段ＬＤＭＬ３を構成するｎチャネル型ＬＤＭＯＳＦＥＴ）が順次接続（多段接続）されて電力増幅回路ＬＤＭＬが形成されている。 Then, three n-channel LDMOSFETs (that is, an n-channel LDMOSFET constituting the amplification stage LDML1, an n-channel LDMOSFET constituting the amplification stage LDML2, and an n-channel LDMOSFET constituting the amplification stage LDML3) are sequentially connected (multistage connection). ) To form a power amplifier circuit LDML.
　具体的には、ＧＳＭ９００用の入力端子１０４ａが、整合回路１０５Ａを介して、増幅段ＬＤＭＬ１を構成するｎチャネル型ＬＤＭＯＳＦＥＴのゲートに電気的に接続され、増幅段ＬＤＭＬ１を構成するｎチャネル型ＬＤＭＯＳＦＥＴのドレインが、整合回路１０２ＡＭ１を介して、増幅段ＬＤＭＬ２を構成するｎチャネル型ＬＤＭＯＳＦＥＴのゲートに電気的に接続されている。そして、増幅段ＬＤＭＬ２を構成するｎチャネル型ＬＤＭＯＳＦＥＴのドレインが、整合回路１０２ＡＭ２を介して、増幅段ＬＤＭＬ３を構成するｎチャネル型ＬＤＭＯＳＦＥＴのゲートに電気的に接続され、増幅段ＬＤＭＬ３を構成するｎチャネル型ＬＤＭＯＳＦＥＴのドレインが、整合回路１０７Ａを介してローパスフィルタ１０８Ａに電気的に接続されている。 Specifically, the input terminal 104a for GSM900 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDML1 via the matching circuit 105A, and the n-channel LDMOSFET constituting the amplification stage LDML1 is electrically connected. The drain is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDML2 through the matching circuit 102AM1. The drain of the n-channel LDMOSFET constituting the amplification stage LDML2 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDML3 via the matching circuit 102AM2, and the n-channel constituting the amplification stage LDML3. The drain of the type LDMOSFET is electrically connected to the low-pass filter 108A through the matching circuit 107A.
　また、３個のｎチャネル型ＬＤＭＯＳＦＥＴ（すなわち増幅段ＬＤＭＨ１を構成するｎチャネル型ＬＤＭＯＳＦＥＴと増幅段ＬＤＭＨ２を構成するｎチャネル型ＬＤＭＯＳＦＥＴと増幅段ＬＤＭＨ３を構成するｎチャネル型ＬＤＭＯＳＦＥＴ）が順次接続（多段接続）されて電力増幅回路ＬＤＭＨが形成されている。 Further, three n-channel LDMOSFETs (that is, an n-channel LDMOSFET constituting the amplification stage LDMH1, an n-channel LDMOSFET constituting the amplification stage LDMH2, and an n-channel LDMOSFET constituting the amplification stage LDMH3) are sequentially connected (multi-stage connection). ) To form a power amplifier circuit LDMH.
　具体的には、ＤＣＳ１８００用の入力端子１０４ｂが、整合回路１０５Ｂを介して、増幅段ＬＤＭＨ１を構成するｎチャネル型ＬＤＭＯＳＦＥＴのゲートに電気的に接続され、増幅段ＬＤＭＨ１を構成するｎチャネル型ＬＤＭＯＳＦＥＴのドレインが、整合回路１０２ＢＭ１を介して、増幅段ＬＤＭＨ２を構成するｎチャネル型ＬＤＭＯＳＦＥＴのゲートに電気的に接続されている。そして、増幅段ＬＤＭＨ２を構成するｎチャネル型ＬＤＭＯＳＦＥＴのドレインが、整合回路１０２ＢＭ２を介して、増幅段ＬＤＭＨ３を構成するｎチャネル型ＬＤＭＯＳＦＥＴのゲートに電気的に接続され、増幅段ＬＤＭＨ３を構成するｎチャネル型ＬＤＭＯＳＦＥＴのドレインが、整合回路１０７Ｂを介してローパスフィルタ１０８Ｂに電気的に接続されている。 Specifically, the input terminal 104b for DCS1800 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDMH1 via the matching circuit 105B, and the n-channel LDMOSFET constituting the amplification stage LDMH1 is connected. The drain is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDMH2 through the matching circuit 102BM1. The drain of the n-channel LDMOSFET constituting the amplification stage LDMH2 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDMH3 via the matching circuit 102BM2, and the n-channel constituting the amplification stage LDMH3. The drain of the type LDMOSFET is electrically connected to the low-pass filter 108B through the matching circuit 107B.
　なお、本実施の形態では、３段の増幅段が接続（多段接続）されて各電力増幅回路ＬＤＭＬ，ＬＤＭＨを形成しているが、他の形態として、２段の増幅段または４段以上の増幅段を接続（多段接続）して各電力増幅回路ＬＤＭＬ，ＬＤＭＨを形成することも可能であり、この場合、各電力増幅回路ＬＤＭＬ，ＬＤＭＨは２個または４個以上のｎチャネル型ＬＤＭＯＳＦＥＴが従属接続した回路構成となる。 In this embodiment, three amplification stages are connected (multi-stage connection) to form each power amplification circuit LDML, LDMH. However, as another form, two amplification stages or four or more stages are used. It is also possible to connect the amplifier stages (multi-stage connection) to form each power amplifier circuit LDML, LDMH. In this case, each power amplifier circuit LDML, LDMH is subordinate to two or four or more n-channel LDMOSFETs. Connected circuit configuration.
　＜電力増幅モジュールの構造について＞
　図３は、本実施の形態の電力増幅モジュールＰＡ１の上面図（平面図）であり、図４は、電力増幅モジュールＰＡ１の下面図であり、図５は、電力増幅モジュールＰＡ１の平面透視図であり、封止樹脂１３を透視した状態が示されている。図６は、本実施の形態の電力増幅モジュールＰＡ１の断面図（側面断面図）である。なお、図６は断面図、図５は平面図に対応するが、いずれも電力増幅モジュールＰＡ１の概念的な構造が示されており、図５の構造を所定の位置で切断した断面と図６の断面図とは完全には一致していない。 <About the structure of the power amplification module>
FIG. 3 is a top view (plan view) of the power amplification module PA1 of the present embodiment, FIG. 4 is a bottom view of the power amplification module PA1, and FIG. 5 is a plan perspective view of the power amplification module PA1. There is shown a state in which the sealing resin 13 is seen through. FIG. 6 is a cross-sectional view (side cross-sectional view) of power amplification module PA1 of the present embodiment. 6 corresponds to a cross-sectional view, and FIG. 5 corresponds to a plan view, both of which show a conceptual structure of the power amplification module PA1. FIG. 6 is a cross-sectional view of the structure of FIG. Is not completely consistent with the cross-sectional view.
　図３～図６に示される本実施の形態の電力増幅モジュールＰＡ１は、配線基板（多層基板、多層配線基板、モジュール基板）１１と、配線基板１１上に搭載（実装）された半導体チップ（半導体素子、能動素子）ＣＰ１と、配線基板１１上に搭載（実装）された受動部品（受動素子、チップ部品）１２と、半導体チップＣＰ１および受動部品１２を含む配線基板１１の上面１１ａを覆う封止樹脂（封止部、封止樹脂部）１３とを有している。半導体チップＣＰ１および受動部品１２は、配線基板１１の導体層（伝送線路）に電気的に接続されている。また、電力増幅モジュールＰＡ１は、例えば図示しない外部回路基板またはマザーボードなどに実装することもできる。電力増幅モジュールＰＡ１は、半導体チップＣＰ１を有しているので半導体装置とみなすことができるが、電子装置とみなすこともできる。 A power amplification module PA1 of the present embodiment shown in FIGS. 3 to 6 includes a wiring board (multilayer board, multilayer wiring board, module board) 11 and a semiconductor chip (semiconductor) mounted (mounted) on the wiring board 11. An element, an active element) CP1, a passive component (passive element, chip component) 12 mounted (mounted) on the wiring substrate 11, and a sealing covering the upper surface 11a of the wiring substrate 11 including the semiconductor chip CP1 and the passive component 12. And a resin (sealing portion, sealing resin portion) 13. The semiconductor chip CP1 and the passive component 12 are electrically connected to the conductor layer (transmission line) of the wiring board 11. The power amplification module PA1 can also be mounted on, for example, an external circuit board (not shown) or a motherboard. The power amplification module PA1 can be regarded as a semiconductor device because it includes the semiconductor chip CP1, but can also be regarded as an electronic device.
　配線基板１１は、例えば、複数の絶縁体層（誘電体層）１４と、複数の導体層（配線層）とを積層して一体化した多層配線基板（多層基板）である。図６では、５つの絶縁体層１４が積層されて配線基板１１が形成されているが、積層される絶縁体層１４の数はこれに限定されるものではなく種々変更可能である。配線基板１１を構成する各導体層（配線層）１５は、必要に応じて絶縁体層１４に形成されたビアホール（スルーホール）１６内の導体（導体膜）を通じて電気的に接続されている。配線基板１１の絶縁体層１４を形成する材料としては、例えばアルミナ（酸化アルミニウム、Ａｌ２Ｏ３）などのようなセラミック材料を用いることができる。この場合、配線基板１１はセラミック多層基板である。配線基板１１の絶縁体層１４の材料は、セラミック材料に限定されるものではなく種々変更可能であり、例えばガラスエポキシ樹脂などを用いても良い。 The wiring board 11 is, for example, a multilayer wiring board (multilayer board) in which a plurality of insulator layers (dielectric layers) 14 and a plurality of conductor layers (wiring layers) are stacked and integrated. In FIG. 6, the five insulating layers 14 are laminated to form the wiring board 11. However, the number of the insulating layers 14 to be laminated is not limited to this and can be variously changed. Each conductor layer (wiring layer) 15 constituting the wiring board 11 is electrically connected through a conductor (conductor film) in a via hole (through hole) 16 formed in the insulator layer 14 as necessary. As a material for forming the insulator layer 14 of the wiring substrate 11, a ceramic material such as alumina (aluminum oxide, Al 2 O 3 ) can be used. In this case, the wiring board 11 is a ceramic multilayer board. The material of the insulator layer 14 of the wiring board 11 is not limited to a ceramic material and can be variously changed. For example, a glass epoxy resin may be used.
　配線基板１１の上面（表面）１１ａ上と下面（裏面）１１ｂ上と絶縁体層１４間とには、配線形成用の導体層（配線層、配線パターン、導体パターン）１５が形成されている。配線基板１１の最上層の導体層１５によって、配線基板１１の上面１１ａに、導電体からなる基板側端子（端子、電極）ＴＥおよびチップ搭載用導体パターン１５ｃが形成され、配線基板１１の最下層の導体層１５によって、配線基板１１の下面１１ｂに、導電体からなる外部接続用端子（端子、電極、モジュール電極）１５ａおよび基準電位供給用端子１５ｂが形成されている。 A conductor layer (wiring layer, wiring pattern, conductor pattern) 15 for wiring formation is formed on the upper surface (front surface) 11a and the lower surface (back surface) 11b of the wiring substrate 11 and between the insulator layers 14. A conductor-side board (terminal, electrode) TE made of a conductor and a chip mounting conductor pattern 15 c are formed on the upper surface 11 a of the wiring board 11 by the uppermost conductor layer 15 of the wiring board 11, and the lowermost layer of the wiring board 11. The conductor layer 15 forms an external connection terminal (terminal, electrode, module electrode) 15 a made of a conductor and a reference potential supply terminal 15 b on the lower surface 11 b of the wiring board 11.
　外部接続用端子１５ａは、上記入力端子１０４ａ，１０４ｂ，１０４ｃに対応する端子と上記端子（出力端子）１０６に対応する端子とを含んでいる。配線基板１１の内部、すなわち絶縁体層１４の間にも導体層（配線層、配線パターン、導体パターン）１５が形成されている。また、配線基板１１の導体層１５により形成される配線パターンのうち、基準電位供給用の配線パターン（例えば配線基板１１の下面１１ｂの基準電位供給用端子１５ｂなど）は、絶縁体層１４の配線形成面の大半の領域を覆うような矩形パターンで形成し、伝送線路用の配線パターンは帯状のパターンで形成することができる。 The external connection terminal 15 a includes terminals corresponding to the input terminals 104 a, 104 b, and 104 c and terminals corresponding to the terminals (output terminals) 106. A conductor layer (wiring layer, wiring pattern, conductor pattern) 15 is also formed in the wiring substrate 11, that is, between the insulator layers 14. Among the wiring patterns formed by the conductor layer 15 of the wiring substrate 11, the wiring pattern for supplying the reference potential (for example, the reference potential supplying terminal 15 b on the lower surface 11 b of the wiring substrate 11) is the wiring of the insulator layer 14. The wiring pattern for the transmission line can be formed as a band-shaped pattern, with a rectangular pattern covering most of the formation surface.
　半導体チップＣＰ１は、単結晶シリコンなどからなる半導体基板（半導体ウエハ）に半導体集積回路を形成した後、必要に応じて半導体基板の裏面研削を行ってから、ダイシングなどにより半導体基板を各半導体チップＣＰ１に分離したものである。半導体チップＣＰ１の表面（上面）には、複数のパッド電極（電極、ボンディングパッド）ＰＤが形成されており、各パッド電極ＰＤは、半導体チップＣＰ１内に形成された半導体素子または半導体集積回路に電気的に接続されている。半導体チップＣＰ１の構成については、後でより詳細に説明する。なお、半導体チップＣＰ１の互いに反対側に位置する２つの主面のうち、パッド電極ＰＤが形成された側の主面を半導体チップＣＰ１の表面と称し、パッド電極ＰＤが形成された側の主面（表面）とは反対側の主面（すなわち裏面電極ＢＥ１が形成された側の主面）を、半導体チップＣＰ１の裏面と称することとする。 The semiconductor chip CP1 is formed by forming a semiconductor integrated circuit on a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like, and then grinding the back surface of the semiconductor substrate as necessary, and then dicing or the like to each semiconductor chip CP1. It is separated. A plurality of pad electrodes (electrodes, bonding pads) PD are formed on the surface (upper surface) of the semiconductor chip CP1, and each pad electrode PD is electrically connected to a semiconductor element or a semiconductor integrated circuit formed in the semiconductor chip CP1. Connected. The configuration of the semiconductor chip CP1 will be described in detail later. Of the two principal surfaces located on opposite sides of the semiconductor chip CP1, the principal surface on the side where the pad electrode PD is formed is referred to as the surface of the semiconductor chip CP1, and the principal surface on the side where the pad electrode PD is formed. The main surface opposite to the (front surface) (that is, the main surface on which the back electrode BE1 is formed) is referred to as the back surface of the semiconductor chip CP1.
　図６に示されるように、半導体チップＣＰ１は配線基板１１の上面１１ａにおけるチップ搭載用導体パターン１５ｃに、例えば半田１８などの接合材（接着材）によりフェイスアップでダイボンディング（接合）されている。半導体チップＣＰ１のダイボンディングには、半田１８の代わりに、銀ペーストなどの導電性ペースト型接着材を用いることもできる。半導体チップＣＰ１の表面（上面）に形成されたパッド電極ＰＤは、導電性のワイヤ（ボンディングワイヤ）ＷＡを介して配線基板１１の上面１１ａの基板側端子ＴＥに電気的に接続されている。また、半導体チップＣＰ１の裏面全面には裏面電極ＢＥ１が形成されており、この半導体チップＣＰ１の裏面電極ＢＥ１は、配線基板１１の上面１１ａのチップ搭載用導体パターン１５ｃに半田１８などの導電性の接合材により接合されて電気的に接続され、更にビアホール１６（１６ａ）内の導体などを介して、配線基板１１の下面１１ｂの基準電位供給用端子１５ｂに電気的に接続されている。なお、ビアホール１６のうち、半導体チップＣＰ１の下方に設けられたビアホール１６ａは、半導体チップＣＰ１で生じた熱を配線基板１１の下面１１ｂ側に伝導させるためのサーマルビアとして機能することもできる。 As shown in FIG. 6, the semiconductor chip CP1 is die-bonded (bonded) to the chip mounting conductor pattern 15c on the upper surface 11a of the wiring substrate 11 with a bonding material (adhesive material) such as solder 18 face up. . For die bonding of the semiconductor chip CP1, instead of the solder 18, a conductive paste adhesive such as silver paste can be used. The pad electrode PD formed on the surface (upper surface) of the semiconductor chip CP1 is electrically connected to the substrate-side terminal TE on the upper surface 11a of the wiring substrate 11 through a conductive wire (bonding wire) WA. Also, a back electrode BE1 is formed on the entire back surface of the semiconductor chip CP1, and the back electrode BE1 of the semiconductor chip CP1 is electrically conductive such as solder 18 on the chip mounting conductor pattern 15c on the top surface 11a of the wiring substrate 11. Bonded by a bonding material and electrically connected, and further electrically connected to a reference potential supply terminal 15b on the lower surface 11b of the wiring substrate 11 via a conductor in the via hole 16 (16a). Of the via holes 16, the via hole 16a provided below the semiconductor chip CP1 can also function as a thermal via for conducting heat generated in the semiconductor chip CP1 to the lower surface 11b side of the wiring substrate 11.
　受動部品１２は、抵抗素子（例えばチップ抵抗）、容量素子（例えばチップコンデンサ）またはインダクタ素子（例えばチップインダクタ）などの受動素子からなり、例えばチップ部品からなる。受動部品１２は、例えば上記整合回路１０５Ａ，１０５Ｂ，１０７Ａ，１０７Ｂ，１０２ＡＭ１，１０２ＡＭ２，１０２ＢＭ１，１０２ＢＭ２などを構成する受動部品である。受動部品１２の電極は、配線基板１１の上面１１ａの基板側端子ＴＥに半田１８などの導電性の接合材により接合されて電気的に接続されている。 The passive component 12 is composed of a passive element such as a resistive element (for example, a chip resistor), a capacitive element (for example, a chip capacitor), or an inductor element (for example, a chip inductor), for example, a chip component. The passive component 12 is a passive component that constitutes the matching circuits 105A, 105B, 107A, 107B, 102AM1, 102AM2, 102BM1, and 102BM2, for example. The electrodes of the passive component 12 are joined and electrically connected to the board-side terminal TE on the upper surface 11a of the wiring board 11 by a conductive joining material such as solder 18.
　半導体チップＣＰ１または受動部品１２が電気的に接続された配線基板１１の上面１１ａの基板側端子ＴＥは、必要に応じて配線基板１１の上面１１ａまたは内部の導体層（配線層）１５やビアホール１６内の導体などを介して結線され、また、必要に応じて配線基板１１の下面１１ｂの外部接続用端子１５ａまたは基準電位供給用端子１５ｂに電気的に接続されている。 The board-side terminal TE on the upper surface 11a of the wiring board 11 to which the semiconductor chip CP1 or the passive component 12 is electrically connected is connected to the upper surface 11a of the wiring board 11 or an internal conductor layer (wiring layer) 15 or via hole 16 as necessary. The wiring is connected via an internal conductor or the like, and is electrically connected to the external connection terminal 15a or the reference potential supply terminal 15b on the lower surface 11b of the wiring board 11 as necessary.
　また、配線基板１１の上面１１ａおよび下面には、半田レジスト層（図示せず）が形成されているが、配線基板１１の上面において、端子ＴＥは半田レジスト層の開口部から露出され、配線基板１１の下面において、外部接続用端子１５ａおよび基準電位供給用端子１５ｂは半田レジスト層から露出されている。 Further, a solder resist layer (not shown) is formed on the upper surface 11a and the lower surface of the wiring substrate 11. On the upper surface of the wiring substrate 11, the terminal TE is exposed from the opening of the solder resist layer. 11, the external connection terminal 15 a and the reference potential supply terminal 15 b are exposed from the solder resist layer.
　封止樹脂１３は、半導体チップＣＰ１、受動部品１２およびワイヤＷＡを覆うように配線基板１１の上面１１ａ上に形成されている。封止樹脂１３は、例えばエポキシ樹脂またはシリコーン樹脂などの樹脂材料からなり、フィラーなどを含有することもできる。 The sealing resin 13 is formed on the upper surface 11a of the wiring board 11 so as to cover the semiconductor chip CP1, the passive component 12, and the wire WA. The sealing resin 13 is made of, for example, a resin material such as an epoxy resin or a silicone resin, and can contain a filler or the like.
　＜電力増幅モジュールの実装例について＞
　図７は、本実施の形態の電力増幅モジュールＰＡ１を実装基板（配線基板、マザーボード、外部回路基板）２１に実装した状態を模式的に示す側面図である。 <About mounting example of power amplification module>
FIG. 7 is a side view schematically showing a state in which the power amplification module PA1 of the present embodiment is mounted on a mounting board (wiring board, motherboard, external circuit board) 21. FIG.
　図７に示されるように、実装基板２１の上面２１ａ上に電力増幅モジュールＰＡ１や他の部品２２（例えば受動部品など）が実装される。この際、電力増幅モジュールＰＡ１の外部接続用端子１５ａは、実装基板２１の端子２３ａに、半田２４などの導電性の接合材を介して接合されて電気的に接続され、電力増幅モジュールＰＡ１の基準電位供給用端子１５ｂは、実装基板２１の端子（基準電位供給用端子）２３ｂに半田２４などの導電性の接合材を介して接合されて電気的に接続される。また、部品２２の電極は、実装基板２１の端子２３ｃに、半田２４などの導電性の接合材を介して接合されて電気的に接続される。このため、実装基板２１の端子（基準電位供給用端子）２３ｂから、半田２４および基準電位供給用端子１５ｂを介して、電力増幅モジュールＰＡ１に基準電位（グランド電位、接地電位）を供給することができる。 7, the power amplification module PA1 and other components 22 (for example, passive components) are mounted on the upper surface 21a of the mounting substrate 21. At this time, the external connection terminal 15a of the power amplification module PA1 is joined and electrically connected to the terminal 23a of the mounting substrate 21 via a conductive joining material such as solder 24, and the reference of the power amplification module PA1. The potential supply terminal 15b is joined to and electrically connected to a terminal (reference potential supply terminal) 23b of the mounting substrate 21 via a conductive joining material such as solder 24. Further, the electrodes of the component 22 are joined and electrically connected to the terminals 23 c of the mounting substrate 21 via a conductive joining material such as solder 24. Therefore, a reference potential (ground potential, ground potential) is supplied from the terminal (reference potential supply terminal) 23b of the mounting substrate 21 to the power amplification module PA1 via the solder 24 and the reference potential supply terminal 15b. it can.
　＜電力増幅モジュールの製造工程について＞
　次に、電力増幅モジュールＰＡ１の製造工程の一例を図面を参照して説明する。 <About manufacturing process of power amplification module>
Next, an example of a manufacturing process of the power amplification module PA1 will be described with reference to the drawings.
　図８は、電力増幅モジュールＰＡ１の製造工程を示す工程フロー図である。図９～図１３は、本実施の形態の電力増幅モジュールＰＡ１の製造工程中の断面図である。本実施の形態の電力増幅モジュールＰＡ１は、例えば次のようにして製造することができる。 FIG. 8 is a process flow diagram showing the manufacturing process of the power amplification module PA1. 9 to 13 are cross-sectional views of the power amplification module PA1 according to the present embodiment during the manufacturing process. The power amplification module PA1 of the present embodiment can be manufactured, for example, as follows.
　まず、図９に示されるように、配線基板として配線基板母体（配線基板）２５を準備する（図８のステップＳ１）。この配線基板母体２５は、後述の切断工程後に配線基板１１となるものであり、例えば、印刷法、シート積層法またはビルドアップ法などを用いて製造することができる。また、配線基板母体２５の上面２５ａは、後述の切断工程後に配線基板１１の上面１１ａとなる。 First, as shown in FIG. 9, a wiring board base (wiring board) 25 is prepared as a wiring board (step S1 in FIG. 8). The wiring board base body 25 becomes the wiring board 11 after a cutting process described later, and can be manufactured using, for example, a printing method, a sheet lamination method, a build-up method, or the like. Further, the upper surface 25a of the wiring board base body 25 becomes the upper surface 11a of the wiring board 11 after a cutting process described later.
　また、半導体チップＣＰ１を準備する（図８のステップＳ２）。ステップＳ２の半導体チップＣＰ１の準備工程は、ステップＳ１の配線基板母体２５の準備工程よりも先に行っても、後に行っても、あるいは同時に行ってもよい。ステップＳ２の半導体チップＣＰ１の準備工程は、後述のステップＳ１１，Ｓ１２，Ｓ１３を有している。 Further, the semiconductor chip CP1 is prepared (Step S2 in FIG. 8). The step of preparing the semiconductor chip CP1 in step S2 may be performed before, after, or simultaneously with the step of preparing the wiring board base 25 in step S1. The preparation process of the semiconductor chip CP1 in step S2 includes steps S11, S12, and S13 described later.
　次に、図１０に示されるように、配線基板母体２５の上面２５ａにおいて、半導体チップＣＰ１を搭載予定のチップ搭載用導体パターン１５ｃおよび受動部品１２を搭載予定の基板側端子ＴＥに、半田などの接合材を必要に応じて印刷または塗布する。それから、配線基板母体２５の上面２５ａ上に半導体チップＣＰ１および受動部品１２を搭載（配置）する（図８のステップＳ３）。この際、半導体チップＣＰ１は、裏面側（裏面電極ＢＥ１側）が下方（配線基板母体２５側）を向き、表面側（パッド電極ＰＤ側）が上方を向くように（フェイスアップボンディング）、配線基板母体２５の上面２５ａ（のチップ搭載用導体パターン１５ｃ）上に搭載（配置）される。それから、半田リフロー処理などを行って、半導体チップＣＰ１および受動部品１２を配線基板母体２５に半田１８などの接合材を介して固着（接合、接続、固定）する（図８のステップＳ４）。半田リフローで溶融・固化した半田が、半田１８となる。また、他の形態として、配線基板母体２５への受動部品１２の実装工程と配線基板２５への半導体チップＣＰ１の実装工程とを、別々に行なうこともでき、この場合、例えば、配線基板母体２５へ受動部品１２を搭載して半田などの接合材で固定してから、配線基板母体２５へ半導体チップＣＰ１を搭載して接合材（半田または導電性ペースト型接着材など）で固定することができる。 Next, as shown in FIG. 10, on the upper surface 25a of the wiring board base 25, the chip mounting conductor pattern 15c on which the semiconductor chip CP1 is to be mounted and the board-side terminal TE on which the passive component 12 is to be mounted are connected to solder or the like. The bonding material is printed or applied as necessary. Then, the semiconductor chip CP1 and the passive component 12 are mounted (arranged) on the upper surface 25a of the wiring board mother body 25 (step S3 in FIG. 8). At this time, in the semiconductor chip CP1, the wiring board is arranged such that the back side (back side electrode BE1 side) faces downward (wiring board base 25 side) and the front side (pad electrode PD side) faces upward (face-up bonding). It is mounted (arranged) on the upper surface 25a (the chip mounting conductor pattern 15c) of the mother body 25. Then, by performing a solder reflow process or the like, the semiconductor chip CP1 and the passive component 12 are fixed (bonded, connected, fixed) to the wiring board base 25 via a bonding material such as solder 18 (step S4 in FIG. 8). The solder melted and solidified by the solder reflow becomes the solder 18. As another form, the mounting process of the passive component 12 on the wiring board base 25 and the mounting process of the semiconductor chip CP1 on the wiring board 25 can be performed separately. In this case, for example, the wiring board base 25 After the passive component 12 is mounted and fixed with a bonding material such as solder, the semiconductor chip CP1 can be mounted on the wiring board base 25 and fixed with a bonding material (such as solder or a conductive paste adhesive). .
　次に、図１１に示されるように、ワイヤボンディング工程を行って、半導体チップＣＰ１の表面の複数のパッド電極ＰＤと配線基板母体２５の上面２５ａの複数の基板側端子ＴＥとを複数のワイヤ（ボンディングワイヤ）ＷＡを介してそれぞれ電気的に接続する（図８のステップＳ５）。 Next, as shown in FIG. 11, a wire bonding step is performed to connect a plurality of pad electrodes PD on the surface of the semiconductor chip CP1 and a plurality of substrate-side terminals TE on the upper surface 25a of the wiring board base 25 to a plurality of wires ( Bonding wires) are electrically connected via WA (step S5 in FIG. 8).
　次に、図１２に示されるように、配線基板母体２５の上面２５ａ上に、半導体チップＣＰ１、受動部品１２およびワイヤＷＡを覆うように、封止樹脂（封止部、封止樹脂部）１３を形成する。封止樹脂１３は、例えば印刷法またはモールド用金型（例えばトランスファモールド）などを用いて形成することができる（図８のステップＳ６）。 Next, as shown in FIG. 12, the sealing resin (sealing part, sealing resin part) 13 is formed on the upper surface 25a of the wiring board base 25 so as to cover the semiconductor chip CP1, the passive component 12, and the wire WA. Form. The sealing resin 13 can be formed using, for example, a printing method or a mold for molding (for example, transfer mold) (step S6 in FIG. 8).
　次に、図１３に示されるように、配線基板母体２５と封止樹脂１３をダイシングなどで切断することで、電力増幅モジュールＰＡ１を製造することができる（図８のステップＳ７）。切断後の配線基板母体２５が上記配線基板１１となる。 Next, as shown in FIG. 13, the power amplification module PA1 can be manufactured by cutting the wiring board base 25 and the sealing resin 13 by dicing or the like (step S7 in FIG. 8). The wiring board matrix 25 after cutting becomes the wiring board 11.
　＜半導体チップの構造について＞
　図１４は、上記図５の部分拡大平面図であり、配線基板１１に搭載された半導体チップＣＰ１とその周辺領域が拡大して示してある。図１５は、図１４からワイヤＷＡおよび基板側端子ＴＥを省略した平面図であり、半導体チップＣＰ１の平面図（平面レイアウト図）に対応している。 <About the structure of the semiconductor chip>
FIG. 14 is a partially enlarged plan view of FIG. 5 and shows an enlarged view of the semiconductor chip CP1 mounted on the wiring board 11 and its peripheral region. FIG. 15 is a plan view in which the wire WA and the substrate-side terminal TE are omitted from FIG. 14, and corresponds to a plan view (planar layout diagram) of the semiconductor chip CP1.
　図１４および図１５では、半導体チップＣＰ１において、ＧＳＭ９００用の１段目の増幅段ＬＤＭＬ１を構成するＬＤＭＯＳＦＥＴ素子が形成された領域を、符号ＲＥＧＬ１を付してＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１として示し、ＧＳＭ９００用の２段目の増幅段ＬＤＭＬ２を構成するＬＤＭＯＳＦＥＴ素子が形成された領域を、符号ＲＥＧＬ２を付してＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ２として示している。そして、ＧＳＭ９００用の３段目（最終段）の増幅段ＬＤＭＬ３を構成するＬＤＭＯＳＦＥＴ素子が形成された領域を、符号ＲＥＧＬ３を付してＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３として示している。 14 and 15, in the semiconductor chip CP1, a region in which the LDMOSFET element constituting the first amplification stage LDML1 for GSM900 is formed is denoted as a LDMOSFET formation region REGL1 with a reference sign REGL1, and the region for GSM900 is used. A region in which the LDMOSFET elements constituting the second amplification stage LDML2 are formed is denoted by a reference sign REGL2 and is indicated as an LDMOSFET formation region REGL2. A region in which the LDMOSFET elements constituting the third (final) amplification stage LDML3 for GSM900 are formed is denoted by the reference numeral REGL3 and indicated as an LDMOSFET formation region REGL3.
　また、ＤＣＳ１８００用の１段目の増幅段ＬＤＭＨ１を構成するＬＤＭＯＳＦＥＴ素子が形成された領域を、符号ＲＥＧＨ１を付してＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ１として示し、ＤＣＳ１８００用の２段目の増幅段ＬＤＭＨ２を構成するＬＤＭＯＳＦＥＴ素子が形成された領域を、符号ＲＥＧＨ２を付してＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ２として示している。そして、ＤＣＳ１８００用の３段目（最終段）の増幅段ＬＤＭＨ３を構成するＬＤＭＯＳＦＥＴ素子が形成された領域を、符号ＲＥＧＨ３を付してＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ３として示している。 Further, the region where the LDMOSFET element constituting the first amplification stage LDMH1 for DCS1800 is formed is denoted by the reference numeral REGH1, and is indicated as LDMOSFET formation region REGH1, and the second amplification stage LDMH2 for DCS1800 is constituted. A region where the LDMOSFET element is formed is indicated as a LDMOSFET formation region REGH2 with a reference sign REGH2. A region in which the LDMOSFET elements constituting the third (final) amplification stage LDMH3 for DCS1800 are formed is denoted by reference numeral REGH3 and is indicated as an LDMOSFET formation region REGH3.
　図１４および図１５は、平面図であるが、理解を簡単にするために、これらＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１～ＲＥＧＬ３，ＲＥＧＨ１～ＲＥＧＨ３にハッチングを付して示してあるが、実際には、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１～ＲＥＧＬ３，ＲＥＧＨ１～ＲＥＧＨ３は、半導体チップＣＰ１の最上層の保護膜（後述の絶縁膜５２に対応）で覆われている。 14 and 15 are plan views, but for the sake of easy understanding, these LDMOSFET formation regions REGL1 to REGL3 and REGH1 to REGH3 are hatched. REGL1 to REGL3 and REGH1 to REGH3 are covered with an uppermost protective film (corresponding to an insulating film 52 described later) of the semiconductor chip CP1.
　更に、半導体チップＣＰ１は、容量素子、抵抗素子または制御用ＭＯＳＦＥＴなどの上記周辺回路１０３を構成する素子が形成された領域も有しているが、この領域については、図１４および図１５では図示を省略している。 Further, the semiconductor chip CP1 also has a region in which elements constituting the peripheral circuit 103 such as a capacitor element, a resistance element, or a control MOSFET are formed. This region is illustrated in FIGS. Is omitted.
　図１４および図１５に示されるように、半導体チップＣＰ１の表面には、複数のパッド電極ＰＤが形成されている。このパッド電極ＰＤは、ドレイン用のパッド電極ＰＤであるドレインパッド（ドレインパッド電極）ＰＤＤ１，ＰＤＤ２，ＰＤＤ３，ＰＤＤ４，ＰＤＤ５，ＰＤＤ６およびゲート用のパッド電極ＰＤであるゲートパッド（ゲートパッド電極）ＰＤＧ１，ＰＤＧ２，ＰＤＧ３，ＰＤＧ４，ＰＤＧ５，ＰＤＧ６を含んでいる。また、それ以外に、パッド電極ＰＤは、制御信号の入力や検出信号の出力などに用いるためのパッド電極ＰＤ１も含んでいる。 14 and 15, a plurality of pad electrodes PD are formed on the surface of the semiconductor chip CP1. The pad electrodes PD are drain pads (drain pad electrodes) PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 which are drain pad electrodes PD and gate pads (gate pad electrodes) PDG1, which are gate pad electrodes PD. PDG2, PDG3, PDG4, PDG5, PDG6 are included. In addition, the pad electrode PD includes a pad electrode PD1 for use in inputting a control signal, outputting a detection signal, and the like.
　このうち、ゲートパッドＰＤＧ１は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１のゲート電極に電気的に接続された入力用のパッド電極（上記整合回路１０５Ａを介してＲＦ信号を入力するためのパッド電極）である。ドレインパッドＰＤＤ１は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１のドレインに電気的に接続された出力用のパッド電極（ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１で増幅したＲＦ信号を出力するためのパッド電極）である。 Among these, the gate pad PDG1 is an input pad electrode (pad electrode for inputting an RF signal through the matching circuit 105A) electrically connected to the gate electrode of the LDMOSFET formation region REGL1. The drain pad PDD1 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGL1) electrically connected to the drain of the LDMOSFET formation region REGL1.
　また、ゲートパッドＰＤＧ２は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ２のゲート電極に電気的に接続された入力用のパッド電極（上記整合回路１０２ＡＭ１を介してＲＦ信号を入力するためのパッド電極）である。ドレインパッドＰＤＤ２は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ２のドレインに電気的に接続された出力用のパッド電極（ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ２で増幅したＲＦ信号を出力するためのパッド電極）である。 The gate pad PDG2 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit 102AM1) electrically connected to the gate electrode of the LDMOSFET formation region REGL2. The drain pad PDD2 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGL2) electrically connected to the drain of the LDMOSFET formation region REGL2.
　また、ゲートパッドＰＤＧ３は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３のゲート電極に電気的に接続された入力用のパッド電極（上記整合回路１０２ＡＭ２を介してＲＦ信号を入力するためのパッド電極）である。ドレインパッドＰＤＤ３は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３のドレインに電気的に接続された出力用のパッド電極（ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３で増幅したＲＦ信号を出力するためのパッド電極）である。 The gate pad PDG3 is an input pad electrode (pad electrode for inputting an RF signal through the matching circuit 102AM2) electrically connected to the gate electrode of the LDMOSFET formation region REGL3. The drain pad PDD3 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGL3) electrically connected to the drain of the LDMOSFET formation region REGL3.
　また、ゲートパッドＰＤＧ４は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ１のゲート電極に電気的に接続された入力用のパッド電極（上記整合回路１０５Ｂを介してＲＦ信号を入力するためのパッド電極）である。ドレインパッドＰＤＤ４は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ１のドレインに電気的に接続された出力用のパッド電極（ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ１で増幅したＲＦ信号を出力するためのパッド電極）である。 The gate pad PDG4 is an input pad electrode (pad electrode for inputting an RF signal through the matching circuit 105B) electrically connected to the gate electrode of the LDMOSFET formation region REGH1. The drain pad PDD4 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGH1) electrically connected to the drain of the LDMOSFET formation region REGH1.
　また、ゲートパッドＰＤＧ５は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ２のゲート電極に電気的に接続された入力用のパッド電極（上記整合回路１０２ＢＭ１を介してＲＦ信号を入力するためのパッド電極）である。ドレインパッドＰＤＤ５は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ２のドレインに電気的に接続された出力用のパッド電極（ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ２で増幅したＲＦ信号を出力するためのパッド電極）である。 The gate pad PDG5 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit 102BM1) electrically connected to the gate electrode of the LDMOSFET formation region REGH2. The drain pad PDD5 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGH2) electrically connected to the drain of the LDMOSFET formation region REGH2.
　また、ゲートパッドＰＤＧ６は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ３のゲート電極に電気的に接続された入力用のパッド電極（上記整合回路１０２ＢＭ２を介してＲＦ信号を入力するためのパッド電極）である。ドレインパッドＰＤＤ６は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ３のドレインに電気的に接続された出力用のパッド電極（ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ３で増幅したＲＦ信号を出力するためのパッド電極）である。 The gate pad PDG6 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit 102BM2) electrically connected to the gate electrode of the LDMOSFET formation region REGH3. The drain pad PDD6 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGH3) electrically connected to the drain of the LDMOSFET formation region REGH3.
　また、半導体チップＣＰ１において、各ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＬ３，ＲＥＧＨ１，ＲＥＧＨ２，ＲＥＧＨ３が形成された領域および制御回路用の素子が形成された領域は、各領域間に形成された埋込酸化膜などからなる素子分離領域（後述の素子分離領域３２に対応）によって、それぞれ他の領域から電気的に分離されている。また、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＬ３，ＲＥＧＨ１，ＲＥＧＨ２，ＲＥＧＨ３および制御回路用の素子が形成された領域の間や、それらとパッド電極ＰＤとの間は、必要に応じて半導体チップＣＰ１の内部配線により電気的に接続されている。 In the semiconductor chip CP1, the regions where the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, and REGH3 are formed and the regions where the elements for the control circuit are formed are buried oxides formed between the regions. Each element is electrically isolated from other regions by element isolation regions (corresponding to element isolation regions 32 described later) made of a film or the like. Further, the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, REGH3 and the region where the elements for the control circuit are formed, and between them and the pad electrode PD, the inside of the semiconductor chip CP1 as necessary. It is electrically connected by wiring.
　また、半導体チップＣＰ１は、上記４つの辺（チップ辺）ＳＤ１，ＳＤ２，ＳＤ３，ＳＤ４を有する矩形の平面形状を有しており、辺ＳＤ１と辺ＳＤ３とは互いに平行でかつ対向し、辺ＳＤ２と辺ＳＤ４とは互いに平行でかつ対向し、辺ＳＤ１と辺ＳＤ２とは直交し、辺ＳＤ１と辺ＳＤ４とは直交し、辺ＳＤ３と辺ＳＤ２とは直交し、辺ＳＤ３と辺ＳＤ４とは直交している。複数のパッド電極ＰＤは半導体チップＣＰ１の表面の周辺部に配置されている。半導体チップＣＰ１の表面において、ドレインパッドＰＤＤ３、ゲートパッドＰＤＧ３、ドレインパッドＰＤＤ２、ゲートパッドＰＤＧ２、ドレインパッドＰＤＤ１およびゲートパッドＰＤＧ１は、この順で辺ＳＤ１に沿って配置されている。また、半導体チップＣＰ１の表面において、ドレインパッドＰＤＤ６、ゲートパッドＰＤＧ６、ドレインパッドＰＤＤ５、ゲートパッドＰＤＧ５、ドレインパッドＰＤＤ４およびゲートパッドＰＤＧ４は、この順で辺ＳＤ３に沿って配置されている。また、半導体チップＣＰ１の表面において、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３，ＲＥＧＬ２，ＲＥＧＬ１は、辺ＳＤ１側に配置され、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ３，ＲＥＧＨ２，ＲＥＧＨ１は辺ＳＤ３側に配置されている。平面的に見ると、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３と辺ＳＤ１との間にドレインパッドＰＤＤ３が位置し、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ２と辺ＳＤ１との間にドレインパッドＰＤＤ２が位置し、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１と辺ＳＤ１との間にドレインパッドＰＤＤ１が位置している。また、平面的に見ると、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ３と辺ＳＤ３との間にドレインパッドＰＤＤ６が位置し、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ２と辺ＳＤ３との間にドレインパッドＰＤＤ５が位置し、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ１と辺ＳＤ３との間にドレインパッドＰＤＤ４が位置している。 The semiconductor chip CP1 has a rectangular planar shape having the four sides (chip sides) SD1, SD2, SD3, and SD4. The side SD1 and the side SD3 are parallel to and face each other, and the side SD2 And the side SD4 are parallel to each other and face each other, the side SD1 and the side SD2 are orthogonal, the side SD1 and the side SD4 are orthogonal, the side SD3 and the side SD2 are orthogonal, and the side SD3 and the side SD4 are orthogonal is doing. The plurality of pad electrodes PD are arranged on the periphery of the surface of the semiconductor chip CP1. On the surface of the semiconductor chip CP1, the drain pad PDD3, the gate pad PDG3, the drain pad PDD2, the gate pad PDG2, the drain pad PDD1, and the gate pad PDG1 are arranged along the side SD1 in this order. On the surface of the semiconductor chip CP1, the drain pad PDD6, the gate pad PDG6, the drain pad PDD5, the gate pad PDG5, the drain pad PDD4, and the gate pad PDG4 are arranged along the side SD3 in this order. On the surface of the semiconductor chip CP1, the LDMOSFET formation regions REGL3, REGL2, and REGL1 are disposed on the side SD1 side, and the LDMOSFET formation regions REGH3, REGH2, and REGH1 are disposed on the side SD3 side. In plan view, the drain pad PDD3 is located between the LDMOSFET formation region REGL3 and the side SD1, the drain pad PDD2 is located between the LDMOSFET formation region REGL2 and the side SD1, and the LDMOSFET formation region REGL1 and the side SD1. A drain pad PDD1 is located between the two. Further, in a plan view, the drain pad PDD6 is located between the LDMOSFET formation region REGH3 and the side SD3, the drain pad PDD5 is located between the LDMOSFET formation region REGH2 and the side SD3, and the LDMOSFET formation region REGH1 and the side A drain pad PDD4 is located between SD3 and SD3.
　＜半導体チップにおけるＬＤＭＯＳＦＥＴ形成領域の構成について＞
　図１６～図２０は、半導体チップＣＰ１の要部断面図である。図１６には、半導体チップＣＰ１において、上記ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＬ３，ＲＥＧＨ１，ＲＥＧＨ２，ＲＥＧＨ３の要部断面図が示されている。図１７は、図１６とは異なる断面位置が示され、素子分離領域３２上においてゲート電極３５をゲート配線Ｍ１Ｇ，Ｍ２Ｇに引き上げている領域の断面図に対応する。図１８は、図１６および図１７とは異なる断面位置が示され、ドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３，ＰＤＤ４，ＰＤＤ５，ＰＤＤ６が形成された領域の断面図に対応する。図１９は、図１６～図１８とは異なる断面位置が示され、ゲートパッドＰＤＧ１，ＰＤＧ２，ＰＤＧ３，ＰＤＧ４，ＰＤＧ５，ＰＤＧ６が形成された領域の断面図に対応する。図２０は、図１６～図１９とは異なる断面位置が示され、ドレインパッドＰＤＤ３，ＰＤＤ６が形成された領域の断面図に対応する。 <Configuration of LDMOSFET formation region in semiconductor chip>
16 to 20 are principal part cross-sectional views of the semiconductor chip CP1. FIG. 16 is a cross-sectional view of a main part of the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, and REGH3 in the semiconductor chip CP1. 17 shows a cross-sectional position different from that in FIG. 16, and corresponds to a cross-sectional view of a region where the gate electrode 35 is pulled up to the gate wirings M1G and M2G on the element isolation region 32. FIG. 18 shows a cross-sectional position different from that in FIGS. 16 and 17, and corresponds to a cross-sectional view of a region where drain pads PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6 are formed. FIG. 19 shows cross-sectional positions different from those in FIGS. 16 to 18, and corresponds to a cross-sectional view of a region where the gate pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6 are formed. FIG. 20 shows a cross-sectional position different from that in FIGS. 16 to 19 and corresponds to a cross-sectional view of a region where the drain pads PDD3 and PDD6 are formed.
　図１６～図２０に示されるように、半導体チップＣＰ１を構成する半導体基板（以下、単に基板という）３１は、ｐ＋型単結晶シリコンなどからなる基板本体（半導体基板、半導体ウエハ）３１ａと、基板本体３１ａの主面上に形成された、例えばｐ－型単結晶シリコンからなるエピタキシャル層（半導体層）３１ｂと、を有している。このため、基板３１は、いわゆるエピタキシャルウエハである。エピタキシャル層３１ｂは、半導体層であるが、エピタキシャル層３１ｂの不純物濃度は基板本体３１ａの不純物濃度よりも低く、エピタキシャル層３１ｂの抵抗率は基板本体３１ａの抵抗率よりも高い。このエピタキシャル層３１ｂには、絶縁体からなる素子分離領域３２が形成されている。なお、図１６は、素子分離領域３２に囲まれた活性領域（後述の活性領域ＡＲ１に対応）を横切る断面図に対応するため、図１６には素子分離領域３２は示されておらず、図１７～図２０は、活性領域を囲む素子分離領域３２を横切る断面図に対応するため、図１７～図２０には素子分離領域３２が示されている。 As shown in FIGS. 16 to 20, a semiconductor substrate (hereinafter simply referred to as a substrate) 31 constituting the semiconductor chip CP1 includes a substrate body (semiconductor substrate, semiconductor wafer) 31a made of p + -type single crystal silicon, and the like. And an epitaxial layer (semiconductor layer) 31b made of, for example, p − type single crystal silicon, formed on the main surface of the substrate body 31a. For this reason, the substrate 31 is a so-called epitaxial wafer. Although the epitaxial layer 31b is a semiconductor layer, the impurity concentration of the epitaxial layer 31b is lower than the impurity concentration of the substrate body 31a, and the resistivity of the epitaxial layer 31b is higher than the resistivity of the substrate body 31a. An element isolation region 32 made of an insulator is formed in the epitaxial layer 31b. 16 corresponds to a cross-sectional view crossing an active region (corresponding to an active region AR1 described later) surrounded by the element isolation region 32, the element isolation region 32 is not shown in FIG. 17 to 20 correspond to cross-sectional views across the element isolation region 32 surrounding the active region, so that the element isolation region 32 is shown in FIGS. 17 to 20.
　素子分離領域３２は、例えばＳＴＩ（Shallow Trench Isolation）法またはＬＯＣＯＳ（Local Oxidization of Silicon）法などにより形成されている。素子分離領域３２により、基板本体３１ａの主面（エピタキシャル層３１ｂの主面）に後述の活性領域ＡＲ１が規定され、この活性領域ＡＲ１にＬＤＭＯＳＦＥＴのセル（単位ＬＤＭＯＳＦＥＴ素子）が複数形成される。活性領域ＡＲ１は、周囲を素子分離領域３２によって囲まれている。 The element isolation region 32 is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. The element isolation region 32 defines an active region AR1 described later on the main surface of the substrate body 31a (main surface of the epitaxial layer 31b), and a plurality of LDMOSFET cells (unit LDMOSFET elements) are formed in the active region AR1. The active region AR1 is surrounded by the element isolation region 32.
　エピタキシャル層３１ｂの主面の一部には、ＬＤＭＯＳＦＥＴのドレインからソースへの空乏層の延びを抑えるパンチスルーストッパとして機能するｐ型ウエル３３が形成されている。ｐ型ウエル３３の表面には、酸化シリコンなどからなるゲート絶縁膜３４を介してＬＤＭＯＳＦＥＴのゲート電極３５が形成されている。ゲート電極３５は、例えばｎ型の多結晶シリコン膜の単体膜あるいはｎ型の多結晶シリコン膜と金属シリサイド膜との積層膜などからなり、ゲート電極３５の側壁には、酸化シリコンなどからなるサイドウォールスペーサ（側壁絶縁膜）３６が形成されている。 A p-type well 33 that functions as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET is formed on a part of the main surface of the epitaxial layer 31b. On the surface of the p-type well 33, a gate electrode 35 of the LDMOSFET is formed via a gate insulating film 34 made of silicon oxide or the like. The gate electrode 35 is made of, for example, a single film of an n-type polycrystalline silicon film or a laminated film of an n-type polycrystalline silicon film and a metal silicide film, and a side wall made of silicon oxide or the like is formed on the side wall of the gate electrode 35. A wall spacer (side wall insulating film) 36 is formed.
　エピタキシャル層３１ｂの内部のチャネル形成領域（ゲート電極３５の直下の領域）を挟んで互いに離間する領域には、ＬＤＭＯＳＦＥＴのソース、ドレインが形成されている。ドレインは、チャネル形成領域に接する第１のｎ－型ドレイン領域３７と、第１のｎ－型ドレイン領域に接し、チャネル形成領域から離間して形成された第２のｎ－型ドレイン領域３８と、第２のｎ－型ドレイン領域に接し、チャネル形成領域からさらに離間して形成されたｎ＋型ドレイン領域（ドレイン高濃度領域、高濃度ｎ型ドレイン領域）３９とからなる。 The source and drain of the LDMOSFET are formed in regions separated from each other across the channel formation region (region immediately below the gate electrode 35) inside the epitaxial layer 31b. Drain first n in contact with the channel forming region - -type drain region 37, the first n - -type drain region 38 - -type drain region in contact with the second n which is spaced apart from the channel forming region And an n + type drain region (drain high concentration region, high concentration n type drain region) 39 formed in contact with the second n − type drain region and further away from the channel formation region.
　これら第１のｎ－型ドレイン領域３７、第２のｎ－型ドレイン領域３８およびｎ＋型ドレイン領域３９のうち、ゲート電極３５に最も近い第１のｎ－型ドレイン領域３７は不純物濃度が最も低く、ゲート電極３５から最も離間したｎ＋型ドレイン領域３９は不純物濃度が最も高い。また、第２のｎ－型ドレイン領域３８の接合深さは、第１のｎ－型ドレイン領域３７の接合深さとほぼ同じであるが、ｎ＋型ドレイン領域３９は、第２のｎ－型ドレイン領域３８および第１のｎ－型ドレイン領域３７に比べて浅く形成されている。 Of these first n − -type drain region 37, second n − -type drain region 38 and n + -type drain region 39, the first n − -type drain region 37 closest to the gate electrode 35 has the highest impurity concentration. The n + -type drain region 39 which is low and is most distant from the gate electrode 35 has the highest impurity concentration. The junction depth of the second n − -type drain region 38 is substantially the same as the junction depth of the first n − -type drain region 37, but the n + -type drain region 39 has the second n − -type drain. It is formed shallower than the drain region 38 and the first n − -type drain region 37.
　第１のｎ－型ドレイン領域（第１の低濃度ｎ型ドレイン領域、第１のｎ型ＬＤＤ領域）３７は、ゲート電極３５に対して自己整合的に形成され、その端部がチャネル形成領域と接するように、ゲート電極３５の側壁下部で終端している。また、第２のｎ－型ドレイン領域（第２の低濃度ｎ型ドレイン領域、第２のｎ型ＬＤＤ領域）３８は、ゲート電極３５のドレイン側の側壁に形成されたサイドウォールスペーサ３６に対して自己整合的に形成されることから、ゲート長方向に沿ったサイドウォールスペーサ３６の膜厚に相当する分、ゲート電極３５から離間して形成される。 The first n − -type drain region (first low-concentration n-type drain region, first n-type LDD region) 37 is formed in a self-aligned manner with respect to the gate electrode 35, and its end is a channel formation region It terminates at the bottom of the side wall of the gate electrode 35 so as to come into contact. Further, the second n − -type drain region (second low-concentration n-type drain region, second n-type LDD region) 38 is formed with respect to the side wall spacer 36 formed on the side wall on the drain side of the gate electrode 35. Therefore, it is formed so as to be separated from the gate electrode 35 by an amount corresponding to the film thickness of the sidewall spacer 36 along the gate length direction.
　ＬＤＭＯＳＦＥＴのソースは、チャネル形成領域に接するｎ－型ソース領域４０と、ｎ－型ソース領域４０に接し、チャネル形成領域から離間して形成され、ｎ－型ソース領域４０よりも不純物濃度が高いｎ＋型ソース領域４１とからなる。 The source of the LDMOSFET is n − -type source region 40 in contact with the channel formation region, and is in contact with the n − -type source region 40, spaced apart from the channel formation region, and has an impurity concentration higher than that of the n − -type source region 40. And a + type source region 41.
　ｎ－型ソース領域４０は、ゲート電極３５に対して自己整合的に形成され、その端部がチャネル形成領域と接するように、ゲート電極３５の側壁下部で終端している。また、ｎ－型ソース領域４０の下部に、ｐ型ハロー領域（図示せず）を形成することもでき、このｐ型ハロー領域は、必ずしも形成する必要はないが、これを形成した場合は、ソースからチャネル形成領域への不純物の広がりがさらに抑制され、さらに短チャネル効果が抑制されるので、しきい値電圧の低下をさらに抑制することができる。 The n − -type source region 40 is formed in a self-aligned manner with respect to the gate electrode 35, and terminates at the lower portion of the side wall of the gate electrode 35 so that the end thereof is in contact with the channel formation region. Also, a p-type halo region (not shown) can be formed below the n − -type source region 40, and this p-type halo region is not necessarily formed, but when formed, The spread of impurities from the source to the channel formation region is further suppressed, and the short channel effect is further suppressed, so that the threshold voltage can be further prevented from decreasing.
　ｎ＋型ソース領域４１は、ゲート電極３５のソース側の側壁に形成されたサイドウォールスペーサ３６に対して自己整合的に形成されているため、ｎ＋型ソース領域４１は、ｎ－型ソース領域４０に接して形成され、かつ、ゲート長方向に沿ったサイドウォールスペーサ３６の膜厚に相当する分、チャネル形成領域から離間して形成されている。ｎ＋型ソース領域４１の底部の位置は、ｎ－型ソース領域４０の底部の位置よりも深い。 Since the n + type source region 41 is formed in a self-aligned manner with respect to the side wall spacer 36 formed on the source side wall of the gate electrode 35, the n + type source region 41 is an n − type source region. 40, and is spaced apart from the channel formation region by an amount corresponding to the film thickness of the sidewall spacer 36 along the gate length direction. The position of the bottom of the n + -type source region 41 is deeper than the position of the bottom of the n − -type source region 40.
　このように、ゲート電極３５とｎ＋型ドレイン領域３９との間に介在する低濃度ｎ型ドレイン領域（ｎ型ＬＤＤ領域）を二重構造とし、ゲート電極３５に最も近い第１のｎ－型ドレイン領域３７の不純物濃度を相対的に低く、ゲート電極３５から離間した第２のｎ－型ドレイン領域３８の不純物濃度を相対的に高くしている。これにより、ゲート電極３５とドレインとの間に空乏層が広がるようになる結果、ゲート電極３５とその近傍の第１のｎ－型ドレイン領域３７との間に形成される帰還容量（Ｃgd）は小さくなる。また、第２のｎ－型ドレイン領域３８の不純物濃度が高いことから、オン抵抗（Ｒon）も小さくなる。第２のｎ－型ドレイン領域３８は、ゲート電極３５から離間した位置に形成されているために、帰還容量（Ｃgd）に及ぼす影響は僅かである。このため、オン抵抗（Ｒon）と帰還容量（Ｃgd）を共に小さくすることができるので、増幅回路の電力付加効率を向上させることができる。 As described above, the lightly doped n-type drain region (n-type LDD region) interposed between the gate electrode 35 and the n + -type drain region 39 has a double structure, and the first n − -type closest to the gate electrode 35 is formed. The impurity concentration of the drain region 37 is relatively low, and the impurity concentration of the second n − -type drain region 38 spaced from the gate electrode 35 is relatively high. As a result, a depletion layer spreads between the gate electrode 35 and the drain. As a result, the feedback capacitance (Cgd) formed between the gate electrode 35 and the first n − -type drain region 37 in the vicinity thereof is reduced. Get smaller. Further, since the impurity concentration of the second n − -type drain region 38 is high, the on-resistance (Ron) is also reduced. Since the second n − -type drain region 38 is formed at a position separated from the gate electrode 35, the influence on the feedback capacitance (Cgd) is small. For this reason, since both the on-resistance (Ron) and the feedback capacitance (Cgd) can be reduced, the power added efficiency of the amplifier circuit can be improved.
　なお、本願において、ＭＯＳＦＥＴまたはＬＤＭＯＳＦＥＴというときは、ゲート絶縁膜に酸化膜（酸化シリコン膜）を用いたＭＩＳＦＥＴだけでなく、酸化膜（酸化シリコン膜）以外の絶縁膜をゲート絶縁膜に用いたＭＩＳＦＥＴも含むものとする。 In the present application, the MOSFET or LDMOSFET is not only a MISFET using an oxide film (silicon oxide film) as a gate insulating film, but also a MISFET using an insulating film other than an oxide film (silicon oxide film) as a gate insulating film. Shall also be included.
　ここで、ＬＤＭＯＳＦＥＴは、ＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor：ＭＩＳ型電界効果トランジスタ）素子であるが、次のような特徴（第１～第３の特徴）を有するＭＩＳＦＥＴ素子である。 Here, the LDMOSFET is a MISFET (Metal-Insulator-Semiconductor-Field-Effect-Transistor) element, and is a MISFET element having the following characteristics (first to third characteristics).
　第１の特徴として、ＬＤＭＯＳＦＥＴは、短いチャネル長で高電圧動作を可能とするために、ゲート電極３５のドレイン側にＬＤＤ（Lightly doped drain）領域が形成されている。すなわち、ＬＤＭＯＳＦＥＴのドレインは、高不純物濃度のｎ＋型領域（ここではｎ＋型ドレイン領域３９）と、それよりも低不純物濃度のＬＤＤ領域（ここでは第１のｎ－型ドレイン領域３７および第２のｎ－型ドレイン領域３８）とから構成され、ｎ＋型領域（ｎ＋型ドレイン領域３９）はＬＤＤ領域を介してゲート電極３５（またはゲート電極３５の下のチャネル形成領域）から離間して形成されている。これにより、高耐圧を実現することができる。ドレイン側のＬＤＤ領域における電荷量（不純物濃度）、およびゲート電極３５の端部とｎ＋型ドレイン領域（ドレイン高濃度領域）３９との間の平面（エピタキシャル層３１ｂの主面）に沿った距離は、ＬＤＭＯＳＦＥＴのブレークダウン電圧が最大値となるように最適化しなければならない。 As a first feature, the LDMOSFET has an LDD (Lightly doped drain) region formed on the drain side of the gate electrode 35 in order to enable a high voltage operation with a short channel length. That is, the drain of the LDMOSFET has a high impurity concentration n + -type region (here, n + -type drain region 39) and a lower impurity concentration LDD region (here, the first n − -type drain region 37 and the first n - type drain region 37). 2 n − -type drain region 38), and the n + -type region (n + -type drain region 39) is separated from the gate electrode 35 (or the channel formation region below the gate electrode 35) via the LDD region. Is formed. Thereby, a high breakdown voltage can be realized. Charge amount (impurity concentration) in the LDD region on the drain side, and distance along the plane (main surface of the epitaxial layer 31b) between the end of the gate electrode 35 and the n + -type drain region (drain high concentration region) 39 Must be optimized to maximize the breakdown voltage of the LDMOSFET.
　第２の特徴として、ＬＤＭＯＳＦＥＴは、ソース側のソース形成領域（ｎ－型ソース領域４０およびｎ＋型ソース領域４１）とチャネル形成領域とに、パンチスルーストッパ用のｐ型ウエル（ｐ型ベース領域）３３が形成されている。ＬＤＭＯＳＦＥＴのドレイン側（ドレイン形成領域）では、このｐ型ウエル３３は、形成されていないか、あるいはチャネル領域に近い側のドレイン形成領域の一部に接するようにしか形成されていない。 As a second feature, the LDMOSFET has a p-type well (p-type base region) for punch-through stoppers in a source-side source formation region (n − -type source region 40 and n + -type source region 41) and a channel formation region. ) 33 is formed. On the drain side (drain formation region) of the LDMOSFET, the p-type well 33 is not formed, or is formed only in contact with a part of the drain formation region closer to the channel region.
　第３の特徴として、ＬＤＭＯＳＦＥＴは、ソース（ここではｎ－型ソース領域４０およびｎ＋型ソース領域４１からなるソース領域）とドレイン（ここでは第１のｎ－型ドレイン領域３７、第２のｎ－型ドレイン領域３８およびｎ＋型ドレイン領域３９からなるドレイン領域）とが、ゲート電極３５に対して非対称な構造を有している。 As a third feature, the LDMOSFET has a source (here, a source region composed of an n − type source region 40 and an n + type source region 41) and a drain (here, a first n − type drain region 37, a second n − type source region 41). The drain region composed of the − type drain region 38 and the n + type drain region 39) has an asymmetric structure with respect to the gate electrode 35.
　ｎ＋型ソース領域４１の端部（ｎ－型ソース領域４０と接する側とは反対側の端部）には、ｎ＋型ソース領域４１と接するｐ型打抜き層（ｐ型半導体領域）４４が形成されている。ｐ型打抜き層４４の表面近傍には、ｐ型打抜き層４４よりも高不純物濃度のｐ＋型半導体領域４５が形成されている。ｐ型打抜き層４４は、ＬＤＭＯＳＦＥＴのソースと基板本体３１ａとを電気的に接続するための導電層であり、例えばエピタキシャル層３１ｂに形成した溝の内部に埋め込んだｐ型多結晶シリコン膜によって形成される。ｐ型打抜き層４４の先端部（底部）は、基板本体３１ａに達している。ｐ型打抜き層４４は、基板３１に形成した溝に埋め込んだ金属層により形成することもできる。 end of the n + -type source region 41 - in the (n end portion opposite to the side in contact with the source region 40), p-type punched layer in contact with the n + -type source region 41 (p-type semiconductor region) 44 Is formed. Near the surface of the p-type punching layer 44, a p + -type semiconductor region 45 having a higher impurity concentration than the p-type punching layer 44 is formed. The p-type punching layer 44 is a conductive layer for electrically connecting the source of the LDMOSFET and the substrate body 31a, and is formed of, for example, a p-type polycrystalline silicon film embedded in a groove formed in the epitaxial layer 31b. The The tip (bottom) of the p-type punching layer 44 reaches the substrate body 31a. The p-type punching layer 44 can also be formed by a metal layer embedded in a groove formed in the substrate 31.
　エピタキシャル層３１ｂの主面上には、ゲート電極３５およびサイドウォールスペーサ３６を覆うように、絶縁膜（層間絶縁膜）４６が形成されている。絶縁膜４６は、例えば、薄い窒化シリコン膜とその上の厚い酸化シリコン膜の積層膜などからなる。絶縁膜４６の上面は平坦化されている。 An insulating film (interlayer insulating film) 46 is formed on the main surface of the epitaxial layer 31b so as to cover the gate electrode 35 and the sidewall spacers 36. The insulating film 46 is made of, for example, a laminated film of a thin silicon nitride film and a thick silicon oxide film thereon. The upper surface of the insulating film 46 is planarized.
　絶縁膜４６には、コンタクトホール（開口部、スルーホール、貫通孔）４７が形成され、コンタクトホール４７内には、タングステン（Ｗ）膜を主体とするプラグ（接続用埋込導体）４８が埋め込まれている。コンタクトホール４７およびそれを埋め込むプラグ４８は、ｐ型打抜き層４４（ｐ＋型半導体領域４５）、ソース（ｎ＋型ソース領域４１）、ドレイン（ｎ＋型ドレイン領域３９）、およびゲート電極３５のそれぞれの上部に形成されている。 A contact hole (opening, through hole, through hole) 47 is formed in the insulating film 46, and a plug (a buried conductor for connection) 48 mainly composed of a tungsten (W) film is embedded in the contact hole 47. It is. The contact hole 47 and the plug 48 filling the contact hole 47 are formed of a p-type punch layer 44 (p + -type semiconductor region 45), a source (n + -type source region 41), a drain (n + -type drain region 39), and a gate electrode 35. It is formed at the top of each.
　プラグ４８が埋め込まれた絶縁膜４６上には、タングステン（Ｗ）などを主体とする導電体膜（タングステン膜）からなる配線（第１層配線）Ｍ１が形成されている。配線Ｍ１は、プラグ４８が埋め込まれた絶縁膜４６上に形成した導電体膜（タングステン膜）をパターニングすることにより形成されている。配線Ｍ１は、タングステン配線に限定されず、アルミニウム配線など他の金属材料を用いた配線とすることもできる。 On the insulating film 46 in which the plug 48 is embedded, a wiring (first layer wiring) M1 made of a conductor film (tungsten film) mainly composed of tungsten (W) or the like is formed. The wiring M1 is formed by patterning a conductor film (tungsten film) formed on the insulating film 46 in which the plug 48 is embedded. The wiring M1 is not limited to the tungsten wiring, and may be a wiring using another metal material such as an aluminum wiring.
　配線Ｍ１は、プラグ４８を介してｎ＋型ソース領域４１およびｐ＋型半導体領域４５の両者に電気的に接続するソース配線（ソース電極）Ｍ１Ｓと、プラグ４８を介してｎ＋型ドレイン領域３９に電気的に接続するドレイン配線（ドレイン電極）Ｍ１Ｄと、プラグ４８を介してゲート電極３５に電気的に接続するゲート配線Ｍ１Ｇとを有している。 The wiring M1 includes a source wiring (source electrode) M1S electrically connected to both the n + -type source region 41 and the p + -type semiconductor region 45 through the plug 48, and an n + -type drain region 39 through the plug 48. A drain wiring (drain electrode) M1D electrically connected to the gate electrode 35 and a gate wiring M1G electrically connected to the gate electrode 35 through the plug 48.
　絶縁膜４６上に、配線Ｍ１を覆うように、酸化シリコン膜などからなる絶縁膜（層間絶縁膜）４９が形成されている。絶縁膜４９には、底部で配線Ｍ１の一部を露出するスルーホール（開口部、貫通孔）５０が形成されている。スルーホール５０内を含む絶縁膜４９上には、アルミニウム（Ａｌ）またはアルミニウム合金などを主体とする導電体膜からなる配線Ｍ２が形成されている。 An insulating film (interlayer insulating film) 49 made of a silicon oxide film or the like is formed on the insulating film 46 so as to cover the wiring M1. In the insulating film 49, a through hole (opening, through hole) 50 exposing a part of the wiring M1 at the bottom is formed. On the insulating film 49 including the inside of the through hole 50, a wiring M2 made of a conductor film mainly composed of aluminum (Al) or an aluminum alloy is formed.
　配線Ｍ２は、例えば、スルーホール５０内を含む絶縁膜４９上に、バリア導体膜（例えばチタン膜と窒化チタン膜の積層膜）、アルミニウム膜（またはアルミニウム合金膜）およびバリア導体膜（例えばチタン膜と窒化チタン膜の積層膜）の積層膜からなる導電体膜を形成してから、この導電体膜をパターニングすることで形成されている。この積層膜では、主導体膜であるアルミニウム膜の膜厚に比べて、その上下のバリア導体膜の膜厚は薄い。この積層膜におけるアルミニウム膜の下側のバリア導体膜は、アルミニウム膜と下層の配線Ｍ１との反応を抑制する機能や、配線Ｍ２と絶縁膜４９との密着性を向上させる機能などを有している。一方、この積層膜におけるアルミニウム膜の上側のバリア導体膜は、配線Ｍ２と絶縁膜（表面保護膜）５２との密着性を向上させる機能や、フォトリソグラフィ処理の露光時の反射防止膜としての機能などを有している。 For example, the wiring M2 includes a barrier conductor film (for example, a laminated film of a titanium film and a titanium nitride film), an aluminum film (or an aluminum alloy film), and a barrier conductor film (for example, a titanium film) on the insulating film 49 including the inside of the through hole 50. And a titanium nitride film) is formed by patterning the conductor film. In this laminated film, the upper and lower barrier conductor films are thinner than the aluminum film as the main conductor film. The barrier conductor film below the aluminum film in the laminated film has a function of suppressing a reaction between the aluminum film and the lower wiring M1, a function of improving the adhesion between the wiring M2 and the insulating film 49, and the like. Yes. On the other hand, the barrier conductor film on the upper side of the aluminum film in the laminated film has a function of improving the adhesion between the wiring M2 and the insulating film (surface protective film) 52 and a function as an antireflection film at the time of exposure in the photolithography process. Etc.
　配線Ｍ２は、絶縁膜４９上に延在するとともに、一部がスルーホール５０内を埋め、スルーホール５０の底部で配線Ｍ１と電気的に接続されている。従って、配線Ｍ２は、絶縁膜４９上を延在する配線部と、スルーホール５０内を埋めるビア部（接続部）とが一体的に形成されている。 The wiring M2 extends on the insulating film 49, partially fills the through hole 50, and is electrically connected to the wiring M1 at the bottom of the through hole 50. Therefore, the wiring M2 is integrally formed with a wiring portion extending on the insulating film 49 and a via portion (connecting portion) filling the through hole 50.
　配線Ｍ２は、ビア部（スルーホール５０を埋める部分）を介してドレイン配線Ｍ１Ｄに電気的に接続するドレイン配線Ｍ２Ｄと、ビア部（スルーホール５０を埋める部分）を介してゲート配線Ｍ１Ｇに電気的に接続するゲート配線Ｍ２Ｇと、ビア部（スルーホール５０を埋める部分）を介してソース配線Ｍ１Ｓに電気的に接続するソース配線Ｍ２Ｓとを有している。 The wiring M2 is electrically connected to the drain wiring M2D that is electrically connected to the drain wiring M1D via the via portion (the portion that fills the through hole 50) and to the gate wiring M1G via the via portion (the portion that fills the through hole 50). And a source wiring M2S electrically connected to the source wiring M1S through a via portion (a portion filling the through hole 50).
　また、他の形態として、スルーホール５０内に上記プラグ４８と同様のプラグ埋め込み、このプラグが埋め込まれた絶縁膜４９上に配線Ｍ２形成用の導電体膜を形成し、この導電体膜をパターニングして配線Ｍ２を形成することもでき、この場合、配線Ｍ２は、スルーホール５０内を埋めるプラグを介して配線Ｍ１と電気的に接続されることになる。 As another form, a plug similar to the plug 48 is embedded in the through hole 50, a conductor film for forming the wiring M2 is formed on the insulating film 49 in which the plug is embedded, and the conductor film is patterned. Thus, the wiring M2 can be formed. In this case, the wiring M2 is electrically connected to the wiring M1 through a plug filling the through hole 50.
　絶縁膜４９上に、配線Ｍ２を覆うように、絶縁膜（表面保護膜）５２が形成されている。この絶縁膜５２は、例えば、酸化シリコン膜とその上の窒化シリコン膜の積層膜などからなり、半導体チップＣＰ１の最表面の保護膜として機能することができる。絶縁膜５２には、パッド電極用の開口部（スルーホール、貫通孔）５３が形成されており、開口部５３の底部で配線Ｍ２が露出されている。すなわち、配線Ｍ２上に開口部５３が形成され、その開口部５３から配線Ｍ２の一部が露出されている。開口部５３から露出する配線Ｍ２が、上記パッド電極ＰＤに対応する。すなわち、開口部５３から露出する配線Ｍ２によって、上記パッド電極ＰＤが形成されている。 An insulating film (surface protective film) 52 is formed on the insulating film 49 so as to cover the wiring M2. The insulating film 52 is made of, for example, a laminated film of a silicon oxide film and a silicon nitride film thereon, and can function as a protective film on the outermost surface of the semiconductor chip CP1. An opening (through hole, through hole) 53 for a pad electrode is formed in the insulating film 52, and the wiring M <b> 2 is exposed at the bottom of the opening 53. That is, an opening 53 is formed on the wiring M2, and a part of the wiring M2 is exposed from the opening 53. The wiring M2 exposed from the opening 53 corresponds to the pad electrode PD. That is, the pad electrode PD is formed by the wiring M2 exposed from the opening 53.
　開口部５３のうち、ドレイン配線Ｍ２Ｄ上に形成されてドレイン配線Ｍ２Ｄの一部を露出する開口部５３をドレインパッド用開口部５３Ｄと称し、ゲート配線Ｍ２Ｇ上に形成されてゲート配線Ｍ２Ｇの一部を露出する開口部をゲートパッド用開口部５３Ｇと称するものとする。従って、ドレインパッド用開口部５３Ｄから露出するドレイン配線Ｍ２Ｄが、上記ドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３，ＰＤＤ４，ＰＤＤ５，ＰＤＤ６に対応し、ゲートパッド用開口部５３Ｇから露出するゲート配線Ｍ２Ｇが、上記ゲートパッドＰＤＧ１，ＰＤＧ２，ＰＤＧ３，ＰＤＧ４，ＰＤＧ５，ＰＤＧ６に対応する。すなわち、ドレインパッド用開口部５３Ｄから露出するドレイン配線Ｍ２Ｄによって、上記ドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３，ＰＤＤ４，ＰＤＤ５，ＰＤＤ６が形成され、ゲートパッド用開口部５３Ｇから露出するゲート配線Ｍ２Ｇによって、上記ゲートパッドＰＤＧ１，ＰＤＧ２，ＰＤＧ３，ＰＤＧ４，ＰＤＧ５，ＰＤＧ６が形成されている。開口部５３から露出する配線Ｍ２（すなわち上記パッド電極ＰＤ）には、上述のように、半導体チップＣＰ１を上記配線基板１１（配線基板母体２５）に搭載してから上記ワイヤＷＡが接続される。 Of the opening 53, the opening 53 formed on the drain wiring M2D and exposing a part of the drain wiring M2D is referred to as a drain pad opening 53D. The opening 53 is formed on the gate wiring M2G and is a part of the gate wiring M2G. The opening that exposes is referred to as a gate pad opening 53G. Accordingly, the drain wiring M2D exposed from the drain pad opening 53D corresponds to the drain pads PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6, and the gate wiring M2G exposed from the gate pad opening 53G is the gate. It corresponds to pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6. That is, the drain pad PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6 are formed by the drain wiring M2D exposed from the drain pad opening 53D, and the gate wiring M2G exposed from the gate pad opening 53G forms the gate. Pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6 are formed. As described above, the wire WA is connected to the wiring M2 exposed from the opening 53 (that is, the pad electrode PD) after the semiconductor chip CP1 is mounted on the wiring substrate 11 (wiring substrate base 25).
　なお、開口部５３が配線Ｍ２に平面的に（平面視で）内包されるように、開口部５３が形成された領域において、配線Ｍ２は、開口部５３よりも大面積のパターンとされている。 Note that, in the region where the opening 53 is formed so that the opening 53 is included in the wiring M2 in a plan view (in a plan view), the wiring M2 has a pattern with a larger area than the opening 53. .
　また、上述のように、配線Ｍ２を、バリア導体膜、アルミニウム膜およびバリア導体膜の積層膜からなる導電体膜をパターニングすることで形成した場合には、絶縁膜５２に開口部５３を形成する際のドライエッチングで、最上層のバリア導体膜を除去することもできる。この場合、配線Ｍ２のうち開口部５３から露出する部分（すなわちパッド電極ＰＤとなる部分）は、バリア導体膜とその上のアルミニウム膜との積層膜からなり、開口部５３からは、配線Ｍ２（パッド電極ＰＤ）を構成するアルミニウム膜（またはアルミニウム合金膜）の表面が露出されており、一方、絶縁膜５２で覆われている部分の配線Ｍ２は、バリア導体膜とその上のアルミニウム膜とその上のバリア導体膜との積層膜からなる。 Further, as described above, when the wiring M2 is formed by patterning a conductor film made of a laminated film of a barrier conductor film, an aluminum film, and a barrier conductor film, an opening 53 is formed in the insulating film 52. The uppermost barrier conductor film can also be removed by dry etching. In this case, a portion of the wiring M2 exposed from the opening 53 (that is, a portion that becomes the pad electrode PD) is formed of a laminated film of a barrier conductor film and an aluminum film thereon, and the wiring M2 ( The surface of the aluminum film (or aluminum alloy film) constituting the pad electrode PD) is exposed, while the portion of the wiring M2 covered with the insulating film 52 includes a barrier conductor film, an aluminum film thereon, and It consists of a laminated film with the upper barrier conductor film.
　基板３１の裏面（エピタキシャル層３１ｂが形成されている側の主面とは反対側の主面）には、ソース裏面電極（裏面電極）５４が形成されている。ソース裏面電極（裏面電極）５４は、半導体チップＣＰ１を構成する基板３１の裏面全体（すなわち基板本体３１ａの裏面全体）に形成されており、上記裏面電極ＢＥ１に対応するものである。 A source back electrode (back electrode) 54 is formed on the back surface of the substrate 31 (the main surface opposite to the main surface on which the epitaxial layer 31b is formed). The source back electrode (back electrode) 54 is formed on the entire back surface of the substrate 31 constituting the semiconductor chip CP1 (that is, the entire back surface of the substrate body 31a), and corresponds to the back electrode BE1.
　エピタキシャル層３１ｂに形成されたＬＤＭＯＳＦＥＴのソース（ｎ－型ソース領域４０およびｎ＋型ソース領域４１）は、プラグ４８（ｎ＋型ソース領域４１上に配置されたプラグ４８）、ソース配線Ｍ１Ｓ、プラグ４８（ｐ＋型半導体領域４５上に配置されたプラグ４８）、ｐ＋型半導体領域４５、ｐ型打抜き層４４および基板３１を介して、ソース裏面電極５４（すなわち裏面電極ＢＥ１）に電気的に接続されている。 The source (n − type source region 40 and n + type source region 41) of the LDMOSFET formed in the epitaxial layer 31b is a plug 48 (plug 48 disposed on the n + type source region 41), source wiring M1S, plug 48 (plug 48 disposed on p + type semiconductor region 45), p + type semiconductor region 45, p type punching layer 44, and substrate 31 are electrically connected to source back electrode 54 (ie, back electrode BE1). It is connected.
　他の形態として、更に、ｎ＋型ソース領域４１およびｐ＋型半導体領域４５の表面（上部）に金属シリサイド層（例えばコバルトシリサイド層またはニッケルシリサイド層、図示せず）を形成し、この金属シリサイド層を介して、ｎ＋型ソース領域４１とｐ＋型半導体領域４５とを電気的に接続することもでき、これによりソース抵抗を更に低減することができる。 As another form, a metal silicide layer (for example, a cobalt silicide layer or a nickel silicide layer, not shown) is further formed on the surface (upper part) of the n + type source region 41 and the p + type semiconductor region 45, and this metal silicide is formed. The n + -type source region 41 and the p + -type semiconductor region 45 can also be electrically connected through the layer, which can further reduce the source resistance.
　エピタキシャル層３１ｂに形成されたＬＤＭＯＳＦＥＴのドレイン（第１のｎ－型ドレイン領域３７、第２のｎ－型ドレイン領域３８およびｎ＋型ドレイン領域３９）は、プラグ４８（ｎ＋型ドレイン領域３９上に配置されたプラグ４８）、ドレイン配線Ｍ１Ｄおよびドレイン配線Ｍ２Ｄを介して、ドレインパッド（ドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３，ＰＤＤ４，ＰＤＤ５，ＰＤＤ６のいずれか）に電気的に接続されている。 The drain (first n − type drain region 37, second n − type drain region 38 and n + type drain region 39) of the LDMOSFET formed in the epitaxial layer 31b is connected to the plug 48 (on the n + type drain region 39). Are electrically connected to a drain pad (any one of drain pads PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6) via a drain wiring M1D and a drain wiring M2D.
　エピタキシャル層３１ｂに形成されたＬＤＭＯＳＦＥＴのゲート電極３５は、プラグ４８（ゲート電極３５上に配置されたプラグ４８）、ゲート配線Ｍ１Ｇおよびゲート配線Ｍ２Ｇを介して、ゲートパッド（ゲートパッドＰＤＧ１，ＰＤＧ２，ＰＤＧ３，ＰＤＧ４，ＰＤＧ５，ＰＤＧ６のいずれか）に電気的に接続されている。 The gate electrode 35 of the LDMOSFET formed on the epitaxial layer 31b is connected to the gate pad (gate pads PDG1, PDG2, PDG3) via the plug 48 (plug 48 disposed on the gate electrode 35), the gate wiring M1G, and the gate wiring M2G. , PDG4, PDG5, PDG6).
　＜半導体チップの製造工程について＞
　次に、半導体チップＣＰ１の製造工程について簡単に説明する。図２１は、半導体チップＣＰ１の製造工程を示す工程フロー図である。 <About semiconductor chip manufacturing process>
Next, a manufacturing process of the semiconductor chip CP1 will be briefly described. FIG. 21 is a process flowchart showing the manufacturing process of the semiconductor chip CP1.
　半導体チップＣＰ１を製造するには、まず、基板本体（半導体基板、半導体ウエハ）３１ａの主面上にエピタキシャル成長法を用いてエピタキシャル層（半導体層）３１ｂを形成することにより、基板本体３１ａと基板本体３１ａ上のエピタキシャル層３１ｂとからなる基板（半導体基板）３１を形成する。この段階の基板３１は、後述のダイシング工程は行われていないため、略円盤状の半導体ウエハの状態である。 In order to manufacture the semiconductor chip CP1, first, the epitaxial layer (semiconductor layer) 31b is formed on the main surface of the substrate body (semiconductor substrate, semiconductor wafer) 31a by using the epitaxial growth method, whereby the substrate body 31a and the substrate body are formed. A substrate (semiconductor substrate) 31 composed of the epitaxial layer 31b on 31a is formed. The substrate 31 at this stage is in a state of a substantially disk-shaped semiconductor wafer because a dicing process described later is not performed.
　次に、フォトリソグラフィ技術およびドライエッチング技術を用いてエピタキシャル層３１ｂの一部をエッチングして、基板本体３１ａに達する溝を形成してから、この溝の内部を含むエピタキシャル層３１ｂ上にＣＶＤ法などを用いてｐ型多結晶シリコン膜を堆積した後、溝の外部のｐ型多結晶シリコン膜をエッチバック法などで除去することにより、溝内に埋め込まれたｐ型多結晶シリコン膜からなるｐ型打抜き層４４を形成する。 Next, a part of the epitaxial layer 31b is etched using a photolithography technique and a dry etching technique to form a groove reaching the substrate body 31a, and then a CVD method or the like is formed on the epitaxial layer 31b including the inside of the groove. After the p-type polycrystalline silicon film is deposited using the p-type, the p-type polycrystalline silicon film outside the trench is removed by an etch back method or the like, thereby forming a p-type polycrystalline silicon film embedded in the trench. A stamping layer 44 is formed.
　次に、ＳＴＩ（Shallow Trench Isolation）法またはＬＯＣＯＳ（Local Oxidization of Silicon ）法などにより、エピタキシャル層３１ｂに素子分離領域３２を形成する。 Next, the element isolation region 32 is formed in the epitaxial layer 31b by STI (Shallow Trench Isolation) method or LOCOS (Local Oxidization of Silicon) method.
　次に、エピタキシャル層３１ｂの一部にｐ型不純物をイオン注入することによって、ｐ型ウエル３３を形成する。それから、エピタキシャル層３１ｂの表面にゲート絶縁膜３４を形成し、ゲート絶縁膜３４の上部にゲート電極３５を形成する。 Next, a p-type well 33 is formed by ion-implanting p-type impurities into a part of the epitaxial layer 31b. Then, a gate insulating film 34 is formed on the surface of the epitaxial layer 31b, and a gate electrode 35 is formed on the gate insulating film 34.
　次に、エピタキシャル層３１ｂの一部にｎ型不純物をイオン注入することによって、第１のｎ－型ドレイン領域３７を形成する。それから、ｐ型ウエル３３の一部にｎ型不純物をイオン注入することによって、ｎ－型ソース領域４０を形成する。 Next, a first n − -type drain region 37 is formed by ion-implanting an n-type impurity into a part of the epitaxial layer 31b. Then, an n − type source region 40 is formed by ion implantation of an n type impurity into a part of the p type well 33.
　次に、ゲート電極３５の側壁にサイドウォールスペーサ３６を形成する。それから、ｎ型不純物のイオン注入により、第２のｎ－型ドレイン領域３８を形成する。それから、ｎ型不純物のイオン注入により、ｎ＋型ドレイン領域３９およびｎ＋型ソース領域４１を形成する。それから、ｐ型不純物のイオン注入により、ｐ＋型半導体領域４５を形成する。 Next, sidewall spacers 36 are formed on the side walls of the gate electrode 35. Then, a second n − type drain region 38 is formed by ion implantation of n type impurities. Then, an n + type drain region 39 and an n + type source region 41 are formed by ion implantation of an n type impurity. Then, a p + type semiconductor region 45 is formed by ion implantation of p type impurities.
　次に、基板３１上にＣＶＤ法などを用いて絶縁膜（層間絶縁膜）４６を形成し、必要に応じてその表面をＣＭＰ（Chemical Mechanical Polishing：化学的機械研磨)法などを用いて平坦化する。それから、フォトリソグラフィ技術およびドライエッチング技術を用いて絶縁膜４６にコンタクトホール４７を形成してから、このコンタクトホール４７内にタングステン（Ｗ）膜を主体とするプラグ４８を形成する。 Next, an insulating film (interlayer insulating film) 46 is formed on the substrate 31 using a CVD method or the like, and the surface thereof is planarized using a CMP (Chemical Mechanical Polishing) method or the like as necessary. To do. Then, a contact hole 47 is formed in the insulating film 46 by using a photolithography technique and a dry etching technique, and then a plug 48 mainly composed of a tungsten (W) film is formed in the contact hole 47.
　次に、プラグ４８が埋め込まれた絶縁膜４６上に導電体膜を形成してから、この導電体膜をフォトリソグラフィ技術およびドライエッチング技術を用いてパターニングすることにより、配線Ｍ１を形成する。 Next, after forming a conductor film on the insulating film 46 in which the plug 48 is embedded, the conductor film is patterned by using a photolithography technique and a dry etching technique to form the wiring M1.
　次に、絶縁膜４６上に、配線Ｍ１を覆うように絶縁膜４９を形成する。それから、フォトリソグラフィ技術およびドライエッチング技術を用いて絶縁膜４９にスルーホール５０を形成する。 Next, an insulating film 49 is formed on the insulating film 46 so as to cover the wiring M1. Then, a through hole 50 is formed in the insulating film 49 using a photolithography technique and a dry etching technique.
　次に、絶縁膜４９上に、スルーホール５０内を埋めるように、導電体膜を形成してから、この導電体膜をフォトリソグラフィ技術およびドライエッチング技術を用いてパターニングすることにより、配線Ｍ２を形成する。 Next, a conductor film is formed on the insulating film 49 so as to fill the through hole 50, and then the conductor film is patterned by using a photolithography technique and a dry etching technique, so that the wiring M2 is formed. Form.
　次に、絶縁膜４９上に、配線Ｍ２を覆うように、絶縁膜（表面保護膜）５２を形成してから、フォトリソグラフィ技術およびドライエッチング技術を用いて絶縁膜４９に開口部５３を形成する。これにより、開口部５３から配線Ｍ２が露出することで、上記ドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３，ＰＤＤ４，ＰＤＤ５，ＰＤＤ６およびゲートパッドＰＤＧ１，ＰＤＧ２，ＰＤＧ３，ＰＤＧ４，ＰＤＧ５，ＰＤＧ６を含むパッド電極ＰＤが形成される。 Next, an insulating film (surface protective film) 52 is formed on the insulating film 49 so as to cover the wiring M2, and then an opening 53 is formed in the insulating film 49 using a photolithography technique and a dry etching technique. . As a result, the wiring M2 is exposed from the opening 53, thereby forming the pad electrode PD including the drain pads PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 and the gate pads PDG1, PDG2, PDG3, PDG4, PDG5, PDG6. Is done.
　次に、基板３１の裏面（エピタキシャル層３１ｂを形成した側とは逆側の主面）を必要に応じて研磨してから、基板３１の裏面の全面にソース裏面電極５４をスパッタリング法などにより形成する。 Next, the back surface of the substrate 31 (the main surface opposite to the side on which the epitaxial layer 31b is formed) is polished as necessary, and then the source back electrode 54 is formed on the entire back surface of the substrate 31 by sputtering or the like. To do.
　ここまでの工程により、半導体ウエハ（基板３１）に対するウエハ・プロセスが完了する（図２１のステップＳ１１）。ここでウエハ・プロセスは、前工程とも呼ばれ、一般的に、半導体ウエハ（基板３１）の主面上に種々の素子（ここではＬＤＭＯＳＦＥＴなど）や配線層を形成し、表面保護膜（およびパッド電極）を形成した後、半導体ウエハに形成された複数のチップ領域（各チップ領域から半導体チップＣＰ１が形成される）の各々の電気的試験をプローブ等により行える状態にするまでの工程を言う。 The wafer process for the semiconductor wafer (substrate 31) is completed through the steps so far (step S11 in FIG. 21). Here, the wafer process is also called a pre-process, and generally, various elements (in this case, LDMOSFETs) and wiring layers are formed on the main surface of the semiconductor wafer (substrate 31), and a surface protective film (and a pad) This is a process from the formation of the electrode) until the electrical test of each of the plurality of chip regions (the semiconductor chip CP1 is formed from each chip region) formed on the semiconductor wafer can be performed by a probe or the like.
　次に、半導体ウエハ（基板３１）に対してプローブ検査工程を行う（図２１のステップＳ１２）。このプローブ検査工程では、半導体ウエハ（基板３１）の各チップ領域（すなわち半導体チップＣＰ１）のパッド電極ＰＤにプローブ（探針）を当てて（押し当てて）、半導体ウエハの各チップ領域（すなわち半導体チップＣＰ１）の電気的特性を検査（試験）する。パッド電極ＰＤに押し当てたプローブからパッド電極ＰＤに所定の電圧が印加されることで、半導体ウエハの各チップ領域（すなわち半導体チップＣＰ１）の電気的特性を検査することができる。半導体ウエハ（基板３１）に形成された複数のチップ領域のうち、プローブ検査工程で不良と判別されたチップ領域は、ダイシング後に半導体チップＣＰ１としては使用せず、プローブ検査工程で良品と判別されたチップ領域が、ダイシング後に半導体チップＣＰ１として使用される。 Next, a probe inspection process is performed on the semiconductor wafer (substrate 31) (step S12 in FIG. 21). In this probe inspection step, a probe (probe) is applied (pressed) to the pad electrode PD of each chip region (ie, semiconductor chip CP1) of the semiconductor wafer (substrate 31), and each chip region (ie, semiconductor) of the semiconductor wafer (ie, semiconductor chip CP1). The electrical characteristics of the chip CP1) are inspected (tested). By applying a predetermined voltage to the pad electrode PD from the probe pressed against the pad electrode PD, the electrical characteristics of each chip region (that is, the semiconductor chip CP1) of the semiconductor wafer can be inspected. Of the plurality of chip regions formed on the semiconductor wafer (substrate 31), the chip region determined to be defective in the probe inspection process is not used as the semiconductor chip CP1 after dicing, and is determined to be a non-defective product in the probe inspection process. The chip area is used as the semiconductor chip CP1 after dicing.
　次に、半導体ウエハ（基板３１）に対してダイシング工程を行い、半導体ウエハ（基板３１）をスクライブ領域（チップ領域の間の切断領域）に沿って切断することにより、半導体ウエハ（基板３１）を個々の半導体チップＣＰ１に個片化する（図２１のステップＳ１３）。このステップＳ１３は、半導体ウエハ（基板３１）を切断して半導体チップＣＰ１を取得する工程とみなすこともできる。上記ステップＳ２の半導体チップＣＰ１の準備工程は、これらステップＳ１１，Ｓ１２，Ｓ１３を有している。個片化された半導体チップＣＰ１は、上記ステップＳ３でピックアップされて、上記図１０に示されるように、上記配線基板母体２５（配線基板１１）に搭載（実装、ダイボンディング）される。 Next, a dicing process is performed on the semiconductor wafer (substrate 31), and the semiconductor wafer (substrate 31) is cut along a scribe region (a cutting region between the chip regions). Individual semiconductor chips CP1 are separated (step S13 in FIG. 21). This step S13 can also be regarded as a process of obtaining the semiconductor chip CP1 by cutting the semiconductor wafer (substrate 31). The preparation process of the semiconductor chip CP1 in step S2 includes these steps S11, S12, and S13. The separated semiconductor chip CP1 is picked up in step S3 and mounted (mounted, die-bonded) on the wiring board base 25 (wiring board 11) as shown in FIG.
　＜ＬＤＭＯＳＦＥＴ形成領域近傍のレイアウトについて＞
　次に、上記ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＬ３，ＲＥＧＨ１，ＲＥＧＨ２，ＲＥＧＨ３およびその近傍における各構成要素の平面レイアウトについて説明する。以降の説明では、主としてＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３について説明するが、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＨ１，ＲＥＧＨ２，ＲＥＧＨ３についても、基本的には同様の説明を適用することができる。 <About the layout near the LDMOSFET formation region>
Next, the planar layout of each component in the LDMOSFET formation region REGL1, REGL2, REGL3, REGH1, REGH2, REGH3 and the vicinity thereof will be described. In the following description, the LDMOSFET formation region REGL3 will be mainly described, but basically the same description can be applied to the LDMOSFET formation regions REGL1, REGL2, REGH1, REGH2, and REGH3.
　図２２～図２４は、半導体チップＣＰ１の要部平面図であり、半導体チップＣＰ１において、上記ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３の平面図が示されている。図２２～図２４は、互いに同じ領域の平面図が示されているが、図２２には、活性領域ＡＲ１の平面レイアウトが示され、図２３には、配線Ｍ１（すなわちソース配線Ｍ１Ｓ、ドレイン配線Ｍ１Ｄおよびゲート配線Ｍ１Ｇ）の平面レイアウトが示され、図２４には、配線Ｍ２（すなわちソース配線Ｍ２Ｓ、ドレイン配線Ｍ２Ｄおよびゲート配線Ｍ２Ｇ）の平面レイアウトが示されている。また、図２２～図２４の平面位置を相互に比較しやすくするために、図２２～図２４では、ドレインパッド用開口部５３Ｄおよびゲートパッド用開口部５３Ｇを点線で示してある。また、図２２は、平面図であるが、図面を見易くするために、図２２においては、活性領域ＡＲ１にハッチングを付してある。なお、図２４のＡ３－Ａ３線の断面図が上記図１８にほぼ対応し、図２４のＡ４－Ａ４線の断面図が上記図１９にほぼ対応し、図２４のＡ５－Ａ５線の断面図が上記図２０にほぼ対応する。 22 to 24 are plan views of main parts of the semiconductor chip CP1, and plan views of the LDMOSFET formation region REGL3 in the semiconductor chip CP1 are shown. 22 to 24 show plan views of the same region, FIG. 22 shows a plan layout of the active region AR1, and FIG. 23 shows a wiring M1 (that is, a source wiring M1S and a drain wiring). A planar layout of M1D and gate wiring M1G) is shown, and FIG. 24 shows a planar layout of wiring M2 (that is, source wiring M2S, drain wiring M2D, and gate wiring M2G). 22 to 24, the drain pad opening 53D and the gate pad opening 53G are indicated by dotted lines in order to make it easy to compare the planar positions of FIGS. 22 to 24 with each other. Further, FIG. 22 is a plan view, but in order to make the drawing easier to see, in FIG. 22, the active region AR1 is hatched. Note that the sectional view taken along the line A3-A3 in FIG. 24 substantially corresponds to FIG. 18, the sectional view taken along the line A4-A4 in FIG. 24 substantially corresponds to FIG. 19, and the sectional view taken along the line A5-A5 in FIG. Substantially corresponds to FIG.
　また、図２５～図２８は、半導体チップＣＰ１の要部平面図であり、図２２の一点鎖線で囲まれた領域５５の拡大図である。図２５～図２８は、互いに同じ領域（すなわち図２２の領域５５）の平面図が示されているが、図２５には活性領域ＡＲ１の平面レイアウトが示され、図２６には、ゲート電極３５、ｎ＋型ドレイン領域３９、ｎ＋型ソース領域４１およびｐ型打抜き層４４の平面レイアウトが示されている。また、図２７には、配線Ｍ１（すなわちソース配線Ｍ１Ｓ、ドレイン配線Ｍ１Ｄおよびゲート配線Ｍ１Ｇ）の平面レイアウトが示され、図２８には、配線Ｍ２（すなわちソース配線Ｍ２Ｓ、ドレイン配線Ｍ２Ｄおよびゲート配線Ｍ２Ｇ）の平面レイアウトが示されている。なお、図２５～図２８の平面位置を相互に比較しやすくするために、図２５、図２７および図２８では、ゲート電極３５を点線で示してある。また、図２７では、配線Ｍ１（すなわちソース配線Ｍ１Ｓ、ドレイン配線Ｍ１Ｄおよびゲート配線Ｍ１Ｇ）の下に位置するコンタクトホール４７の位置も図示し、図２８では、配線Ｍ２（すなわちソース配線Ｍ２Ｓ、ドレイン配線Ｍ２Ｄおよびゲート配線Ｍ２Ｇ）の下に位置するスルーホール５０の位置も図示している。 25 to 28 are main part plan views of the semiconductor chip CP1, and are enlarged views of a region 55 surrounded by a one-dot chain line in FIG. 25 to 28 show plan views of the same region (that is, the region 55 in FIG. 22). FIG. 25 shows a plan layout of the active region AR1, and FIG. The planar layout of the n + -type drain region 39, the n + -type source region 41 and the p-type punching layer 44 is shown. 27 shows a planar layout of the wiring M1 (that is, the source wiring M1S, the drain wiring M1D, and the gate wiring M1G), and FIG. 28 shows the wiring M2 (that is, the source wiring M2S, the drain wiring M2D, and the gate wiring M2G). ) Planar layout is shown. In FIG. 25, FIG. 27 and FIG. 28, the gate electrode 35 is indicated by a dotted line in order to make it easy to compare the planar positions of FIGS. 27 also shows the position of the contact hole 47 located below the wiring M1 (that is, the source wiring M1S, the drain wiring M1D, and the gate wiring M1G), and FIG. 28 shows the wiring M2 (that is, the source wiring M2S and the drain wiring). The position of the through hole 50 located below M2D and the gate wiring M2G) is also illustrated.
　また、図２５～図２８は、平面図であるが、図面を見易くするために、図２５においては、活性領域ＡＲ１にドットのハッチングを付し、図２６においては、ゲート電極３５にドットのハッチングを付してある。また、図２７においては、配線Ｍ１（すなわちソース配線Ｍ１Ｓ、ドレイン配線Ｍ１Ｄおよびゲート配線Ｍ１Ｇ）にドットのハッチングを付し、図２８においては、配線Ｍ２（すなわちソース配線Ｍ２Ｓ、ドレイン配線Ｍ２Ｄおよびゲート配線Ｍ２Ｇ）にドットのハッチングを付してある。また、図２５のＡ１－Ａ１線の断面図が上記図１６にほぼ対応し、図２８のＡ２－Ａ２線の断面図が上記図１７にほぼ対応する。 25 to 28 are plan views. To make the drawing easier to see, in FIG. 25, the active region AR1 is hatched with dots, and in FIG. 26, the gate electrode 35 is hatched with dots. Is attached. In FIG. 27, the wiring M1 (that is, the source wiring M1S, the drain wiring M1D, and the gate wiring M1G) is hatched with dots, and in FIG. 28, the wiring M2 (that is, the source wiring M2S, the drain wiring M2D, and the gate wiring). M2G) is hatched with dots. Further, the sectional view taken along line A1-A1 in FIG. 25 substantially corresponds to FIG. 16, and the sectional view taken along line A2-A2 in FIG. 28 substantially corresponds to FIG.
　また、図２２～図２８などの平面図に示されるＸ方向は、半導体チップＣＰ１において、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３およびドレインパッドＰＤＤ３が形成された側の辺（チップ辺）ＳＤ１に平行な方向である。また、図２２～図２８の平面図に示されるＹ方向は、Ｘ方向に交差する方向であり、好ましくはＸ方向に直交する方向である。 Further, the X direction shown in the plan views of FIGS. 22 to 28 is a direction parallel to the side (chip side) SD1 on the side where the LDMOSFET formation region REGL3 and the drain pad PDD3 are formed in the semiconductor chip CP1. Further, the Y direction shown in the plan views of FIGS. 22 to 28 is a direction intersecting the X direction, and preferably a direction orthogonal to the X direction.
　上記素子分離領域３２によって、図２２および図２５に示されるような活性領域ＡＲ１が規定され、活性領域ＡＲ１は、周囲を上記素子分離領域３２によって囲まれている。活性領域ＡＲ１にＬＤＭＯＳＦＥＴのドレイン領域（第１のｎ－型ドレイン領域３７、第２のｎ－型ドレイン領域３８およびｎ＋型ドレイン領域３９）およびソース領域（ｎ－型ソース領域４０およびｎ＋型ソース領域４１）が形成され、また、ゲート絶縁膜３４を介してゲート電極３５が形成されている。 The element isolation region 32 defines an active region AR1 as shown in FIG. 22 and FIG. 25, and the active region AR1 is surrounded by the element isolation region 32. In the active region AR1, the drain region of the LDMOSFET (first n − type drain region 37, second n − type drain region 38 and n + type drain region 39) and source region (n − type source region 40 and n + type) A source region 41) is formed, and a gate electrode 35 is formed via a gate insulating film 34.
　図２５に示されるように、ＬＤＭＯＳＦＥＴのゲート電極３５はＹ方向に延在している。そして、ＬＤＭＯＳＦＥＴのドレイン領域（第１のｎ－型ドレイン領域３７、第２のｎ－型ドレイン領域３８およびｎ＋型ドレイン領域３９）は、活性領域ＡＲ１において、隣り合うゲート電極３５の間の領域に形成されてＹ方向に延在している。また、ＬＤＭＯＳＦＥＴのソース領域（ｎ－型ソース領域４０およびｎ＋型ソース領域４１）は、活性領域ＡＲ１において、隣り合うゲート電極３５の他の間の領域に形成されてＹ方向に延在している。また、ｐ型打抜き層４４は、隣り合うＬＤＭＯＳＦＥＴのｎ＋型ソース領域４１の間の領域に形成されている。 As shown in FIG. 25, the gate electrode 35 of the LDMOSFET extends in the Y direction. The drain region of the LDMOSFET (the first n − -type drain region 37, the second n − -type drain region 38 and the n + -type drain region 39) is a region between the adjacent gate electrodes 35 in the active region AR1. Formed in the Y direction. Also, the source region (n − type source region 40 and n + type source region 41) of the LDMOSFET is formed in a region between the other adjacent gate electrodes 35 in the active region AR1 and extends in the Y direction. Yes. The p-type punching layer 44 is formed in a region between the n + type source regions 41 of adjacent LDMOSFETs.
　また、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３（活性領域ＡＲ１）では、図１６および図２６に示されるような単位セル（繰り返し単位、繰り返しピッチ、基本セル、単位領域、ＬＤＭＯＳＦＥＴの単位セル）６０の構造（レイアウト）がＸ方向に繰り返されている。一つの単位セル６０により２つの単位ＬＤＭＯＳＦＥＴ（単位ＬＤＭＯＳＦＥＴ素子、ＬＤＭＯＳＦＥＴセル、単位ＭＩＳＦＥＴ素子）６０ａが形成される。すなわち、繰り返しの単位は単位セル６０であるが、各単位セル６０は、ｎ＋型ドレイン領域３９を共通にしてＸ方向に対称な構造の２つの単位ＬＤＭＯＳＦＥＴ６０ａにより構成されている。なお、ＬＤＭＯＳＦＥＴは、ＭＩＳＦＥＴ素子であるため、単位ＬＤＭＯＳＦＥＴ６０ａを単位ＭＩＳＦＥＴ素子とみなすこともできる。 In the LDMOSFET formation region REGL3 (active region AR1), the structure (layout) of the unit cell (repeating unit, repetitive pitch, basic cell, unit region, LDMOSFET unit cell) 60 as shown in FIGS. Repeated in the X direction. One unit cell 60 forms two unit LDMOSFETs (unit LDMOSFET element, LDMOSFET cell, unit MISFET element) 60a. That is, the unit of repetition is the unit cell 60, but each unit cell 60 is configured by two unit LDMOSFETs 60a having a common n + -type drain region 39 and symmetrical in the X direction. Since the LDMOSFET is a MISFET element, the unit LDMOSFET 60a can be regarded as a unit MISFET element.
　ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３においては、単位セル６０の構造（レイアウト）がＸ方向に繰り返されることで、多数（複数）の単位ＬＤＭＯＳＦＥＴ６０ａが形成（配列）され、それら多数（複数）の単位ＬＤＭＯＳＦＥＴ６０ａが並列に接続されている。すなわち、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３においては、単位ＬＤＭＯＳＦＥＴ６０ａがＸ方向に繰り返し配列し、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３に配列したこれら複数の単位ＬＤＭＯＳＦＥＴ６０ａが並列に接続されているのである。 In the LDMOSFET formation region REGL3, the structure (layout) of the unit cell 60 is repeated in the X direction, so that a large number (a plurality of) unit LDMOSFETs 60a are formed (arranged), and the large number (a plurality of) unit LDMOSFETs 60a are connected in parallel. Has been. That is, in the LDMOSFET formation region REGL3, the unit LDMOSFETs 60a are repeatedly arranged in the X direction, and the plurality of unit LDMOSFETs 60a arranged in the LDMOSFET formation region REGL3 are connected in parallel.
　ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３に形成されている複数の単位ＬＤＭＯＳＦＥＴ６０ａを並列に接続するために、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３のそれら複数の単位ＬＤＭＯＳＦＥＴ６０ａのゲート電極３５同士は、プラグ４８及びゲート配線Ｍ１Ｇ，Ｍ２Ｇを介して互いに電気的に接続され、ドレイン領域（ｎ＋型ドレイン領域３９）同士は、プラグ４８及びドレイン配線Ｍ１Ｄ，Ｍ２Ｄを介して互いに電気的に接続されている。また、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３に形成されている複数（多数）の単位ＬＤＭＯＳＦＥＴ６０ａにおいて、ソース領域（ｎ＋型ソース領域４１）同士は、プラグ４８、ソース配線Ｍ１Ｓ，Ｍ２Ｓ、ｐ＋型半導体領域４５、ｐ型打抜き層４４、基板３１およびソース裏面電極５４を介して互いに電気的に接続されている。 In order to connect the plurality of unit LDMOSFETs 60a formed in the LDMOSFET formation region REGL3 in parallel, the gate electrodes 35 of the plurality of unit LDMOSFETs 60a in the LDMOSFET formation region REGL3 are connected to each other via the plug 48 and the gate wirings M1G and M2G. The drain regions (n + -type drain regions 39) are electrically connected to each other via the plug 48 and the drain wirings M1D and M2D. Further, in the plural (many) unit LDMOSFETs 60a formed in the LDMOSFET formation region REGL3, the source regions (n + type source regions 41) are connected to each other by the plug 48, the source wiring M1S, M2S, the p + type semiconductor region 45, p. The die punching layer 44, the substrate 31 and the source back electrode 54 are electrically connected to each other.
　ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３は、上記増幅段ＬＤＭＬ３を構成するＭＩＳＦＥＴ素子が形成された領域に対応しており、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３に形成されている複数の単位ＬＤＭＯＳＦＥＴ６０ａが並列に接続されて、上記増幅段ＬＤＭＬ３が構成されている。従って、上記増幅段ＬＤＭＬ３を構成するＭＩＳＦＥＴ素子は、複数の単位ＬＤＭＯＳＦＥＴ６０ａを並列に接続して構成されている。 The LDMOSFET formation region REGL3 corresponds to a region in which the MISFET elements constituting the amplification stage LDML3 are formed, and a plurality of unit LDMOSFETs 60a formed in the LDMOSFET formation region REGL3 are connected in parallel to form the amplification stage LDML3. Is configured. Therefore, the MISFET element constituting the amplification stage LDML3 is configured by connecting a plurality of unit LDMOSFETs 60a in parallel.
　また、上述のように、活性領域ＡＲ１に形成されたＬＤＭＯＳＦＥＴのドレイン領域（ｎ＋型ドレイン領域３９）上にドレイン配線Ｍ１Ｄが形成され、ｎ＋型ドレイン領域３９上に配置されたプラグ４８を介して、ドレイン配線Ｍ１Ｄとその下方のＬＤＭＯＳＦＥＴのドレイン領域（ｎ＋型ドレイン領域３９）とが電気的に接続されている。活性領域ＡＲ１において、ドレイン領域はＹ方向に延在しているので、ドレイン配線Ｍ１Ｄも活性領域ＡＲ１上をＹ方向に延在しているが、活性領域ＡＲ１の間の素子分離領域３２上にはドレイン配線Ｍ１Ｄは形成されていない。このため、ドレイン配線Ｍ１Ｄは、各活性領域ＡＲ１上にのみ形成された孤立パターンであるが、図１６、図２７および図２８などに示されるように、ドレイン配線Ｍ１Ｄの上部をＹ方向に延在する最上層のドレイン配線Ｍ２Ｄと、ドレイン配線Ｍ２Ｄのビア部（スルーホール５０を埋める部分）を介して電気的に接続されている。 Further, as described above, the drain wiring M1D is formed on the drain region (n + -type drain region 39) of the LDMOSFET formed in the active region AR1, and the plug 48 disposed on the n + -type drain region 39 is interposed. Thus, the drain wiring M1D and the drain region (n + -type drain region 39) of the LDMOSFET thereunder are electrically connected. In the active region AR1, since the drain region extends in the Y direction, the drain wiring M1D also extends in the Y direction on the active region AR1, but on the element isolation region 32 between the active regions AR1. The drain wiring M1D is not formed. Therefore, although the drain wiring M1D is an isolated pattern formed only on each active region AR1, the upper portion of the drain wiring M1D extends in the Y direction as shown in FIGS. The drain wiring M2D of the uppermost layer is electrically connected to the drain wiring M2D via a via portion (a portion filling the through hole 50).
　図２２、図２４および図２８に示されるように、最上層のドレイン配線Ｍ２Ｄは、Ｙ方向に配列する複数の活性領域ＡＲ１（ドレイン領域）にまたがってＹ方向に延在する配線部（ドレイン配線部）Ｍ２Ｄ１と、Ｘ方向に延在して複数の配線部Ｍ２Ｄ１の一方の端部同士を連結する連結配線部（ドレイン配線部）Ｍ２Ｄ２とを有している。これら複数の配線部Ｍ２Ｄ１と連結配線部Ｍ２Ｄ２とが一体的に形成されてドレイン配線Ｍ２Ｄが構成されている。従って、ドレイン配線Ｍ２Ｄは、いわゆる櫛歯状のパターンとなっている。各配線部Ｍ２Ｄ１は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３に形成された複数の単位ＬＤＭＯＳＦＥＴ６０ａの各ドレイン領域上に位置するようにＹ方向に延在し、かつドレイン配線Ｍ１Ｄおよびプラグ４８を介して、複数の単位ＬＤＭＯＳＦＥＴ６０ａの各ドレイン領域と電気的に接続されている。 As shown in FIG. 22, FIG. 24 and FIG. 28, the uppermost drain wiring M2D is a wiring portion (drain wiring) extending in the Y direction across a plurality of active regions AR1 (drain regions) arranged in the Y direction. Part) M2D1, and a connecting wiring part (drain wiring part) M2D2 that extends in the X direction and connects one ends of the plurality of wiring parts M2D1. The plurality of wiring parts M2D1 and the connection wiring part M2D2 are integrally formed to constitute the drain wiring M2D. Accordingly, the drain wiring M2D has a so-called comb-like pattern. Each wiring portion M2D1 extends in the Y direction so as to be positioned on each drain region of the plurality of unit LDMOSFETs 60a formed in the LDMOSFET formation region REGL3, and a plurality of unit LDMOSFETs 60a are connected via the drain wiring M1D and the plug 48. Are electrically connected to each drain region.
　ドレイン配線Ｍ２Ｄの連結配線部Ｍ２Ｄ２の上部にドレインパッド用開口部５３Ｄが形成されており、ドレインパッド用開口部５３Ｄが連結配線部Ｍ２Ｄ２に平面的に（平面視で）内包されるように、連結配線部Ｍ２Ｄ２はドレインパッド用開口部５３Ｄよりも大面積のパターンとされている。ドレインパッド用開口部５３Ｄから露出するドレイン配線Ｍ２Ｄ、すなわち、ドレインパッド用開口部５３Ｄから露出する連結配線部Ｍ２Ｄ２によって、ドレインパッドＰＤＤ３が形成されている。 A drain pad opening 53D is formed above the connection wiring portion M2D2 of the drain wiring M2D, and the drain pad opening 53D is connected to the connection wiring portion M2D2 in a plane (in a plan view). The wiring portion M2D2 has a larger area pattern than the drain pad opening 53D. The drain pad PDD3 is formed by the drain wiring M2D exposed from the drain pad opening 53D, that is, the connection wiring M2D2 exposed from the drain pad opening 53D.
　すなわち、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３において、上記各単位セル６０のドレイン領域（ｎ＋型ドレイン領域３９）を、プラグ４８およびドレイン配線Ｍ１Ｄを介して、最上層のドレイン配線Ｍ２Ｄの配線部Ｍ２Ｄ１まで引き上げてから、ドレイン配線Ｍ２Ｄの連結配線部Ｍ２Ｄ２によって互いに電気的に接続させる。そして、このドレイン配線Ｍ２Ｄ（連結配線部Ｍ２Ｄ２）の一部をドレインパッド用開口部５３Ｄから露出させることで、ドレインパッドＰＤＤ３を形成しているのである。 That is, in the LDMOSFET formation region REGL3, the drain region (n + -type drain region 39) of each unit cell 60 is pulled up to the wiring portion M2D1 of the uppermost drain wiring M2D through the plug 48 and the drain wiring M1D. The drain wiring M2D is electrically connected to each other by the connecting wiring portion M2D2. The drain pad PDD3 is formed by exposing a part of the drain wiring M2D (connection wiring portion M2D2) from the drain pad opening 53D.
　また、上述のように、活性領域ＡＲ１に形成されたＬＤＭＯＳＦＥＴのソース領域（ｎ＋型ソース領域４１）に電気的に接続されたソース配線Ｍ１Ｓが、活性領域ＡＲ１のソース領域（ｎ＋型ソース領域４１）およびｐ＋型半導体領域４５上に形成されている。活性領域ＡＲ１において、ソース領域はＹ方向に延在しているので、ソース配線Ｍ１Ｓも活性領域ＡＲ１上をＹ方向に延在しているが、活性領域ＡＲ１の間の素子分離領域３２上にはソース配線Ｍ１Ｓは形成されていない。このため、ソース配線Ｍ１Ｓは、各活性領域ＡＲ１上にのみ形成された孤立パターンであるが、図１６、図２７および図２８などに示されるように、ソース配線Ｍ１Ｓの上部をＹ方向に延在する最上層のソース配線Ｍ２Ｓと、ソース配線Ｍ２Ｓのビア部（スルーホール５０を埋める部分）を介して電気的に接続されている。 Further, as described above, the source region of LDMOSFET formed in the active region AR1 (n + -type source region 41) electrically connected to have been the source wiring M1S is, the source region (n + -type source region of the active region AR1 41) and the p + type semiconductor region 45. In the active region AR1, since the source region extends in the Y direction, the source wiring M1S also extends in the Y direction on the active region AR1, but in the element isolation region 32 between the active regions AR1, The source wiring M1S is not formed. Therefore, the source line M1S is an isolated pattern formed only on each active region AR1, but as shown in FIGS. 16, 27, 28, etc., the upper part of the source line M1S extends in the Y direction. The uppermost source wiring M2S is electrically connected to the source wiring M2S via a via portion (a portion filling the through hole 50).
　図２２、図２４および図２８に示されるように、最上層のソース配線Ｍ２Ｓは、Ｙ方向に配列する複数の活性領域ＡＲ１（ソース領域）にまたがってＹ方向に延在しているが、各ソース配線Ｍ２Ｓ同士は連結されていない。また、ソース配線Ｍ２Ｓには、パッド電極ＰＤは接続されていないが、これは、ＬＤＭＯＳＦＥＴのソースは、ｐ型打抜き層４４などを介して、基板３１の裏面のソース裏面電極５４から引き出しているためである。 As shown in FIGS. 22, 24 and 28, the uppermost source line M2S extends in the Y direction across a plurality of active regions AR1 (source regions) arranged in the Y direction. The source lines M2S are not connected to each other. The pad electrode PD is not connected to the source wiring M2S because the source of the LDMOSFET is drawn from the source back electrode 54 on the back surface of the substrate 31 through the p-type punching layer 44 and the like. It is.
　図１７および図２５～図２８に示されるように、ゲート電極３５はＹ方向に延在し、活性領域ＡＲ１の周囲または間の素子分離領３２上に位置する部分で、コンタクトホール４７に埋め込まれたプラグ４８を介して、ゲート配線Ｍ１Ｇに電気的に接続されている。ゲート配線Ｍ１Ｇは、活性領域ＡＲ１の周囲および間の素子分離領域３２上をＸ方向およびＹ方向に延在している。ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３において、Ｙ方向に延在する各ゲート電極３５は、ゲート配線Ｍ１ＧのＸ方向に延在する部分とプラグ４８を介して電気的に接続され、ゲート配線Ｍ１ＧのＸ方向に延在する部分とＹ方向に延在する部分とが一体的に連結されていることで、各ゲート電極３５は、ゲート配線Ｍ１Ｇを介して互いに電気的に接続されている。 As shown in FIGS. 17 and 25 to 28, the gate electrode 35 extends in the Y direction and is buried in the contact hole 47 at a portion located on the element isolation region 32 around or between the active regions AR1. The gate wiring M1G is electrically connected through the plug 48. The gate wiring M1G extends in the X direction and the Y direction on the element isolation region 32 around and between the active regions AR1. In the LDMOSFET formation region REGL3, each gate electrode 35 extending in the Y direction is electrically connected to a portion extending in the X direction of the gate wiring M1G via a plug 48, and extends in the X direction of the gate wiring M1G. The gate electrode 35 is electrically connected to each other via the gate wiring M1G by integrally connecting the portion to be extended and the portion extending in the Y direction.
　ゲート配線Ｍ１Ｇはドレイン配線Ｍ１Ｄおよびソース配線Ｍ１Ｓと同層の配線であるが、図２３および図２７に示されるように活性領域ＡＲ１の間の素子分離領域３２上にはドレイン配線Ｍ１Ｄおよびソース配線Ｍ１Ｓが形成されておらず、そこでゲート配線Ｍ１ＧがＸ方向に延在している。従って、ゲート配線Ｍ１ＧのＸ方向に延在する部分同士の間に、Ｙ方向に延在するドレイン配線Ｍ１Ｄおよびソース配線Ｍ１Ｓが配置された状態となっている。 The gate wiring M1G is a wiring in the same layer as the drain wiring M1D and the source wiring M1S. However, as shown in FIGS. 23 and 27, the drain wiring M1D and the source wiring M1S are formed on the element isolation region 32 between the active regions AR1. Is not formed, and the gate wiring M1G extends in the X direction. Therefore, the drain wiring M1D and the source wiring M1S extending in the Y direction are arranged between the portions of the gate wiring M1G extending in the X direction.
　図１７、図２３、図２７および図２８に示されるように、ゲート配線Ｍ１Ｇは、ドレイン配線Ｍ２Ｄの連結配線部Ｍ２Ｄ２と反対側（連結配線部Ｍ２Ｄ２から遠い側）に位置しかつＸ方向に延在する部分において、素子分離領域３２上をＸ方向に延在するゲート配線Ｍ２Ｇと、ゲート配線Ｍ２Ｇのビア部（スルーホール５０を埋める部分）を介して電気的に接続されている。すなわち、Ｘ方向に延在するゲート配線Ｍ２Ｇの少なくとも一部が、Ｘ方向に延在する部分のゲート配線Ｍ１Ｇと平面的に重なっており、その重なり領域において、ゲート配線Ｍ２Ｇのビア部（スルーホール５０を埋める部分）を介して上層のゲート配線Ｍ２Ｇと下層のゲート配線Ｍ１Ｇとが電気的に接続されている。 As shown in FIGS. 17, 23, 27, and 28, the gate wiring M1G is located on the opposite side of the drain wiring M2D from the connection wiring portion M2D2 (the side far from the connection wiring portion M2D2) and extends in the X direction. In the existing portion, the gate wiring M2G extending in the X direction on the element isolation region 32 is electrically connected to the via portion of the gate wiring M2G (the portion filling the through hole 50). That is, at least a portion of the gate wiring M2G extending in the X direction overlaps with the portion of the gate wiring M1G extending in the X direction in a plane, and the via portion (through hole) of the gate wiring M2G in the overlapping region. 50), the upper gate wiring M2G and the lower gate wiring M1G are electrically connected.
　このように、活性領域ＡＲ１の周囲または間の素子分離領域３２上で、上記各単位ＬＤＭＯＳＦＥＴ６０ａのゲート電極３５を、プラグ４８を介してゲート配線Ｍ１Ｇまで引き上げ、このゲート配線Ｍ１Ｇを最上層のゲート配線Ｍ２Ｇに接続し、このゲート配線Ｍ２Ｇをゲートパッド用開口部５３Ｇまで延在させ、このゲートパッド用開口部５３Ｇからゲート配線Ｍ２Ｇの一部を露出させることで、ゲートパッドＰＤＧ３を形成している。 In this way, on the element isolation region 32 around or between the active regions AR1, the gate electrode 35 of each unit LDMOSFET 60a is pulled up to the gate wiring M1G via the plug 48, and this gate wiring M1G is pulled up to the uppermost gate wiring. The gate wiring M2G is connected to M2G, extends to the gate pad opening 53G, and a part of the gate wiring M2G is exposed from the gate pad opening 53G, thereby forming the gate pad PDG3.
　＜課題について＞
　図２９は、半導体チップＣＰ１の要部平面図であり、上記図２２～図２４と同じ領域が示されている。但し、図２９では、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３、ドレイン配線Ｍ２Ｄの連結配線部Ｍ２Ｄ２、ドレインパッド用開口部５３Ｄ、ゲート配線Ｍ２Ｇ、およびゲートパッド用開口部５３Ｇのレイアウト（配置）を示し、他の構成要素の図示を省略したものである。従って、図２４に示されていたソース配線Ｍ２Ｓと、ドレイン配線Ｍ２Ｄの配線部Ｍ２Ｄ１とは、図２９では図示を省略してある。なお、図２９は、平面図であるが、図面を見やすくするために、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３と、ゲート配線Ｍ２Ｇと、ドレイン配線Ｍ２Ｄの連結配線部Ｍ２Ｄ２とを、ハッチングを付して示してある。また、図２９では、ゲートパッド用開口部５３Ｇおよびドレインパッド用開口部５３Ｄを点線で示してあり、ゲートパッド用開口部５３Ｇから露出する部分のゲート配線Ｍ２ＧがゲートパッドＰＤＧ３であり、ドレインパッド用開口部５３Ｄから露出する部分のドレイン配線Ｍ２Ｄ（連結配線部Ｍ２Ｄ２）がドレインパッドＰＤＤ３である。図３０および図３１は、電力増幅モジュールＰＡ１の製造工程中の要部平面図であり、図３０には、上記配線基板母体２５（配線基板１１）上に半導体チップＣＰ１を搭載した後でかつステップＳ５のワイヤボンディング工程（ワイヤＷＡの接続工程）を行う直前の段階が示され、図３１には、ステップＳ５のワイヤボンディング工程（ワイヤＷＡの接続工程）を行った直後の段階が示されている。図３２は、電力増幅モジュールＰＡ１の製造工程中の要部斜視図（鳥瞰図）であり、半導体チップＣＰ１に対するステップＳ５のワイヤボンディング工程（ワイヤＷＡの接続工程）を行った直後の段階（すなわち図３１と同じ段階）が示されている。なお、図３０および図３１には、上記図１５において二点鎖線で囲まれた領域５６に相当する領域が示されており、図３２には、図３１の一部が示されている。 <Issues>
FIG. 29 is a plan view of an essential part of the semiconductor chip CP1, and shows the same regions as those in FIGS. However, FIG. 29 shows the layout (arrangement) of the LDMOSFET formation region REGL3, the connection wiring portion M2D2 of the drain wiring M2D, the drain pad opening 53D, the gate wiring M2G, and the gate pad opening 53G, and other components. Is omitted. Accordingly, the source wiring M2S and the wiring portion M2D1 of the drain wiring M2D shown in FIG. 24 are not shown in FIG. Note that FIG. 29 is a plan view, but the LDMOSFET formation region REGL3, the gate wiring M2G, and the connection wiring portion M2D2 of the drain wiring M2D are hatched for easy understanding of the drawing. In FIG. 29, the gate pad opening 53G and the drain pad opening 53D are indicated by dotted lines, and the portion of the gate wiring M2G exposed from the gate pad opening 53G is the gate pad PDG3. A portion of the drain wiring M2D (connection wiring portion M2D2) exposed from the opening 53D is the drain pad PDD3. 30 and 31 are main part plan views of the power amplification module PA1 during the manufacturing process. FIG. 30 shows a step after mounting the semiconductor chip CP1 on the wiring board matrix 25 (wiring board 11). The stage immediately before the wire bonding process (wire WA connection process) in S5 is shown, and FIG. 31 shows the stage immediately after the wire bonding process (wire WA connection process) in step S5. . FIG. 32 is a perspective view (bird's eye view) of a main part during the manufacturing process of the power amplification module PA1, and a stage immediately after performing the wire bonding process (connection process of the wire WA) of step S5 to the semiconductor chip CP1 (that is, FIG. 31). The same stage) is shown. 30 and 31 show a region corresponding to the region 56 surrounded by the two-dot chain line in FIG. 15, and FIG. 32 shows a part of FIG.
　また、図３３は、第１の比較例の半導体チップＣＰ１０１の要部平面図であり、本実施の形態の図２９に対応するものである。なお、図３３に示されるＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１０３、ドレイン配線Ｍ２Ｄ１０１、ドレインパッド用開口部１５３Ｄ、ゲート配線Ｍ２Ｇ１０１、およびゲートパッド用開口部１５３Ｇは、それぞれ、本実施の形態におけるＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３、ドレイン配線Ｍ２Ｄ、ドレインパッド用開口部５３Ｄ、ゲート配線Ｍ２Ｇ、およびゲートパッド用開口部５３Ｇに相当するものである。図３４および図３５は、第１の比較例の電力増幅モジュールの製造工程中の要部平面図であり、本実施の形態の図３０および図３１にそれぞれ対応するものである。図３４には、上記配線基板母体２５上に第１の比較例の半導体チップＣＰ１０１を搭載した後でかつワイヤボンディング工程（ワイヤＷＡ１０１の接続工程）を行う直前の段階が示され、図３５には、ワイヤボンディング工程（ワイヤＷＡ１０１の接続工程）を行った直後の段階が示されている。図３６は、第１の比較例の電力増幅モジュールの製造工程中の要部斜視図（鳥瞰図）であり、本実施の形態の図３２に対応するものである。図３６には、第１の比較例の半導体チップＣＰ１０１に対するワイヤボンディング工程（ワイヤＷＡ１０１の接続工程）を行った直後の段階（すなわち図３５と同じ段階）が示されている。なお、図３４～図３６に示されるＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１０１，ＲＥＧＬ１０２，ＲＥＧＬ１０３は、本実施の形態におけるＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＬ３にそれぞれ相当するものである。また、図３４～図３６に示されるゲートパッドＰＤＧ１０１，ＰＤＧ１０２，ＰＤＧ１０３、ドレインパッドＰＤＤ１０１，ＰＤＤ１０２，ＰＤＤ１０３およびワイヤＷＡ（ボンディングワイヤ）１０１は、それぞれ、本実施の形態におけるゲートパッドＰＤＧ１，ＰＤＧ２，ＰＤＧ３、ドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３およびワイヤＷＡに相当するものである。 FIG. 33 is a plan view of the main part of the semiconductor chip CP101 of the first comparative example, and corresponds to FIG. 29 of the present embodiment. 33, the LDMOSFET formation region REGL103, the drain wiring M2D101, the drain pad opening 153D, the gate wiring M2G101, and the gate pad opening 153G are respectively the LDMOSFET formation region REGL3 and the drain wiring in this embodiment. This corresponds to M2D, drain pad opening 53D, gate wiring M2G, and gate pad opening 53G. FIG. 34 and FIG. 35 are main part plan views during the manufacturing process of the power amplifying module of the first comparative example, and correspond to FIG. 30 and FIG. 31 of the present embodiment, respectively. FIG. 34 shows a stage after mounting the semiconductor chip CP101 of the first comparative example on the wiring board base 25 and immediately before performing the wire bonding process (connection process of the wire WA101). The stage immediately after performing the wire bonding process (connection process of the wire WA101) is shown. FIG. 36 is a perspective view (bird's eye view) of the main part during the manufacturing process of the power amplifying module of the first comparative example, and corresponds to FIG. 32 of the present embodiment. FIG. 36 shows a stage immediately after the wire bonding process (connection process of the wire WA101) to the semiconductor chip CP101 of the first comparative example (that is, the same stage as FIG. 35). The LDMOSFET formation regions REGL101, REGL102, and REGL103 shown in FIGS. 34 to 36 correspond to the LDMOSFET formation regions REGL1, REGL2, and REGL3 in the present embodiment, respectively. Also, the gate pads PDG101, PDG102, PDG103, the drain pads PDD101, PDD102, PDD103, and the wire WA (bonding wire) 101 shown in FIGS. 34 to 36 are the gate pads PDG1, PDG2, PDG3 in the present embodiment, respectively. This corresponds to the drain pads PDD1, PDD2, PDD3 and the wire WA.
　図３３～図３６に示される第１の比較例の半導体チップＣＰ１０１の場合、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１０３に形成されたＬＤＭＯＳＦＥＴのドレインに電気的に接続されたドレイン配線Ｍ２Ｄ１０１上には、複数（図３３の場合は７つ）のドレインパッド用開口部１５３Ｄが設けられ、各ドレインパッド用開口部１５３Ｄから露出するドレイン配線Ｍ２Ｄ１０１によってドレインパッドＰＤＤ１０３が形成されている。すなわち、第１の比較例の半導体チップＣＰ１０１場合、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１０３に対して、７つのドレインパッドＰＤＤ１０３が形成されており、これら７つのドレインパッドＰＤＤ１０３は、所定の間隔を空けてＸ方向に並んで配置されている。 In the case of the semiconductor chip CP101 of the first comparative example shown in FIGS. 33 to 36, a plurality of (as shown in FIG. 33) are formed on the drain wiring M2D101 electrically connected to the drain of the LDMOSFET formed in the LDMOSFET formation region REGL103. In this case, seven drain pad openings 153D are provided, and the drain pad PDD103 is formed by the drain wiring M2D101 exposed from each drain pad opening 153D. That is, in the semiconductor chip CP101 of the first comparative example, seven drain pads PDD103 are formed with respect to the LDMOSFET formation region REGL103, and these seven drain pads PDD103 are arranged in the X direction with a predetermined interval. Is arranged in.
　図３５および図３６に示されるように、第１の比較例の半導体チップＣＰ１０１の場合、７つのドレインパッドＰＤＤ１０３のそれぞれに対して、一本のワイヤＷＡ１０１が接続される。すなわち、一つのドレインパッドＰＤＤ１０３に接続されるワイヤＷＡの数は一本である。このため、第１の比較例の半導体チップＣＰ１０１では、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１０３に対して７つのドレインパッドＰＤＤ１０３が設けられ、これら７つのドレインパッドＰＤＤ１０３に合計７本のワイヤＷＡ１０１が接続されている。 As shown in FIGS. 35 and 36, in the case of the semiconductor chip CP101 of the first comparative example, one wire WA101 is connected to each of the seven drain pads PDD103. That is, the number of wires WA connected to one drain pad PDD103 is one. Therefore, in the semiconductor chip CP101 of the first comparative example, seven drain pads PDD103 are provided for the LDMOSFET formation region REGL103, and a total of seven wires WA101 are connected to these seven drain pads PDD103.
　ところで、半導体チップを製造するには、ウエハ・プロセスの後にプローブ検査を行うが、このプローブ検査の際に、検査用のプローブ（探針）が半導体ウエハの各チップ領域のパッド電極に押し当てられ、各チップ領域のパッド電極は、半導体ウエハのダイシング後に各半導体チップのパッド電極となる。プローブ検査でパッド電極にプローブが押し当てられると、プローブが押し当てられた（接触した）領域でパッド電極は変形するため、プローブ検査でプローブが押し当てられたパッド電極には、プローブが押し当てられた（接触した）痕であるプローブ痕（後述のプローブ痕ＰＲＢ，ＰＲＢ１０１，ＰＲＢ２０１がこれに対応している）が形成される。 By the way, in order to manufacture a semiconductor chip, a probe inspection is performed after the wafer process. During this probe inspection, a probe (probe) for inspection is pressed against the pad electrode in each chip area of the semiconductor wafer. The pad electrode in each chip region becomes the pad electrode of each semiconductor chip after dicing of the semiconductor wafer. When the probe is pressed against the pad electrode in the probe inspection, the pad electrode is deformed in the area where the probe is pressed (contacted). Therefore, the probe is pressed against the pad electrode where the probe is pressed in the probe inspection. Probe marks (probe marks PRB, PRB101, and PRB201 described later correspond to this) are formed (contacted) marks.
　図３３～図３６の第１の比較例の半導体チップＣＰ１０１の場合は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１０３に対して７つのドレインパッドＰＤＤ１０３が形成され、それぞれのドレインパッドＰＤＤ１０３に対してワイヤＷＡ１０１が接続されるが、７つのドレインパッドＰＤＤ１０３のいずれかには、プローブ検査工程においてプローブが押し当てられたことで、プローブ痕ＰＲＢ１０１が形成されている。 In the case of the semiconductor chip CP101 of the first comparative example of FIGS. 33 to 36, seven drain pads PDD103 are formed in the LDMOSFET formation region REGL103, and the wire WA101 is connected to each drain pad PDD103. A probe mark PRB101 is formed on any of the seven drain pads PDD103 by pressing the probe in the probe inspection process.
　図３７は、第１の比較例の半導体チップＣＰ１０１のドレインパッドＰＤＤ１０３に形成されたプローブ痕ＰＲＢ１０１と、ドレインパッドＰＤＤ１０３におけるワイヤＷＡ１０１の接続領域ＲＧＷ１０１とを示す説明図（平面図）である。図３７において、（ａ）には、プローブ検査前のドレインパッドＰＤＤ１０３が示され、（ｂ）には、プローブ検査で７つのドレインパッドＰＤＤ１０３のうちの２つのドレインパッドＰＤＤ１０３に検査用のプローブ（探針）が押し当てられたことで、プローブ痕ＰＲＢ１０１が形成された状態が模式的に示されている。図３７において、（ｃ）には、ワイヤボンディング工程でドレインパッドＰＤＤ１０３にワイヤＷＡ１０１が接続されたときのワイヤＷＡ１０１の接続領域ＲＧＷ１０１が示されている。 FIG. 37 is an explanatory diagram (plan view) showing the probe mark PRB101 formed on the drain pad PDD103 of the semiconductor chip CP101 of the first comparative example and the connection region RGW101 of the wire WA101 on the drain pad PDD103. In FIG. 37, (a) shows the drain pad PDD103 before the probe test, and (b) shows a probe (probe for inspection) on two drain pads PDD103 of the seven drain pads PDD103 in the probe test. A state in which the probe mark PRB101 is formed by pressing the needle) is schematically shown. In FIG. 37, (c) shows a connection region RGW101 of the wire WA101 when the wire WA101 is connected to the drain pad PDD103 in the wire bonding step.
　なお、本実施の形態の場合（半導体チップＣＰ１を用いた場合）と第１の比較例の場合（半導体チップＣＰ１０１を用いた場合）のいずれの場合も、ワイヤボンディング工程においては、ファーストボンディングは半導体チップＣＰ１，ＣＰ１０１の各パッド電極（ＰＤＤ３，ＰＤＤ１０３）に対して行われ、セカンドボンディングは基板側端子ＴＥに対して行われている。また、このワイヤボンディングには、好ましくはボールボンディングを用いている。このため、ワイヤボンディングの際には、半導体チップＣＰ１，ＣＰ１０１の各パッド電極（ＰＤＤ３，ＰＤＤ１０３）にワイヤ先端の金属ボール（ワイヤが金線の場合は金ボール）が接続される（具体的には、押し潰されて接続または圧着される）。ワイヤＷＡ１０１の接続領域ＲＧＷ１０１や後述のワイヤＷＡ１０１の接続領域ＲＧＷ２０１およびワイヤＷＡの接続領域ＲＧＷは、この金属ボール（ワイヤが金線の場合は金ボール）が接続された領域である。また、ワイヤＷＡ，ＷＡ１０１は好ましくは金からなるワイヤ（金線）であるが、アルミニウム（Ａｌ）を主体とするパッド電極（ＰＤＤ３，ＰＤＤ１０３）に金のワイヤ（ＷＡ，ＷＡ１０１）を接続する場合は、ワイヤ（ＷＡ，ＷＡ１０１）先端の金ボールがパッド電極（ＰＤＤ３，ＰＤＤ１０３）のアルミニウムと合金化することにより、ワイヤ（の先端の金ボール）がパッド電極（ＰＤＤ３，ＰＤＤ１０３）に接続される。このため、ワイヤ（の先端の金属ボール）をパッド電極（ＰＤＤ３，ＰＤＤ１０３）に接続する際には、下地となるパッド電極（ＰＤＤ３，ＰＤＤ１０３）の表面状態が均一であることが重要であり、下地となるパッド電極（ＰＤＤ３，ＰＤＤ１０３）の平坦性が高いことが好ましい。パッド電極の平坦面にワイヤ（の先端の金属ボール）を接続すれば、パッド電極に対するワイヤの接続強度を高めることができる。しかしながら、半導体チップ（ＣＰ１，ＣＰ１０１）は、電気的な良品のみを電力増幅モジュールのような半導体装置の製造に使用するため、プローブ検査によるパッド電極（ＰＤＤ３，ＰＤＤ１０３）へのプローブの接触は避けられず、ワイヤボンディングを行うべきパッド電極（ＰＤＤ３，ＰＤＤ１０３）にプローブ痕（ＰＲＢ，ＰＲＢ１０１）が発生してしまう。 In both the case of the present embodiment (in the case of using the semiconductor chip CP1) and the case of the first comparative example (in the case of using the semiconductor chip CP101), the first bonding is performed in the wire bonding process. The bonding is performed on the pad electrodes (PDD3 and PDD103) of the chips CP1 and CP101, and the second bonding is performed on the substrate-side terminal TE. Further, ball bonding is preferably used for the wire bonding. For this reason, at the time of wire bonding, a metal ball at the tip of the wire (a gold ball when the wire is a gold wire) is connected to each pad electrode (PDD3, PDD103) of the semiconductor chips CP1, CP101 (specifically, , Crushed and connected or crimped). A connection area RGW101 of the wire WA101, a connection area RGW201 of the wire WA101, which will be described later, and a connection area RGW of the wire WA are areas to which the metal balls (gold balls when the wires are gold wires) are connected. The wires WA and WA101 are preferably wires (gold wires) made of gold, but when the gold wires (WA and WA101) are connected to the pad electrodes (PDD3 and PDD103) mainly made of aluminum (Al). The gold ball at the tip of the wire (WA, WA101) is alloyed with the aluminum of the pad electrode (PDD3, PDD103), so that the wire (the gold ball at the tip thereof) is connected to the pad electrode (PDD3, PDD103). Therefore, when connecting the wire (the metal ball at the tip of the wire) to the pad electrode (PDD3, PDD103), it is important that the surface state of the pad electrode (PDD3, PDD103) serving as the base is uniform. It is preferable that the pad electrode (PDD3, PDD103) to be formed has high flatness. If the wire (the metal ball at the tip thereof) is connected to the flat surface of the pad electrode, the connection strength of the wire to the pad electrode can be increased. However, since the semiconductor chips (CP1 and CP101) are used only for the production of a semiconductor device such as a power amplification module, contact of the probe to the pad electrodes (PDD3 and PDD103) by probe inspection is avoided. Therefore, probe marks (PRB, PRB101) are generated on the pad electrodes (PDD3, PDD103) to be wire-bonded.
　第１の比較例の半導体チップＣＰ１０１の場合、ワイヤボンディング工程でドレインパッドＰＤＤ１０３にワイヤＷＡ１０１を接続する際に、図３７のようにワイヤＷＡ１０１の接続領域ＲＧＷ１０１がプローブ痕ＰＲＢ１０１に重なることで、ドレインパッドＰＤＤ１０３とワイヤＷＡ１０１との接続強度が低下してしまう。図３７の場合、７つのドレインパッドＰＤＤ１０３のうちの２つのドレインパッドＰＤＤ１０３でワイヤＷＡ１０１の接続領域ＲＧＷ１０１がプローブ痕ＰＲＢ１０１に重なり、この２つのドレインパッドＰＤＤ１０３において、ワイヤＷＡ１０１の接続強度が低下する。これは、プローブ検査前にはドレインパッドＰＤＤ１０３の表面は平坦であっても、プローブ検査で形成されたプローブ痕ＰＲＢ１０１により平坦性が崩れ、ワイヤボンディングの際にワイヤＷＡ１０１の接続領域ＲＧＷ１０１がプローブ痕ＰＲＢ１０１に重なると、プローブ痕に起因して平坦でない領域にワイヤ（の先端の金属ボール）が接続されることになるため、ワイヤＷＡ１０１の接続強度が低下するためである。ワイヤＷＡ１０１の接続強度の低下は、製造された電力増幅モジュールの信頼性を低下させる。なお、プローブ痕ＰＲＢ１０１の面積の一例を挙げると、例えば、ワイヤＷＡ１０１の接続領域ＲＧＷ１０１の面積の４０％程度である。 In the case of the semiconductor chip CP101 of the first comparative example, when the wire WA101 is connected to the drain pad PDD103 in the wire bonding process, the connection region RGW101 of the wire WA101 overlaps the probe mark PRB101 as shown in FIG. The connection strength between the PDD 103 and the wire WA101 is reduced. In the case of FIG. 37, the connection region RGW101 of the wire WA101 overlaps the probe mark PRB101 at two drain pads PDD103 of the seven drain pads PDD103, and the connection strength of the wire WA101 decreases at the two drain pads PDD103. Even if the surface of the drain pad PDD103 is flat before the probe inspection, the flatness is lost due to the probe mark PRB101 formed by the probe inspection, and the connection region RGW101 of the wire WA101 becomes the probe mark PRB101 during wire bonding. This is because the wire (the metal ball at the tip thereof) is connected to a non-flat region due to the probe mark, and the connection strength of the wire WA101 is reduced. The decrease in the connection strength of the wire WA101 decreases the reliability of the manufactured power amplification module. An example of the area of the probe mark PRB101 is, for example, about 40% of the area of the connection region RGW101 of the wire WA101.
　そこで、図３８に示されるように、ドレインパッドＰＤＤ１０３のＹ方向の寸法を拡大することが考えられる。ここで、図３８は、第２の比較例の半導体チップのドレインパッドＰＤＤ２０３に形成されたプローブ痕ＰＲＢ２０１と、ドレインパッドＰＤＤ２０３におけるワイヤＷＡ１０１の接続領域ＲＧＷ２０１とを示す説明図（平面図）であり、上記図３７に対応するものである。図３８において、（ａ）には、プローブ検査前のドレインパッドＰＤＤ２０３が示され、（ｂ）には、プローブ検査で７つのドレインパッドＰＤＤ２０３のうちの２つのドレインパッドＰＤＤ２０３に検査用のプローブ（探針）が押し当てられたことで、プローブ痕ＰＲＢ２０１が形成された状態が模式的に示されている。図３８において、（ｃ）には、ワイヤボンディング工程でドレインパッドＰＤＤ２０３にワイヤＷＡ１０１が接続されたときのワイヤＷＡ１０１の接続領域ＲＧＷ２０１が示されている。図３８の第２の比較例の半導体チップのドレインパッドＰＤＤ２０３は、図３７の第１の比較例の半導体チップＣＰ１０１のドレインパッドＰＤＤ１０３のＹ方向の寸法を大きくしたものに対応している。 Therefore, as shown in FIG. 38, it is conceivable to enlarge the dimension in the Y direction of the drain pad PDD103. Here, FIG. 38 is an explanatory diagram (plan view) showing the probe mark PRB201 formed on the drain pad PDD203 of the semiconductor chip of the second comparative example and the connection region RGW201 of the wire WA101 in the drain pad PDD203. This corresponds to FIG. In FIG. 38, (a) shows the drain pad PDD 203 before the probe test, and (b) shows a probe (probe for inspection) on two drain pads PDD 203 of the seven drain pads PDD 203 in the probe test. A state in which the probe mark PRB201 is formed by pressing the needle) is schematically shown. In FIG. 38, (c) shows a connection region RGW201 of the wire WA101 when the wire WA101 is connected to the drain pad PDD203 in the wire bonding step. The drain pad PDD203 of the semiconductor chip of the second comparative example of FIG. 38 corresponds to the drain pad PDD103 of the semiconductor chip CP101 of the first comparative example of FIG.
　図３８に示される第２の比較例の半導体チップのドレインパッドＰＤＤ２０３は、第１の比較例の半導体チップＣＰ１０１のドレインパッドＰＤＤ１０３に比べてＹ方向の寸法が大きい。このため、第２の比較例の半導体チップでは、プローブ検査でプローブが押し当てられたドレインパッドＰＤＤ２０３にワイヤボンディング工程でワイヤＷＡ１０１を接続したとしても、図３８に示されるように、ワイヤＷＡ１０１の接続領域ＲＧＷ２０１とプローブ痕ＰＲＢ２０１とがＹ方向にずれるようにし、ワイヤＷＡ１０１の接続領域ＲＧＷ２０１とプローブ痕ＰＲＢ２０１とが重ならないようにすることができる。 38. The drain pad PDD203 of the semiconductor chip of the second comparative example shown in FIG. 38 has a larger dimension in the Y direction than the drain pad PDD103 of the semiconductor chip CP101 of the first comparative example. For this reason, in the semiconductor chip of the second comparative example, even if the wire WA101 is connected to the drain pad PDD203 to which the probe is pressed in the probe inspection in the wire bonding process, as shown in FIG. 38, the connection of the wire WA101 is performed. The region RGW201 and the probe mark PRB201 can be shifted in the Y direction so that the connection region RGW201 of the wire WA101 and the probe mark PRB201 do not overlap.
　このため、図３８に示される第２の比較例のドレインパッドＰＤＤ２０３の場合は、同じドレインパッドＰＤＤ２０３に対してプローブ検査でプローブを押し当てかつワイヤボンディング工程でワイヤＷＡ１０１を接続したとしても、ドレインパッドＰＤＤ２０３におけるプローブ痕ＰＲＢ２０１とワイヤＷＡ１０１の接続領域ＲＧＷ２０１とが重ならないようにすることができる。これにより、ドレインパッドＰＤＤ２０３とワイヤＷＡ１０１との接続強度を確保することができる。 Therefore, in the case of the drain pad PDD 203 of the second comparative example shown in FIG. 38, even if the probe is pressed against the same drain pad PDD 203 by the probe inspection and the wire WA 101 is connected in the wire bonding process, It is possible to prevent the probe mark PRB201 in the PDD 203 and the connection region RGW201 of the wire WA101 from overlapping each other. Thereby, the connection strength between the drain pad PDD203 and the wire WA101 can be ensured.
　しかしながら、図３８に示される第２の比較例の半導体チップのドレインパッドＰＤＤ２０３の場合、ドレインパッドＰＤＤ２０３におけるワイヤＷＡ１０１の接続領域ＲＧＷ２０１とプローブ痕ＰＲＢ２０１との位置をＹ方向にずらすために、ドレインパッドＰＤＤ２０３のＹ方向の寸法を拡大する必要がある。このため、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１０３とそれに接続されたドレインパッドＰＤＤ２０３およびゲートパッドとに要する面積は、ドレインパッドＰＤＤ２０３のＹ方向の寸法が大きい分、第１の比較例の半導体チップＣＰ１０１よりも、ドレインパッドＰＤＤ２０３を適用した第２の比較例の半導体チップの方が大きくなってしまう。ドレインパッドＰＤＤ２０３を適用した第２の比較例の半導体チップは、ドレインパッドＰＤＤ２０３のＹ方向の寸法が大きい分、第１の比較例の半導体チップＣＰ１０１よりもチップサイズ（特にＹ方向寸法）が大きくなってしまう。これは、１枚のウエハから取得できる半導体チップ数を少なくしてしまうため、製造コストの増大を招き、また、半導体チップを搭載した半導体装置（ここでは電力増幅モジュール）の小型化（平面寸法の縮小）には不利となる。 However, in the case of the drain pad PDD203 of the semiconductor chip of the second comparative example shown in FIG. 38, the drain pad PDD203 is used to shift the position of the connection region RGW201 of the wire WA101 and the probe mark PRB201 in the drain pad PDD203 in the Y direction. It is necessary to enlarge the dimension in the Y direction. Therefore, the area required for the LDMOSFET formation region REGL103 and the drain pad PDD203 and the gate pad connected thereto is larger than that of the semiconductor chip CP101 of the first comparative example because the size of the drain pad PDD203 in the Y direction is larger. The semiconductor chip of the second comparative example to which the PDD 203 is applied becomes larger. The semiconductor chip of the second comparative example to which the drain pad PDD203 is applied has a larger chip size (particularly the dimension in the Y direction) than the semiconductor chip CP101 of the first comparative example because the dimension of the drain pad PDD203 in the Y direction is larger. End up. This reduces the number of semiconductor chips that can be obtained from a single wafer, leading to an increase in manufacturing cost, and miniaturization of semiconductor devices (here, power amplification modules) on which semiconductor chips are mounted (planar dimensions). (Reduction) is disadvantageous.
　従って、パッド電極においてワイヤの接続領域とプローブ検査工程でプローブを押し当てる領域（プローブ痕）とを単に分ける（別々の領域にする）のではなく、ワイヤの接続強度の向上とチップサイズの抑制とを考慮した総合的な設計が望まれる。 Therefore, the pad connection area in the pad electrode and the area where the probe is pressed in the probe inspection process (probe marks) are not simply separated (separate areas), but the wire connection strength is improved and the chip size is reduced. A comprehensive design that considers
　＜本実施の形態の主要な特徴と効果について＞
　本実施の形態では、図２９～図３２に示されるように、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３に対して設けるドレインパッド（すなわちＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３に形成されたＬＤＭＯＳＦＥＴのドレインに電気的に接続されたドレインパッド）として、Ｙ方向の寸法よりもＸ方向の寸法が大きなドレインパッドＰＤＤ３が形成されている。ドレインパッドＰＤＤ３のＸ方向の寸法は、ドレインパッドＰＤＤ３のＹ方向の寸法の２倍以上であり、ドレインパッドＰＤＤ３は略長方形状の平面形状を有している（但し、長方形の角部に丸みを持たせることもできる）。そして、この１つのドレインパッドＰＤＤ３に対して、ワイヤＷＡを複数接続していることが、本実施の形態の主要な特徴の一つである。 <Main features and effects of the present embodiment>
In the present embodiment, as shown in FIGS. 29 to 32, a drain pad provided for the LDMOSFET formation region REGL3 (that is, a drain pad electrically connected to the drain of the LDMOSFET formed in the LDMOSFET formation region REGL3). As a result, a drain pad PDD3 having a larger dimension in the X direction than a dimension in the Y direction is formed. The dimension in the X direction of the drain pad PDD3 is at least twice the dimension in the Y direction of the drain pad PDD3, and the drain pad PDD3 has a substantially rectangular planar shape (however, the rectangular corners are rounded). Can also be held). One of the main features of the present embodiment is that a plurality of wires WA are connected to the one drain pad PDD3.
　ここで、ドレインパッドＰＤＤ３は、長方形の平面形状を有しているが、その長方形の長辺方向（Ｘ方向）は、半導体チップＣＰ１の表面におけるそのドレインパッドＰＤＤ３を配置した側の辺（チップ辺）ＳＤ１に平行な方向であることが好ましい。すなわち、半導体チップＣＰ１の４つの辺（チップ辺）ＳＤ１，ＳＤ２，ＳＤ３，ＳＤ４のうち、ドレインパッドＰＤＤ３の最も近傍に位置するチップ辺（ここでは辺ＳＤ１）に平行な方向に、ドレインパッドＰＤＤ３の長辺方向を設定することが好ましい。このため、半導体チップＣＰ１の表面において、もしも辺ＳＤ１ではなく辺ＳＤ２に沿ってドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３およびゲートパッドＰＤＧ１，ＰＤＧ２，ＰＤＧ３を配置し、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＬ３を、辺ＳＤ１側ではなく辺ＳＤ２側に配置した場合には、ドレインパッドＰＤＤ３の長辺方向（Ｘ方向）は、辺ＳＤ２に平行な方向になる。 Here, the drain pad PDD3 has a rectangular planar shape, and the long side direction (X direction) of the rectangle is the side (chip side) on the surface of the semiconductor chip CP1 where the drain pad PDD3 is disposed. ) The direction is preferably parallel to SD1. That is, of the four sides (chip sides) SD1, SD2, SD3, and SD4 of the semiconductor chip CP1, the drain pad PDD3 is aligned in a direction parallel to the chip side (here, the side SD1) located closest to the drain pad PDD3. It is preferable to set the long side direction. Therefore, on the surface of the semiconductor chip CP1, the drain pads PDD1, PDD2, and PDD3 and the gate pads PDG1, PDG2, and PDG3 are arranged along the side SD2 instead of the side SD1, and the LDMOSFET formation regions REGL1, REGL2, and REGL3 are When arranged on the side SD2 side instead of the SD1 side, the long side direction (X direction) of the drain pad PDD3 is parallel to the side SD2.
　図２９～図３２と図３３～図３６とを比べると分かるように、図３３～図３６のＸ方向に並んだ７つのドレインパッドＰＤＤ１０３をつないだものが、図２９～図３２のドレインパッドＰＤＤ３に相当している。すなわち、図３３～図３６において、７つのドレインパッドＰＤＤ１０３と、Ｘ方向に隣接するドレインパッドＰＤＤ１０３間の領域とを足して全体を１つのドレインパッドにしたものが、図２９～図３２のドレインパッドＰＤＤ３に相当している。 As can be seen from a comparison between FIGS. 29 to 32 and FIGS. 33 to 36, the drain pad PDD3 in FIGS. 29 to 32 is connected to the seven drain pads PDD103 arranged in the X direction in FIGS. It corresponds to. That is, in FIGS. 33 to 36, seven drain pads PDD103 and a region between drain pads PDD103 adjacent in the X direction are added to form one drain pad as a whole. It corresponds to PDD3.
　図３３～図３６の第１比較例の半導体チップＣＰ１０１では、７つのドレインパッドＰＤＤ１０３のそれぞれに１本のワイヤＷＡ１０１が接続されるため、７つのドレインパッドＰＤＤ１０３全体では、合計７本のワイヤＷＡ１０１が接続される。このため、図３３～図３６の第１比較例の半導体チップＣＰ１０１では、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１０３に形成されたＬＤＭＯＳＦＥＴのドレインからの出力電流は、７つのドレインパッドＰＤＤ１０３から合計７本のワイヤＷＡ１０１を経て、配線基板１１の基板側端子ＴＥに出力される。一方、本実施の形態の半導体チップＣＰ１では、図２９～図３２にも示される様に、１つのドレインパッドＰＤＤ３に７本のワイヤＷＡが接続されるため、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３に形成されたＬＤＭＯＳＦＥＴのドレインからの出力電流は、１つのドレインパッドＰＤＤ３から合計７本のワイヤＷＡ１０１を経て、配線基板１１の基板側端子ＴＥに出力される。従って、図２９～図３２（本実施の形態）と図３３～図３６（第１比較例）とを比べると、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３，ＲＥＧＬ１０３に形成されたＬＤＭＯＳＦＥＴのドレインからの出力電流が流れるワイヤ（ＷＡ，ＷＡ１０１）の数は、同じ（ここでは７本）である。 In the semiconductor chip CP101 of the first comparative example shown in FIGS. 33 to 36, one wire WA101 is connected to each of the seven drain pads PDD103. Therefore, a total of seven wires WA101 are formed in the seven drain pads PDD103 as a whole. Connected. For this reason, in the semiconductor chip CP101 of the first comparative example of FIGS. 33 to 36, the output current from the drain of the LDMOSFET formed in the LDMOSFET formation region REGL103 passes through seven wires WA101 from the seven drain pads PDD103 in total. And output to the board-side terminal TE of the wiring board 11. On the other hand, in the semiconductor chip CP1 of the present embodiment, as shown in FIGS. 29 to 32, since seven wires WA are connected to one drain pad PDD3, the LDMOSFET formed in the LDMOSFET formation region REGL3. The output current from the drain of the wiring board 11 is output from one drain pad PDD3 to the board-side terminal TE of the wiring board 11 through a total of seven wires WA101. Therefore, comparing FIGS. 29 to 32 (this embodiment) and FIGS. 33 to 36 (first comparative example), the wire through which the output current flows from the drains of the LDMOSFETs formed in the LDMOSFET formation regions REGL3 and REGL103. The number of (WA, WA101) is the same (here, 7).
　図３９は、本実施の形態の半導体チップＣＰ１のドレインパッドＰＤＤ３に形成されたプローブ痕ＰＲＢと、ドレインパッドＰＤＤ３におけるワイヤＷＡの接続領域ＲＧＷとを示す説明図（平面図）であり、上記図３７および図３８に対応するものである。図３９において、（ａ）には、プローブ検査前のドレインパッドＰＤＤ３が示され、（ｂ）には、プローブ検査（上記ステップＳ１２に対応）でドレインパッドＰＤＤ３において２箇所に検査用のプローブ（探針）が押し当てられたことで、プローブ痕ＰＲＢが形成された状態が模式的に示されている。図３９において、（ｃ）には、ワイヤボンディング工程（上記ステップＳ５に対応）でドレインパッドＰＤＤ３にワイヤＷＡが接続されたときのワイヤＷＡの接続領域ＲＧＷが示されている。また、図４０は、本実施の形態の半導体チップＣＰ１のドレインパッドＰＤＤ３に形成されたプローブ痕ＰＲＢと、ドレインパッドＰＤＤ３におけるワイヤＷＡの接続領域ＲＧＷとを示す説明図であり、図４０の（ａ）には、図３９において二点鎖線で囲まれた領域５７の拡大図が示されており、図４０の（ｂ）には、図４０の（ａ）のＢ１－Ｂ１線の断面図が示されている。なお、図４０の（ａ）は、平面図であるが、図面を見やすくするために、プローブ痕ＰＲＢとワイヤＷＡの接続領域ＲＧＷとにハッチングを付してある。 FIG. 39 is an explanatory view (plan view) showing the probe mark PRB formed on the drain pad PDD3 of the semiconductor chip CP1 of this embodiment and the connection region RGW of the wire WA in the drain pad PDD3. This corresponds to FIG. In FIG. 39, (a) shows the drain pad PDD3 before the probe test, and (b) shows a probe (probe for inspection) at two locations on the drain pad PDD3 in the probe test (corresponding to step S12). A state in which the probe mark PRB is formed by pressing the needle) is schematically shown. In FIG. 39, (c) shows a connection region RGW of the wire WA when the wire WA is connected to the drain pad PDD3 in the wire bonding step (corresponding to step S5). FIG. 40 is an explanatory diagram showing the probe mark PRB formed on the drain pad PDD3 of the semiconductor chip CP1 of this embodiment and the connection region RGW of the wire WA in the drain pad PDD3. ) Shows an enlarged view of a region 57 surrounded by a two-dot chain line in FIG. 39, and FIG. 40 (b) shows a cross-sectional view taken along line B1-B1 of FIG. 40 (a). Has been. FIG. 40A is a plan view, but the probe mark PRB and the connection region RGW of the wire WA are hatched for easy viewing of the drawing.
　また、図４１は、プローブ検査（上記ステップＳ１２に対応）でドレインパッドＰＤＤ３に検査用のプローブ（探針）５８を押し当てる様子を示す断面図であり、図４２は、図４１でプローブ５８をドレインパッドＰＤＤ３に押し当てたことで、ドレインパッドＰＤＤ３にプローブ痕ＰＲＢが形成された状態を示す断面図であり、いずれも上記図１８に相当する断面が示されている。図４１からも分かるように、プローブ検査前は、ドレインパッドＰＤＤ３の表面（上面）はほぼ平坦である。しかしながら、図４１に示されるように、プローブ検査（上記ステップＳ１２）でプローブ５８をドレインパッドＰＤＤ３に押し当てると、図４２に示されるように、ドレインパッドＰＤＤ３を構成する導電体膜（すなわちソース配線Ｍ２Ｓを構成する導電体膜）が変形して窪み（凹部）が形成され、場合によっては窪み（凹部）とともに凸部も形成される。ドレインパッドＰＤＤ３において、この平坦性が崩れた部分（窪みが形成された部分または窪みと凸部とが形成された部分）により、プローブ痕ＰＲＢが形成される。 41 is a cross-sectional view showing a state in which the probe (probe) 58 for inspection is pressed against the drain pad PDD3 in the probe inspection (corresponding to step S12 above), and FIG. 42 shows the probe 58 in FIG. FIG. 19 is a cross-sectional view showing a state in which a probe mark PRB is formed on the drain pad PDD3 by being pressed against the drain pad PDD3, and each shows a cross-section corresponding to FIG. As can be seen from FIG. 41, the surface (upper surface) of the drain pad PDD3 is substantially flat before the probe test. However, as shown in FIG. 41, when the probe 58 is pressed against the drain pad PDD3 in the probe test (step S12), as shown in FIG. 42, the conductor film (that is, the source wiring) constituting the drain pad PDD3. The conductor film constituting the M2S is deformed to form a depression (concave part), and in some cases, a convex part is formed together with the depression (concave part). In the drain pad PDD3, a probe mark PRB is formed by a portion where the flatness is lost (a portion where a recess is formed or a portion where a recess and a projection are formed).
　本実施の形態の主要な特徴の他の一つは、ドレインパッドＰＤＤ３に複数のワイヤＷＡを接続するとともに、図３９および図４０からも分かるように、ドレインパッドＰＤＤ３において、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ痕ＰＲＢが形成されていることである。すなわち、パッド電極ＰＤＤ３において、上記ステップＳ１２のプローブ検査でプローブが当てられる（接触する）位置（すなわちプローブ痕ＰＲＢが形成される位置）は、上記ステップＳ５のワイヤボンディング工程で複数（ここでは７本）のワイヤＷＡを接続する位置の間に位置している。つまり、ドレインパッドＰＤＤ３において、あるワイヤＷＡの接続領域ＲＧＷとその隣のワイヤＷＡの接続領域ＲＧＷとの間に、プローブ検査においてプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）が位置しているのである。 Another main feature of the present embodiment is that a plurality of wires WA are connected to the drain pad PDD3 and, as can be seen from FIGS. 39 and 40, a plurality of wires WA are connected in the drain pad PDD3. The probe mark PRB is formed between the regions RGW. That is, in the pad electrode PDD3, a plurality of (here, seven) positions where the probe is applied (contacted) in the probe inspection in step S12 (that is, the position where the probe mark PRB is formed) are formed in the wire bonding step in step S5. ) Between the positions where the wire WA is connected. That is, in the drain pad PDD3, the region where the probe is pressed in the probe inspection (that is, the probe mark PRB) is located between the connection region RGW of a certain wire WA and the connection region RGW of the adjacent wire WA. is there.
　具体的には、ドレインパッドＰＤＤ３のＸ方向の寸法はドレインパッドＰＤＤ３のＹ方向の寸法よりも大きくなっており、このドレインパッドＰＤＤ３に複数（ここでは７本）のワイヤＷＡが接続されているが、ドレインパッドＰＤＤ３におけるワイヤＷＡの接続領域ＲＧＷは、Ｘ方向に並んでいる（配列している）。そして、図３９の（ｃ）に示されるように、ドレインパッドＰＤＤ３において、ワイヤＷＡの接続領域ＲＧＷ同士は、Ｘ方向に隣り合っており、Ｘ方向に隣り合う接続領域ＲＧＷの間に、プローブ痕ＰＲＢ（すなわち上記ステップＳ１２のプローブ検査でプローブが当てられる位置）が位置するようにしている。このため、ドレインパッドＰＤＤ３において、隣り合うワイヤＷＡの接続領域ＲＧＷと、その隣り合うワイヤＷＡの接続領域ＲＧＷの間にあるプローブ痕ＰＲＢとが、Ｘ方向に並んでいる。 Specifically, the dimension in the X direction of the drain pad PDD3 is larger than the dimension in the Y direction of the drain pad PDD3, and a plurality of (in this case, seven) wires WA are connected to the drain pad PDD3. The connection regions RGW of the wires WA in the drain pad PDD3 are aligned (arranged) in the X direction. As shown in FIG. 39 (c), in the drain pad PDD3, the connection regions RGW of the wires WA are adjacent to each other in the X direction, and probe traces are connected between the connection regions RGW adjacent in the X direction. The PRB (that is, the position where the probe is applied in the probe inspection in step S12) is positioned. For this reason, in the drain pad PDD3, the connection region RGW of the adjacent wires WA and the probe mark PRB between the connection regions RGW of the adjacent wires WA are arranged in the X direction.
　ドレインパッドＰＤＤ３に複数のワイヤＷＡを接続し、ドレインパッドＰＤＤ３における複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査工程においてプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）が位置していることは、以下の利点を生じさせる。 A plurality of wires WA are connected to the drain pad PDD3, and a region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) is located between the connection regions RGW of the plurality of wires WA in the drain pad PDD3. Produces the following advantages:
　まず、半導体チップＣＰ１のドレインパッドＰＤＤ３と配線基板１１（配線基板母体２５）の端子ＴＥとの間を複数のワイヤＷＡを介して接続したことにより、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３に形成されたＬＤＭＯＳＦＥＴのドレインからの出力電流は、ドレインパッドＰＤＤ３から複数（ここでは７本）のワイヤＷＡを経て、配線基板１１の基板側端子ＴＥに出力される。これにより、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３（のドレイン）からの出力電流を、ドレインパッドＰＤＤ３から配線基板１１の端子ＴＥに出力するためのワイヤＷＡの数を増やすことができるため、ワイヤＷＡによる抵抗成分を低減し、電力損失を低減することができる。 First, by connecting the drain pad PDD3 of the semiconductor chip CP1 and the terminal TE of the wiring board 11 (wiring board base body 25) via a plurality of wires WA, from the drain of the LDMOSFET formed in the LDMOSFET formation region REGL3. Is output from the drain pad PDD3 to the board-side terminal TE of the wiring board 11 through a plurality of (here, seven) wires WA. As a result, the number of wires WA for outputting the output current from the LDMOSFET formation region REGL3 (the drain thereof) from the drain pad PDD3 to the terminal TE of the wiring substrate 11 can be increased, so that the resistance component due to the wire WA is reduced. In addition, power loss can be reduced.
　更に、ドレインパッドＰＤＤ３において、隣り合うワイヤＷＡの接続領域ＲＧＷの間にプローブ検査でプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）が位置していることで、ドレインパッドＰＤＤ３において、ワイヤＷＡの接続領域ＲＧＷとプローブ痕ＰＲＢとの重なりを小さくすることができ、好ましくはワイヤＷＡの接続領域ＲＧＷとプローブ痕ＰＲＢとが重ならない（平面視で重ならない）ようにすることができる。これにより、ドレインパッドＰＤＤ３の平坦な部分（プローブ痕ＰＲＢが形成されていない部分）にワイヤＷＡを接続することができるため、ドレインパッドＰＤＤ３とワイヤＷＡとの接続強度を向上させることができる。このため、製造された電力増幅モジュールＰＡ１の信頼性を向上させることができる。 Further, in the drain pad PDD3, the region where the probe is pressed by the probe inspection (that is, the probe mark PRB) is located between the connection regions RGW of the adjacent wires WA, so that the connection of the wire WA is performed in the drain pad PDD3. The overlap between the region RGW and the probe mark PRB can be reduced, and preferably, the connection region RGW of the wire WA and the probe mark PRB can be prevented from overlapping (not overlapping in plan view). As a result, the wire WA can be connected to the flat portion of the drain pad PDD3 (the portion where the probe mark PRB is not formed), so that the connection strength between the drain pad PDD3 and the wire WA can be improved. For this reason, the reliability of manufactured power amplification module PA1 can be improved.
　また、ドレインパッドＰＤＤ３において、隣り合うワイヤＷＡの接続領域ＲＧＷの間にプローブ検査においてプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させるため、プローブ検査においてプローブを押し当てる領域（すなわちプローブ痕ＰＲＢ）を確保するための平面領域が、半導体チップＣＰ１のチップサイズの増大に寄与せず、半導体チップＣＰ１の平面寸法（平面積）の縮小の点で有利である。 In addition, in the drain pad PDD3, a region where the probe is pressed in the probe inspection (that is, the probe mark PRB) is positioned between the connection regions RGW of the adjacent wires WA. The planar area for securing (PRB) does not contribute to an increase in the chip size of the semiconductor chip CP1, and is advantageous in terms of reducing the planar dimension (planar area) of the semiconductor chip CP1.
　すなわち、ワイヤボンディング工程を行う際には、ワイヤボンディング装置（ボンディングツール）などに起因して、隣り合うワイヤＷＡの接続領域ＲＧＷの間に所定の間隔を空ける必要がある。ドレインパッドＰＤＤ３において、この隣り合うワイヤＷＡの接続領域ＲＧＷの間の空いたスペースを、プローブ検査においてプローブを押し当てる領域（すなわちプローブ痕ＰＲＢが形成される領域）に割り当てる。つまり、図３３～図３７の第１比較例の半導体チップＣＰ１０１では、隣り合うドレインパッドＰＤＤ１０３の間の領域（表面保護膜である上記絶縁膜５２が形成されている領域）であったところを、図２９～図３２、図３９および図４０の本実施の形態の半導体チップＣＰ１ではドレインパッドＰＤＤ３の一部とし、そこをプローブ検査においてプローブを押し当てる領域（すなわちプローブ痕ＰＲＢが形成される領域）として使用できる。このため、図３３～図３７の第１比較例の半導体チップＣＰ１０１ではパッド電極としても回路領域としても使用していなかった領域（すなわち隣り合うドレインパッドＰＤＤ１０３の間の領域）を、図２９～図３２、図３９および図４０の本実施の形態の半導体チップＣＰ１では、プローブ検査でプローブを押し当てる領域（すなわちプローブ痕ＰＲＢが形成される領域）として使用することになる。このため、半導体チップＣＰ１のチップサイズの増大を抑制することができる。従って、１枚のウエハから取得できる半導体チップＣＰ１の数を増やすことができるため、製造コストを低減することができ、また、半導体チップＣＰ１を搭載した半導体装置（ここでは電力増幅モジュールＰＡ１）の小型化（平面寸法の縮小）を図ることができる。 That is, when performing the wire bonding step, it is necessary to leave a predetermined interval between the connection regions RGW of the adjacent wires WA due to a wire bonding apparatus (bonding tool) or the like. In the drain pad PDD3, an empty space between the connection regions RGW of the adjacent wires WA is assigned to a region where the probe is pressed in the probe inspection (that is, a region where the probe mark PRB is formed). That is, in the semiconductor chip CP101 of the first comparative example of FIGS. 33 to 37, the region between the adjacent drain pads PDD103 (the region where the insulating film 52 as the surface protective film is formed) In the semiconductor chip CP1 of the present embodiment shown in FIGS. 29 to 32, 39 and 40, a part of the drain pad PDD3 is used, and this is a region where the probe is pressed in the probe inspection (that is, the region where the probe mark PRB is formed). Can be used as For this reason, in the semiconductor chip CP101 of the first comparative example of FIGS. 33 to 37, a region that is not used as a pad electrode or a circuit region (that is, a region between adjacent drain pads PDD103) is shown in FIGS. In the semiconductor chip CP1 of this embodiment shown in FIGS. 32, 39 and 40, it is used as a region where the probe is pressed in the probe inspection (that is, a region where the probe mark PRB is formed). For this reason, an increase in the chip size of the semiconductor chip CP1 can be suppressed. Accordingly, since the number of semiconductor chips CP1 that can be obtained from one wafer can be increased, the manufacturing cost can be reduced, and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted can be reduced in size. (Reduction of planar dimensions) can be achieved.
　また、図３８の第２の比較例の半導体チップのドレインパッドＰＤＤ２０３の場合は、ワイヤＷＡ１０１の接続領域ＲＧＷ２０１とプローブ痕ＰＲＢ２０１とをＹ方向にずらしているため、ドレインパッドＰＤＤ２０３のＹ方向の寸法を、プローブ痕ＰＲＢ２０１の分だけ大きくする必要がある。それに対して、本実施の形態の半導体チップＣＰ１では、Ｘ方向に隣り合うワイヤＷＡ１０１の接続領域ＲＧＷの間にプローブ痕ＰＲＢが配置されるため、ドレインパッドＰＤＤ３のＹ方向の寸法は、ワイヤＷＡ１０１の接続領域ＲＧＷを確保できる寸法に設定すればよく、プローブ痕ＰＲＢの面積を考慮してドレインパッドＰＤＤ３のＹ方向の寸法を大きくする必要がない。すなわち、本実施の形態の半導体チップＣＰ１のドレインパッドＰＤＤ３のＹ方向の寸法は、第１比較例の半導体チップＣＰ１０１におけるドレインパッドＰＤＤ１０３のＹ方向の寸法と同程度とすることができ、図３８の第２比較例の半導体チップにおけるドレインパッドＰＤＤ２０３のＹ方向の寸法よりも小さくすることができる。このため、本実施の形態では、図３８のドレインパッドＰＤＤ２０３を適用した場合に比べて、半導体チップＣＰ１の平面寸法（平面積）を小さくすることができ、製造コストの低減や、半導体チップＣＰ１を搭載した半導体装置（ここでは電力増幅モジュールＰＡ１）の小型化（平面寸法の縮小）を図ることができる。 In the case of the drain pad PDD203 of the semiconductor chip of the second comparative example of FIG. 38, the connection region RGW201 of the wire WA101 and the probe mark PRB201 are shifted in the Y direction. It is necessary to enlarge the probe mark PRB201. On the other hand, in the semiconductor chip CP1 of the present embodiment, since the probe mark PRB is arranged between the connection regions RGW of the wires WA101 adjacent in the X direction, the dimension of the drain pad PDD3 in the Y direction is the same as that of the wire WA101. It is only necessary to set a dimension that can secure the connection region RGW, and it is not necessary to increase the dimension in the Y direction of the drain pad PDD3 in consideration of the area of the probe mark PRB. That is, the dimension in the Y direction of the drain pad PDD3 of the semiconductor chip CP1 of the present embodiment can be approximately the same as the dimension in the Y direction of the drain pad PDD103 in the semiconductor chip CP101 of the first comparative example. It can be made smaller than the dimension in the Y direction of the drain pad PDD203 in the semiconductor chip of the second comparative example. Therefore, in the present embodiment, the planar dimension (planar area) of the semiconductor chip CP1 can be reduced compared with the case where the drain pad PDD203 of FIG. 38 is applied, and the manufacturing cost can be reduced and the semiconductor chip CP1 can be manufactured. The mounted semiconductor device (here, power amplification module PA1) can be reduced in size (reduction in planar dimensions).
　このように、上記第１の比較例の半導体チップＣＰ１０１を用いた場合に比べて、本実施の形態では、ドレインパッドＰＤＤ３とワイヤＷＡとの接続強度を向上させることができ、製造された電力増幅モジュールＰＡ１の信頼性を向上させることができる。また、図３８のドレインパッドＰＤＤ２０３を適用した第２の比較例の半導体チップを用いた場合に比べて、本実施の形態では、半導体チップＣＰ１の平面寸法（平面積）を小さくすることができ、製造コストの低減や、半導体チップＣＰ１を搭載した半導体装置（ここでは電力増幅モジュールＰＡ１）の小型化（平面寸法の縮小）を図ることができる。 Thus, compared to the case where the semiconductor chip CP101 of the first comparative example is used, in this embodiment, the connection strength between the drain pad PDD3 and the wire WA can be improved, and the manufactured power amplification The reliability of the module PA1 can be improved. In addition, compared with the case where the semiconductor chip of the second comparative example to which the drain pad PDD203 of FIG. 38 is applied is used, in this embodiment, the planar dimension (planar area) of the semiconductor chip CP1 can be reduced. The manufacturing cost can be reduced, and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted can be downsized (planar dimensions can be reduced).
　ここで、ドレインパッドＰＤＤ３の寸法の一例を挙げる。ドレインパッドＰＤＤ３は、このドレインパッドＰＤＤ３が配置された側のチップ辺（ここでは辺ＳＤ１）に沿って長い平面形状を有しているが、ドレインパッドＰＤＤ３の短辺方向（Ｙ方向）の寸法（長さ）Ｌ１は、接続するワイヤＷＡの先端の金属ボールの大きさにもよるが、例えば６５μｍ程度とすることができる（寸法Ｌ１は図４０に示してある）。ドレインパッドＰＤＤ３におけるワイヤＷＡの接続ピッチ（接続間隔）Ｐ１（接続ピッチＰ１は図４０に示してある）は、プローブ痕ＰＲＢの配置を考慮すると、ドレインパッドＰＤＤ３の短辺方向の寸法Ｌ１の１．２倍以上（すなわちＰ１≧Ｌ１×１．２）が好ましい。また、ドレインパッドＰＤＤ３の短辺方向（Ｙ方向）にワイヤＷＡの接続領域ＲＧＷとプローブ痕ＰＲＢとが並ばないので、面積節約の観点から、ワイヤＷＡの接続領域ＲＧＷの直径Ｌ２（直径Ｌ２は図４０に示してある）が、ドレインパッドＰＤＤ３の短辺方向の寸法Ｌ１の６０％以上（すなわちＬ２≧Ｌ１×０．６）になるように、ドレインパッドＰＤＤ３の短辺方向の寸法Ｌ１を設定することが好ましい。また、ドレインパッドＰＤＤ３を構成する導電体膜（上記ソース配線Ｍ２Ｓに対応）の厚みは、例えば０．３～３μｍ程度とすることができる。 Here, an example of the dimensions of the drain pad PDD3 is given. Although the drain pad PDD3 has a long planar shape along the chip side (here, the side SD1) on the side where the drain pad PDD3 is disposed, the dimension of the drain pad PDD3 in the short side direction (Y direction) ( The length L1 depends on the size of the metal ball at the tip of the wire WA to be connected, but can be, for example, about 65 μm (the dimension L1 is shown in FIG. 40). The connection pitch (connection interval) P1 of the wires WA in the drain pad PDD3 (the connection pitch P1 is shown in FIG. 40) is set to 1 of the dimension L1 in the short side direction of the drain pad PDD3 in consideration of the arrangement of the probe marks PRB. Two times or more (that is, P1 ≧ L1 × 1.2) is preferable. Further, since the connection region RGW of the wire WA and the probe trace PRB are not arranged in the short side direction (Y direction) of the drain pad PDD3, the diameter L2 (diameter L2 is a figure of the connection region RGW of the wire WA from the viewpoint of area saving). 40) is set to be 60% or more of the dimension L1 in the short side direction of the drain pad PDD3 (that is, L2 ≧ L1 × 0.6), and the dimension L1 in the short side direction of the drain pad PDD3 is set. It is preferable. The thickness of the conductor film (corresponding to the source line M2S) constituting the drain pad PDD3 can be set to, for example, about 0.3 to 3 μm.
　また、ドレインパッドＰＤＤ３において、Ｘ方向に隣り合うワイヤＷＡの接続領域ＲＧＷの間にプローブ痕ＰＲＢが配置されていれば、プローブ痕ＰＲＢの一部がワイヤＷＡの接続領域ＲＧＷと重なっている場合であっても、プローブ痕ＰＲＢとワイヤＷＡの接続領域ＲＧＷとの重なり面積を縮小することができるため、ドレインパッドＰＤＤ３に対するワイヤＷＡの接続強度の向上効果を得ることができる。しかしながら、ドレインパッドＰＤＤ３に対するワイヤＷＡの接続強度をできるだけ高める上では、プローブ痕ＰＲＢとワイヤＷＡの接続領域ＲＧＷとの重なり面積をできるだけ小さくすることが望ましく、プローブ痕ＰＲＢとワイヤＷＡの接続領域ＲＧＷとが重ならないようにすることが、より好ましい。このため、本実施の形態では、ドレインパッドＰＤＤ３において、Ｘ方向に隣り合うワイヤＷＡの接続領域ＲＧＷの間にプローブ痕ＰＲＢが配置されるが、プローブ痕ＰＲＢは、ワイヤＷＡの接続領域ＲＧＷと重なっていない（平面視で重なっていない）ことが、より好ましい。すなわち、上記ステップＳ５のワイヤボンディング工程では、ドレインパッドＰＤＤ３において、プローブ痕ＰＲＢに平面視で重ならない位置に、複数のワイヤＷＡが接続されることが、より好ましい。プローブ痕ＰＲＢとワイヤＷＡの接続領域ＲＧＷとが重ならない（平面視で重ならない）ことにより、プローブ痕ＰＲＢが形成されていない平坦な部分のドレインパッドＰＤＤ３にワイヤＷＡが接続されることになるため、ドレインパッドＰＤＤ３に対するワイヤＷＡの接続強度を、より的確に向上させることができ、電力増幅モジュールＰＡ１の信頼性を、より的確に向上させることができるようになる。 Further, in the drain pad PDD3, if the probe mark PRB is arranged between the connection regions RGW of the wires WA adjacent in the X direction, the probe mark PRB is partially overlapped with the connection region RGW of the wire WA. Even if it exists, since the overlapping area of the probe mark PRB and the connection region RGW of the wire WA can be reduced, the effect of improving the connection strength of the wire WA to the drain pad PDD3 can be obtained. However, in order to increase the connection strength of the wire WA to the drain pad PDD3 as much as possible, it is desirable to reduce the overlapping area between the probe mark PRB and the connection area RGW of the wire WA as much as possible, and the connection area RGW between the probe mark PRB and the wire WA It is more preferable that the two do not overlap. For this reason, in this embodiment, in the drain pad PDD3, the probe mark PRB is arranged between the connection regions RGW of the wires WA adjacent in the X direction, but the probe mark PRB overlaps with the connection region RGW of the wire WA. It is more preferable that they are not overlapped (in a plan view). That is, in the wire bonding process of step S5, it is more preferable that the plurality of wires WA are connected to the drain pad PDD3 at a position that does not overlap the probe mark PRB in plan view. Since the probe mark PRB and the connection region RGW of the wire WA do not overlap (does not overlap in plan view), the wire WA is connected to the drain pad PDD3 in a flat portion where the probe mark PRB is not formed. The connection strength of the wire WA to the drain pad PDD3 can be improved more accurately, and the reliability of the power amplification module PA1 can be improved more accurately.
　また、ドレインパッドＰＤＤ３に複数のワイヤＷＡが接続されているが、ドレインパッドＰＤＤ３における複数のワイヤＷＡの各接続領域ＲＧＷは、一列に（一直線上に）配列していることが好ましい。すなわち、上記ステップＳ５のワイヤボンディング工程では、ドレインパッドＰＤＤ３において、複数のワイヤＷＡを接続する位置は、一列に（一直線上に）配列していることが好ましい。より具体的には、ドレインパッドＰＤＤ３における複数のワイヤＷＡの接続領域ＲＧＷは、ドレインパッドＰＤＤ３の長辺方向（Ｘ方向）に沿って一列に（一直線上に）配列していることが好ましい。つまり、Ｙ方向寸法よりもＸ方向寸法が大きなドレインパッドＰＤＤ３において、ワイヤＷＡの接続領域ＲＧＷをいわゆる千鳥配列とはせずに（Ｙ方向にずらさずに）、図３１、図３２および図３９に示されるように、Ｘ方向（すなわちドレインパッドＰＤＤ３の長辺方向）に一列に（一直線上に）複数のワイヤＷＡの各接続領域ＲＧＷが配列するようにすることが好ましい。これにより、ドレインパッドＰＤＤ３のＹ方向の寸法を縮小することができる。このため、半導体チップＣＰ１の平面寸法（平面積）を小さくすることができ、製造コストの低減や、半導体チップＣＰ１を搭載した半導体装置（ここでは電力増幅モジュールＰＡ１）の小型化（平面寸法の縮小）を図ることができる。 Further, although a plurality of wires WA are connected to the drain pad PDD3, it is preferable that the connection regions RGW of the plurality of wires WA in the drain pad PDD3 are arranged in a line (on a straight line). That is, in the wire bonding process of step S5, it is preferable that the positions where the plurality of wires WA are connected in the drain pad PDD3 are arranged in a line (on a straight line). More specifically, the connection regions RGW of the plurality of wires WA in the drain pad PDD3 are preferably arranged in a line (on a straight line) along the long side direction (X direction) of the drain pad PDD3. That is, in the drain pad PDD3 whose dimension in the X direction is larger than the dimension in the Y direction, the connection region RGW of the wires WA is not arranged in a so-called staggered arrangement (without shifting in the Y direction), as shown in FIGS. As shown, it is preferable that the connection regions RGW of the plurality of wires WA are arranged in a line (on a straight line) in the X direction (that is, the long side direction of the drain pad PDD3). Thereby, the dimension of the drain pad PDD3 in the Y direction can be reduced. For this reason, the planar dimension (planar area) of the semiconductor chip CP1 can be reduced, the manufacturing cost can be reduced, and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted is reduced (the planar dimension is reduced). ).
　また、図３１、図３２および図３９では、ドレインパッドＰＤＤ３に７本のワイヤＷＡを接続しているが、ドレインパッドＰＤＤ３に接続するワイヤＷＡの数は７本に限定されず、複数（すなわち２本以上）であればよい。また、図３９では、プローブ検査工程においてドレインパッドＰＤＤ３にプローブを押し当てる領域の数（すなわちドレインパッドＰＤＤ３に形成されたプローブ痕ＰＲＢの数、あるいはプローブ検査工程においてドレインパッドＰＤＤ３に押し当てるプローブの数）を２つ（２箇所）としているが、これに限定されず、１つ以上（１箇所以上）であればよく、プローブ検査で的確な検査を行えるように設定すればよい。また、図３９では、ドレインパッドＰＤＤ３におけるワイヤＷＡの接続領域ＲＧＷの間の領域には、プローブ痕ＰＲＢが配置されている領域と、プローブ痕ＰＲＢが配置されていない領域とが混在している。他の形態として、ドレインパッドＰＤＤ３におけるワイヤＷＡの接続領域ＲＧＷの間の領域の全てに対して（ドレインパッドＰＤＤ３に７本のワイヤＷＡを接続した場合は７つの接続領域ＲＧＷの間の６箇所に対して）、プローブ検査においてプローブを押し当てる領域（すなわちプローブ痕ＰＲＢ）を位置させることもできる。また、図３０～図３２では、ドレインパッドＰＤＤ３に一端が接続された複数のワイヤＷＡの他端は、配線基板１１の１つの端子ＴＥに接続されているが、他の形態として、複数のワイヤＷＡの一端をドレインパッドＰＤＤ３に接続し、その複数のワイヤの他端を複数の端子ＴＥにそれぞれ接続することもできる。 In FIG. 31, FIG. 32 and FIG. 39, seven wires WA are connected to the drain pad PDD3. However, the number of wires WA connected to the drain pad PDD3 is not limited to seven. Or more). In FIG. 39, the number of regions in which the probe is pressed against the drain pad PDD3 in the probe inspection process (that is, the number of probe marks PRB formed on the drain pad PDD3, or the number of probes pressed against the drain pad PDD3 in the probe inspection process). ) Is two (two places), but is not limited to this, and may be one or more (one or more places), and may be set so that an accurate inspection can be performed by the probe inspection. In FIG. 39, the region between the connection regions RGW of the wires WA in the drain pad PDD3 includes a region where the probe mark PRB is arranged and a region where the probe mark PRB is not arranged. As another form, for all of the regions between the connection regions RGW of the wires WA in the drain pad PDD3 (when seven wires WA are connected to the drain pad PDD3, there are six locations between the seven connection regions RGW. On the other hand, a region where the probe is pressed in the probe inspection (ie, the probe mark PRB) can be located. 30 to 32, the other ends of the plurality of wires WA whose one ends are connected to the drain pad PDD3 are connected to one terminal TE of the wiring substrate 11. However, as another form, One end of the WA may be connected to the drain pad PDD3, and the other ends of the plurality of wires may be connected to the plurality of terminals TE, respectively.
　なお、ドレインパッドＰＤＤ３に接続するワイヤＷＡの数が３本以上の場合は、２本の場合よりもワイヤＷＡによる抵抗成分を更に低減でき（すなわち電力損失の低減効果をより大きくでき）、また、プローブ検査工程においてドレインパッドＰＤＤ３にプローブを押し当てる領域の数（すなわちドレインパッドＰＤＤ３に形成されたプローブ痕ＰＲＢの数）が２つ以上の場合は、１つの場合よりもプローブ検査の信頼性を更に向上できる。 When the number of wires WA connected to the drain pad PDD3 is three or more, the resistance component due to the wires WA can be further reduced as compared with the case of two wires WA (that is, the power loss reduction effect can be further increased). When the number of regions where the probe is pressed against the drain pad PDD3 in the probe inspection process (that is, the number of probe marks PRB formed on the drain pad PDD3) is two or more, the reliability of the probe inspection is further improved than the case of one. Can be improved.
　また、本実施の形態では、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ３のドレインに電気的に接続されたドレインパッドＰＤＤ３について、ワイヤＷＡの接続領域ＲＧＷとプローブ検査においてプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）との関係を説明したが、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ３のドレインに電気的に接続されたドレインパッドＰＤＤ６についても、同様に適用することができる。すなわち、上記図１４および図１５に示されるように、ドレインパッドＰＤＤ６に複数のワイヤＷＡを接続しているが、図３９および図４０のドレインパッドＰＤＤ３と同様に、ドレインパッドＰＤＤ６においても、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査においてプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）が位置している。これにより、ドレインパッドＰＤＤ６とワイヤＷＡとの接続強度を向上させることができ、電力増幅モジュールＰＡ１の信頼性を向上させることができる。また、半導体チップＣＰ１のチップサイズを抑制することができ、製造コストの低減や、半導体チップＣＰ１を搭載した半導体装置（ここでは電力増幅モジュールＰＡ１）の小型化（平面寸法の縮小）を図ることができる。 In the present embodiment, the drain pad PDD3 electrically connected to the drain of the LDMOSFET formation region REGL3 is connected to the connection region RGW of the wire WA and the region where the probe is pressed in the probe inspection (that is, the probe mark PRB). Although the relationship has been described, the same applies to the drain pad PDD6 electrically connected to the drain of the LDMOSFET formation region REGH3. That is, as shown in FIGS. 14 and 15, a plurality of wires WA are connected to the drain pad PDD6. However, similarly to the drain pad PDD3 in FIGS. Between the connection areas RGW of the wires WA, an area where the probe is pressed in the probe inspection (that is, the probe mark PRB) is located. Thereby, the connection strength between the drain pad PDD6 and the wire WA can be improved, and the reliability of the power amplification module PA1 can be improved. In addition, the chip size of the semiconductor chip CP1 can be suppressed, so that the manufacturing cost can be reduced and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted can be downsized (planar dimensions are reduced). it can.
　また、半導体チップＣＰ１は、多段接続された複数の電力増幅回路（ここでは増幅段ＬＤＭＬ１，ＬＤＭＬ２，ＬＤＭＬ３および増幅段ＬＤＭＨ１，ＬＤＭＨ２，ＬＤＭＨ３）を有しているが、このうち最終段の電力増幅回路（ここでは増幅段ＬＤＭＬ３，ＬＤＭＨ３）を構成する半導体素子（ここではＬＤＭＯＳＦＥＴ）の出力に接続されたパッド電極ＰＤが、ドレインパッドＰＤＤ３，ＰＤＤ６である。最終段の電力増幅回路（ここでは増幅段ＬＤＭＬ３，ＬＤＭＨ３）を構成する半導体素子（ここではＬＤＭＯＳＦＥＴ）の出力に接続されたパッド電極（ドレインパッドＰＤＤ３，ＰＤＤ６）は、出力される電流が大きいため、接続するワイヤＷＡの本数を複数にする（多くする）ことで、ワイヤＷＡによる抵抗成分を低減して電力損失を低減できる効果は極めて大きい。このため、図３９および図４０のドレインパッドＰＤＤ３のように、パッド電極ＰＤにワイヤＷＡを複数本接続し、かつそのパッド電極ＰＤにおける複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査でプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させる上記特徴は、最終段の電力増幅回路の出力に接続されたパッド電極（ここではドレインパッドＰＤＤ３，ＰＤＤ６）に適用すれば、特に有効である。また、最終段の電力増幅回路（ここでは増幅段ＬＤＭＬ３，ＬＤＭＨ３）は、前段の電力増幅回路に比べて面積が大きいため、出力に接続されたパッド電極（ドレインパッドＰＤＤ３，ＰＤＤ６）を長方形状のパッド電極にしてそこに複数のワイヤＷＡを接続しても、半導体チップＣＰ１の面積増大を招きにくい。 The semiconductor chip CP1 has a plurality of power amplifier circuits (in this case, the amplifier stages LDML1, LDML2, and LDML3 and the amplifier stages LDMH1, LDMH2, and LDMH3) connected in multiple stages. The pad electrodes PD connected to the outputs of the semiconductor elements (here, LDMOSFETs) constituting the amplification stages (LDML3, LDMH3) are drain pads PDD3, PDD6. Since the pad electrode (drain pad PDD3, PDD6) connected to the output of the semiconductor element (here LDMOSFET) constituting the final stage power amplification circuit (here amplification stage LDML3, LDMH3) has a large output current, By making the number of wires WA to be connected to be plural (increase), the effect of reducing the resistance component by the wires WA and reducing the power loss is extremely great. Therefore, like the drain pad PDD3 in FIGS. 39 and 40, a plurality of wires WA are connected to the pad electrode PD, and a probe inspection is performed between the connection regions RGW of the plurality of wires WA in the pad electrode PD. The above-described feature of locating the region where the is pressed (ie, the probe mark PRB) is particularly effective when applied to the pad electrodes (here, drain pads PDD3 and PDD6) connected to the output of the power amplifier circuit in the final stage. . Further, since the power amplifier circuit in the final stage (here, the amplifier stages LDML3 and LDMH3) has a larger area than the power amplifier circuit in the previous stage, the pad electrodes (drain pads PDD3 and PDD6) connected to the output are rectangular. Even if a plurality of wires WA are connected to the pad electrode, it is difficult to increase the area of the semiconductor chip CP1.
　また、最終段の増幅段ＬＤＭＬ３，ＬＤＭＨ３よりも前の増幅段ＬＤＭＬ１，ＬＤＭＬ２，ＬＤＭＨ１，ＬＤＭＨ２を構成する半導体素子（ここではＬＤＭＯＳＦＥＴ）の出力に接続されたパッド電極ＰＤ（ここではドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ４，ＰＤＤ５）であっても、そのパッド電極ＰＤにワイヤＷＡを複数本、接続する場合は、図３９および図４０のドレインパッドＰＤＤ３の特徴を適用できる。すなわち、そのパッド電極ＰＤにおいても、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査でプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させることができる。例えば、図１４および図１５のようにドレインパッドＰＤＤ２に複数（図１４の場合は２本）のワイヤＷＡを接続し、かつ、このドレインパッドＰＤＤ２においても、上記図４０のドレインパッドＰＤＤ３のように、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査でプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させることができる。また、図１４および図１５のようにドレインパッドＰＤＤ５に複数（図１４の場合は２本）のワイヤＷＡを接続し、かつ、このドレインパッドＰＤＤ５においても、上記図４０のドレインパッドＰＤＤ３のように、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査でプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させることができる。 Also, pad electrodes PD (here, drain pads PDD1, PDD2) connected to the outputs of the semiconductor elements (here, LDMOSFETs) constituting the amplification stages LDML1, LDML2, LDMH1, and LDMH2 prior to the last amplification stages LDML3 and LDMH3. , PDD4, PDD5), when connecting a plurality of wires WA to the pad electrode PD, the features of the drain pad PDD3 of FIGS. 39 and 40 can be applied. That is, also in the pad electrode PD, the region where the probe is pressed in the probe inspection (that is, the probe mark PRB) can be positioned between the connection regions RGW of the plurality of wires WA. For example, as shown in FIGS. 14 and 15, a plurality (two in the case of FIG. 14) of wires WA are connected to the drain pad PDD2, and also in this drain pad PDD2, like the drain pad PDD3 in FIG. Between the connection regions RGW of the plurality of wires WA, a region where the probe is pressed in the probe inspection (that is, the probe mark PRB) can be positioned. Further, as shown in FIGS. 14 and 15, a plurality (two in the case of FIG. 14) of wires WA are connected to the drain pad PDD5, and also in this drain pad PDD5, as in the drain pad PDD3 of FIG. Between the connection regions RGW of the plurality of wires WA, a region where the probe is pressed in the probe inspection (that is, the probe mark PRB) can be positioned.
　すなわち、本実施の形態では、電力増幅回路を有する半導体チップＣＰ１のパッド電極ＰＤのうち、電力増幅回路を構成する半導体素子（ここではＬＤＭＯＳＦＥＴ）の出力に接続されたパッド電極ＰＤ（ここではドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３、ＰＤＤ４，ＰＤＤ５，ＰＤＤ６のいずれか）に複数のワイヤＷＡを接続している。そして、このパッド電極ＰＤにおいて、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査でプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させているのである。 That is, in the present embodiment, among the pad electrodes PD of the semiconductor chip CP1 having the power amplifier circuit, the pad electrode PD (here, drain pad) connected to the output of the semiconductor element (here, LDMOSFET) constituting the power amplifier circuit. A plurality of wires WA are connected to any one of PDD1, PDD2, PDD3, PDD4, PDD5 and PDD6). And in this pad electrode PD, the area | region (namely, probe mark PRB) which pressed the probe by the probe test | inspection is located between the connection area | region RGW of several wire WA.
　＜第１の変形例について＞
　図４３は、第１の変形例の説明図であり、上記図３９に対応するものである。図４３において、（ａ）には、プローブ検査前のドレインパッドＰＤＤ３が示され、（ｂ）には、プローブ検査（上記ステップＳ１２に対応）でドレインパッドＰＤＤ３において２箇所に検査用のプローブ（探針）が押し当てられたことで、プローブ痕ＰＲＢが形成された状態が模式的に示されている。図４３において、（ｃ）には、ワイヤボンディング工程（上記ステップＳ５に対応）でドレインパッドＰＤＤ３にワイヤＷＡが接続されたときのワイヤＷＡの接続領域ＲＧＷが示されている。 <About the first modification>
FIG. 43 is an explanatory diagram of the first modified example and corresponds to FIG. 39 described above. In FIG. 43, (a) shows the drain pad PDD3 before the probe inspection, and (b) shows the probe (probing for inspection) at two locations on the drain pad PDD3 in the probe inspection (corresponding to step S12). A state in which the probe mark PRB is formed by pressing the needle) is schematically shown. In FIG. 43, (c) shows a connection region RGW of the wire WA when the wire WA is connected to the drain pad PDD3 in the wire bonding step (corresponding to step S5).
　上記図３９の場合は、ドレインパッドＰＤＤ３にワイヤＷＡは３本以上接続され、かつ等間隔で接続されている。すなわち、ドレインパッドＰＤＤ３において、複数のワイヤＷＡが等ピッチ（等間隔）で接続されており、ワイヤＷＡの接続領域ＲＧＷとその隣のワイヤＷＡの接続領域ＲＧＷとの間の間隔（Ｘ方向の距離、上記ピッチＰ１）は、ドレインパッドＰＤＤ３に接続されたいずれのワイヤＷＡに対しても同じである。これは、上記ステップＳ５のワイヤボンディング工程で、ドレインパッドＰＤＤ３に３本以上のワイヤＷＡが接続され、かつそれら３本以上のワイヤＷＡがドレインパッドＰＤＤ３に等ピッチ（等間隔）で接続されたためである。ドレインパッドＰＤＤ３における複数のワイヤＷＡの接続領域ＲＧＷの間の領域には、プローブ痕ＰＲＢが配置されている領域と、プローブ痕ＰＲＢが配置されていない領域とが混在している。 In the case of FIG. 39, three or more wires WA are connected to the drain pad PDD3 and are connected at equal intervals. That is, in the drain pad PDD3, a plurality of wires WA are connected at an equal pitch (equal interval), and an interval (a distance in the X direction) between the connection region RGW of the wire WA and the connection region RGW of the adjacent wire WA. The pitch P1) is the same for any wire WA connected to the drain pad PDD3. This is because in the wire bonding step of step S5, three or more wires WA are connected to the drain pad PDD3, and these three or more wires WA are connected to the drain pad PDD3 at equal pitches (equal intervals). is there. In the region between the connection regions RGW of the plurality of wires WA in the drain pad PDD3, a region where the probe mark PRB is arranged and a region where the probe mark PRB is not arranged are mixed.
　一方、図４３の場合は、ドレインパッドＰＤＤ３にワイヤＷＡは３本以上接続され、かつ、ドレインパッドＰＤＤ３における複数のワイヤＷＡの接続領域ＲＧＷの間の領域には、プローブ痕ＰＲＢが配置されている領域と、プローブ痕ＰＲＢが配置されていない領域とが混在している。そして、このドレインパッドＰＤＤ３において、複数のワイヤＷＡは等ピッチ（等間隔）では接続されていない。すなわち、ドレインパッドＰＤＤ３において、間にプローブ痕ＰＲＢが配置されている接続領域ＲＧＷ間の間隔（ピッチ、距離）Ｐ５は、間にプローブ痕ＰＲＢが配置されていない接続領域ＲＧＷ間の間隔（ピッチ、距離）Ｐ６よりも大きくなっている（すなわちＰ５＞Ｐ６）。ここで、間隔Ｐ５，Ｐ６は図４３に示されており、間隔Ｐ５は、ドレインパッドＰＤＤ３に接続された複数のワイヤＷＡについて、プローブ痕ＰＲＢを間に挟んで隣り合うワイヤＷＡの接続領域ＲＧＷの間隔（ピッチ、距離）に対応している。また、間隔Ｐ６は、ドレインパッドＰＤＤ３に接続された複数のワイヤＷＡについて、プローブ痕ＰＲＢを間に挟まずに隣り合うワイヤＷＡの接続領域ＲＧＷの間隔（ピッチ、距離）に対応している。 On the other hand, in the case of FIG. 43, three or more wires WA are connected to the drain pad PDD3, and a probe mark PRB is arranged in a region between the connection regions RGW of the plurality of wires WA in the drain pad PDD3. A region and a region where the probe mark PRB is not arranged are mixed. In the drain pad PDD3, the plurality of wires WA are not connected at an equal pitch (equal interval). That is, in the drain pad PDD3, the interval (pitch, distance) P5 between the connection regions RGW between which the probe marks PRB are disposed is the interval (pitch, distance) between the connection regions RGW between which the probe marks PRB are not disposed. Distance) is larger than P6 (that is, P5> P6). Here, the intervals P5 and P6 are shown in FIG. 43, and the interval P5 indicates a plurality of wires WA connected to the drain pad PDD3 in the connection region RGW of adjacent wires WA with the probe mark PRB interposed therebetween. It corresponds to the interval (pitch, distance). The interval P6 corresponds to the interval (pitch, distance) between the connection regions RGW of adjacent wires WA without interposing the probe mark PRB between the plurality of wires WA connected to the drain pad PDD3.
　上記図３９のようにパッド電極ＰＤ（ここではドレインパッドＰＤＤ３）にワイヤＷＡが等間隔（等ピッチ）で接続されている場合には、ワイヤＷＡの接続領域ＲＧＷの間隔をワイヤボンディング装置（ボンディングツール）に起因して設定する必要がある最小限の間隔（ピッチ）に設定することができ、パッド電極ＰＤ（ここではドレインパッドＰＤＤ３）に接続するワイヤＷＡの数を効率的に増やすことができる。このため、ワイヤＷＡによる抵抗成分を効率的に低減し、電力損失を効率的に低減することができる。また、パッド電極ＰＤの長辺方向の寸法も抑制でき、半導体チップＣＰ１のチップサイズの縮小も可能になる。 As shown in FIG. 39, when the wires WA are connected to the pad electrodes PD (here, the drain pads PDD3) at equal intervals (equal pitch), the interval between the connection regions RGW of the wires WA is set to a wire bonding apparatus (bonding tool). ) Can be set to the minimum interval (pitch) that needs to be set, and the number of wires WA connected to the pad electrode PD (here, the drain pad PDD3) can be efficiently increased. For this reason, the resistance component by wire WA can be reduced efficiently and a power loss can be reduced efficiently. Further, the dimension of the pad electrode PD in the long side direction can be suppressed, and the chip size of the semiconductor chip CP1 can be reduced.
　一方、図４３のように、パッド電極ＰＤ（ここではドレインパッドＰＤＤ３）において、間にプローブ痕ＰＲＢが配置されているワイヤＷＡの接続領域ＲＧＷ間の間隔Ｐ５を、間にプローブ痕ＰＲＢが配置されていないワイヤＷＡの接続領域ＲＧＷ間の間隔Ｐ６よりも大きく（Ｐ５＞Ｐ６）した場合には、以下の利点を得られる。すなわち、間隔Ｐ５が小さすぎると、ワイヤＷＡの接続領域ＲＧＷとプローブ痕ＰＲＢとが重なってワイヤＷＡの接続強度が低下しやすくなる。また、間隔Ｐ６を小さくしても、ワイヤＷＡの接続領域ＲＧＷとプローブ痕ＰＲＢとが重ることはなく、ワイヤＷＡの接続強度の低下は招かないが、間隔Ｐ６を大きくすると、パッド電極ＰＤ（ここではドレインパッドＰＤＤ３）に接続できるワイヤＷＡの本数が少なくなり、あるいは、パッド電極ＰＤ（ここではドレインパッドＰＤＤ３）の長辺方向（ここではＸ方向）の寸法が増大してしまう。このため、間隔Ｐ５を間隔Ｐ６よりも大きく（Ｐ５＞Ｐ６）することで、ワイヤＷＡの接続領域ＲＧＷとプローブ痕ＰＲＢとが重なりをより的確に抑制または防止してワイヤＷＡの接続強度を向上することができるとともに、間隔Ｐ６を間隔Ｐ５よりも小さく（Ｐ５＞Ｐ６）することで、パッド電極ＰＤに接続できるワイヤＷＡの本数を増やすことができ、また、パッド電極ＰＤの長辺方向の寸法も抑制できる。第１の変形例では、ワイヤＷＡの接続領域ＲＧＷとプローブ痕ＰＲＢとが重なりをより的確に抑制または防止しながら、パッド電極ＰＤ（ここではドレインパッドＰＤＤ３）に接続できるワイヤＷＡの本数を増やすことで、ワイヤＷＡによる抵抗成分を効率的に低減し、電力損失を効率的に低減することができ、また、パッド電極ＰＤの長辺方向の寸法も抑制することで、半導体チップＣＰ１のチップサイズの縮小も可能になる。 On the other hand, as shown in FIG. 43, in the pad electrode PD (here, the drain pad PDD3), the interval P5 between the connection regions RGW of the wires WA between which the probe traces PRB are arranged is arranged, and the probe trace PRB is arranged therebetween. When the distance P6 between the connection areas RGW of the unwired wires WA is larger (P5> P6), the following advantages can be obtained. That is, if the interval P5 is too small, the connection region RGW of the wire WA and the probe mark PRB overlap with each other, and the connection strength of the wire WA tends to decrease. Even if the interval P6 is reduced, the connection region RGW of the wire WA and the probe mark PRB do not overlap with each other, and the connection strength of the wire WA does not decrease. However, if the interval P6 is increased, the pad electrode PD ( Here, the number of wires WA that can be connected to the drain pad PDD3) decreases, or the size of the pad electrode PD (here, the drain pad PDD3) in the long side direction (here, the X direction) increases. For this reason, by making the interval P5 larger than the interval P6 (P5> P6), the connection region RGW of the wire WA and the probe trace PRB are more accurately suppressed or prevented and the connection strength of the wire WA is improved. In addition, by making the interval P6 smaller than the interval P5 (P5> P6), the number of wires WA that can be connected to the pad electrode PD can be increased, and the dimension of the pad electrode PD in the long side direction can also be increased. Can be suppressed. In the first modified example, the number of wires WA that can be connected to the pad electrode PD (here, the drain pad PDD3) is increased while the overlapping of the connection region RGW of the wire WA and the probe mark PRB is more accurately suppressed or prevented. Thus, the resistance component due to the wire WA can be efficiently reduced, the power loss can be efficiently reduced, and the size of the pad electrode PD in the long side direction is also suppressed, so that the chip size of the semiconductor chip CP1 can be reduced. Reduction is also possible.
　＜第２の変形例について＞
　図４４～図４６は、第２の変形例の説明図であり、上記図５、図１４および図１５にそれぞれ対応するものである。図４４には、半導体チップＣＰ１の代わりに第２変形例の半導体チップＣＰ１ａを用いた電力増幅モジュールＰＡ１の平面透視図であり、封止樹脂１３を透視した状態が示されている。図４５は、図４４の部分拡大平面図であり、配線基板１１に搭載された半導体チップＣＰ１ａとその周辺領域が拡大して示してある。図４６は、図４５からワイヤＷＡおよび基板側端子ＴＥを省略した平面図であり、半導体チップＣＰ１ａの平面図（平面レイアウト図）に対応している。 <About the second modification>
44 to 46 are explanatory diagrams of the second modification, and correspond to FIGS. 5, 14 and 15, respectively. FIG. 44 is a plan perspective view of the power amplification module PA1 using the semiconductor chip CP1a of the second modified example instead of the semiconductor chip CP1, and shows a state where the sealing resin 13 is seen through. FIG. 45 is a partially enlarged plan view of FIG. 44, in which the semiconductor chip CP1a mounted on the wiring board 11 and its peripheral region are enlarged. FIG. 46 is a plan view in which the wires WA and the substrate-side terminals TE are omitted from FIG. 45, and corresponds to a plan view (planar layout diagram) of the semiconductor chip CP1a.
　上記半導体チップＣＰ１は、２系統の電力増幅回路ＬＤＭＬ，ＬＤＭＨを有していたが、第２変形例の半導体チップＣＰ１ａは、２系統の電力増幅回路ＬＤＭＬ，ＬＤＭＨに加えて更に２系統の電力増幅回路が追加されており、合計で４系統の電力増幅回路を有している。すなわち、半導体チップＣＰ１ａは、４つの周波数帯にそれぞれ対応する４系統電力増幅回路を有しており、半導体チップＣＰ１ａを用いた図４４の電力増幅モジュールＰＡ１は、４つの周波数帯にそれぞれ対応する４系統電力増幅回路を有する電力増幅モジュールである。 The semiconductor chip CP1 has two systems of power amplification circuits LDML and LDMH. However, the semiconductor chip CP1a of the second modified example has two systems of power amplification in addition to the two systems of power amplification circuits LDML and LDMH. A circuit is added, and a total of four power amplifier circuits are provided. That is, the semiconductor chip CP1a has four-system power amplifier circuits corresponding to the four frequency bands, and the power amplifier module PA1 of FIG. 44 using the semiconductor chip CP1a corresponds to the four frequency bands. A power amplifier module having a system power amplifier circuit.
　このため、半導体チップＣＰ１ａは、図４５および図４６に示されるように、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＬ３，ＲＥＧＨ１，ＲＥＧＨ２，ＲＥＧＨ３に加えて、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＭ１，ＲＥＧＭ２，ＲＥＧＮ１，ＲＥＧＮ２も有している。ここで、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＬ３にそれぞれ形成されたＬＤＭＯＳＦＥＴにより、１系統目の電力増幅回路ＬＤＭＬが形成され、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＨ１，ＲＥＧＨ２，ＲＥＧＨ３にそれぞれ形成されたＬＤＭＯＳＦＥＴにより、２系統目の電力増幅回路ＬＤＭＨが形成される点は、半導体チップＣＰ１ａも上記半導体チップＣＰ１と同様である。そして、半導体チップＣＰ１ａでは、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＭ１に形成されたＬＤＭＯＳＦＥＴにより構成される初段の増幅段と、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＭ２に形成されたＬＤＭＯＳＦＥＴにより構成される２段目の増幅段とが接続されて３系統目の電力増幅回路が形成されている。更に、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＮ１に形成されたＬＤＭＯＳＦＥＴにより構成される初段の増幅段と、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＮ２に形成されたＬＤＭＯＳＦＥＴにより構成される２段目の増幅段とが接続されて４系統目の電力増幅回路が形成されている。 Therefore, as shown in FIGS. 45 and 46, the semiconductor chip CP1a has LDMOSFET formation regions REGM1, REGM2, REGN1, and REGN2 in addition to the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, and REGH3. ing. Here, the first power amplifier circuit LDML is formed by the LDMOSFETs formed in the LDMOSFET formation regions REGL1, REGL2, and REGL3, respectively, and the second system is formed by the LDMOSFETs formed in the LDMOSFET formation regions REGH1, REGH2, and REGH3, respectively. The semiconductor chip CP1a is the same as the semiconductor chip CP1 in that the power amplifier circuit LDMH is formed. In the semiconductor chip CP1a, the first amplification stage constituted by the LDMOSFET formed in the LDMOSFET formation region REGM1 and the second amplification stage constituted by the LDMOSFET formed in the LDMOSFET formation region REGM2 are connected. A third system power amplifier circuit is formed. Furthermore, the first stage amplification stage configured by the LDMOSFET formed in the LDMOSFET formation region REGN1 and the second stage amplification stage configured by the LDMOSFET formed in the LDMOSFET formation region REGN2 are connected, and the fourth system power is connected. An amplifier circuit is formed.
　このため、半導体チップＣＰ１ａは、パッド電極ＰＤとして、ドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３，ＰＤＤ４，ＰＤＤ５，ＰＤＤ６およびゲートパッドＰＤＧ１，ＰＤＧ２，ＰＤＧ３，ＰＤＧ４，ＰＤＧ５，ＰＤＧ６に加えて、更に、ドレインパッドＰＤＤ７，ＰＤＤ８，ＰＤＤ９，ＰＤＤ１０およびゲートパッドＰＤＧ７，ＰＤＧ８，ＰＤＧ９，ＰＤＧ１０も有している。ここで、ゲートパッドＰＤＧ７は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＭ１のゲート電極に電気的に接続された入力用のパッド電極であり、ドレインパッドＰＤＤ７は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＭ１のドレインに電気的に接続された出力用のパッド電極である。また、ここで、ゲートパッドＰＤＧ８は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＭ２のゲート電極に電気的に接続された入力用のパッド電極であり、ドレインパッドＰＤＤ８は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＭ２のドレインに電気的に接続された出力用のパッド電極である。また、ゲートパッドＰＤＧ９は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＮ１のゲート電極に電気的に接続された入力用のパッド電極であり、ドレインパッドＰＤＤ９は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＮ１のドレインに電気的に接続された出力用のパッド電極である。また、ゲートパッドＰＤＧ１０は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＮ２のゲート電極に電気的に接続された入力用のパッド電極であり、ドレインパッドＰＤＤ１０は、ＬＤＭＯＳＦＥＴ形成領域ＲＥＧＮ２のドレインに電気的に接続された出力用のパッド電極である。 Therefore, the semiconductor chip CP1a has, as the pad electrode PD, in addition to the drain pads PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 and the gate pads PDG1, PDG2, PDG3, PDG4, PDG5, PDG6, and further drain pads PDD7, PDD8, PDD9, PDD10 and gate pads PDG7, PDG8, PDG9, PDG10 are also provided. Here, the gate pad PDG7 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGM1, and the drain pad PDD7 is an output pad electrically connected to the drain of the LDMOSFET formation region REGM1. The pad electrode. Here, the gate pad PDG8 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGM2, and the drain pad PDD8 is electrically connected to the drain of the LDMOSFET formation region REGM2. This is a pad electrode for output. The gate pad PDG9 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGN1, and the drain pad PDD9 is an output pad electrically connected to the drain of the LDMOSFET formation region REGN1. It is a pad electrode. The gate pad PDG10 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGN2, and the drain pad PDD10 is an output pad electrically connected to the drain of the LDMOSFET formation region REGN2. It is a pad electrode.
　半導体チップＣＰ１の代わりに、半導体チップＣＰ１ａを用いた場合には、ドレインパッドＰＤＤ１，ＰＤＤ２，ＰＤＤ３，ＰＤＤ４，ＰＤＤ５，ＰＤＤ６だけでなく、ドレインパッドＰＤＤ７，ＰＤＤ８，ＰＤＤ９，ＰＤＤ１０のうちの１つ以上に対しても、図２９～図３２および図３９を参照して説明したパッド電極、ワイヤＷＡの接続領域ＲＧＷおよびプローブ痕ＰＲＢの関係を適用することができる。すなわち、図４４～図４６では、ドレインパッドＰＤＤ７に複数のワイヤＷＡを接続しているが、上記図３９または図４３のドレインパッドＰＤＤ３と同様に、ドレインパッドＰＤＤ７においても、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査工程においてプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させることができる。また、図４４～図４６では、ドレインパッドＰＤＤ８に複数のワイヤＷＡを接続しているが、上記図３９または図４３のドレインパッドＰＤＤ３と同様に、ドレインパッドＰＤＤ８においても、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査工程においてプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させることができる。図４４～図４６では、ドレインパッドＰＤＤ９に複数のワイヤＷＡを接続しているが、上記図３９または図４３のドレインパッドＰＤＤ３と同様に、ドレインパッドＰＤＤ９においても、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査工程においてプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させることができる。また、図４４～図４６では、ドレインパッドＰＤＤ１０に複数のワイヤＷＡを接続しているが、上記図３９または図４３のドレインパッドＰＤＤ３と同様に、ドレインパッドＰＤＤ７においても、複数のワイヤＷＡの接続領域ＲＧＷの間に、プローブ検査工程においてプローブを押し当てた領域（すなわちプローブ痕ＰＲＢ）を位置させることができる。 When the semiconductor chip CP1a is used instead of the semiconductor chip CP1, not only the drain pads PDD1, PDD2, PDD3, PDD4, PDD5 and PDD6 but also one or more of the drain pads PDD7, PDD8, PDD9 and PDD10. The relationship between the pad electrode, the connection region RGW of the wire WA, and the probe mark PRB described with reference to FIGS. 29 to 32 and 39 can also be applied. That is, in FIG. 44 to FIG. 46, a plurality of wires WA are connected to the drain pad PDD7. However, similarly to the drain pad PDD3 in FIG. A region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned between the regions RGW. 44 to 46, a plurality of wires WA are connected to the drain pad PDD8. Similarly to the drain pad PDD3 in FIG. 39 or FIG. 43, a plurality of wires WA are connected to the drain pad PDD8. A region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned between the regions RGW. 44 to 46, a plurality of wires WA are connected to the drain pad PDD9. However, similarly to the drain pad PDD3 in FIG. 39 or 43, the drain pad PDD9 also has a connection region RGW of the plurality of wires WA. In the meantime, the region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned. 44 to 46, a plurality of wires WA are connected to the drain pad PDD10. However, similarly to the drain pad PDD3 in FIG. 39 or 43, a plurality of wires WA are connected to the drain pad PDD7. A region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned between the regions RGW.
　また、本実施の形態では、本発明の好適な適用例として電力増幅モジュールを例に挙げて説明したが、増幅素子を有する半導体チップのパッド電極にワイヤを接続した種々の半導体装置およびその製造方法に適用することができる。 Further, in the present embodiment, the power amplification module has been described as a preferred application example of the present invention. However, various semiconductor devices in which wires are connected to pad electrodes of a semiconductor chip having an amplification element, and manufacturing methods thereof Can be applied to.
　以上、本発明者によってなされた発明をその実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
　本発明は、半導体装置およびその製造技術に適用して有効である。 The present invention is effective when applied to a semiconductor device and its manufacturing technology.
１１　配線基板
１１ａ　上面
１１ｂ　下面
１２　受動部品
１３　封止樹脂
１４　絶縁体層
１５　導体層
１５ａ　外部接続用端子
１５ｂ　基準電位供給用端子
１５ｃ　チップ搭載用導体パターン
１６，１６ａ　ビアホール
１８　半田
２１　実装基板
２１ａ　上面
２２　部品
２３ａ，２３ｂ，２３ｃ　端子
２４　半田
２５　配線基板母体
２５ａ　上面
３１　基板（半導体基板）
３１ａ　基板本体
３１ｂ　エピタキシャル層
３２　素子分離領域
３３　ｐ型ウエル
３４　ゲート絶縁膜
３５　ゲート電極
３６　サイドウォールスペーサ
３７　　第１のｎ－型ドレイン領域
３８　　第２のｎ－型ドレイン領域
３９　ｎ＋型ドレイン領域
４０　ｎ－型ソース領域
４１　ｎ＋型ソース領域
４４　ｐ型打抜き層
４５　ｐ＋型半導体領域
４６　絶縁膜
４７　コンタクトホール
４８　プラグ
４９　絶縁膜
５０　スルーホール
５２　絶縁膜
５３　開口部
５３Ｄ　ドレインパッド用開口部
５３Ｇ　ゲートパッド用開口部
５４　ソース裏面電極
５５，５６，５７　領域
５８　プローブ
６０　単位セル
６０ａ　単位ＬＤＭＯＳＦＥＴ
１０２ＡＭ１，１０２ＡＭ２，１０２ＢＭ１，１０２ＢＭ２　整合回路
１０３　周辺回路
１０３Ａ　制御回路
１０３Ａ１　電源制御回路
１０３Ａ２　バイアス電圧生成回路
１０３Ｂ　バイアス回路
１０３Ｃ　制御回路
１０４ａ，１０４ｂ，１０４ｃ　入力端子
１０５Ａ，１０５Ｂ　整合回路
１０６　端子
１０７Ａ，１０７Ｂ　整合回路
１０８Ａ，１０８Ｂ　ローパスフィルタ
１０９Ａ，１０９Ｂ　スイッチ回路
１１０ａ，１１０ｂ　端子
１５３Ｄ　ドレインパッド用開口部
１５３Ｇ　ゲートパッド用開口部
ＡＧＣＡＭＰ　ＡＧＣアンプ
ＡＮＴ　アンテナ
ＡＮＴ－ＳＷ　アンテナスイッチ
ＡＲ１　活性領域
ＢＢＰ　ベースバンド部
ＢＥ１　裏面電極
ＣＤＰ　表示・制御部
ＣＯＤ１　音声ＣＯＤＥＣ
ＣＯＤ２　チャネルＣＯＤＥＣ
ＣＰ１　半導体チップ
ＣＰ１０１　半導体チップ
ＣＰ１ａ　半導体チップ
ＤＡＣ　Ｄ／Ａ変換回路
ＤＭＤＬ　復調回路
ＤＰＳ　デジタル携帯電話機
ＦＰＬ１　ＲＦ－ＰＬＬ（ＲＦ周波数位相同期回路）
ＦＰＬ２　ＩＦ－ＰＬＬ（ＩＦ周波数位相同期回路）
ＩＦＣ　ＩＦ回路
ＬＣＤ　液晶表示部
ＬＤＭＨ　電力増幅回路
ＬＤＭＨ１，ＬＤＭＨ２，ＬＤＭＨ３　増幅段
ＬＤＭＬ　電力増幅回路
ＬＤＭＬ１，ＬＤＭＬ２，ＬＤＭＬ３　増幅段
ＬＮＡ　低雑音アンプ
Ｍ１　配線
Ｍ１Ｄ　ドレイン配線
Ｍ１Ｇ　ゲート配線
Ｍ１Ｓ　ソース配線
Ｍ２　配線
Ｍ２Ｄ　ドレイン配線
Ｍ２Ｄ１　配線部
Ｍ２Ｄ１０１　ドレイン配線
Ｍ２Ｄ２　連結配線部
Ｍ２Ｇ　ゲート配線
Ｍ２Ｇ１０１　ゲート配線
Ｍ２Ｓ　ソース配線
ＭＣＮ　マイコン
ＭＤＬ　変調回路
ＭＩＣ　マイク
ＭＲＹ　メモリ
Ｐ５，Ｐ６　間隔
ＰＡ１　電力増幅モジュール
ＰＤ，ＰＤ１　パッド電極
ＰＤＤ１，ＰＤＤ２，ＰＤＤ３，ＰＤＤ４，ＰＤＤ５，ＰＤＤ６　ドレインパッド
ＰＤＤ７，ＰＤＤ８，ＰＤＤ９，ＰＤＤ１０　ドレインパッド
ＰＤＤ１０１，ＰＤＤ１０３，ＰＤＤ２０３　ドレインパッド
ＰＤＧ１，ＰＤＧ２，ＰＤＧ３，ＰＤＧ４，ＰＤＧ５，ＰＤＧ６　ゲートパッド
ＰＤＧ７，ＰＤＧ８，ＰＤＧ９，ＰＤＧ１０，ＰＤＧ１０１　ゲートパッド
ＰＲＢ，ＰＲＢ１０１，ＰＲＢ２０１　プローブ痕
ＱＭＤ　直交変調器
ＲＥＧＨ１，ＲＥＧＨ２，ＲＥＧＨ３，ＲＥＧＬ１０１　ＬＤＭＯＳＦＥＴ形成領域
ＲＥＧＬ１，ＲＥＧＬ２，ＲＥＧＬ３，ＲＥＧＬ１０３　ＬＤＭＯＳＦＥＴ形成領域
ＲＥＧＭ１，ＲＥＧＭ２，ＲＥＧＮ１，ＲＥＧＮ２　ＬＤＭＯＳＦＥＴ形成領域
ＲＦＢＰ　ＲＦブロック部
ＲＧＷ　接続領域
ＲＧＷ１０１　接続領域
ＲＧＷ２０１　接続領域
ＲＸ－ＭＩＸ　受信ミクサ
ＳＤ１，ＳＤ２，ＳＤ３，ＳＤ４　辺（チップ辺）
ＳＰ　スピーカ
ＴＥ　基板側端子
ＴＥ　端子
ＴＸ－ＭＩＸ　送信ミクサ
ＷＡ，ＷＡ１０１　ワイヤ 11 Wiring board 11a Upper surface 11b Lower surface 12 Passive component 13 Sealing resin 14 Insulator layer 15 Conductor layer 15a External connection terminal 15b Reference potential supply terminal 15c Chip mounting conductor pattern 16, 16a Via hole 18 Solder 21 Mounting substrate 21a Upper surface 22 Components 23a, 23b, 23c Terminal 24 Solder 25 Wiring board base 25a Upper surface 31 Substrate (semiconductor substrate)
31a Substrate body 31b Epitaxial layer 32 Element isolation region 33 P type well 34 Gate insulating film 35 Gate electrode 36 Side wall spacer 37 First n − type drain region 38 Second n − type drain region 39 n + type drain region 40 n − type source region 41 n + type source region 44 p type punching layer 45 p + type semiconductor region 46 insulating film 47 contact hole 48 plug 49 insulating film 50 through hole 52 insulating film 53 opening 53D drain pad opening 53G gate Pad opening 54 Source back electrode 55, 56, 57 Region 58 Probe 60 Unit cell 60a Unit LDMOSFET
102AM1, 102AM2, 102BM1, 102BM2 Matching circuit 103 Peripheral circuit 103A Control circuit 103A1 Power supply control circuit 103A2 Bias voltage generation circuit 103B Bias circuit 103C Control circuit 104a, 104b, 104c Input terminal 105A, 105B Matching circuit 106 Terminal 107A, 107B Matching circuit 108A , 108B Low pass filter 109A, 109B Switch circuit 110a, 110b Terminal 153D Drain pad opening 153G Gate pad opening AGCAMP AGC amplifier ANT Antenna ANT-SW Antenna switch AR1 Active area BBP Baseband part BE1 Back electrode CDP Display / control part COD1 voice CODEC
COD2 channel CODEC
CP1 Semiconductor chip CP101 Semiconductor chip CP1a Semiconductor chip DAC D / A conversion circuit DMDL Demodulation circuit DPS Digital mobile phone FPL1 RF-PLL (RF frequency phase synchronization circuit)
FPL2 IF-PLL (IF frequency phase synchronization circuit)
IFC IF circuit LCD Liquid crystal display portion LDMH Power amplifier circuit LDMH1, LDMH2, LDMH3 Amplifier stage LDML Power amplifier circuit LDML1, LDML2, LDML3 Amplifier stage LNA Low noise amplifier M1 Wiring M1D Drain wiring M1G Gate wiring M1S Source wiring M2 Wiring M2D1 Drain wiring M2D1 Wiring part M2D101 Drain wiring M2D2 Connection wiring part M2G Gate wiring M2G101 Gate wiring M2S Source wiring MCN Microcomputer MDL Modulation circuit MIC Microphone MRY Memory P5, P6 Spacing PA1 Power amplification module PD, PD1 Pad electrodes PDD1, PDD2, PDD3, PDD4, PDD5 PDD6 Drain pad PDD7, PDD8, PDD9, PDD10 Drain pad PDD101, PDD103, PDD203 Drain Pads PDG1, PDG2, PDG3, PDG4, PDG5, PDG6 Gate pads PDG7, PDG8, PDG9, PDG10, PDG101 Gate pads PRB, PRB101, PRB201 Probe trace QMD Quadrature modulators REGH1, REGH2, REGH3, REGL101 LDMOSFET formation regions REGL1, REGL2, REGL3, REGL103 LDMOSFET formation region REGM1, REGM2, REGN1, REGN2 LDMOSFET formation region RFBP RF block part RGW Connection region RGW101 Connection region RGW201 Connection region RX-MIX Reception mixer SD1, SD2, SD3, SD4 side (chip side)
SP Speaker TE Board side terminal TE Terminal TX-MIX Transmission mixer WA, WA101 Wire

Claims (20)

  1. 　複数のパッド電極を有する半導体チップを備え、前記複数のパッド電極に複数のワイヤが接続された半導体装置であって、
    　前記半導体チップは、第１電力増幅回路を有しており、
    　前記複数のパッド電極は、前記第１電力増幅回路を構成する半導体素子の出力に接続された第１パッド電極を含み、
    　前記第１パッド電極に、前記複数のワイヤのうちの複数の第１ワイヤが接続されており、
    　前記第１パッド電極において、前記複数の第１ワイヤの接続領域の間に、プローブ痕が形成されていることを特徴とする半導体装置。     A semiconductor device comprising a semiconductor chip having a plurality of pad electrodes, wherein a plurality of wires are connected to the plurality of pad electrodes,
    The semiconductor chip has a first power amplifier circuit,
    The plurality of pad electrodes include a first pad electrode connected to an output of a semiconductor element constituting the first power amplifier circuit,
    A plurality of first wires of the plurality of wires are connected to the first pad electrode,
    In the first pad electrode, a probe mark is formed between connection regions of the plurality of first wires.
  2. 　請求項１記載の半導体装置において、
    　前記第１パッド電極における前記複数の第１ワイヤの接続領域は、一列に配列していることを特徴とする半導体装置。     The semiconductor device according to claim 1,
    A connection region of the plurality of first wires in the first pad electrode is arranged in a line.
  3. 　請求項２記載の半導体装置において、
    　前記プローブ痕は、プローブ検査でプローブが当たることにより形成されていることを特徴とする半導体装置。     The semiconductor device according to claim 2,
    2. The semiconductor device according to claim 1, wherein the probe mark is formed when the probe hits the probe.
  4. 　請求項３記載の半導体装置において、
    　前記第１パッド電極は、長方形状の平面形状を有し、
    　前記第１パッド電極における前記複数の第１ワイヤの接続領域は、前記第１パッド電極の長辺方向に沿って一列に配列していることを特徴とする半導体装置。     The semiconductor device according to claim 3.
    The first pad electrode has a rectangular planar shape,
    The connection region of the plurality of first wires in the first pad electrode is arranged in a line along the long side direction of the first pad electrode.
  5. 　請求項４記載の半導体装置において、
    　前記第１パッド電極において、前記プローブ痕は、前記複数の第１ワイヤの接続領域と重なっていないことを特徴とする半導体装置。     The semiconductor device according to claim 4.
    In the first pad electrode, the probe mark does not overlap a connection region of the plurality of first wires.
  6. 　請求項５記載の半導体装置において、
    　前記半導体チップは、多段接続された複数の電力増幅回路を有しており、
    　前記第１電力増幅回路は、前記複数の電力増幅回路のうちの最終段の電力増幅回路であることを特徴とする半導体装置。     The semiconductor device according to claim 5.
    The semiconductor chip has a plurality of power amplifier circuits connected in multiple stages,
    The semiconductor device according to claim 1, wherein the first power amplifier circuit is a power amplifier circuit at a final stage of the plurality of power amplifier circuits.
  7. 　請求項１乃至６の何れか１項記載の半導体装置において、
    　前記半導体素子は、ＬＤＭＯＳＦＥＴであり、
    　前記第１パッド電極は、前記ＬＤＭＯＳＦＥＴのドレイン用パッド電極であることを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 6,
    The semiconductor element is an LDMOSFET,
    The semiconductor device according to claim 1, wherein the first pad electrode is a drain pad electrode of the LDMOSFET.
  8. 　請求項７記載の半導体装置において、
    　前記第１パッド電極に前記第１ワイヤは３本以上接続され、かつ等間隔で接続されていることを特徴とする半導体装置。     The semiconductor device according to claim 7.
    Three or more first wires are connected to the first pad electrode, and are connected at equal intervals.
  9. 　請求項８記載の半導体装置において、
    　前記第１パッド電極における前記複数の第１ワイヤの接続領域の間の領域には、前記プローブ痕が配置されている領域と、前記プローブ痕が配置されていない領域とが混在していることを特徴とする半導体装置。     The semiconductor device according to claim 8.
    In the region between the connection regions of the plurality of first wires in the first pad electrode, a region where the probe mark is arranged and a region where the probe mark is not arranged are mixed. A featured semiconductor device.
  10. 　請求項１記載の半導体装置において、
    　前記第１パッド電極に前記第１ワイヤは３本以上接続されており、
    　前記第１パッド電極における前記複数の第１ワイヤの接続領域の間の領域には、前記プローブ痕が配置されている領域と、前記プローブ痕が配置されていない領域とが混在しており、
    　前記第１パッド電極において、間に前記プローブ痕が配置されている前記接続領域の間隔は、間に前記プローブ痕が配置されていない前記接続領域の間隔よりも大きいことを特徴とする半導体装置。     The semiconductor device according to claim 1,
    Three or more first wires are connected to the first pad electrode,
    In the region between the connection regions of the plurality of first wires in the first pad electrode, a region where the probe mark is arranged and a region where the probe mark is not arranged are mixed,
    In the first pad electrode, the interval between the connection regions in which the probe marks are arranged is larger than the interval between the connection regions in which the probe marks are not arranged.
  11. 　（ａ）半導体チップを準備する工程、
    　（ｂ）前記半導体チップを配線基板上に搭載する工程、
    　（ｃ）前記半導体チップの複数のパッド電極と前記配線基板の複数の端子とを複数のワイヤを介して電気的に接続する工程、
    　を有する半導体装置の製造方法であって、
    　前記半導体チップは、第１電力増幅回路を有しており、
    　前記複数のパッド電極は、前記第１電力増幅回路を構成する半導体素子の出力に接続された第１パッド電極を含み、
    　前記（ｃ）工程では、前記第１パッド電極に、前記複数のワイヤのうちの複数の第１ワイヤが接続され、
    　前記（ａ）工程は、
    　（ａ１）前記半導体基板に対してプローブ検査を行う工程、
    　（ａ２）前記（ａ１）工程後、前記半導体基板を切断して前記半導体チップを取得する工程、
    　を有し、
    　前記第１パッド電極において、前記（ａ１）工程でプローブが当てられる位置は、前記（ｃ）工程で前記複数の第１ワイヤを接続する位置の間に位置することを特徴とする半導体装置の製造方法。     (A) a step of preparing a semiconductor chip;
    (B) mounting the semiconductor chip on a wiring board;
    (C) electrically connecting a plurality of pad electrodes of the semiconductor chip and a plurality of terminals of the wiring board via a plurality of wires;
    A method of manufacturing a semiconductor device having
    The semiconductor chip has a first power amplifier circuit,
    The plurality of pad electrodes include a first pad electrode connected to an output of a semiconductor element constituting the first power amplifier circuit,
    In the step (c), a plurality of first wires of the plurality of wires are connected to the first pad electrode,
    The step (a)
    (A1) performing a probe inspection on the semiconductor substrate;
    (A2) after the step (a1), cutting the semiconductor substrate to obtain the semiconductor chip;
    Have
    In the first pad electrode, the position where the probe is applied in the step (a1) is located between the positions where the plurality of first wires are connected in the step (c). Method.
  12. 　請求項１１記載の半導体装置の製造方法において、
    　前記第１パッド電極において、前記（ｃ）工程で前記複数の第１ワイヤを接続する位置は、一列に配列していることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 11.
    In the first pad electrode, the positions where the plurality of first wires are connected in the step (c) are arranged in a line.
  13. 　請求項１２記載の半導体装置の製造方法において、
    　前記第１パッド電極は、長方形状の平面形状を有し、
    　前記第１パッド電極において、前記（ｃ）工程で前記複数の第１ワイヤを接続する位置は、前記第１パッド電極の長辺方向に沿って一列に配列していることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 12,
    The first pad electrode has a rectangular planar shape,
    In the first pad electrode, the positions where the plurality of first wires are connected in the step (c) are arranged in a line along the long side direction of the first pad electrode. Manufacturing method.
  14. 　請求項１３記載の半導体装置の製造方法において、
    　前記（ａ１）工程で前記第１パッド電極にプローブ痕が形成されることを特徴とする半導体装置の製造方法。     14. The method of manufacturing a semiconductor device according to claim 13,
    A method of manufacturing a semiconductor device, wherein a probe mark is formed on the first pad electrode in the step (a1).
  15. 　請求項１４記載の半導体装置の製造方法において、
    　前記（ｃ）工程では、前記第１パッド電極において、前記プローブ痕に重ならない位置に、前記複数の第１ワイヤが接続されることを特徴とする半導体装置の製造方法。     15. The method of manufacturing a semiconductor device according to claim 14,
    In the step (c), in the first pad electrode, the plurality of first wires are connected to positions that do not overlap the probe marks.
  16. 　請求項１５記載の半導体装置の製造方法において、
    　前記半導体チップは、多段接続された複数の電力増幅回路を有しており、
    　前記第１電力増幅回路は、前記複数の電力増幅回路のうちの最終段の電力増幅回路であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 15,
    The semiconductor chip has a plurality of power amplifier circuits connected in multiple stages,
    The method of manufacturing a semiconductor device, wherein the first power amplifier circuit is a power amplifier circuit at a final stage of the plurality of power amplifier circuits.
  17. 　請求項１１乃至１６の何れか１項記載の半導体装置の製造方法において、
    　前記半導体素子は、ＬＤＭＯＳＦＥＴであり、前記第１パッド電極は、前記ＬＤＭＯＳＦＥＴのドレイン用パッド電極であることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 11,
    The method of manufacturing a semiconductor device, wherein the semiconductor element is an LDMOSFET, and the first pad electrode is a drain pad electrode of the LDMOSFET.
  18. 　請求項１７記載の半導体装置の製造方法において、
    　前記（ｃ）工程では、前記第１パッド電極に前記第１ワイヤは３本以上接続され、かつ、等間隔で接続されることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 17.
    In the step (c), at least three of the first wires are connected to the first pad electrode and are connected at equal intervals.
  19. 　請求項１１記載の半導体装置の製造方法において、
    　前記（ｃ）工程では、前記第１パッド電極に前記第１ワイヤは３本以上接続され、
    　前記第１パッド電極における前記複数の第１ワイヤの接続領域の間の領域には、前記プローブ痕が配置されている領域と、前記プローブ痕が配置されていない領域とが混在し、
    　前記第１パッド電極において、間に前記プローブ痕が配置されている前記接続領域の間隔は、間に前記プローブ痕が配置されていない前記接続領域の間隔よりも大きいことを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 11.
    In the step (c), three or more first wires are connected to the first pad electrode,
    In the region between the connection regions of the plurality of first wires in the first pad electrode, a region where the probe mark is arranged and a region where the probe mark is not arranged are mixed,
    In the first pad electrode, the interval between the connection regions in which the probe marks are disposed is larger than the interval between the connection regions in which the probe marks are not disposed. Production method.
  20. 　第１主面を有する配線基板と、
    　第２主面と、前記第２主面とは反対側の第１裏面とを有し、前記第１裏面が前記配線基板の前記第１主面と対向するように前記配線基板の前記第１主面に搭載された半導体チップと、
    　前記半導体チップの前記第２主面に形成された複数のパッド電極と前記配線基板の前記第１主面に形成された複数の端子とを電気的に接続する複数のワイヤと、
    　を備えた半導体装置であって、
    　前記半導体チップは、第１電力増幅回路を有しており、
    　前記複数のパッド電極は、前記第１電力増幅回路を構成する半導体素子の出力に接続された第１パッド電極を含み、
    　前記第１パッド電極に、前記複数のワイヤのうちの複数の第１ワイヤが接続されており、
    　前記第１パッド電極において、前記複数の第１ワイヤの接続領域の間に、プローブ痕が形成されていることを特徴とする半導体装置。     A wiring board having a first main surface;
    The wiring board has a second main surface and a first back surface opposite to the second main surface, and the first back surface of the wiring board is opposed to the first main surface of the wiring board. A semiconductor chip mounted on the main surface;
    A plurality of wires that electrically connect a plurality of pad electrodes formed on the second main surface of the semiconductor chip and a plurality of terminals formed on the first main surface of the wiring board;
    A semiconductor device comprising:
    The semiconductor chip has a first power amplifier circuit,
    The plurality of pad electrodes include a first pad electrode connected to an output of a semiconductor element constituting the first power amplifier circuit,
    A plurality of first wires of the plurality of wires are connected to the first pad electrode,
    In the first pad electrode, a probe mark is formed between connection regions of the plurality of first wires.
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