JP2006310425A - Electronic apparatus and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sealed RF module which constitutes a transmission line with a lead frame without deteriorating the high frequency characteristics. <P>SOLUTION: The module has a semiconductor amplifier element chip 3 containing a power amplifier circuit, upper layer leads 4a forming a signal transmission line, lower layer leads 4b forming a reference potential conductor pattern, a plurality of conductive wires 6 for electrically connecting the upper layer leads 4a with the lower layer leads 4b, and a seal 7 for sealing them. For each of the upper and lower layer leads 4a, 4b, two different lead frames are laminated one above the other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic device and a manufacturing technique thereof, and more particularly, to a technique effective when applied to an RF (Radio Frequency) module and a manufacturing technique thereof.

  In recent years, mobile communication devices represented by communication systems such as GSM (Global System for Mobile Communications) system, PCS (Personal Communication Systems) system, PDC (Personal Digital Cellular) system, and CDMA (Code Division Multiple Access) system (for example, mobile phones) Phone) is widespread worldwide.

  In general, this type of mobile communication device includes an antenna that emits and receives radio waves, an electronic device that is an RF module (RF power module, high-frequency power amplifier) that amplifies a power-modulated high-frequency signal and supplies the signal to the antenna, The receiving unit is configured to process a high-frequency signal received by an antenna, a control unit that controls these, and a battery (battery) that supplies a power supply voltage thereto.

  Patent Documents 1 to 3 describe a technique for mounting a semiconductor chip on a lead frame having a transmission line.

Patent Document 4 discloses a resin-encapsulated structure in which a lead electrically connected to a signal terminal of a semiconductor chip and a plate-like conductor electrically connected to a power supply terminal of the semiconductor chip have a parallel two-layer structure. The technology to stop is described.
US Pat. No. 6,621,140 US Pat. No. 6,608,367 US Pat. No. 6,765,284 JP-A-6-188352

  In recent years, along with demands for downsizing, thinning, and cost reduction of mobile communication devices, RF (Radio Frequency) modules mounted thereon are also required to be downsized, thinned, and low in cost.

  A general RF module has a structure in which electronic components such as a semiconductor chip, a passive element, and a passive component are mounted on a laminated substrate in which a transmission line is configured by a conductive pattern, for example. For example, a PCB (Printed Circuit Board), a ceramic substrate, or the like is used as the laminated substrate of the RF module. In addition to the signal wiring layer, these substrates are formed by forming a power supply wiring layer and a reference potential wiring layer as a large area plane pattern (plane) in a layer different from the signal wiring layer, and interconnecting layers between the via holes ( Via hole). However, a ceramic substrate, for example, requires ceramic lamination, metallization and ceramic simultaneous firing technology, gold (Au) plating, and the like, and its structure is complicated and expensive.

  Further, the RF module is required to suppress signal reflection in the transmission line and transmit power with high efficiency, that is, good high frequency characteristics in a high frequency region. In the present application, “high frequency” refers to a frequency band of about 500 MHz or more.

  Here, in order to transmit electric power with high efficiency, it is necessary to perform impedance matching (matching), and in general, the characteristic impedance is adjusted to 50Ω. This impedance matching can be adjusted in various ways depending on the required frequency band, stripline (transmission line), circuit configuration and members. For example, in an RF module that operates at a high frequency of 900 MHz, for example, the pattern length of a stripline pattern for configuring a transmission line on a substrate cannot be ignored compared to a semiconductor device that operates at, for example, several hundred kHz. That is, for example, in an RF module that operates at a high frequency of 900 MHz, the phase and amplitude of the signal are greatly different only by the position between the transmission lines being different by several centimeters. Thus, for example, it is difficult to adjust impedance matching at a high frequency from 100 kHz to 900 MHz.

  The present inventors formed a sealed RF module such as a quad flat non-leaded package (QFN) equipped with a semiconductor amplifying element chip with a built-in power amplifier circuit, and reduced the cost of an RF module with good high-frequency characteristics. We are studying technologies that can be used.

  In Patent Document 4, in a resin-encapsulated semiconductor device in which a semiconductor element chip that requires an operation at a frequency of several hundred kHz or more is mounted, in order to suppress signal reflection, signal interference, and noise generation, There is a technique of resin-sealing a lead electrically connected to a signal terminal of a semiconductor element chip and a plate-like conductor electrically connected to a power supply terminal of the semiconductor element chip with a parallel two-layer structure. Are listed. However, for example, an RF module operating at a high frequency of 900 MHz is different from a semiconductor device operating at a frequency of several hundred kHz in order to suppress reflection of a signal in a transmission line and transmit power with high efficiency as described above. The method of adjusting impedance matching is different. Also, the transmission line of the RF module is more complicated than the transmission line of a semiconductor device that operates at a frequency of several hundred kHz because impedance matching is performed in a high frequency band of about 900 MHz, for example. Therefore, it is considered that an RF module having good high-frequency characteristics cannot be formed simply by configuring a signal transmission line and a power supply conductive pattern with a two-layer structure.

  Further, Patent Documents 1 to 3 describe a technique related to an RF module in which a transmission line for a signal and a conductive pattern for a power supply are configured by a single-layer lead frame structure. As described above, the present inventors have the following problems in the RF module in which the transmission line for signal and the conductive pattern for power supply constitute a transmission line including a strip line in a single-layer lead frame structure. I found it.

  FIG. 21 schematically shows a state in which the RF module 1 in which the signal transmission line and the power supply conductive pattern are formed by the single-layer structure lead 4 examined by the present inventors is mounted on the mounting substrate (motherboard) 2. It is sectional drawing shown.

  As shown in FIG. 21, the RF module 1 examined by the present inventors is a QFN (Quad Flat Non-leaded package) sealed RF module on which a semiconductor amplifying element chip 3 is mounted. That is, the RF module 1 includes a semiconductor amplifying element chip 3, a lead 4, a die pad portion 5, a conductive wire 6, and a sealing portion 7. The lead 4 has a single-layer structure that constitutes a transmission line for signals and a conductive pattern for power supply, and is processed from a lead frame (conductor layer). The lead 4 has a half-etched portion 8 to prevent a short circuit with the signal wiring layer 9 formed on the mounting substrate 2. The die pad portion 5 is processed from the same lead frame as the lead 4 and has the semiconductor amplification element chip 3 mounted thereon. The conductive wire 6 electrically connects the semiconductor amplification element chip 3 and the lead 4. The sealing part 7 seals a part of the semiconductor amplifying element chip 3, the conductive wire 6 and the lead 4 and is made of a mold resin.

  The mounting board 2 has a signal wiring layer 9 on the main surface of the mounting board 2. The RF module 1 is mounted on the mounting substrate 2 via a bonding material 10 made of, for example, mounting solder. The bonding material 10 is bonded to and electrically connected to an input terminal or an output terminal of the RF module 1 on the RF module 1 side. Further, the bonding material 10 is bonded to and electrically connected to the signal wiring layer 9 on the mounting substrate 2 side. The mounting board 2 has a laminated structure, and has a signal wiring layer (not shown) between the layers of the mounting board 2, and the signal wiring layer (not shown) and the signal wiring on the main surface of the mounting board 2. The layer 9 is electrically connected via a via hole (not shown) formed in the mounting substrate 2.

  As described above, the RF module 1 having the single-layer structure lead 4 investigated by the present inventors also realizes an RF module having good high frequency characteristics (power added efficiency (PAE), power gain (Gp), etc.). Therefore, impedance matching is performed (where power-added efficiency (PAE) is one of indices indicating the efficiency with which DC power supplied to an amplifier is converted into high-frequency power as an output signal) The power gain (Gp) indicates the ratio of the input signal to the output signal supplied to the amplifier, that is, the amplified ratio). That is, the transmission line adjusted so as to suppress signal reflection, signal interference, and noise generation is configured by the single-layer structure lead 4. However, even if the RF module 1 is formed so as to have good high frequency characteristics, when mounted on the mounting substrate 2, problems such as deterioration (instability, oscillation) of the high frequency characteristics of the RF module 1 occur. When mounted on the mounting board 2, the high frequency characteristics of the RF module 1 are deteriorated because of the height variation of the bonding material 10, the transmission line constituted by the leads 4 of the RF module 1, and the signal of the mounting board 2. It is considered that the high frequency characteristics fluctuate when the distance to the wiring layer 9 fluctuates. Further, since the distance between the signal wiring layer 9 of the mounting substrate 2 and the lead 4 constituting the transmission line of the RF module 1 is short, the signal of the signal wiring layer 9 of the mounting substrate 2 passes through the transmission line of the RF module 1. It is also conceivable to affect the constituent leads 4. For this reason, the loss in the RF module 1 increases and the power gain (Gp) decreases.

  An object of the present invention is to provide a technique capable of improving the high-frequency characteristics of a sealed RF module in which a signal transmission line and a reference potential conductive pattern are configured by a plurality of conductor layers.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  An electronic device according to the present invention includes a semiconductor chip on which a power amplifier circuit is formed, and a plurality of conductor layers each including a signal transmission line and a reference potential conductive pattern. The signal transmission line and the reference potential conductive pattern are formed of different conductor layers among the plurality of conductor layers.

  The electronic device manufacturing method according to the present invention includes a semiconductor chip on which a power amplifier circuit is formed, and a plurality of conductor layers each having a signal transmission line and a reference potential conductive pattern. In the method of manufacturing an electronic device, when the plurality of conductor layers are prepared, the signal transmission line and the reference potential conductive pattern are formed of different conductor layers.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The high frequency characteristics of the RF module can be improved by employing a laminated structure of a plurality of conductor layers in which a transmission line for signals is formed in the upper layer and a conductive pattern for reference potential is formed in the lower layer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections. However, unless otherwise specified, they are not irrelevant to each other, and one is a part of the other or All the modifications, details, supplementary explanations, and the like are related.

(Embodiment 1)
An example of an RF (Radio Frequency) module and a mobile communication device using the same shown in this embodiment will be described with reference to FIGS. 1 to 7, and a method for manufacturing the RF module will be described with reference to FIGS. The RF module shown in this embodiment mode includes an RF module (RF power module, high-frequency wave) in which a signal transmission line and a reference potential conductive pattern are two-layered conductor layers composed of an upper layer and a lower layer. Power amplifier, power amplifier module). Further, this RF module is an RF module used for a digital mobile phone (mobile communication device) that transmits information using a network such as a GSM system or a W-CDMA system. This GSM (Global System for Mobile Communication) is one of radio communication systems or standards used for digital mobile phones. GSM has three frequency bands of radio waves to be used: 900 MHz band is GSM900 or simply GSM, 1800 MHz band is GSM1800 or DCS (Digital Cellular System) 1800 or PCN, 1900 MHz band is GSM1900 or DCS1900 or PCS (Personal Communication Services). GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may also be used. The W-CDMA (Wideband Code Division Multiple Access) system is a system that performs communication in a frequency band of 1.92 GHz or higher.

  FIG. 1 is an explanatory diagram showing an example of a digital cellular phone system DPS using the RF module 1 of the present embodiment. FIG. 1 shows a circuit block diagram of a power amplifier circuit constituting the RF module 1 of the present embodiment. FIG. 2 is a circuit diagram of a circuit block diagram of a power amplifier circuit constituting the RF module 1 of FIG. 2 indicates a terminal wire-bonded to a lead frame configured as a reference potential conductive pattern. 2 indicates the inductor elements L1 and L2, which are passive elements, and the inductor elements L1 and L2 are mounted on the lead frame as air-core coils.

  In FIG. 1 and FIG. 2, for example, two frequency bands of GSM900 (824 to 915 MHz) and DCS1800 (1710 to 1910 MHz) can be used (dual band system), and GMSK (Gaussian filtered Minimum Shift Keying) is used in each frequency band. The power amplifying circuit of the RF module 1 that can use two communication systems, ie, a modulation system and an EDGE (Enhanced Data GSM Environment) modulation system, is shown. Note that the GMSK modulation method is a method used for communication of audio signals, and is a method of shifting the phase of a carrier wave according to transmission data. The EDGE modulation method is a method used for data communication and is a method in which an amplitude shift is further added to the phase shift of GMSK modulation.

  The power amplifying circuit of the RF module 1 includes, for example, a power amplifying circuit 102A for GSM900 having two amplifying stages and a power amplifying circuit 102B for DCS1800 having, for example, two amplifying stages. Peripheral circuits for controlling and assisting the amplification operation of the power amplifier circuits 102A and 102B are arranged. On the input side of the RF module 1, a matching circuit (input matching circuit) 105A between the input terminal Pin1 for GSM900 and the power amplifier circuit 102A, and a matching circuit (input) between the input terminal Pin2 for DCS1800 and the power amplifier circuit 102B are input. Matching circuit) 105B. Further, on the output side of the RF module 1, a matching circuit (output matching circuit) 107A and a low-pass filter 108A between the output terminal Pout1 for GSM900 and the power amplifier circuit 102A, an output terminal Pout2 for DCS 1800, and power A matching circuit (output matching circuit) 107B and a low-pass filter 108B between the amplifier circuits 102B are arranged.

  The low-pass filter 108A for GSM900 is provided between the matching circuit 107A and the output terminal Pout1, and the output of the power amplification circuit 102A is input through the matching circuit 107A. The low-pass filter 108B for DCS 1800 is provided between the matching circuit 107B and the output terminal Pout2, and the output of the power amplifier circuit 102B is input through the matching circuit 107B. Further, an interstage matching circuit (interstage matching circuit) is provided between the amplification stages of the power amplification circuit 102A for GSM900, and an interstage between the amplification stages of the power amplification circuit 102B for DCS1800. Matching circuit (interstage matching circuit) is provided.

  Among these, the power amplifier circuit 102A for GSM900, the power amplifier circuit 102B for DCS1800, and the peripheral circuits are formed in one semiconductor amplifier element chip (semiconductor chip, high-frequency power amplifier element chip) 3. . The peripheral circuit includes a control circuit and a bias circuit that applies a bias voltage to each amplification stage. This control circuit is a circuit that generates a desired voltage to be applied to the power amplifier circuits 102A and 102B, and is a drain of each output amplifier element (for example, MOSFET (Metal Oxide Semiconductor Field Effect Transistor)) of each amplifier stage. A power supply control circuit that generates a first power supply voltage applied to the terminal and a bias voltage generation circuit that generates a first control voltage for controlling the bias circuit are provided. Here, when the power supply control circuit generates the first power supply voltage based on the output level designation signal supplied from the external baseband circuit 152, the bias voltage generation circuit is based on the first power supply voltage generated by the power supply control circuit. Thus, the first control voltage is generated. Here, the baseband circuit 152 is a circuit that generates an output level designation signal. This output level designation signal is a signal that designates the output level of the power amplifier circuits 102A and 102B, and is generated based on the distance between the mobile phone and the base station, that is, the output level corresponding to the strength of the radio wave. It is like that.

  The RF input signal input to the input terminal Pin1 for GSM900 of the RF module 1 is input to the semiconductor amplifying element chip 3 via the matching circuit 105A, and the power amplifying circuit 102A in the semiconductor amplifying element chip 3, for example, three amplifying stages. Is output from the semiconductor amplifying element chip 3 and output as an RF output signal from the output terminal Pout1 for GSM900 through the matching circuit 107A and the low-pass filter 108A. Further, the RF input signal input to the DCS 1800 input terminal Pin2 of the RF module 1 is input to the semiconductor amplifying element chip 3 through the matching circuit 105B, and the power amplifying circuit 102B in the semiconductor amplifying element chip 3, for example, two Amplified at the amplification stage and output from the semiconductor amplifying element chip 3, passes through the matching circuit 107 B and the low-pass filter 108 B, and is output as an RF output signal from the output terminal Pout 2 for DCS 1800.

  Such RF output signals output from the output terminals Pout1 and Pout2 are transmitted through a transmission line for signals. On the other hand, in the conductive pattern for the reference potential of the RF module 1, the capacitor (CP11) is grounded, for example, between the drain of the MOSFET (Q3) and the output terminal Pout1.

  Each matching circuit is a circuit that performs impedance matching as described above. In order to transmit electric power with high efficiency, it is necessary to perform impedance matching. For example, the characteristic impedance is adjusted to 50Ω.

  The low-pass filters 108A and 108B are circuits that attenuate harmonics. Harmonics (second harmonic and third harmonic) components are generated in the power amplifier circuits 102A and 102B, but low-pass filters 108A and 108B are interposed between the power amplifier circuits 102A and 102B and the output terminals Pout1 and Pout2. The harmonic components included in the amplified RF signal can be attenuated by the low-pass filters 108A and 108B so that the RF output signals output from the output terminals Pout1 and Pout2 do not include the harmonic components.

  A GSM900 low-pass filter (bandpass filter) 108A between the GSM900 output terminal Pout1 and the power amplifier circuit 102A for GSM900 passes a signal in the frequency band of 824 to 915 MHz, and doubles the frequency ( 1648 to 1830 MHz) and triple band (2472 to 2745 MHz) can be cut (attenuated) so as not to pass. The DCS1800 low-pass filter (bandpass filter) 108B between the DCS1800 output terminal Pout2 and the DCS1800 power amplifier circuit 102B passes a signal in the frequency band of 1710 to 1910 MHz, and doubles the frequency. A band (3420 to 3820 MHz) or a triple band (5130 to 5730 MHz) can be cut (attenuated) so as not to pass. Accordingly, the low-pass filters 108A and 108B can function as band-pass filters that pass signals in a predetermined frequency band and attenuate signals in other frequency bands.

  As described above, the RF module 1 of the present embodiment has two systems (that is, for GSM900 and DCS1800) of power amplification circuits 102A and 102B, and each of the two systems of power amplification circuits 102A and 102B has a low-pass filter circuit. The transmission frequency bands of the two power amplifier circuits 102A and 102B are 0.9 GHz band and 1.8 GHz band, respectively.

  In FIG. 1, reference numeral ANT denotes an antenna, reference numeral 151 denotes a front end module, reference numeral 152 denotes a baseband circuit, reference numeral 153 denotes a modulation / demodulation circuit, and FLT1 and FLT2 denote filters.

  The antenna ANT is an antenna for transmitting and receiving signal radio waves. The front end module 151 includes switch circuits 154a and 154b, capacitors C5 and C6, and a duplexer 156. The baseband circuit 152 converts an audio signal into a baseband signal, converts a received signal into an audio signal, and generates a modulation system switching signal and a band switching signal. A DSP (Digital Signal Processor) And a plurality of semiconductor integrated circuits such as a microprocessor and a semiconductor memory. The modulation / demodulation circuit 153 generates a baseband signal or modulates a transmission signal by down-converting and demodulating the reception signal. The filters FLT1 and FLT2 are filters that remove noise and interference waves from the received signal. The filter FLT1 is for GSM and the filter FLT2 is for DCS.

  The switch circuits 154a and 154b are switch circuits for switching between transmission and reception, the capacitors C5 and C6 are elements for cutting a direct current component from the received signal, and the duplexer 156 is a circuit for demultiplexing a GSM900 band signal and a DCS1800 band signal These circuits and elements are mounted on one wiring board to form a module. The switching signals CNT1 and CNT2 of the switch circuits 154a and 154b are supplied from the baseband circuit 152.

  FIG. 3 is a cross-sectional view schematically showing the RF module 1 of the present embodiment. FIG. 4 is a cross-sectional view schematically showing the RF module 1 at a location different from the cross-sectional location of the RF module 1 of FIG. FIG. 5 is a plan view (top view) schematically showing the RF module 1 of the present embodiment, and shows a state where the sealing portion 7 is seen through. 3 and 4 show a schematic structure of the RF module 1 and do not completely coincide with a cross section obtained by cutting the structure of FIG. 5 at a predetermined position.

  The RF module 1 of the present embodiment is a QFN (Quad Flat Non-leaded package) sealed RF module on which a semiconductor amplifying element chip 3 is mounted. In FIG. 3, the RF module 1 includes a semiconductor amplification element chip 3, leads 4, a die pad portion 5, a conductive wire 6, and a sealing portion 7. In FIG. 4, the RF module 1 includes a semiconductor amplifying element chip 3, leads 4, a die pad part 5, a conductive wire 6, a sealing part 7, and an inductor element 20 made of, for example, an air-core coil.

  The lead 4 has a two-layer structure of an upper layer lead 4a and a lower layer lead 4b. This lower layer lead 4 b has a half-etched portion 8 in order to prevent short circuit with the signal wiring layer 9 formed on the mounting substrate (motherboard) 2. The upper layer lead 4a and the lower layer lead 4b are processed from two lead frames that are different conductor layers. As shown in FIG. 5, the upper layer (the uppermost layer of the two lead frames) in which the upper layer lead 4a is processed is the lower layer (the uppermost of the two lead frames) in which the lower layer lead 4b is processed. It overlaps with the lead frame of the lower layer. Therefore, the transmission line constituted by the upper layer lead 4a and the transmission line constituted by the lower layer lead 4b intersect three-dimensionally. For example, when impedance matching of a transmission line having a two-layer structure is performed, the RF module 1 of the present embodiment intersects with an RF module whose transmission line is not three-dimensionally crossed. can do. In the RF module 1 of the present embodiment, the signal transmission line is configured by the upper layer lead 4a, and the reference potential conductive pattern is configured by the lower layer lead 4b.

  The die pad portion 5 is for mounting the semiconductor amplifying element chip 3. This die pad part 5 has a half-etched part 8 in order to make it difficult to remove the die pad part 5 from the exposed part. The die pad portion 5 is processed from the same lead frame as the lower layer lead 4b. Therefore, since the die pad portion 5 which is a part of the lowermost lead frame is exposed, it is electrically connected (bonded) to the signal wiring layer 9 of the mounting substrate 2 via the bonding material 10. The heat generated during the operation of the semiconductor amplifying element chip 3 mounted on the die pad portion 5 can be dissipated to the mounting substrate 2 side.

  The conductive wire 6 electrically connects the electrode (pad) 3a formed on the main surface of the semiconductor amplifying element chip 3 with the upper layer lead 4a and the lower layer lead 4b, and the upper layer lead 4a and the lower layer lead 4b. Are electrically connected.

  The sealing portion 7 is made of, for example, a mold resin. In FIG. 3, the semiconductor amplifying element chip 3, the conductive wire 6, the lead 4a, and a part of the lead 4b are sealed. That is, a part of the lead frame (conductor layer) constituting the lower layer lead 4 b is exposed from the lower surface of the sealing portion 7. This exposed portion becomes an input / output terminal (external terminal) of the RF module 1.

  The inductor element 20 is composed of, for example, an air-core coil, and is the inductor element of the enclosing portion A2 shown in FIG. As shown in FIG. 4, the structure in which the inductor element 20 is mounted across the upper layer leads 4a is shown. The upper layer lead 4a and the inductor element 20 are electrically connected via a bonding material 17 such as silver (Ag) paste. The bonding material 17 may be a bonding material having good conductivity on the upper surface of the inductor element 20 and the upper layer lead 4a or the lower layer lead 4b. Further, in the present embodiment, the inductor element 20 is mounted across the upper layer leads 4a, but may be mounted across the lower layer leads 4b.

  The mounting board 2 has a signal wiring layer 9 on the main surface of the mounting board 2. The RF module 1 is mounted on the mounting substrate 2 via a bonding material 10 made of, for example, mounting solder. The bonding material 10 is bonded to and electrically connected to an input terminal or an output terminal of the RF module 1 on the RF module 1 side. Further, the bonding material 10 is bonded to and electrically connected to the signal wiring layer 9 on the mounting substrate 2 side. The mounting board 2 has a laminated structure, and has a signal wiring layer (not shown) between the layers of the mounting board 2, and the signal wiring layer (not shown) and the signal wiring on the main surface of the mounting board 2. The layer 9 is electrically connected via a via hole (not shown) formed in the mounting substrate 2.

  The semiconductor amplifying element chip 3 is a semiconductor chip on which a semiconductor integrated circuit corresponding to the circuit configuration surrounded by a dotted line in the circuit diagram of FIG. 2 is formed. Therefore, in the semiconductor amplifying element chip 3 (or the surface layer portion), a semiconductor amplifying element (for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a heterojunction bipolar transistor) constituting a power amplifying circuit and a semiconductor constituting a peripheral circuit are included. Passive elements and the like constituting the elements and the matching circuit (interstage matching circuit) are formed. The semiconductor amplifying element chip 3 is formed by, for example, forming a semiconductor amplifying element on a semiconductor substrate (semiconductor wafer) made of a compound such as single crystal silicon or GaAs, and then grinding the back surface of the semiconductor substrate as necessary, followed by dicing. The semiconductor substrate is separated into each semiconductor amplifying element chip 3 by, for example.

  A plurality of electrodes 3 a are formed on the main surface of the semiconductor amplifying element chip 3. The electrodes 3 a corresponding to the input terminals Pin 1 and Pin 2, the output terminals Pout 1 and Pout 2, and the control terminal Ctrl are electrically connected to the upper layer lead 4 a through the conductive wire 6. Further, the electrodes 3 a corresponding to the power sources Vdd 1, Vdd 2 and the reference potential GND are electrically connected to the lower layer lead 4 b through the conductive wire 6.

  FIG. 6 shows an example of the semiconductor amplifying element chip 3 when the semiconductor amplifying elements constituting the power amplifying circuits 102A and 102B are formed by LDMOSFETs (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors). It is principal part sectional drawing.

As shown in FIG. 6, an epitaxial layer 202 made of p ⁻ type single crystal silicon is formed on the main surface of a semiconductor substrate 201 made of p ⁺ type single crystal silicon, and a part of the main surface of the epitaxial layer 202 is formed on the main surface. A p-type well 203 that functions as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET is formed. On the surface of the p-type well 203, a gate electrode 205 of the LDMOSFET is formed via a gate insulating film 204 made of silicon oxide or the like. The gate electrode 205 is made of, for example, a laminated film of an n-type polycrystalline silicon film and a metal silicide film, and sidewall spacers 206 made of silicon oxide or the like are formed on the side walls of the gate electrode 205.

The source and drain of the LDMOSFET are formed in regions separated from each other across the channel formation region inside the epitaxial layer 202. Drain, n contact with the channel forming region ^- -type offset drain region 207, n ^- -type contact offset drain region 207, an n-type offset drain region 208 formed apart from the channel forming region, n-type offset drain region And an n ⁺ -type drain region 209 formed in contact with 208 and further away from the channel formation region. Of these n ⁻ type offset drain region 207, n type offset drain region 208 and n ⁺ type drain region 209, n ⁻ type offset drain region 207 closest to gate electrode 205 has the lowest impurity concentration and is the lowest from gate electrode 205. The separated n ⁺ -type drain region 209 has the highest impurity concentration.

The source of the LDMOSFET, n contact with the channel forming region ^- -type source region 210, n ^- -type source region 210 in contact, are formed apart from the channel forming region, n ^- impurity concentration than -type source region 210 higher n ^{And a +} type source region 211. A p-type halo region 212 is formed below the n ⁻ -type source region 210.

A p-type punching layer 214 in contact with the n ⁺ -type source region 211 is formed at the end of the n ⁺ -type source region 211 (the end opposite to the side in contact with the n ⁻ -type source region 210). A p ⁺ type semiconductor region 215 is formed near the surface of the p type punching layer 214. The p-type punched layer 214 is a conductor layer for electrically connecting the source of the LDMOSFET and the semiconductor substrate 201, and is formed of, for example, a p-type polycrystalline silicon film embedded in the groove 213 formed in the epitaxial layer 202. It is formed.

A silicon nitride film 221 and a silicon oxide film are formed on the p-type punching layer 214 (p ⁺ -type semiconductor region 215), source (n ⁺ -type source region 211), and drain (n ⁺ -type drain region 209) of the LDMOSFET. A plug 224 in a contact hole 223 formed at 222 is connected. A source electrode 225 is connected to the p-type punching layer 214 (p ⁺ -type semiconductor region 215) and the source (n ⁺ -type source region 211) through a plug 224, and the drain (n ⁺ -type drain region 209) is connected to A drain electrode 226 is connected through a plug 224.

  A wiring 229 is connected to each of the drain electrode 226 and the source electrode 225 through a through hole 228 formed in the silicon oxide film 227 that covers the drain electrode 226 and the source electrode 225. A surface protection film 230 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the wiring 229. A source back electrode 231 is formed on the back surface of the semiconductor substrate 201.

  FIG. 7 shows, as another example, a main part of the semiconductor amplifying element chip 3 in the case where the semiconductor amplifying elements constituting the power amplifying circuits 102A and 102B are formed of heterojunction bipolar transistors (HBTs). It is sectional drawing.

As shown in FIG. 7, a subcollector layer 252 made of an n ⁺ -type GaAs layer is formed on a semi-insulating GaAs substrate (semiconductor substrate) 251, and an HBT 253 is formed on the subcollector layer 252.

  Each HBT 253 has a collector electrode 254 made of gold or the like formed on the sub-collector layer 252 and a collector mesa 255 formed at a predetermined distance from the collector electrode 254. The collector mesa 255 is formed of, for example, an n-type GaAs layer, and the collector mesa 255 and the collector electrode 254 are electrically connected via the subcollector layer 252.

  A base mesa 256 made of, for example, a p-type GaAs layer is formed on the collector mesa 255. A base electrode 257 made of gold or the like is formed in the peripheral region on the base mesa 256. An emitter layer 258 is formed on a substantially central portion of the base mesa 256, and an emitter electrode 259 is formed on the emitter layer 258. The emitter layer 258 is formed of, for example, an n-type InGaP layer, a GaAs layer, and an InGaAs layer, and the emitter electrode 259 is formed of, for example, tungsten silicide. As described above, a heterogeneous semiconductor junction (heterojunction) is formed between the base mesa (p-type GaAs layer) 256 and the emitter layer (n-type InGaP layer) 258.

  A base mesa 256 made of, for example, a p-type GaAs layer is formed on the collector mesa 255. A base electrode 257 made of gold or the like is formed in the peripheral region on the base mesa 256. An emitter layer 258 is formed on a substantially central portion of the base mesa 256, and an emitter electrode 259 is formed on the emitter layer 258. The emitter layer 258 is formed of, for example, an n-type InGaP layer, a GaAs layer, and an InGaAs layer, and the emitter electrode 259 is formed of, for example, tungsten silicide. As described above, a heterogeneous semiconductor junction (heterojunction) is formed between the base mesa (p-type GaAs layer) 256 and the emitter layer (n-type InGaP layer) 258.

  As shown in FIGS. 2 to 5, the RF module 1 shown in the present embodiment is an RF module in which a transmission line for a signal and a conductive pattern for a reference potential are configured by an upper layer lead 4 a and a lower layer lead 4 b, respectively. It is. That is, the upper layer lead 4a is processed with one lead frame (conductor layer), the lower layer lead 4b is processed with one lead frame (conductor layer), and the two lead frames are laminated. Thus, the RF module has a transmission line for signals and a conductive pattern for reference potential. The lower lead frame has a die pad portion 5.

  In the circuit configuration of the RF module 1 shown in FIG. 2, for example, the transmission line from the drain of the MOSFET (Q3) to the output terminal Pout1 is one of the transmission lines for signals, and the upper layer lead 4a (FIGS. 3 to 5). Reference). The transmission line from the drain of the MOSFET (Q3) to the output terminal Pout1 to the reference potential via the capacitor (CP11) is composed of a conductive wire 6 (see FIGS. 3 to 5). Become. The conductive wire 6 is grounded to the conductive pattern for the reference potential of the RF module 1. This conductive pattern for reference potential is composed of the lower layer lead 4b (see FIGS. 3 to 5).

  As shown in FIG. 3, the gap G between the upper lead frame having the upper lead 4a and the lower lead frame having the lower lead 4b is, for example, about 150 to 200 μm. Further, the thickness T of the lower lead frame is, for example, about 125 μm. In this case, a distance of at least about 275 μm is ensured between the signal wiring layer 9 on the main surface of the mounting substrate 2 and the lead frame having the upper layer lead 4a in which the signal line is configured. It becomes. In the present embodiment, a distance of at least about 275 μm is secured, but a lead frame having a signal wiring layer 9 on the main surface of the mounting substrate 2 and an upper layer lead 4a in which signal lines are formed. Since the stripline, the transmission line, the circuit configuration, the members, and the like differ depending on the required frequency band, the distance between the two can be adjusted in various ways.

  When the RF module 1 is mounted on the mounting substrate 2 via, for example, a bonding material 10 made of mounting solder, even if the height of the bonding material 10 varies, the signal layer (4a) and the reference potential Since the distance G of the layer (4b) is always constant, fluctuations in high frequency characteristics can be reduced. Further, in the RF module 1 having the two-layer lead frame structure, a high frequency signal is transmitted to the upper layer lead 4a of the uppermost lead frame, and the lower layer lead 4b of the lowermost lead frame is set as a reference potential, for example, a customer's motherboard. It is possible to prevent deterioration of high frequency characteristics due to interference with signals generated from the mounting substrate 2.

  Further, the semiconductor amplifying element chip 3 mounted on the RF module 1 has an output of, for example, 2 to 3 W, and is a heat generating active element that generates the most heat among the elements constituting the RF module 1. Therefore, as shown in the present embodiment, the package of the RF module 1 is a sealing type QFN, and the semiconductor amplifying element chip 3 which is a heat generating active element is mounted on the die pad portion 5 exposed from the sealing portion 7. is doing. Therefore, the thermal resistance of the RF module 1 can be reduced by mounting the semiconductor amplifying element chip 3 which is a heat generating active element on the die pad portion 5 of the lower lead frame.

  Further, the signal transmission line and the reference potential conductive pattern by the lead frame (upper layer lead 4a and lower layer lead 4b) of the two-layer structure shown in the present embodiment are conventionally used, for example, a ceramic substrate, PCB, etc. The signal transmission line formed on the substrate having the two main surfaces and the back surface (the surface opposite to the main surface) and the conductive pattern for the different potential can be used.

  The RF module 1 shown in the present embodiment includes a lead frame having an upper layer lead 4a in which a signal transmission line is configured, and a lead frame having a lower layer lead 4b in which a conductive pattern for reference potential is configured. Due to the laminated structure, the upper layer lead 4a and the lower layer lead 4b can be configured to cross three-dimensionally.

  Next, an example of a manufacturing process of the RF module 1 shown in the present embodiment will be described with reference to the drawings. 8 to 14 are cross-sectional views schematically showing the RF module 1 during the manufacturing process. 8 to 14, a region where one RF module 1 is formed is indicated by a symbol R, and two regions R are illustrated.

  First, as shown in FIG. 8, after preparing two lead frames 11a and 11b obtained by punching or etching a thin metal plate, the lead frames 11a and 11b are overlapped in parallel, They are integrated by caulking in the cavity 12 of the frame part. A transmission line for signals of the RF module 1 (see FIGS. 3 to 5) is formed on the upper lead frame 11a. On the other hand, a conductive pattern for a reference potential of the RF module 1 (see FIGS. 3 to 5) is formed on the lower lead frame 11b. In the lower lead frame 11b, a die pad portion 5 and a half-etched portion 8 are formed. In the present embodiment, a plurality of RF modules 1 are collectively formed from the lead frames 11a and 11b.

  Subsequently, as shown in FIG. 9, the semiconductor amplifying element chip 3 is mounted on the die pad portion 5 of the lower lead frame 11b and die-bonded.

  Subsequently, as shown in FIG. 10, the conductive wires 6 are wire-bonded between the semiconductor amplifying element chip 3 and the lead frames 11 a and 11 b and between the lead frame 11 a and the lead frame 11 b.

  Subsequently, as shown in FIG. 11 and FIG. 12, the die-bonded semiconductor amplifying element chip 3, the wire-bonded conductive wire 6, and the wire-bonded conductive wire 6 are interposed between the upper mold 13 a and the lower mold 13 b via the sheet 14. In order to seal the lead frames 11a and 11b with a sealing portion 7 made of, for example, an epoxy resin, transfer molding is performed. That is, resin sealing is performed by transfer molding while a sheet is laid on the lower mold 13b. The molding by transfer molding is a method in which a heat-pressed resin is injected into a closed heating mold and pressure-molded, and a plurality of moldings can be performed at one time, and the productivity is excellent.

  Subsequently, as shown in FIG. 13, two RF modules 1 are formed from a die-bonded semiconductor amplifying element chip 3, a wire-bonded conductive wire 6 and lead frames 11a and 11b, and a sealing portion 7 that seals them. Dicing to cut out. Thereby, although the RF module 1 is substantially completed, as shown in FIG. 14, the corners of the sealing portion 7 may be chamfered.

(Embodiment 2)
In the present embodiment, the passive element constituting the circuit of the RF module 1 shown in the first embodiment is not a semiconductor amplifying element chip 3 as in the first embodiment, but is used as a discrete component in the semiconductor amplifying element chip. 3. Place outside.

  FIG. 15 is a circuit diagram of the RF module 1 of the present embodiment. The circuit configuration of the RF module 1 is the same as the circuit diagram of FIG. 2 shown in the first embodiment. The enclosing portion A1 indicates a terminal that is wire-bonded to a lead frame (lead) applied as a conductive pattern for a reference potential. The enclosure A3 indicates a passive element that is a discrete component.

  FIG. 16 is a cross-sectional view schematically showing the RF module 1 of the present embodiment. As shown in FIG. 16, a structure in which the discrete component 16 is mounted across the upper layer leads 4a is shown. The upper layer lead 4a and the discrete component 16 are electrically connected via a bonding material 17 such as silver (Ag) paste. Other structures are the same as those in the first embodiment. In the present embodiment, the discrete component 16 is shown as a capacitive element, but is not limited thereto, and may be a passive element such as a resistance element or an inductor element. Further, the bonding material 17 may be any bonding material having good conductivity on the discrete component 16 and the upper surface of the upper layer lead 4a or the lower layer lead 4b. Further, in the present embodiment, the discrete component 16 is mounted across the upper layer leads 4a, but may be mounted across the lower layer leads 4b.

  Further, the manufacturing process of the RF module 1 shown in the present embodiment includes a process of electrically connecting the upper layer lead 4 a and the discrete component 16 via the bonding material 17. The other steps are realized in the same manner as in the first embodiment.

  When the circuit of the RF module is configured with a passive element such as a bypass capacitor of several thousand pF to several tens of thousands pF, which cannot be formed in the semiconductor amplifying element chip 3, the RF module 1 described in the present embodiment has such a passive The element can be applied as a discrete component 16 outside the semiconductor amplifying element chip 3.

(Embodiment 3)
In the present embodiment, the passive elements constituting the circuit of the RF module 1 shown in the second embodiment are not integrated discrete components 16 as in the second embodiment, but are integrated passive components (IPDs). ) 18 is arranged outside the semiconductor amplifying element chip 3.

  FIG. 17 is a cross-sectional view schematically showing the integrated passive component 18 of the present embodiment. FIG. 18 is a cross-sectional view schematically showing the RF module 1 of the present embodiment. The integrated passive component 18 refers to a component in which a plurality of passive elements are formed on the substrate 31 and no active elements are formed. The plurality of passive elements are formed by the conductor layer and / or the insulator layer on the substrate 31. The integrated passive element is formed.

  Reference numeral 31 in FIG. 17 denotes a substrate. The substrate 31 is a semiconductor substrate (semiconductor wafer) made of, for example, a silicon single crystal. If a semiconductor substrate made of a silicon single crystal or the like is used as the substrate 31, for example, a package process is performed on a plurality of integrated passive component chips formed on the wafer through a wafer process in a lump in the wafer state. It is easy to manufacture the integrated passive component 18 by using a wafer process package (WPP) technology. As another form, an insulating substrate such as a GaAs (gallium arsenide) substrate, a sapphire substrate, or a glass substrate can be used for the substrate 31.

  Reference numeral 32 denotes an insulating film (oxide film, silicon oxide film). The insulating film 32 is formed on the surface of the substrate 31 by using, for example, a thermal oxidation method or CVD (Chemical Vapor Deposition). In addition, when an insulating substrate (for example, a glass substrate) is used as the substrate 31, the formation of the insulating film 32 can be omitted.

  Reference numeral 33 denotes a wiring. For the wiring 33, a conductor film (conductor layer) mainly composed of, for example, an aluminum (Al) alloy film is formed on the insulating film 32, and this conductor film is patterned by using a photolithography technique and a dry etching technique. Thus, a patterned conductor film (conductor layer, aluminum alloy film) is formed. The wiring 33 forms a lower electrode 34 a of a MIM (Metal Insulator Metal) type capacitive element (MIM capacitor) 34.

  Reference numeral 35 denotes an insulating film. The insulating film 35 is formed on the substrate 31 (insulating film 32) so as to cover the wiring 33. The insulating film 35 functions as an interlayer insulating film, and is made of, for example, a silicon oxide film.

  Reference numeral 36 denotes an opening. The opening 36 is formed in the insulating film 35 by dry etching the insulating film 35 using a photoresist pattern (not shown) formed on the insulating film 35 as an etching mask. The wiring 33 (lower electrode 34a) is exposed at the bottom of the opening 36.

  Reference numeral 37 denotes an insulating film. The insulating film 37 is formed as a capacitor insulating film (for example, a silicon nitride film) of the capacitor on the insulating film 35 including the bottom and sidewalls of the opening 36, and is patterned using a photolithography method and a dry etching method. ing. This insulating film 37 exists on the lower electrode 34 a (wiring 33) at the bottom of the opening 36, and becomes the capacitive insulating film 34 b of the MIM type capacitive element 34.

  Reference numeral 38 denotes an opening. The opening 38 is formed by dry etching the insulating film 35 using a photoresist pattern (not shown) as an etching mask. The wiring 33 is exposed at the bottom of the opening 38.

  Reference numeral 41 denotes a wiring. The wiring 41 is formed by forming a conductor film (conductor layer) mainly composed of, for example, an aluminum (Al) alloy film on the substrate 31 (insulating film 35) so as to fill the openings 36 and 38. . The wiring 41 is formed of a patterned conductor film (conductor layer, aluminum alloy film) by patterning the conductor film using a photolithography method and a dry etching method. The wiring 41 is electrically connected to the wiring 33 at the bottom of the opening 38. In the capacitor formation region, the upper electrode 34c of the MIM type capacitive element 34 is formed by the wiring 41 formed on the lower electrode 34a made of the wiring 33 via the capacitive insulating film 34b (insulating film 37). . Therefore, the lower electrode 34a (wiring 33), the capacitive insulating film 34b (insulating film 37), and the upper electrode 34c (wiring 41) form an MIM (Metal Insulator Metal) type capacitive element (MIM capacitor) 34.

  Reference numeral 43 denotes an insulating film (protective film, protective resin film). The insulating film 43 is formed by forming a relatively thin insulating film 43a made of a silicon oxide film, a silicon nitride film, or a laminated film thereof so as to cover the wiring 41 on the substrate 31 (insulating film 35), and then insulating the insulating film 43. A relatively thick surface protective film is formed on the film 43a. The insulating film 43 is made of a resin material film such as polyimide resin (resin material).

  Reference numeral 44 denotes an opening. The opening 44 is formed by selectively removing a part of the insulating films 43 and 43a.

  Reference numeral 45 denotes a pad portion (pad electrode). The pad portion 45 is formed from the wiring 41 by exposing a part of the wiring 41 at the bottom of the opening 44.

  Reference numeral 51 denotes a seed film. The seed film 51 is formed on the substrate 31 (the main surface on the side where the passive elements are formed). The seed film 51 is made of, for example, a chromium (Cr) film, and can be formed by, for example, a sputtering method. That is, the seed film 51 is formed on the insulating film 43 including the pad portion 45 (wiring 41) exposed at the opening 44.

  Reference numeral 53 denotes a wiring (relocation wiring layer, rewiring). The wiring 53 is made of a copper film (conductor layer) by forming a copper (Cu) film on the exposed seed film 51. The wiring 53 is electrically connected to the wiring 41 (pad portion 45) at the bottom of the opening 44 of the insulating films 43 and 43a. By forming the wiring 53 in a spiral pattern (spiral pattern) on the insulating film 43, a spiral inductor (spiral coil) is formed.

  Reference numeral 54 denotes a nickel film. The nickel film 54 is formed using, for example, a plating method.

  Reference numeral 61 denotes an insulating film (protective film, protective resin film). The insulating film 61 is made of a resin material film such as polyimide resin as a surface protective film on the substrate 31 (insulating film 43) so as to cover the wiring 53 and the nickel film 54. By using an organic insulating film such as polyimide resin as the uppermost insulating film 61, it is possible to easily handle a chip (integrated passive component) with a relatively soft organic insulating film as the uppermost layer.

  Reference numeral 62 denotes an opening. The opening 62 is formed in the insulating film 61 so as to expose a part of the wiring 53.

  Reference numeral 63 denotes a gold (Au) film. The gold film 63 is formed as a terminal surface film (bump base metal layer) on the wiring 53 (the upper nickel film 54) of the opening 62 by using, for example, a plating method.

  Reference numeral 64 denotes a bump electrode. The bump electrode 64 is formed on the gold film 63 on the wiring 53 in the opening 62. The bump electrode 64 is made of, for example, a solder bump, and is formed, for example, by printing a solder paste by a printing method or the like and then performing a heat treatment.

  As shown in FIG. 18, in the RF module 1 of the present embodiment, a structure in which the integrated passive component 18 is mounted on the lower layer lead 4b is shown. In the present embodiment, the integrated passive component 18 is mounted on the lower layer lead 4b, but may be mounted on the upper layer lead 4a. However, in order to dissipate heat generated during operation of the integrated passive component 18, it is desirable to mount the integrated passive component 18 on the lower layer lead 4b formed in the lowermost lead frame.

  Further, the manufacturing process of the RF module 1 shown in the present embodiment includes a step of mounting the integrated passive component 18 on the lower layer lead 4b, and electrically connecting the integrated passive component 18 and the upper layer lead 4a with the conductive wire 6. And a step of electrically connecting the discrete component 16 to each other. The other steps are realized in the same manner as in the first embodiment.

  The formation of a more compact RF module can be realized by applying an integrated passive component 18 in which a plurality of passive elements are integrated as in the RF module 1 shown in the present embodiment.

(Embodiment 4)
In the present embodiment, the semiconductor amplifying element chip 3 is mounted on the die pad portion 5 shown in the first embodiment via the interposer 19.

  FIG. 19 is a cross-sectional view schematically showing the RF module 1 of the present embodiment. As shown in FIG. 19, the semiconductor amplifying element chip 3 and the discrete component 16 are mounted on the die pad portion 5 via an interposer 19 such as a flexible substrate or a tape. The interposer 19 may be mounted on the die pad portion 5 so as to be laid over the lower layer lead 4b.

  Further, the manufacturing process of the RF module 1 shown in the present embodiment includes a process of mounting the interposer 19 on the die pad portion 5. The other steps are realized in the same manner as in the first embodiment.

  In particular, when configuring a circuit of an RF module such that the peripheral circuit of the semiconductor amplifying element chip 3 is complicated, it can be realized by applying the interposer 19 as in the RF module 1 shown in the present embodiment. .

(Embodiment 5)
In the present embodiment, the semiconductor amplifying element chip 3 is mounted on the die pad portion 5 shown in the first embodiment via the upper layer lead 4a.

  FIG. 20 is a cross-sectional view schematically showing the RF module 1 of the present embodiment. As shown in FIG. 20, the semiconductor amplifying element chip 3 is mounted on the die pad portion 5 composed of the lower lead frame via the upper layer lead 4 a composed of the upper lead frame.

  In addition, the manufacturing process of the RF module 1 shown in the present embodiment includes a process of joining the upper lead frame and the lower lead frame so that the upper lead 4 a is disposed on the die pad portion 5. The other steps are realized in the same manner as in the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is widely used in the manufacturing industry for manufacturing RF modules.

It is explanatory drawing which shows an example of the digital mobile telephone system using RF module of Embodiment 1 of this invention. FIG. 2 is a circuit diagram of a circuit block diagram of a power amplifier circuit constituting the RF module of FIG. 1. It is sectional drawing which shows typically RF module of this Embodiment 1. FIG. It is sectional drawing which shows typically the RF module of a location different from the cross-sectional location of the RF module of FIG. It is a top view which shows typically RF module of this Embodiment 1. FIG. It is sectional drawing which shows typically the semiconductor chip at the time of forming a semiconductor amplifier element by LDMOSFET. It is sectional drawing which shows typically the semiconductor chip at the time of forming a semiconductor amplifier element with a heterojunction bipolar transistor. It is sectional drawing which shows typically the RF module in the manufacturing process of this Embodiment 1. FIG. FIG. 9 is a cross-sectional view schematically showing an RF module in the manufacturing process subsequent to FIG. 8. FIG. 10 is a cross-sectional view schematically showing the RF module in the manufacturing process subsequent to FIG. 9. It is sectional drawing which shows typically the RF module in the manufacturing process following FIG. It is sectional drawing which shows typically the RF module in the manufacturing process following FIG. It is sectional drawing which shows typically the RF module in the manufacturing process following FIG. It is sectional drawing which shows typically the RF module in the manufacturing process following FIG. It is a circuit diagram of RF module of this Embodiment 2. It is sectional drawing which shows typically RF module of this Embodiment 2. FIG. It is sectional drawing which shows the integrated passive component of this Embodiment 3 typically. It is sectional drawing which shows typically RF module of this Embodiment 3. FIG. It is sectional drawing which shows typically RF module of this Embodiment 4. FIG. It is sectional drawing which shows typically RF module of this Embodiment 5. FIG. It is sectional drawing which shows typically the RF module which comprised the transmission line for signals, and the conductive pattern for power supplies by the 1 layer structure which the present inventors examined.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 RF module 2 Mounting board 3 Semiconductor amplifier element chip 3a Electrode 4 Lead 4a Upper layer lead 4b Lower layer lead 5 Die pad part 6 Conductive wire 7 Sealing part 8 Half etch part 9 Signal wiring layer 10 Bonding material 11a, 11b Lead frame 12 Cavity 13a Upper mold 13b Lower mold 14 Sheet 15 Resin injection port 16 Discrete component 17 Bonding material 18 Integrated passive component 19 Interposer 20 Inductor element 31 Substrate 32 Insulating film 33 Wiring 34 Capacitor element 34a Lower electrode 34b Capacitor insulating film 34c Upper part Electrode 35 Insulating film 36 Opening 37 Insulating film 38 Opening 41 Wiring 43 Insulating film 43a Insulating film 44 Opening 45 Pad part 51 Seed film 53 Wiring 54 Nickel film 61 Insulating film 62 Opening 63 Gold film 64 Bump electrode 102 Semiconductor chip 102A, 102B Power amplifier circuit 105A, 105B Matching circuit 107A, 107B Matching circuit 108A, 108B Low-pass filter 151 Front end module 152 Baseband circuit 153 Modulation / demodulation circuit 154a Switch circuit 154b Switch circuit 156 Demultiplexer 201 Semiconductor substrate 202 Epitaxial Layer 203 p-type well 204 gate insulating film 205 gate electrode 206 sidewall spacer 207 n ⁻ type offset drain region 208 n type offset drain region 209 n ⁺ type drain region 210 n ⁻ type source region 211 n ⁺ type source region 212 p type Halo region 213 groove 214 p-type punching layer 215 p ⁺ -type semiconductor region 221 silicon nitride film 222 silicon oxide film 223 contact hole 224 plug 225 Source electrode 226 drain electrode 227 silicon oxide film 228 through hole 229 wiring 230 surface protective film 231 source back electrode 251 GaAs substrate 252 subcollector layer 253 HBT
254 Collector electrode 255 Collector mesa 256 Base mesa 257 Base electrode 258 Emitter layer 259 Emitter electrode 261 Insulating film 262 Contact hole 263 Collector wiring 264 Insulating film 265 Through hole 266 Emitter wiring A1, A2, A3 Enclosure ANT Antenna C5, C6 Capacitor CNT1, CNT2 Switching signal Ctrl Control terminal DPS Digital mobile phone system FLT1, FLT2 Filter G Gap Pin1, Pin2 Input terminal Pout1, Pout2 Output terminal R Region T Thickness Vdd1, Vdd2 Power supply GND Reference potential

Claims (19)

An electronic device having a power amplifier circuit,
The electronic device is
A first conductor layer;
A second conductor layer disposed above the first conductor layer;
A semiconductor chip mounted on the first conductor layer or the second conductor layer and having the power amplifier circuit formed thereon;
A sealing portion covering the semiconductor chip and the first and second conductor layers;
A back surface of the first conductor layer is exposed from the sealing portion;
The semiconductor chip has an input signal electrode, an output signal electrode, and a reference potential electrode;
The electronic device, wherein the first conductor layer is electrically connected to the reference potential electrode. The electronic device according to claim 1.
The electronic device, wherein the first and second conductor layers are constituted by a lead frame. The electronic device according to claim 1.
The electronic device, wherein the second conductor layer is electrically connected to the input and output signal electrodes. The electronic device according to claim 1.
The electronic device is characterized in that the semiconductor chip is mounted on the first conductor layer. The electronic device according to claim 2.
The electronic device, wherein the first conductor layer and the second conductor layer are electrically connected by a conductive wire. The electronic device according to claim 2.
The electronic device is characterized in that the sealing portion is made of resin. The electronic device according to claim 2.
The electronic device according to claim 1, wherein the first conductor layer has a half-etched portion. The electronic device according to claim 2.
The electronic device further includes a matching circuit,
The matching circuit includes a passive element,
The electronic device according to claim 1, wherein the passive element is a discrete component and is mounted on the first or second conductor layer. The electronic device according to claim 2.
The electronic device further includes an output matching circuit,
The output matching circuit has integrated passive components,
The integrated passive component is mounted on the first conductor layer. The electronic device according to claim 2.
The electronic device further includes an interposer,
The interposer is mounted on the first conductor layer;
The semiconductor chip is mounted on the interposer,
The electronic device is characterized in that the interposer is a flexible substrate or a tape. The electronic device according to claim 2.
The electronic device is mounted on a mounting substrate,
A planar pattern layer is formed on the main surface of the mounting substrate,
The electronic device, wherein the first conductor layer is electrically connected to the planar pattern layer. A method of manufacturing an electronic device having a power amplifier circuit,
(A) preparing a first lead frame constituting the first conductor layer and a second lead frame constituting the second conductor layer;
(B) preparing a semiconductor chip in which the power amplifier circuit is formed and the input signal electrode, the output signal electrode, and the reference potential electrode are formed;
(C) disposing the second lead frame above the first lead frame;
(D) electrically connecting the first conductor layer and the reference potential electrode;
(E) exposing the back surface of the first conductor layer and sealing the semiconductor chip and the first and second conductor layers;
A method for manufacturing an electronic device, comprising: In the manufacturing method of the electronic device according to claim 12,
Furthermore,
(F) electrically connecting the second conductor layer and the input and output signal electrodes;
A method for manufacturing an electronic device, comprising: In the manufacturing method of the electronic device according to claim 12,
Furthermore,
(G) mounting the semiconductor chip on the first conductor layer;
A method for manufacturing an electronic device, comprising: In the manufacturing method of the electronic device according to claim 12,
Furthermore,
(H) A method of manufacturing an electronic device, wherein the first conductor layer and the second conductor layer are electrically connected by a conductive wire. In the manufacturing method of the electronic device according to claim 12,
In the step (e), a sealing portion that covers the semiconductor chip and the first and second conductor layers is formed,
After the step (e),
(I) a step of holding the first and second conductor layers by the sealing portion after cutting the first and second conductor layers from the first lead frame and the second lead frame;
A method for manufacturing an electronic device, comprising: In the manufacturing method of the electronic device according to claim 12,
The step (a) further comprises:
(A1) A method for manufacturing an electronic device, comprising a step of half-etching the first conductor layer. In the manufacturing method of the electronic device according to claim 12,
In the step (e), the resin device is sealed by transfer molding. In the manufacturing method of the electronic device according to claim 12,
In the step (e), the resin device is sealed by transfer molding in a state where a sheet is laid on a mold, and the method for manufacturing an electronic device is characterized.

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