JP2006180151A - Power amplifier module and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost of a power amplifier module while improving its performance. <P>SOLUTION: An amplifier circuit of a driver stage of a power amplifier circuit of multistage configuration is formed of LDMOSFET circuits 31A1 and 31A2 of a semiconductor chip 2. The amplifier circuit of an output stage is formed of HBT of another semiconductor chip. The semiconductor chips and passive components are mounted on a wiring board constituting an RF power module for a mobile communication equipment. A plurality of bonding pads 33 including a plurality of Vcc pads 33a and 33b are formed on the semiconductor chip 2. Each of the bonding pads 33 is connected to the terminal of wiring board using a bonding wire. The LDMOSFET circuits 31A1 and 31A2 as well as the bonding pad 33 are arranged at the outer periphery of the semiconductor chip 2. The Vcc pads 33a and 33b are electrically connected for identical potential by wiring 36 formed on the side of outer periphery of the semiconductor chip 2 where the LDMOSFET circuits 31A1 and 31A2 are not arranged. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power amplification module and a method for manufacturing the same, and more particularly, to a power amplification module for a mobile phone and a technology effective when applied to the manufacturing technology.

  In recent years, mobile communication devices (so-called mobile phones) represented by communication methods such as GSM (Global System for Mobile Communications), PCS (Personal Communication Systems), PDC (Personal Digital Cellular), and CDMA (Code Division Multiple Access) Phone) is widespread worldwide.

  In general, this type of mobile communication device includes an antenna that radiates and receives radio waves, a power amplification module (high frequency power amplifier) that amplifies a power-modulated high-frequency signal and supplies the signal to the antenna, and a high-frequency signal received by the antenna. A receiving unit that performs signal processing, a control unit that performs these controls, and a battery that supplies a power supply voltage to these units are configured.

  Japanese Patent Application Laid-Open No. 11-204596 (Patent Document 1) describes a technique in which an external input / output line for connecting an external connection pad and an internal circuit is routed along the chip periphery.

  Japanese Patent Laid-Open No. 9-246481 (Patent Document 2) discloses that a portion of an empty I / O that is not actually used as an external interface among portions originally allocated as an external interface of a semiconductor chip is originally in the chip core region. A part of a circuit to be formed, for example, an output buffer circuit of a RAM mounted on a semiconductor chip or a control logic circuit for selecting one appropriately from a plurality of RAMs is allocated, and an empty I / O part is assigned. A technique is described in which the chip size is made smaller than before by making effective use.

In Japanese Patent Laid-Open No. 2003-124333 (Patent Document 3), a chip core portion having a semiconductor integrated circuit is disposed close to the outside of the chip core portion, and is used as a terminal for electrical connection between the chip core portion and the outside. A technology related to a semiconductor IC chip, which is composed of a pad and a power line and a ground line that are arranged outside the pad and supplies power to the chip core part so that the connection line between the pad and chip core part does not overlap the power line and the ground line. Are listed.
JP-A-11-204596 JP-A-9-246481 JP 2003-124333 A

  According to the study of the present inventor, the following has been found.

  In recent years, along with demands for reducing the size, thickness and performance of mobile communication devices (mobile phones), power amplification modules mounted on them have also been required to be reduced in size, thickness and performance. . In addition, since the addition of functions of mobile communication devices and the development of new communication methods are rapidly progressing, it is also required to shorten the development period of the power amplification module installed therein.

  Customers building mobile communication devices such as mobile phones use their own motherboards, and manufacturers of power amplification modules customize the power amplification modules to be installed on them according to the specifications of the customer's motherboard. There must be. However, customizing the power amplification module for each customer and changing the design of the semiconductor chip used for the power amplification module lengthens the development period of the power amplification module and increases the cost of the power amplification module.

  The objective of this invention is providing the technique which can reduce the cost of a power amplification module.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a power amplifying module for a mobile communication device having a power amplifying circuit having a multistage configuration, and includes a wiring board and first and second semiconductor chips mounted on a main surface of the wiring board. A final amplifier circuit of the power amplifier circuit is formed on the second semiconductor chip, an amplifier circuit upstream of the final circuit of the power amplifier circuit is formed on the first semiconductor chip, and A plurality of pad electrodes are formed on the semiconductor chip, and the plurality of pad electrodes include a plurality of first pad electrodes of the same potential that are electrically connected by wiring of the first semiconductor chip.

  The present invention also relates to a method for manufacturing a power amplifier module for a mobile communication device having a power amplifier circuit having a multistage configuration, wherein: (a) a plurality of terminals including a first terminal for supplying a fixed potential on its main surface; And (b) preparing the first and second semiconductor chips on the main surface of the wiring board, and preparing a first and second semiconductor chip each having a plurality of pad electrodes formed thereon. Mounting the semiconductor chip; (c) electrically connecting the plurality of pad electrodes of the first and second semiconductor chips and the plurality of terminals of the wiring board; and The amplifier circuit at the final stage of the amplifier circuit is formed on the second semiconductor chip, and the amplifier circuit at the stage before the final stage of the power amplifier circuit is formed on the first semiconductor chip. The plurality of formed pads The electrode includes a plurality of first pad electrodes of the same potential that are electrically connected by the wiring of the first semiconductor chip, and in the step (c), the position of the first terminal on the main surface of the wiring board The first pad electrode to be connected to the first terminal of the wiring board is selected from the plurality of first pad electrodes, and the selected first pad electrode and the first terminal of the wiring board are selected. Are electrically connected to each other.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The cost of the power amplification module can be reduced. In addition, the performance of the power amplification module can be improved.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections. However, unless otherwise specified, they are not irrelevant to each other, and one is a part of the other or All the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
In the present embodiment, for example, an RF (Radio Frequency) power module used for a digital cellular phone (mobile communication device) that transmits information using a network such as a W-CDMA (Wideband Code Division Multiple Access) system. And a semiconductor element (semiconductor device, semiconductor chip) mounted thereon.

  Here, W-CDMA (Wideband Code Division Multiple Access) refers to one or standard of a wireless communication system used for digital mobile phones. The RF power module 1 of the present embodiment is an RF power module (power amplification module) used in the W-CDMA system, for example.

  FIG. 1 shows an amplification constituting an RF power module (power amplification module, HPA (High Power Amplifier), power amplifier module, high-frequency power amplification module, power amplifier module, high-frequency power amplification device, electronic device) 1 of the present embodiment. The circuit block diagram of a circuit is shown.

  As shown in FIG. 1, the circuit configuration of the RF power module 1 includes a power amplifier circuit 102 including three amplifier stages (amplifier circuits and amplifiers) 102A1, 102A2, and 102A3, and control of the amplification operation of the power amplifier circuit 102. A control circuit (peripheral circuit) 103 for assisting, a matching circuit (input matching circuit) 105 between the input terminal (RF signal input terminal) 104 and the power amplifier circuit 102, an output terminal (RF signal output terminal) 106, and power A matching circuit (output matching circuit) 107 and a low pass filter 108 between the amplifier circuits 102 are included. In addition, an interstage matching circuit (interstage matching circuit) 102AM1 is provided between the amplification stage 102A1 and the amplification stage 102A2 of the power amplifier circuit 102, and an interstage between the amplification stage 102A2 and the amplification stage 102A3. Matching circuit (interstage matching circuit) 102AM2 is provided. Each matching circuit is a circuit that performs impedance matching, and the low-pass filter 108 is a circuit that attenuates harmonics.

  The control circuit 103 is configured to input a control signal from an input terminal (control signal input terminal) 110 and control each amplification stage 102A1, 102A2, 102A3 of the power amplifier circuit 102 based on the input control signal. Yes. Therefore, the control circuit 103 controls each amplification stage 102A1, 102A2, 102A3 of the power amplification circuit 102, and for example, a desired voltage (for example, power supply voltage) applied to each amplification stage 102A1, 102A2, 102A3 of the power amplification circuit 102. And a bias circuit that applies a bias voltage to the amplification stages 102A1, 102A2, and 102A3. The control circuit 103 includes, for example, a MISFET element (active element) and a passive element. The control signal, fixed potential, and the like are input to the control circuit 103 as necessary.

  As described above, the power amplifier circuit 102 includes the three amplification stages 102A1, 102A2, and 102A3. The first stage, which is the driver stage (the preceding stage (the amplification stage) before the output stage (the final stage)) and The second amplification stage 102A1 and 102A2 are formed in one semiconductor chip (semiconductor amplification element chip, high frequency power amplification element chip) 2, and the third amplification stage 102A3 which is the output stage (final stage) These are formed in another semiconductor chip (semiconductor amplification element chip, high frequency power amplification element chip) 3. In the present embodiment, each amplification stage 102A1 and 102A2 formed on the semiconductor chip 2 includes a MISFET (Metal Insulator) such as an n-channel LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor). (Semiconductor Field Effect Transistor) element. The amplification stage 102A3 formed on the semiconductor chip 3 is formed of a heterojunction bipolar transistor (HBT) element.

  Of the three amplification stages 102A1, 102A2, and 102A3 constituting the power amplification circuit 102, the driver stage amplification stages 102A1 and 102A2 are required to reduce noise. By forming the power amplifier circuit 102 and the RF power module having the power amplifier circuit 102, noise can be reduced and the cost can be reduced. On the other hand, among the three amplification stages 102A1, 102A2 and 102A3 constituting the power amplification circuit 102, the amplification stage 102A3 of the output stage is required to have high efficiency (high amplification factor). As described above, the amplification stage 102A3 is replaced by the HBT. By forming the power amplifier circuit 102, it is possible to increase the efficiency of the power amplifier circuit 102 and the RF power module having the power amplifier circuit 102. In particular, in an RF power module used in a high frequency band (for example, a high frequency band of about 2 GHz), the effect of increasing the efficiency by forming the amplification stage 102A3 with HBT is great. As described above, in this embodiment, the three amplification stages 102A1, 102A2, and 102A3 constituting the power amplifier circuit 102 are not constituted by one semiconductor chip, but are constituted by the two semiconductor chips 2 and 3, and the most efficient. The amplifier stage 102A3 of the output stage that affects the output is configured by the HBT formed on the semiconductor chip 3, and the driver stage amplifier stages 102A1 and 102A2 that have relatively little influence on the efficiency are configured by the LDMOSFET formed on the semiconductor chip 2. Therefore, it is possible to achieve both high efficiency (high gain) and low cost and low noise.

  Therefore, in the present embodiment, the three amplification stages 102A1, 102A2, and 102A3 are connected (multistage connection, multistage connection) to form the power amplification circuit 102, and the driver amplification stages 102A1 and 102A2 are The amplification stage 102A3 of the output stage is composed of an HBT formed on the semiconductor chip 3, and is composed of an LDMOSFET formed on the semiconductor chip 2. Therefore, the power amplifier circuit 102 includes two n-channel LDMOSFETs (that is, an n-channel LDMOSFET that forms the amplification stage 102A1 and an n-channel LDMOSFET that forms the amplification stage 102A2) and one HBT (that is, the amplification stage 102A3). HBT) is dependently connected (multi-stage connection, multi-stage connection).

  As described above, the RF power module 1 is a power amplification module for a mobile communication device having the power amplification circuit 102 having a multistage configuration (multistage configuration). The power amplifier circuit 102 of the RF power module 1 includes two LDMOSFETs (corresponding to LDMOSFET circuits 31A1 and 31A2 described later formed on the semiconductor chip 2) and one HBT (semiconductor chip) as three amplification stages 102A1, 102A2 and 102A3. 3 (corresponding to the HBT formed in FIG. 3) in cascade connection (multistage connection), and the output level of the power amplifier circuit 102 is the power supply voltage Vdd or bias voltage supplied from the control circuit 103. It is controlled by etc.

  An RF input signal (RF transmission signal) input to the input terminal 104 of the RF power module 1 is input to the semiconductor chip 2 through the matching circuit 105 and amplified by the two amplification stages 102A1 and 102A2 in the semiconductor chip 2. Output from the semiconductor chip 2, input to the semiconductor chip 3 through the matching circuit 102 AM 2, amplified by the amplification stage 102 A 3 in the semiconductor chip 3, output from the semiconductor chip 3, output to the output terminal 106 through the matching circuit 107 and the low-pass filter 108. Is output as an RF output signal (amplified RF transmission signal). When the matching circuit 102AM1 is formed by a passive component outside the semiconductor chip 2 (corresponding to a passive component 5 described later), the RF signal input to the semiconductor chip 2 and amplified by the amplification stage 102A1 is 2 is output once from the semiconductor chip 2 through the matching circuit 102AM1, and then amplified by the amplification stage 102A2 and output from the semiconductor chip 2. The RF signal output from the semiconductor chip 2 is output from the matching circuit 102AM2. And input to the semiconductor chip 3.

  FIG. 2 is a conceptual top view (plan view) showing the structure of the RF power module 1 of the present embodiment, and FIG. 3 is a conceptual cross-sectional view of the RF power module 1 of the present embodiment. FIG. 2 shows a state in which the sealing resin 6 is seen through. 3 corresponds to a cross-sectional view (side cross-sectional view), but shows a conceptual structure of the RF power module 1, which is completely different from a cross-section obtained by cutting the structure of FIG. 2 at a predetermined position. I have not done it. 2 is a plan view, the substrate side terminals 12 (including the terminals 12a) to which the bonding wires 8 are connected are hatched for easy understanding of the drawing.

  The RF power module 1 of the present embodiment shown in FIGS. 2 and 3 includes a wiring board (module board) 4 and a semiconductor chip (semiconductor element, active element) 2 mounted (mounted) on the wiring board 4. 3, a passive component (passive element, chip component) 5 mounted (mounted) on the wiring substrate 4, and a sealing resin (sealing) covering the upper surface 4 a of the wiring substrate 4 including the semiconductor chips 2, 3 and the passive component 5 Stopping resin part) 6. The electrodes of the semiconductor chips 2 and 3 and the passive component 5 are electrically connected to the conductor layer (transmission line) of the wiring board 4. Further, the RF power module 1 can be mounted on, for example, an external circuit board (not shown) or a mother board (corresponding to a mother board 51 described later).

The wiring substrate 4 is, for example, a multilayer substrate (multilayer wiring substrate) in which a plurality of insulator layers (dielectric layers) 11 and a plurality of conductor layers or wiring layers (not shown) are stacked and integrated. In FIG. 3, four insulating layers 11 are laminated to form the wiring board 4. However, the number of laminated insulating layers 11 is not limited to this and can be variously changed. As a material for forming the insulator layer 11 of the wiring board 4, for example, a ceramic material such as alumina (aluminum oxide, Al ₂ O ₃ ) can be used. In this case, the wiring board 4 is a ceramic multilayer board. The material of the insulator layer 11 of the wiring board 4 is not limited to a ceramic material and can be variously changed. For example, a glass epoxy resin may be used.

  Between the upper surface (front surface, main surface) 4a and lower surface (back surface, main surface) 4b of the wiring substrate 4 and between the insulator layers 11, there are wiring formation conductor layers (wiring layers, wiring patterns, conductor patterns). Is formed. A plurality of board-side terminals (terminals, electrodes, transmission lines, wiring patterns, strip lines) 12 made of a conductor are formed on the upper surface 4 a of the wiring board 4 by the uppermost conductor layer of the wiring board 4. A plurality of external connection terminals (terminals, electrodes, module electrodes) 13 made of a conductor are formed on the lower surface 4b of the wiring board 4 by the lowermost conductor layer. The external connection terminal 13 corresponds to, for example, the input terminals 104 and 110 and the output terminal 106 in FIG. A conductor layer (wiring layer, wiring pattern, conductor pattern) is also formed inside the wiring substrate 4, that is, between the insulator layers 11, but is not shown in FIG. 3 for simplification. Among the wiring patterns formed by the conductor layer of the wiring substrate 4, a wiring pattern for supplying a reference potential (for example, the reference potential supplying terminal 13 a on the lower surface 4 b of the wiring substrate 4) is used for forming the wiring of the insulator layer 11. It can be formed in a rectangular pattern that covers most of the area of the surface, and the wiring pattern for the transmission line can be formed in a strip pattern. Further, on the upper surface 4a of the wiring substrate 4, terminals (substrate side terminals, electrodes, transmission lines, wiring patterns, strip lines) for supplying (inputting) a fixed potential (ground potential, power supply potential, Vcc) to the semiconductor chip 2 are provided. ) 12 a is also formed as the substrate-side terminal 12. That is, on the upper surface 4 a of the wiring substrate 4, a plurality of substrate-side terminals 12 including fixed potential supply terminals 12 a are formed.

  Each conductor layer (wiring layer) constituting the wiring board 4 is electrically connected through a conductor or a conductor film in a via hole (through hole) 14 formed in the insulator layer 11 as necessary. Accordingly, the board-side terminal 12 on the upper surface 4a of the wiring board 4 is connected to the upper surface 4a of the wiring board 4 and / or an internal wiring layer (wiring layer between the insulator layers 11), a conductor film in the via hole 14 or the like as necessary. Is electrically connected to the external connection terminal 13 on the lower surface 4 b of the wiring board 4. Of the via holes 14, the via holes 14 a provided below the semiconductor chip 2 can also function as thermal vias for conducting heat generated in the semiconductor chips 2 and 3 to the lower surface 4 b side of the wiring substrate 4. .

  The semiconductor chips 2 and 3 are formed by forming a semiconductor integrated circuit on a semiconductor substrate (semiconductor wafer), grinding the back surface of the semiconductor substrate as necessary, and then separating the semiconductor substrate into each semiconductor chip by dicing or the like. is there. The semiconductor chip 2 is a semiconductor chip 2 on which a semiconductor integrated circuit corresponding to a circuit configuration surrounded by a dotted line indicating the semiconductor chip 2 in the circuit block diagram of FIG. 1 is formed. The semiconductor chip 3 is a semiconductor chip 3 on which a semiconductor integrated circuit corresponding to a circuit configuration surrounded by a dotted line indicating the semiconductor chip 3 in the circuit block diagram of FIG. 1 is formed. Accordingly, LDMOSFETs (corresponding to LDMOSFET circuits 31A1 and 31A2, which will be described later) as semiconductor amplification elements constituting the amplification stages 102A1 and 102A2 of the power amplification circuit 102 are formed in the semiconductor chip 2 (or the surface layer portion). 3 (or the surface layer portion) is formed with an HBT as a semiconductor amplifying element constituting the amplification stage 102A3 of the power amplification circuit 102. A circuit corresponding to the control circuit 103 is also formed in the semiconductor chip 2 (or the surface layer portion).

  As shown in FIGS. 2 and 3, the semiconductor chips 2 and 3 are die-bonded face-up to a conductor layer 15 on the upper surface 4 a of the wiring substrate 4 with a bonding material (adhesive) 16 such as solder. A silver paste or the like can be used for the bonding material 16 for die bonding of the semiconductor chips 2 and 3 instead of solder. A plurality of electrodes (bonding pads, pad electrodes) 2 a formed on the surface of the semiconductor chip 2 and a plurality of electrodes (bonding pads, pad electrodes) 3 a formed on the surface of the semiconductor chip 3 are connected via a plurality of bonding wires 8. The wiring board 4 is electrically connected to the plurality of board-side terminals 12 on the upper surface 4a. The electrode 2a of the semiconductor chip 2 corresponds to a bonding pad 33 described later.

  Further, a back electrode 2b is formed on the back surface of the semiconductor chip 2, and the back electrode 2b of the semiconductor chip 2 is connected (bonded) to the conductor layer 15 on the top surface 4a of the wiring substrate 4 by a bonding material 16 such as solder. Further, it is electrically connected to the reference potential supply terminal 13a on the lower surface 4b of the wiring board 4 through a conductor film in the via hole 14 or the like.

  The passive component 5 includes a passive element such as a resistance element (for example, a chip resistor), a capacitance element (for example, a chip capacitor), or an inductor element (for example, a chip inductor), and includes, for example, a chip component. The passive component 5 is a passive component that constitutes, for example, the matching circuits 102AM1, 102AM2, 105, 107, the low-pass filter 108, and / or the control circuit 111 (a part for the control circuit 103). The passive component 5 is mounted on the board-side terminal 12 on the upper surface 4 a of the wiring board 4 by a conductive bonding material 17 such as solder. The matching circuits 102AM1 and 102AM2 can also be configured by passive elements formed in the semiconductor chip 2 or the semiconductor chip 3.

  Between the substrate-side terminals 12 on the upper surface 4a of the wiring substrate 4 to which the semiconductor chips 2 and 3 or the passive component 5 are electrically connected, the upper surface 4a of the wiring substrate 4 or the internal wiring layers and via holes 14 are provided as necessary. Wired through a conductor film or the like, it is electrically connected to the external connection terminal 13 or the reference potential supply terminal 13a on the lower surface 4b of the wiring board 4.

  The sealing resin 6 is formed on the upper surface 4 a of the wiring substrate 4 so as to cover the semiconductor chips 2 and 3, the passive component 5 and the bonding wire 8. The sealing resin 6 is made of a resin material such as an epoxy resin, for example, and can contain a filler.

  As described above, in this embodiment, the power amplification circuit 102 is formed by the two semiconductor chips 2 and 3, and the amplification stage 102 A 3 of the output stage (final stage) of the power amplification circuit 102 is connected to the semiconductor chip 3. Amplification stages 102A1 and 102A2 of the driver stage (preceding to the output stage) of the power amplifier circuit 102 are formed by LDMOSFET elements formed on the semiconductor chip 2 and formed by the formed HBT elements.

  FIG. 4 is a cross-sectional view of a main part of the semiconductor chip 3, and a cross-sectional view of a main part of a region where the HBT forming the amplification stage 102 </ b> A <b> 3 of the power amplifier circuit 102 is formed.

As shown in FIG. 4, a subcollector layer 152 made of an n ⁺ -type GaAs layer is formed on a semi-insulating GaAs substrate (semiconductor substrate) 151, and an HBT 153 is formed on the subcollector layer 152.

  Each HBT 153 has a collector electrode 154 made of gold or the like formed on the sub-collector layer 152, and a collector mesa 155 formed with a predetermined distance from the collector electrode 154. The collector mesa 155 is formed of, for example, an n-type GaAs layer, and the collector mesa 155 and the collector electrode 154 are electrically connected via the subcollector layer 152.

  A base mesa 156 made of, for example, a p-type GaAs layer is formed on the collector mesa 155. A base electrode 157 made of gold or the like is formed in the peripheral region on the base mesa 156. An emitter layer 158 is formed on a substantially central portion of the base mesa 156, and an emitter electrode 159 is formed on the emitter layer 158. The emitter layer 158 is formed of, for example, a layer in which an n-type InGaP layer, a GaAs layer, and an InGaAs layer are stacked, and the emitter electrode 159 is formed of, for example, tungsten silicide. Thus, a heterogeneous semiconductor junction (heterojunction) is formed between the base mesa (p-type GaAs layer) 156 and the emitter layer (n-type InGaP layer) 158.

  A collector wiring 163 is connected to the collector electrode 154 through a contact hole 162 formed in the insulating film 161. An emitter wiring 166 is connected to the emitter electrode 159 through a through hole 165 formed in the insulating films 164 and 161. Illustration and description of the structure above the emitter wiring 166 is omitted here.

  FIG. 5 is a plan view (plan layout diagram) of the semiconductor chip 2 and shows an example of circuit arrangement of the semiconductor chip 2. Although FIG. 5 is a plan view, the LDMOSFET circuits 31A1 and 31A2, the bonding pad 33, the Vcc pads 33a and 33b, the Vcc wiring 34 and the wiring 36 are hatched for easy understanding of the drawing.

  As shown in FIG. 5, the semiconductor chip 2 of the present embodiment includes an LDMOSFET circuit (LDMOSFET circuit region, LDMOSFET formation region, high-frequency amplification transistor region, amplification element formation region) 31A1 corresponding to the amplification stage 102A1. An LDMOSFET circuit (LDMOSFET circuit region, LDMOSFET formation region, high frequency amplification transistor region, amplification element formation region) 31A2 corresponding to the amplification stage 102A2 and a control circuit block (control circuit, control circuit unit, peripheral circuit unit) 32 are provided. Have. The control circuit block 32 corresponds to the control circuit 103 and the like. A plurality of bonding pads (pad electrodes, electrode pads, pad portions) 33 are formed on the surface of the semiconductor chip 2.

  The bonding pad 33 is an input gate pad (bonding pad for inputting an RF signal through the matching circuit 105) electrically connected to the gate electrode of the LDMOSFET circuit 31A1, and is electrically connected to the drain of the LDMOSFET circuit 31A1. Connected output drain pad (bonding pad for outputting RF signal amplified by LDMOSFET circuit 31A1), input gate pad electrically connected to gate electrode of LDMOSFET circuit 31A2 (via matching circuit 102AM1) Bonding pad for inputting RF signal), drain pad for output electrically connected to the drain of LDMOSFET circuit 31A2 (bonding pad for outputting RF signal amplified by LDMOSFET circuit 31A2), It includes such a bonding pad for inputting a control signal to the fine control circuit block 32 (control circuit 103). The bonding pad 33 has a plurality of Vcc pads (bonding pads, pad electrodes) 33a, 33b (a plurality of first pads) for supplying (inputting) a fixed potential (ground potential, power supply potential, Vcc) to the semiconductor chip 2. Pad electrode). For example, in FIG. 5, two Vcc pads 33 a and 33 b are formed on the surface of the semiconductor chip 2.

  Further, in the semiconductor chip 2, the region where the LDMOSFET circuit 31A1 is formed, the region where the LDMOSFET circuit 31A2 is formed, and the region where each control circuit block 32 is formed are formed from a buried oxide film formed between the regions. Each element isolation region is electrically isolated from other regions. Further, the internal wiring of the semiconductor chip 2 is provided between the LDMOSFET circuit 31A1, the LDMOSFET circuit 31A2 and each control circuit block 32, and between the LDMOSFET circuit 31A1, the LDMOSFET circuit 31A2, each control circuit block 32 and the bonding pad 33 as required. They are electrically connected by (wiring in the same layer as wirings 231 and 241 described later).

  For example, the Vcc pad 33a or the Vcc pad 33b is electrically connected to a circuit in the control circuit block 32 via the Vcc wiring 34, and the fixed potential input to the Vcc pad 33a or the Vcc pad 33b is Vcc. The circuit is supplied to the circuit in each control circuit block 32 through the wiring 34. In addition, a plurality of control circuit blocks 32 are formed in the semiconductor chip 2, and the control circuit blocks 32 are electrically connected as necessary by wiring 35 (wiring different from the Vcc wiring 34). Yes. The plurality of Vcc pads 33a and 33b are electrically connected by wirings (Vcc pad connection wirings) 36 formed on the semiconductor chip 2. Since the plurality of Vcc pads 33a, 33b are electrically connected by the wiring 36, the plurality of Vcc pads 33a, 33b are bonding pads (pad electrodes, electrode pads, pad portions) having the same potential. Since the plurality of Vcc pads 33a and 33b are electrically connected by the wiring 36 and have the same potential, if a fixed potential is inputted to any of the plurality of Vcc pads 33a and 33b, the inputted fixed potential is changed to Vcc. It can be supplied to the circuit in each control circuit block 32 via the wiring 34. A guard ring 38 made of a wiring layer (internal wiring layer) of the semiconductor chip 2 is formed on the outermost periphery of the semiconductor chip 2, and the wiring 36 connecting the plurality of Vcc pads 33a and 33b is as follows. It is provided in a region between the bonding pad 33 and the guard ring 38 (that is, a region outside the bonding pad 33).

  As described above, the amplifier stages 102A1 and 102A2 (that is, LDMOSFET circuits 31A1 and 31A2) constituting the power amplifier circuit 102 are formed in the same semiconductor chip 2, and further control for controlling the amplifier stages 102A1 and 102A2 is performed. The circuit 103 (control circuit block 32) is also formed in the semiconductor chip 2 in which the amplification stages 102A1 and 102A2 are formed. In the present embodiment, the passive elements for the interstage matching circuits 102AM1 and 102AM2 are described as being formed by passive elements (passive components 5) outside the semiconductor chip 2, but are formed in the semiconductor chip 2. The matching circuits 102AM1 and 102AM2 between the stages can be formed by the passive elements.

  FIG. 6 is a cross-sectional view of a main part of the semiconductor chip 2, showing a cross-sectional view of the main part of a region where the LDMOSFET circuit 31A1 or the LDMOSFET circuit 31A2 is formed.

As shown in FIG. 6, an epitaxial layer 202 made of p ⁻ type single crystal silicon is formed on the main surface of a semiconductor substrate 201 made of p ⁺ type single crystal silicon, and a part of the main surface of the epitaxial layer 202 is formed. Is formed with a p-type well 203 that functions as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET. On the surface of the p-type well 203, a gate electrode 205 of the LDMOSFET is formed via a gate insulating film 204 made of silicon oxide or the like. The gate electrode 205 is made of, for example, a laminated film of an n-type polycrystalline silicon film and a metal silicide film, and sidewall spacers 206 made of silicon oxide or the like are formed on the side walls of the gate electrode 205.

The source and drain of the LDMOSFET are formed in regions separated from each other across the channel formation region inside the epitaxial layer 202. Drain, n contact with the channel forming region ^- -type offset drain region 207, n ^- -type contact offset drain region 207, an n-type offset drain region 208 formed apart from the channel forming region, n-type offset drain region And an n ⁺ -type drain region 209 formed in contact with 208 and further away from the channel formation region. Of these n ⁻ type offset drain region 207, n type offset drain region 208 and n ⁺ type drain region 209, n ⁻ type offset drain region 207 closest to gate electrode 205 has the lowest impurity concentration and is the lowest from gate electrode 205. The separated n ⁺ -type drain region 209 has the highest impurity concentration.

The source of the LDMOSFET, n contact with the channel forming region ^- -type source region 210, n ^- -type source region 210 in contact, are formed apart from the channel forming region, n ^- impurity concentration than -type source region 210 higher n ^{And a +} type source region 211. A p-type halo region 212 is formed below the n ⁻ -type source region 210.

A p-type punching layer 214 in contact with the n ⁺ -type source region 211 is formed at the end of the n ⁺ -type source region 211 (the end opposite to the side in contact with the n ⁻ -type source region 210). A p ⁺ type semiconductor region 215 is formed near the surface of the p type punching layer 214. The p-type punching layer 214 is a conductive layer for electrically connecting the source of the LDMOSFET and the semiconductor substrate 201, and is formed by, for example, a p-type polycrystalline silicon film embedded in the groove 213 formed in the epitaxial layer 202. Is done.

A silicon nitride film 221 and a silicon oxide film are formed on the p-type punching layer 214 (p ⁺ -type semiconductor region 215), source (n ⁺ -type source region 211), and drain (n ⁺ -type drain region 209) of the LDMOSFET, respectively. A plug 224 filling the contact hole 223 formed in the laminated film 222 is connected.

On the silicon oxide film 222 in which the plug 224 is embedded, a wiring (first wiring layer) 231 mainly composed of, for example, an aluminum (Al) alloy film is formed. A source electrode 231a and a drain electrode 231b are formed by the wiring 231. A source electrode 231a is connected to the p-type punching layer 214 (p ⁺ -type semiconductor region 215) and the source (n ⁺ -type source region 211) via a plug 224, and the drain (n ⁺ -type drain region 209) is connected to The drain electrode 231b is connected through the plug 224.

  An insulating film 232 made of a silicon oxide film or the like is formed on the silicon oxide film 222 so as to cover the wiring 231, and a through hole 233 that exposes the wiring 231 is formed at the bottom of the insulating film 232. A plug 234 mainly composed of a tungsten (W) film is embedded therein. On the insulating film 232 in which the plug 234 is embedded, a wiring (second layer wiring) 241 mainly composed of an aluminum (Al) alloy film or the like is formed. The wiring 241 forms a source wiring 241a and a drain wiring 241b. The source wiring 241a is electrically connected to the source electrode 231a through the plug 234, and the drain wiring 241b is connected to the drain electrode 231b through the plug 234. Electrically connected.

  A surface protective film (passivation film) 242 made of a laminated film of a silicon oxide film and a silicon nitride film or the like is formed on the insulating film 232 so as to cover the wiring 241. Although not shown in the cross-sectional view of the main part of FIG. 6, the surface protection film 242 is formed with an opening for a bonding pad (corresponding to an opening 262 described later, but not shown in FIG. 6). The bonding pad 33 is formed by the wiring 241 (aluminum film or aluminum alloy film) exposed from the opening.

On the entire back surface of the semiconductor substrate 201, a source back electrode (back electrode, back source electrode) 251 made of, for example, a laminated film of a nickel (Ni) film, a titanium (Ti) film, a Ni film, and a gold (Au) film is formed. Is formed. The source back electrode 251 is electrically connected to the source of the LDMOSFET (n ⁺ type source region 211) via the p type punching layer 214, the p ⁺ type semiconductor region 215, the plug 224, the source electrode 231a, and the plug 224. Yes. The source back electrode 251 corresponds to the back electrode 2 b of the semiconductor chip 2. By extracting the source of the LDMOSFET from the source back electrode 251 (back electrode 2b), the inductance and resistance of the source can be reduced, which is advantageous for use at high frequencies.

  Thus, LDMOSFET circuits 31A1 and 31A2 corresponding to the amplifier stages 102A1 and 102A2 of the driver stage of the power amplifier circuit 102 are formed by the LDMOSFET elements (MISFET elements) formed on the semiconductor chip 2.

  FIG. 7 is another cross-sectional view of the main part of the semiconductor chip 2 and substantially corresponds to the cross-sectional view of the main part in the region from the Vcc pad 33b to the Vcc pad 33a through the wiring 36 in FIG.

  As shown in FIG. 7, an epitaxial layer 202 is formed on the main surface of the semiconductor substrate 201, an element isolation region 261 made of a buried oxide film or the like is formed on the main surface, and a silicon nitride film 221 is formed thereon. A silicon oxide film 222, an insulating film 232, a wiring 241 and a surface protective film 242 are formed. An opening 262 for bonding pad is formed in the surface protective film 242, and the bonding pad 33 is formed by the wiring 241 exposed from the opening 262. In FIG. 7, Vcc pads 33a and 33b are formed as bonding pads 33 by wiring 241 exposed from the opening 262 of the surface protective film 242, and the Vcc pads 33a and 33b are connected to the semiconductor chip 2 at a fixed potential (ground potential). , A power supply potential, Vcc) for supplying (inputting) a bonding pad.

  The plurality of Vcc pads 33a and 33b are electrically connected by a wiring 36 composed of the uppermost wiring 241. That is, the wiring 36 is a wiring for connecting the plurality of Vcc pads 33a and 33b, and is formed by the same conductor layer as the conductor layer (wiring 241) constituting the plurality of Vcc pads 33a and 33b. Yes. Accordingly, the plurality of Vcc pads 33a and 33b are electrically connected only by the same layer (a single layer) wiring layer (that is, the wiring 36 made of the wiring 241) without vias (plugs). Also, as shown in FIG. 7, no semiconductor element (active element) is formed immediately below (below) the wiring 36 connecting the plurality of Vcc pads 33a and 33b.

  The semiconductor chip 2 is formed with semiconductor integrated circuits such as the LDMOSFET circuits 31A1 and 31A2 and the control circuit block 32, and a plurality of bonding pads 33 electrically connected to these semiconductor integrated circuits. As shown, the plurality of bonding pads 33 and the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) are arranged (formed) on the outer peripheral portion (outer peripheral region, outer peripheral side, peripheral portion, peripheral region) of the semiconductor chip 2. Has been. The semiconductor chip 2 is also formed with a plurality of Vcc pads 33a and 33b having the same potential for supplying (inputting) a fixed potential (ground potential, power supply potential, Vcc) to the semiconductor chip 2 as bonding pads 33. The plurality of Vcc pads 33a and 33b are also arranged (formed) on the outer peripheral portion (the outer peripheral region, the outer peripheral side, the peripheral portion, and the peripheral region) of the semiconductor chip 2. For example, the Vcc pads 33a and 33b are disposed on two opposing sides of the semiconductor chip 2, respectively. Further, the plurality of Vcc pads 33a and 33b are electrically connected by the wiring 36 of the semiconductor chip 2, and the wiring 36 connecting the plurality of Vcc pads 33a and 33b is also the outer peripheral portion (outer peripheral region, It is arranged (formed) on the outer peripheral side, the peripheral part, and the peripheral region. The plurality of Vcc pads 33a and 33b are bonding pads (pad electrodes) for supplying a fixed potential (input), and the plurality of Vcc pads 33a and 33b are electrically connected by the wiring 36. 33a and 33b have the same potential, that is, bonding pads having the same potential.

  In FIG. 5, two Vcc pads 33 a and 33 b are formed on the semiconductor chip 2, and the two Vcc pads 33 a and 33 b are electrically connected by the wiring 36 that is an internal wiring of the semiconductor chip 2 to have the same potential. However, the number of Vcc pads connected by the wiring 36 is not limited to two, and three or more Vcc pads can be electrically connected by the wiring 36 to have the same potential. That is, three or more Vcc pads can be provided on the semiconductor chip 2 and these three or more Vcc pads can be electrically connected by the wiring 36 that is the internal wiring of the semiconductor chip 2 to have the same potential. In the present embodiment, the Vcc pads 33a and 33b for fixed potential supply (input) are exemplified as the bonding pads that are connected by the wiring 36 in the semiconductor chip 2 and have the same potential. However, high-frequency signals can be transmitted. If there is no bonding pad (no input or output), the same configuration as that of the plurality of Vcc pads 33a and 33b and the wiring 36 for connecting them to bonding pads other than the Vcc pads 33a and 33b. Can be applied. That is, a plurality of bonding pads that do not allow high-frequency signals to pass (not input or output) can be provided on the semiconductor chip 2 and these can be electrically connected by the wiring 36 to have the same potential.

  As described above, the plurality of Vcc pads 33a and 33b are electrically connected by the wiring 36 provided on the outer peripheral portion of the semiconductor chip 2, but the wiring 36 connecting the plurality of Vcc pads 33a and 33b. As shown in FIG. 5, it is provided on the side where the LDMOSFET circuits 31A1, 31A2 (amplification stages 102A1, 102A2) are not arranged in the outer peripheral portion of the semiconductor chip 2. That is, the wiring 36 is formed on the outer peripheral portion of the semiconductor chip 2 but is formed so as not to go around the outer peripheral portion of the semiconductor chip 2. In the outer peripheral portion of the semiconductor chip 2, the LDMOSFET circuits 31A1, 31A2 (amplification stages 102A1, 102A2 ) Is not formed on the side where the circuit is disposed, and the wiring 36 is formed on the side where the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) are not disposed.

  As shown in FIGS. 2 and 3, in the RF power module 1, the semiconductor chip 2 is mounted on the upper surface 4 a of the wiring substrate 4, and a plurality of bonding pads 33 (electrodes 2 a) of the semiconductor chip 2 are connected to the wiring substrate 4. A plurality of substrate-side terminals 12 are electrically connected via a plurality of bonding wires 8. A fixed potential supply terminal 12 a is also formed on the upper surface 4 a of the wiring substrate 4 as the substrate-side terminal 12. A terminal 12a for supplying a fixed potential on the wiring board 4 is a terminal for supplying (inputting) a fixed potential to the semiconductor chip 2 by being electrically connected to one of the plurality of Vcc pads 33a and 33b of the semiconductor chip 2. is there. In the present embodiment, the fixed potential supply terminal 12a of the wiring board 4 is bonded to a bonding pad that is close (closer or closest) to the terminal 12a among the plurality of Vcc pads 33a and 33b of the semiconductor chip 2. It is electrically connected via. In the RF power module 1 of FIG. 2, the Vcc pad 33 a is closer to the terminal 12 a of the wiring board 4 than the Vcc pad 33 b among the plurality of Vcc pads 33 a and 33 b of the semiconductor chip 2. 2 Vcc pads 33a are electrically connected to the terminals 12a of the wiring board 4 via the bonding wires 8, and the Vcc of the semiconductor chip 2 is connected to the fixed potential supply terminals 12a of the wiring board 4 via the bonding wires 8. A fixed potential (ground potential, power supply potential, Vcc) is supplied (input) to the pad 33a. Further, the bonding wire 8 is not connected to a bonding pad far from (more far from) the terminal 12a among the plurality of Vcc pads 33a and 33b of the semiconductor chip 2. In the RF power module 1 of FIG. 2, among the plurality of Vcc pads 33 a and 33 b of the semiconductor chip 2, the Vcc pad 33 b is farther from the fixed potential supply terminal 12 a of the wiring substrate 4 than the Vcc pad 33 a. Therefore, the bonding wire 8 is not connected to the Vcc pad 33b of the semiconductor chip 2.

  FIG. 8 is an explanatory diagram showing a digital mobile phone (mobile communication device) 50a using the RF power module of the present embodiment. FIG. 9 is an explanatory diagram showing another digital mobile phone (mobile communication device) 50b.

  As shown in FIGS. 8 and 9, in each of the digital mobile phones 50 a and 50 b, a baseband LSI 53 and a microcomputer 54 are mounted on a baseband portion 52 of a mother board (mounting board, mobile phone terminal motherboard) 51. The RF unit 55 includes a transmission / reception circuit 56, a SAW filter 57, a VCO (Voltage Controlled Oscillator) 58, and an RF power module 59. In the RF section 55 of the mother board 51, a transmission / reception circuit 56, a SAW filter 57, a VCO (Voltage Controlled Oscillator) 58 and an RF power module 59 are electrically connected by a Vcc line (power supply line) 60. The RF power module 59 corresponds to the RF power module 1 and RF power modules 1a and 1b described later. As described above, the RF power module 59 (that is, the RF power modules 1, 1a, and 1b) is a power amplification module as a transmission stage amplification high-frequency component mounted on a mobile phone, that is, power for a mobile communication device (mobile phone). Amplification module.

  The digital cellular phone 50a in FIG. 8 and the digital cellular phone 50b in FIG. 9 use a mother board 51 having different specifications. The transceiver circuit 56, SAW filter 57, VCO 58, and RF power module in the RF section 55 of the mother board 51 are used. 59 is located at different positions. In the mother board 51 of the digital mobile phone 50a of FIG. 8, a Vcc line 60 is provided on the right side of FIG. 8 with respect to the RF power module 59 and connected to the RF power module 59, and the mother board of the digital mobile phone 50b of FIG. In FIG. 51, a Vcc line 60 is disposed in the lower direction of FIG. 9 with respect to the RF power module 59 and connected to the RF power module 59. The fixed potential (ground potential, power supply potential, Vcc) input from the Vcc line 60 of the motherboard 51 to the RF power module 59 (external connection terminal thereof) is, for example, the wiring layer inside the wiring board 4 or the via hole 14. The signal is input to one of the plurality of Vcc pads 33 a and 33 b of the semiconductor chip 2 through the conductor film, the terminal 12 a and the bonding wire 8.

  When a plurality of customers assembling mobile phones use their own (different) motherboard 51, for example, in the case of FIG. 8 and FIG. 9, the terminals (Vcc) of the RF power module 59 corresponding to the specifications of the motherboard 51. There is a possibility that the position of the terminal) connected to the line 60 is changed. For this reason, when the original (different) motherboard 51 is used by a plurality of customers assembling the mobile phone, the relative positional relationship between the RF power module 59 mounted on the motherboard 51 and the Vcc line 60 of the motherboard 51. Accordingly, the position of the external connection terminal connected to the Vcc line 60 in the RF power module 59 is changed, and accordingly, the position of the fixed potential supply terminal 12a of the wiring board 4 constituting the RF power module is required to be changed. There is a possibility that.

  FIG. 10 is a conceptual top view (plan view) showing the structure of the RF power module 1a of another embodiment, and corresponds to FIG. Although FIG. 10 is a plan view, in order to make the drawing easy to see, the substrate side terminals 12 (including the terminals 12a) to which the bonding wires 8 are connected are hatched as in FIG.

  The RF power module 1 in FIG. 2 and the RF power module 1 a in FIG. 10 are different in the formation position of the fixed potential supply terminal 12 a on the upper surface 4 a of the wiring board 4. In the RF power module 1 of FIG. 2, the Vcc pad 33a of the semiconductor chip 2 is electrically connected to the fixed potential supply terminal 12a of the wiring substrate 4 via the bonding wire 8. In the RF power module 1 a, the Vcc pad 33 b of the semiconductor chip 2 is electrically connected to the fixed potential supply terminal 12 a of the wiring substrate 4 through the bonding wire 8. Since the other configuration of the RF power module 1a is almost the same as that of the RF power module 1, the description thereof is omitted here. Therefore, the RF power module 1a also has the same circuit configuration as the RF power module 1 (that is, the circuit configuration of FIG. 1).

  As described above, the position of the fixed potential supply terminal 12a of the wiring board 4 of the RF power module 1 may be changed according to the specifications of the mother board 51 on which the RF power module is mounted. 8 corresponds to the RF power module 1 shown in FIG. 2, and the RF power module 59 used in the digital mobile phone 50b shown in FIG. 9 corresponds to the RF power module 1a shown in FIG. It corresponds to.

  The RF power module 1 of FIG. 2 and the RF power module 1a of FIG. 10 use the same semiconductor chips 2 and 3. However, the RF power module 1 of FIG. 2 and the RF power module 1a of FIG. 10 are different in the position of the fixed potential supply terminal 12a of the wiring board 4, so that the fixed potential supply terminal 12a of the wiring board 4 is The plurality of Vcc pads 33a and 33b of the semiconductor chip 2 are electrically connected via bonding wires 8 to bonding pads that are close to (closer to or closest to) the terminal 12a. That is, in the RF power module 1 of FIG. 2, among the plurality of Vcc pads 33 a and 33 b of the semiconductor chip 2, the Vcc pad 33 a is closer to the fixed potential supply terminal 12 a of the wiring substrate 4 than the Vcc pad 33 b. Therefore, the Vcc pad 33a of the semiconductor chip 2 is electrically connected to the fixed potential supply terminal 12a of the wiring substrate 4 via the bonding wire 8. In the RF power module 1a of FIG. Among the plurality of Vcc pads 33a and 33b, the Vcc pad 33b is closer to the fixed potential supply terminal 12a of the wiring board 4 than the Vcc pad 33a. 4 is connected to a fixed potential supply terminal 12 a via a bonding wire 8.Therefore, in the RF power module 1 of FIG. 2, a fixed potential (ground potential, power supply potential, Vcc) is supplied from the fixed potential supply terminal 12 a of the wiring substrate 4 to the Vcc pad 33 a of the semiconductor chip 2 through the bonding wire 8. In the RF power module 1a shown in FIG. 10, the fixed potential (ground potential, power supply potential, and the like) is supplied from the fixed potential supply terminal 12a of the wiring board 4 to the Vcc pad 33b of the semiconductor chip 2 through the bonding wire 8. Vcc) is supplied (input). Further, in both the RF power module 1 and the RF power module 1a, bonding pads that are far from (more far from) the terminal 12a of the plurality of Vcc pads 33a and 33b of the semiconductor chip 2 (Vcc pads in the case of the RF power module 1). The bonding wire 8 is not connected to the RF power module 1a (corresponding to the Vcc pad 33a).

  Unlike this embodiment, when only one bonding pad (corresponding to the Vcc pads 33a and 33b in this embodiment) for supplying (inputting) a fixed potential to the semiconductor chip 2 is provided, for example, Vcc When only the Vcc pad 33a is provided without providing the pad 33b, the following problems may occur. That is, in the RF power module 1 (wiring board 4 used in FIG. 2), the fixed potential supply terminal 12a of the wiring board 4 and the Vcc pad 33a of the semiconductor chip 2 are relatively close to each other. Although it is easy to connect the fixed potential supply terminal 12a of the wiring board 4 and the Vcc pad 33a of the semiconductor chip 2 with the bonding wire 8, the RF power module 1a in FIG. Since the fixed potential supply terminal 12a of the wiring substrate 4 and the Vcc pad 33a of the semiconductor chip 2 are in a relatively separated positional relationship, it is necessary to perform wire bonding so as to straddle the semiconductor chip 2. It is easy to connect the terminal 12a for supplying a fixed potential of the substrate 4 and the Vcc pad 33a of the semiconductor chip 2 with the bonding wire 8. No. For this reason, in order to enable (easy) wire bonding between the fixed potential supply terminal 12a of the wiring board 4 and the Vcc pad 33a of the semiconductor chip 2, the fixed potential supply terminal 12a of the wiring board 4 is not provided. When changing the position, it is necessary to change the position of the Vcc pad 33a in the semiconductor chip 2 in accordance with the position of the terminal 12a of the wiring board 4. Whenever the position of the terminal 12a of the wiring board 4 used in the RF module is changed, the design of the semiconductor chip 2 is changed to change the position of the Vcc pad 33a in the semiconductor chip 2, so that the semiconductor chip 2 and the RF using the semiconductor chip 2 are changed. This will increase the manufacturing cost of the power module. In addition, when different mother boards 51 are used on each customer side for assembling a mobile phone, the RF power module mounted on the mother board 51 must be customized according to the specifications of the mother board 51 of the customer, and the arrangement of the Vcc line 60 of the mother board 51 is required. When the position of the terminal 12a of the wiring board 4 of the RF power module is changed according to the installation position or the like, the design of the semiconductor chip 2 must be changed to change the position of the Vcc pad 33a in the semiconductor chip 2. Changing the design of the semiconductor chip 2 used for the RF power module for each customer increases the development period of the RF power module and increases the cost of the RF power module.

  In contrast, in the present embodiment, a plurality of Vcc pads 33a and 33b for supplying (inputting) a fixed potential (ground potential, power supply potential, Vcc) to the semiconductor chip 2 are provided in the semiconductor chip 2, and the plurality of these The Vcc pads 33a and 33b are electrically connected via the wiring 36 of the semiconductor chip 2. Therefore, the plurality of Vcc pads 33a and 33b of the semiconductor chip 2 have the same potential, and any of the plurality of Vcc pads 33a and 33b may be electrically connected to the fixed potential supply terminal 12a of the wiring board 4. become. When the RF chip is manufactured by mounting the semiconductor chip 2 having such a configuration on the wiring board 4, the fixed potential supply terminal 12 a of the wiring board 4 is selected from the plurality of Vcc pads 33 a and 33 b of the semiconductor chip 2. Any Vcc pad (bonding pad) can be electrically connected. For this reason, a Vcc pad (bonding pad) that can be easily wire-bonded is selected from the plurality of Vcc pads 33 a and 33 b of the semiconductor chip 2, and the selected Vcc pad is bonded to the fixed potential supply terminal 12 a of the wiring board 4. It can be electrically connected via the wire 8. That is, a Vcc pad close to (closer to, the closest to) the terminal 12a among the plurality of Vcc pads 33a and 33b of the semiconductor chip 2 is selected, and the selected Vcc pad is used for supplying a fixed potential to the wiring board 4. It can be electrically connected to the terminal 12a through the bonding wire 8. Thus, a fixed potential can be supplied (input) from the fixed potential supply terminal 12a of the wiring board 4 to the selected Vcc pad via the bonding wire 8.

  For example, in the RF power module 1 of FIG. 2, among the plurality of Vcc pads 33 a and 33 b of the semiconductor chip 2, the Vcc pad 33 a is closer to the fixed potential supply terminal 12 a of the wiring board 4 than the Vcc pad 33 b. 10, it is easy to wire bond with the terminal 12 a of the wiring board 4, and the Vcc pad 33 a and the terminal 12 a of the wiring board 4 are electrically connected via the bonding wire 8. In the RF power module 1 a of FIG. Of the plurality of Vcc pads 33a and 33b of the semiconductor chip 2, the Vcc pad 33b is closer to the fixed potential supply terminal 12a of the wiring substrate 4 than the Vcc pad 33a. 12a is easily wire-bonded, and the Vcc pad 33b and the terminal 12a of the wiring board 4 It can be electrically connected through the bonding wires 8.

  As described above, in the present embodiment, since the plurality of Vcc pads 33 a and 33 b connected by the wiring 36 are provided in the semiconductor chip 2, the terminals of the wiring board 4 are connected from the plurality of Vcc pads 33 a and 33 b of the conductor chip 2. A Vcc pad (bonding pad) that is close to (a closer to, the closest to) 12 a and is easy to perform wire bonding is selected, and the bonding wire 8 is connected to the terminal 12 a for supplying a fixed potential of the wiring substrate 4 with the selected Vcc pad. Therefore, the wire bonding process can be performed easily and accurately. Further, even when the position of the fixed potential supply terminal 12a of the wiring board 4 is changed, a Vcc pad (bonding pad) that is close (closer to, closest) to the terminal 12a after the change and is easy to perform wire bonding is provided. Since a plurality of Vcc pads 33a and 33b can be selected and the selected Vcc pad can be electrically connected to the terminal 12a of the wiring board 4 via the bonding wire 8, the position of the terminal 12a of the wiring board 4 is determined. Accordingly, it is not necessary to change the positions of the Vcc pads 33a and 33b in the semiconductor chip 2. Therefore, it is not necessary to change the design of the semiconductor chip 2 even if the position of the terminal 12a of the wiring board 4 used in the RF module is changed, and the versatility of the semiconductor chip 2 used in the RF power module can be improved. RF power modules having various specifications can be manufactured using the same (common) semiconductor chip 2. Therefore, the manufacturing cost of the RF power module can be reduced. Even when a plurality of customers assembling mobile phones (mobile communication devices) use their own (different) motherboards 51 (for example, in the case of FIG. 8 and FIG. 9, the same (common) semiconductor) Using the chip 2, the RF power modules 1 and 1a corresponding to the mother board 51 having different specifications can be manufactured. This eliminates the need to change the design of the semiconductor chip 2 used for the RF power module for each customer, shortens the development period of the RF power module corresponding to the mother board 51 used on the customer side, and reduces the cost of the RF power module. it can. Further, if the Vcc pads 33a and 33b are arranged on the two opposite sides of the semiconductor chip 2 as shown in FIG. 5, the degree of freedom of the arrangement position of the terminal 12a on the wiring board 4 increases, and the wiring board 4 and RF power are increased. Module design becomes easier.

  In the present embodiment, the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) are arranged on the outer periphery of the semiconductor chip 2, and the plurality of bonding pads 33 including the plurality of Vcc pads 33a and 33b are also included in the semiconductor chip. 2, and a plurality of Vcc pads 33 a and 33 b are electrically connected by wiring 36 provided on the outer periphery of the semiconductor chip 2.

  Unlike the present embodiment, when the wiring 36 for connecting the plurality of Vcc pads 33a and 33b is provided in the central portion of the semiconductor chip 2, the following problems may occur. That is, a semiconductor integrated circuit such as the control circuit block 32 is formed at a relatively high density (high integration degree) in the central portion (circuit formation region) of the semiconductor chip 2 and wiring (wiring connected to the control circuit block 32) Etc.) is also formed at a relatively high density (high density), but it is necessary to form wirings 36 connecting the plurality of Vcc pads 33a and 33b while avoiding those wirings. This may increase the area, increase the number of wiring layers, and increase the cost of the semiconductor chip 2.

  On the other hand, in the present embodiment, the wiring 36 that connects the plurality of Vcc pads 33a and 33b is avoided from the central portion (circuit formation region) of the semiconductor chip 2, and the wiring has a high density (high density). Since it is provided on the outer periphery of the semiconductor chip 2 that is not formed, even if the wiring 36 for connecting the plurality of Vcc pads 33a and 33b is provided, the area of the semiconductor chip 2 is increased, the number of wiring layers is increased, etc. Therefore, the cost of the semiconductor chip 2 can be reduced. In the present embodiment, the wiring 36 for connecting the plurality of Vcc pads 33a and 33b is provided in the region between the bonding pad 33 and the guard ring 38 (that is, the region outside the bonding pad 33). The layout design is easy, and the design period of the semiconductor chip 2 can be shortened. Further, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is a central portion (circuit formation region) of the semiconductor chip 2 in which semiconductor integrated circuits such as the control circuit block 32 are formed at a relatively high density (high integration degree). ) Rather than on the semiconductor chip 2, no semiconductor element (active element) is formed immediately below (below) the wiring 36 connecting the plurality of Vcc pads 33a and 33b.

  Further, in the present embodiment, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is provided on the side where the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) are not disposed on the outer periphery of the semiconductor chip 2. It has been.

  Unlike the present embodiment, the wiring 36 for connecting the plurality of Vcc pads 33a and 33b is provided on the side where the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) are arranged on the outer periphery of the semiconductor chip 2. In this case, the wiring 36 and the LDMOSFET circuits 31A1 and 31A2 are close to each other. In a high-frequency amplifier circuit such as the LDMOSFET circuits 31A1 and 31A2, in order to amplify a high-frequency signal, if the wiring 36 connecting the plurality of Vcc pads 33a and 33b and the LDMOSFET circuits 31A1 and 31A2 are close to each other, There is a possibility that high-frequency noise is generated in the wiring 36 due to the interference or coupling (high-frequency noise is added to the wiring 36). When high-frequency noise is generated in the wiring 36, this supply is performed when a fixed potential is supplied from the fixed potential supply terminal 12 a of the wiring substrate 4 to any of the plurality of Vcc pads 33 a and 33 b via the bonding wire 8. High-frequency noise is added to the fixed potential, which is supplied to the control circuit block 32 via the Vcc wiring 34, which may cause a malfunction in the operation of the control circuit block 32. Further, in order to prevent high frequency noise from being generated in the wiring 36, it is necessary to form the wiring 36 connecting the plurality of Vcc pads 33a and 33b at a position away from the LDMOSFET circuits 31A1 and 31A2. May increase the area of the semiconductor chip 2 and increase the cost of the semiconductor chip 2.

  On the other hand, in the present embodiment, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is arranged on the side where the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) are arranged on the outer periphery of the semiconductor chip 2. Are provided on the side where the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) are not disposed in the outer peripheral portion of the semiconductor chip 2. Therefore, the wiring 36 connecting the plurality of Vcc pads 33a and 33b and the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) do not approach each other. In the present embodiment, LDMOSFET circuits 31A1, 31A2 (amplification stages 102A1, 102A2) are provided on the outer periphery of the semiconductor chip 2, a plurality of Vcc pads 33a, 33b are provided on the outer periphery of the semiconductor chip 2, and a plurality of Vcc pads 33a are provided. , 33b is provided on the side where the LDMOSFET circuits 31A1, 31A2 (amplification stages 102A1, 102A2) of the outer peripheral portion of the semiconductor chip 2 are not disposed, so that the wiring 36 and the LDMOSFET circuit in the semiconductor chip 2 are provided. 31A1 and 31A2 (amplification stages 102A1 and 102A2) are separated from each other without being close to each other, and even if a high frequency signal is amplified by the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2), a plurality of Vcc pads 33a and 33b are connected. High-frequency noise with wiring 36 that connects It never occurs. For this reason, when a fixed potential (ground potential, power supply potential, Vcc) is supplied from the fixed potential supply terminal 12a of the wiring board 4 to any of the plurality of Vcc pads 33a, 33b via the bonding wire 8, the semiconductor It is possible to prevent high-frequency noise from being added to the fixed potential supplied (input) to the chip 2, and to operate the control circuit block 32 (control circuit 103) more accurately. Therefore, the performance of the semiconductor chip 2 and the RF power module using the semiconductor chip 2 can be improved. Further, in the present embodiment, in the semiconductor chip 2, the wiring 36 connecting the plurality of Vcc pads 33a and 33b and the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) are not close to each other but separated from each other. When the wiring 36 is provided, it is not necessary to provide a space in consideration of interference between the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) and the wiring 36. For this reason, the area of the semiconductor chip 2 can be further reduced, and the cost of the semiconductor chip 2 and the RF power module using the semiconductor chip 2 can be further reduced.

  As described above, in the present embodiment, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is connected to the outer peripheral portion of the semiconductor chip 2 on the side where the LDMOSFET circuits 31A1 and 31A2 (amplification stages 102A1 and 102A2) are not formed. Are provided in the semiconductor element formation region and the wiring (in FIG. 5) through which the RF signal (high frequency signal) passes through the plurality of Vcc pads 33a and 33b which are bonding pads of the same potential and the wiring 36 connecting them. The LDMOSFET circuits 31A1 and 31A2 and bonding pads and wirings connected to the LDMOSFET circuits 31A1 and 31A2) can be arranged at positions away from each other. Can be prevented, the semiconductor chip 2 and It performance of the RF power module 1,1a can be improved using.

  In the present embodiment, in the semiconductor chip 2, the wiring 36 connecting the plurality of Vcc pads 33a, 33b is the same layer as the conductor layer (wiring 241) constituting the plurality of Vcc pads 33a, 33b. It is formed of a conductor layer. In other words, the plurality of Vcc pads 33a and 33b are electrically connected only by the wiring layer of the same layer (one layer) without vias (plug portions, conductor portions burying connection holes). Since the via causes manufacturing variations, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is formed in the same layer as the conductor layer constituting the plurality of Vcc pads 33a and 33b as in the present embodiment. By forming the conductive layer, the fixed potential supplied to the plurality of Vcc pads 33a and 33b can be stabilized. Further, in the present embodiment, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is not formed by the lower wiring layer (for example, the wiring layer in the same layer as the wiring 231), but rather than the lower wiring layer. Since the plurality of Vcc pads 33a and 33b, which are the uppermost wiring layer (wiring 241), are formed of the same conductive layer as the uppermost wiring layer (wiring 241), the space between the plurality of Vcc pads 33a and 33b is formed. It is possible to prevent parasitic resistance and the like from being generated in the wiring 36 to be connected, and the fixed potential supplied to the plurality of Vcc pads 33a and 33b can be further stabilized.

  In addition, the semiconductor chip for RF power module that requires low cost (corresponding to the semiconductor chip 2 here) is mainly a two-layer wiring (wirings 231 and 241). Unlike the present embodiment, a plurality of semiconductor chips are used. If the wiring 36 for connecting the Vcc pads 33a and 33b is provided so as to pass between the control circuit blocks 32 in the central portion of the semiconductor chip 2, the wiring 36 is configured by two-layer wiring (wirings 231 and 241). Therefore, it is necessary to connect the two-layer wiring with a plug, and an area for arranging the through hole is required in the central portion of the semiconductor chip 2 to increase the area of the semiconductor chip 2, and the through hole has a manufacturing variation. Since it is relatively large, there is a possibility that the manufacturing yield of the semiconductor chip 2 is reduced. In contrast, in the present embodiment, the wiring 36 for connecting the plurality of Vcc pads 33a and 33b is provided between the bonding pad 33 and the guard ring 38 (that is, the region outside the other bonding pads 33). The layout in the semiconductor chip 2 is easy, the design period of the semiconductor chip 2 can be shortened, and the conductor layer that is the same layer as the conductor layers constituting the plurality of Vcc pads 33a and 33b, that is, one wiring layer Since the wiring 36 can be formed by the (wiring 241), the area of the semiconductor chip 2 can be reduced, and the manufacturing yield of the semiconductor chip 2 can be improved.

  The RF power module 1 or the RF power module 1a of the present embodiment can be manufactured by the following method, for example.

  FIGS. 11-14 is principal part sectional drawing in the manufacturing process of RF power module 1 or RF power module 1a which is one embodiment of this invention. 15 and 17 are main part plan views (top view) during the manufacturing process of the RF power module 1, and FIGS. 16 and 18 are main part plan views (top view) during the manufacturing process of the RF power module 1a. ). 15 and FIG. 16 correspond to the same process step, and the process step corresponding to FIG. 12, that is, the state before performing the wire bonding process is shown. FIG. 17 and FIG. 18 correspond to the same process step, and the process step corresponding to FIG. 13, that is, the state after performing the wire bonding process is shown. 15 to 18 are plan views, but in order to make the drawings easy to see, the substrate-side terminals 12 (including the terminals 12a) to which the bonding wires 8 are connected are hatched in the same way as in FIGS. It is.

  First, as shown in FIG. 11, the wiring board 4 is prepared. The wiring board 4 can be manufactured using, for example, a build-up method, a printing method, a sheet lamination method, or the like. As described above, a plurality of substrate-side terminals 12 including the fixed potential supply terminals 12a are formed on the upper surface 4a of the wiring substrate 4. In addition, the semiconductor chips 2 and 3 and the passive component 5 to be mounted on the wiring board 4 are also prepared. Since the configurations of the semiconductor chips 2 and 3 are as described above, the description thereof is omitted here.

  Next, as shown in FIGS. 12, 15, and 16, bonding materials 16 and 17 such as solder are printed or printed on the region where the semiconductor chips 2 and 3 and the passive component 5 on the upper surface 4 a of the wiring substrate 4 are to be mounted. After the application, the semiconductor chips 2 and 3 and the passive component 5 are mounted on the upper surface 4 a of the wiring substrate 4. Then, a solder reflow process or the like is performed, and the semiconductor chips 2 and 3 and the passive component 5 are fixed to the wiring board 4 via bonding materials 16 and 17 such as solder.

  Next, as shown in FIGS. 13, 17, and 18, a wire bonding process is performed, and a plurality of electrodes 2 a, 3 a on the surface of the semiconductor chips 2, 3 and a plurality of substrates on the upper surface 4 a of the wiring substrate 4. The terminal 12 is electrically connected through a plurality of bonding wires 8.

  In the wire bonding process, the Vcc pads to be connected to the terminals 12a of the wiring board 4 from the plurality of Vcc pads 33a and 33b of the semiconductor chip 2 in accordance with the positions of the fixed potential supply terminals 12a on the upper surface 4a of the wiring board 4. (Bonding pad) is selected, and the selected Vcc pad and the terminal 12a of the wiring board 4 are electrically connected through the bonding wire 8. At this time, a Vcc pad (bonding pad) close to (closer to or closest to) the terminal 12a of the wiring board 4 among the plurality of Vcc pads 33a and 33b of the semiconductor chip 2 is selected, and the selected Vcc pad and wiring board are selected. 4 terminals 12a are electrically connected via bonding wires 8. Accordingly, the Vcc pad close to (closer to, the closest to) the terminal 12a of the wiring board 4 among the plurality of Vcc pads 33a, 33b of the semiconductor chip 2 and the terminal 12a of the wiring board 4 are electrically connected via the bonding wires 8. The bonding wire 8 is not connected to the Vcc pad far from the terminal 12a of the wiring board 4 among the plurality of Vcc pads 33a and 33b. For example, in FIG. 15, among the plurality of Vcc pads 33 a and 33 b of the semiconductor chip 2, the Vcc pad 33 a is closer to the fixed potential supply terminal 12 a of the wiring substrate 4 than the Vcc pad 33 b. As shown in FIG. 17, the Vcc pad 33 a and the terminal 12 a of the wiring board 4 are electrically connected through the bonding wire 8. In the case of FIG. 16, among the plurality of Vcc pads 33 a and 33 b of the semiconductor chip 2, the Vcc pad 33 b is closer to the fixed potential supply terminal 12 a of the wiring substrate 4 than the Vcc pad 33 a. Therefore, as shown in FIG. 18, the Vcc pad 33 b and the terminal 12 a of the wiring board 4 are electrically connected via the bonding wire 8.

  As described above, in the wire bonding step, depending on the position of the fixed potential supply terminal 12a on the upper surface 4a of the wiring substrate 4, the Vcc pads that are easily wire-bonded from the plurality of Vcc pads 33a and 33b of the semiconductor chip 2, That is, a Vcc pad close to (closer to, the closest to) the terminal 12 a is selected as a Vcc pad to be connected to the terminal 12 a of the wiring board 4, and the selected Vcc pad is used as the fixed potential supply terminal 12 a of the wiring board 4. Electrical connection is made via the bonding wire 8. Thereby, the fixed potential supply (input) bonding pad (Vcc pad) of the semiconductor chip 2 and the fixed potential supply terminal 12 a of the wiring substrate 4 can be easily and accurately connected via the bonding wire 8. .

  Next, as shown in FIG. 14, the sealing resin 6 is formed on the upper surface 4 a of the wiring substrate 4 so as to cover the semiconductor chips 2 and 3, the passive component 5 and the bonding wire 8. The sealing resin 6 can be formed by using, for example, a printing method or a mold for molding (for example, transfer mold). In the case of manufacturing a plurality of RF power modules from one wiring board 4, after the formation of the sealing resin 6, the wiring board 4 and the sealing resin 6 are divided at predetermined positions, and the RF power modules as individual pieces are obtained. Obtainable.

(Embodiment 2)
In the first embodiment, the RF power module 1 has one power amplification circuit 102. In the present embodiment, the RF power module 1b has two power amplification circuits 102B and 102C. is doing.

  In the present embodiment, for example, a power amplification module such as an RF power module used in a digital mobile phone (mobile communication device) that transmits information using a network such as a GSM system, and a semiconductor element (semiconductor) mounted thereon Device, semiconductor chip).

  Here, GSM (Global System for Mobile Communication) refers to one or standard of a wireless communication method used for digital mobile phones. GSM has three frequency bands of radio waves to be used: 900 MHz band is GSM900 or simply GSM, 1800 MHz band is GSM1800 or DCS (Digital Cellular System) 1800 or PCN, 1900 MHz band is GSM1900 or DCS1900 or PCS (Personal Communication Services) ). GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may also be used. The RF power module 1b according to the present embodiment is an RF power module (power amplification module) used in these frequency bands (high frequency bands), for example.

  FIG. 19 shows the amplification constituting the RF power module (HPA (High Power Amplifier), power amplification module, power amplifier module, high frequency power amplification module, power amplifier module, high frequency power amplification device, electronic device) 1b of this embodiment. The circuit block diagram of a circuit is shown. In this figure, for example, two frequency bands of GSM900 and DCS1800 can be used (dual band system), and GMSK (Gaussian filtered Minimum Shift Keying) modulation system and EDGE (Enhanced Data GSM Environment) modulation system in each frequency band. The circuit block diagram (amplifier circuit) of the RF power module 1b that can use the two communication methods is shown.

  As shown in FIG. 19, the RF power module 1b of the present embodiment has a circuit configuration of GSM900 (transmission frequency band is 0.9 GHz band, which includes three amplification stages (amplification circuit, amplifier) 102B1, 102B2, and 102B3, That is, a DCS1800 (transmission frequency band is 1.8 GHz band) including a power amplifier circuit (first system power amplifier circuit) 102B for three-stage amplifiers (amplifier, amplifier circuit) 102C1, 102C2, and 102C3, for 824 to 915 MHz) That is, a power amplifier circuit (second system power amplifier circuit) 102C for 1710-1910 MHz), a control circuit (peripheral circuit) 103a for controlling and assisting the amplification operation of these power amplifier circuits 102B and 102C, and for GSM900 Matching circuit (input matching between the input terminal 104b and the power amplifier circuit 102B Path) 105B, a matching circuit (input matching circuit) 105C between DCS 1800 input terminal 104c and power amplifier circuit 102C, a matching circuit (output matching circuit) 107B between output terminal 106b and power amplifier circuit 102B for GSM900, and It has a low-pass filter 108B, a matching circuit (output matching circuit) 107C and a low-pass filter 108C between the output terminal 106c for DCS 1800 and the power amplifier circuit 102C. Further, an interstage matching circuit (interstage matching circuit) 102BM1 is provided between the amplification stage 102B1 and the amplification stage 102B2 of the power amplification circuit 102B for GSM900, and between the amplification stage 102B2 and the amplification stage 102B3. An interstage matching circuit (interstage matching circuit) 102BM2 is provided, and an interstage matching circuit (interstage matching circuit) is provided between the amplification stage 102C1 and the amplification stage 102C2 of the power amplification circuit 102C for the DCS 1800. 102CM1 is provided, and an interstage matching circuit (interstage matching circuit) 102CM2 is provided between the amplification stage 102C2 and the amplification stage 102C3. As in the first embodiment, each matching circuit is a circuit that performs impedance matching, and the low-pass filters 108B and 108C are circuits that attenuate harmonics.

  In the first embodiment, the RF power module 1 has one power amplification circuit 102, and this power amplification circuit 102 is a multistage in which three amplification stages 102A1 to 102A3 are connected (multistage connection, multistage connection). The first and second amplification stages 102A1 and 102A2, which have a configuration (multi-stage configuration) and are driver stages (prior to the output stage), are n-channel LDMOSFETs formed in the semiconductor chip 2. The third amplification stage 102A3, which is an output stage (final stage), formed by such a MISFET element, is formed by an HBT element formed in another semiconductor chip 3. The RF power module 1b according to the present embodiment includes two systems of power amplification circuits 102B and 102C for GSM900 (0.9 GHz band) and DCS1800 (1.8 GHz band) for higher frequency bands. Each of the power amplification circuits 102B and 102C has a multistage configuration (multistage configuration) in which three amplification stages are connected (multistage connection, multistage connection), and a driver stage (output stage (final stage)) of the power amplification circuit 102B. The first and second amplification stages 102B1 and 102B2 and the driver stage of the power amplification circuit 102C (the previous stage (the amplification stage) than the output stage (final stage)). The first and second amplification stages 102C1 and 102C2 are formed by MISFET elements such as n-channel type LDMOSFETs formed in the semiconductor chip 2, The third amplification stage 102B3, which is the output stage (final stage) of the force amplification circuit 102B, and the third amplification stage 102C3, which is the output stage (final stage) of the power amplification circuit 102C, are in the other semiconductor chip 3. The HBT element is formed.

  As described above, the RF power module 1b according to the present embodiment is a power amplification module having two power amplification circuits 102B and 102C having a multi-stage configuration (multi-stage configuration), and the amplification constituting the power amplification circuits 102B and 102C. The stages 102B1 to 102B3 and 102C1 to 102C3 are not composed of one semiconductor chip, but are composed of two semiconductor chips 2 and 3, and the amplification stages 102B3 and 102C3 of the output stage that most affect the efficiency are formed on the semiconductor chip 3. By configuring the amplifier stages 102B1, 102B2, 102C1, and 102C2 of the driver stage, which are formed of the HBT, and having relatively little influence on the efficiency, by using the LDMOSFET formed on the semiconductor chip 2, high efficiency (high amplification factor) and low cost are achieved. And compatibility with low noise.

  The control circuit 103a corresponds to the control circuit 103 of the first embodiment. The control circuit 103a receives a control signal, and based on the input control signal, the amplification stages 102B1 to 102B3 and 102C1 of the power amplification circuits 102B and 102C. ˜102 C3. The control circuit 103a of the present embodiment inputs a control signal for controlling the amplification stages 102B1 to 102B3 of the power amplification circuit 102B and a control signal for controlling the amplification stages 102C1 to 102C3 of the power amplification circuit 102C, respectively. When the power amplifier circuit 102B is used, the power amplifier circuit 102B is controlled based on the GSM control signal input from the input terminal (control signal input terminal) 110b, and the power amplifier circuit When 102C is used, the power amplifying circuit 102C is controlled based on a DCS control signal input from an input terminal (control signal input terminal) 110c. The control circuit 103a is composed of, for example, a MISFET element and a passive element, and the control signal, fixed potential, and the like are input to the control circuit 103a as necessary.

  An RF input signal (RF transmission signal) input to the input terminal 104b for GSM900 of the RF power module 1b is input to the semiconductor chip 2 through the matching circuit 105B, and is input to the two amplification stages 102B1 and 102B2 in the semiconductor chip 2. Amplified and output from the semiconductor chip 2, is input to the semiconductor chip 3 through the matching circuit 102BM2, is amplified by the amplification stage 102B3 in the semiconductor chip 3, is output from the semiconductor chip 3, and passes through the matching circuit 107B and the low-pass filter 108B. An RF output signal (amplified RF transmission signal) is output from the output terminal 106b. When the matching circuit 102BM1 is formed by the passive component 5 outside the semiconductor chip 2, the RF signal that is input to the semiconductor chip 2 and amplified by the amplification stage 102B1 is output once from the semiconductor chip 2 and is then matched. The signal is again input to the semiconductor chip 2 via the 102BM1, and then amplified by the amplification stage 102B2, and then output from the semiconductor chip 2. The RF signal output from the semiconductor chip 2 is input to the semiconductor chip 3 via the matching circuit 102BM2. The An RF input signal (RF transmission signal) input to the DCS 1800 input terminal 104c of the RF power module 1b is input to the semiconductor chip 2 through the matching circuit 105C, and is input to the two amplification stages 102C1 and 102C2 in the semiconductor chip 2. Amplified and output from the semiconductor chip 2, is input to the semiconductor chip 3 through the matching circuit 102CM2, is amplified by the amplification stage 102C3 in the semiconductor chip 3, is output from the semiconductor chip 3, and passes through the matching circuit 107C and the low-pass filter 108C. An RF output signal (amplified RF transmission signal) is output from the output terminal 106c. When the matching circuit 102CM1 is formed by the passive component 5 outside the semiconductor chip 2, the RF signal that is input to the semiconductor chip 2 and amplified by the amplification stage 102C1 is once output from the semiconductor chip 2 and then the matching circuit. The signal is input to the semiconductor chip 2 again through 102CM1, and then amplified by the amplification stage 102C2 and then output from the semiconductor chip 2. The RF signal output from the semiconductor chip 2 is input to the semiconductor chip 3 through the matching circuit 102CM2. The

  Although an HBT element is formed on the semiconductor chip 3 as shown in FIG. 4, the description thereof is omitted here.

  FIG. 20 is a plan view (planar layout diagram) of the semiconductor chip 2 of the present embodiment, showing an example of circuit arrangement of the semiconductor chip 2, and corresponds to FIG. 5 of the first embodiment. Although FIG. 20 is a plan view, the LDMOSFET circuits 31B1, 31B2, 31C1, and 31C2, the bonding pad 33, the Vcc pads 33a and 33b, the Vcc wiring 34, and the wiring 36 are hatched for easy understanding of the drawing. It is.

  As shown in FIG. 20, the semiconductor chip 2 of the present embodiment includes an LDMOSFET circuit (LDMOSFET circuit region, LDMOSFET formation region, high-frequency amplification transistor region, amplification element formation region) 31B1 corresponding to the amplification stage 102B1. An LDMOSFET circuit 31B2 corresponding to the amplification stage 102B2, an LDMOSFET circuit 31C1 corresponding to the amplification stage 102C1, an LDMOSFET circuit 31C2 corresponding to the amplification stage 102C2, and a control circuit block 32 are provided. The control circuit block 32 corresponds to the control circuit 103a and the like. A plurality of bonding pads (pad electrodes) 33 are formed on the surface of the semiconductor chip 2. The plurality of bonding pads 33 are a plurality of Vcc pads (bonding pads, pad electrodes) 33 a and 33 b (a plurality of first pads) for supplying (inputting) a fixed potential (ground potential, power supply potential, Vcc) to the semiconductor chip 2. Pad electrode). For example, in FIG. 20, two Vcc pads 33 a and 33 b are formed on the semiconductor chip 2.

  Although LDMOSFET elements are formed in the LDMOSFET circuits 31B1, 31B2, 31C1, and 31C2 of the semiconductor chip 2 as shown in FIG. 6, the description thereof is omitted here. Also in this embodiment, the cross-sectional view of the region from the Vcc pad 33b of the semiconductor chip 2 to the Vcc pad 33a through the wiring 36 is the same as that in FIG.

  Further, in the semiconductor chip 2, the regions where the LDMOSFET circuits 31B1, 31B2, 31C1, 31C2 are formed and the regions where the control circuit blocks 32 are formed are elements composed of buried oxide films formed between the regions. Each isolation region is electrically isolated from other regions. Further, between the LDMOSFET circuits 31B1, 31B2, 31C1, 31C2 and the control circuit block 32, and between the LDMOSFET circuits 31B1, 31B2, 31C1, 31C2, and the control circuit block 32 and the bonding pad 33, the semiconductor chip 2 is provided as necessary. It is electrically connected by internal wiring.

  For example, the Vcc pad 33a or the Vcc pad 33b is electrically connected to a circuit in the control circuit block 32 via the Vcc wiring 34, and the fixed potential input to the Vcc pad 33a or the Vcc pad 33b is Vcc. The circuit is supplied to the circuit in each control circuit block 32 through the wiring 34. Further, the control circuit blocks 32 of the semiconductor chip 2 are electrically connected by wiring 35 as necessary. The plurality of Vcc pads 33a and 33b are electrically connected by wirings 36 formed on the semiconductor chip 2. Since the plurality of Vcc pads 33a and 33b are electrically connected by the wiring 36, the plurality of Vcc pads 33a and 33b are bonding pads (pad electrodes) having the same potential. Since the plurality of Vcc pads 33a and 33b are electrically connected by the wiring 36 and have the same potential, if a fixed potential is inputted to any of the plurality of Vcc pads 33a and 33b, the inputted fixed potential is changed to Vcc. It can be supplied to the circuit in each control circuit block 32 via the wiring 34.

  Also in the present embodiment, as in the first embodiment, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is the same conductor as the conductor layer constituting the plurality of Vcc pads 33a and 33b. A semiconductor element (active element) is not formed immediately below (below) the wiring 36 that is formed of layers and connects the plurality of Vcc pads 33a and 33b.

  As shown in FIG. 20, also in the present embodiment, LDMOSFET circuits 31B1, 31B2, 31C1, and 31C2 (amplification stages 102B1, 102B2, 102C1, and 102C2) are semiconductors as in the first embodiment. A plurality of bonding pads 33 including a plurality of Vcc pads 33a and 33b are also disposed on the outer peripheral portion of the semiconductor chip 2 and disposed on the outer peripheral portion of the chip 2 (peripheral region, outer peripheral side, peripheral portion, peripheral region). A wiring 36 for connecting the Vcc pads 33a and 33b is also provided on the outer periphery of the semiconductor chip 2. For example, the Vcc pads 33a and 33b are disposed on two opposite sides of the semiconductor chip 2, respectively. A guard ring 38 made of a wiring layer (internal wiring layer) of the semiconductor chip 2 is formed on the outermost periphery of the semiconductor chip 2, and the wiring 36 connecting the plurality of Vcc pads 33a and 33b is as follows. It is provided in a region between the bonding pad 33 and the guard ring 38 (that is, a region outside the bonding pad 33).

  As in the first embodiment, in FIG. 20, two Vcc pads 33 a and 33 b are formed on the semiconductor chip 2, and the two Vcc pads 33 a and 33 b are formed by a wiring 36 that is an internal wiring of the semiconductor chip 2. Although they are electrically connected to have the same potential, three or more Vcc pads can be electrically connected by the wiring 36 to have the same potential. In addition, the bonding pads other than the Vcc pads 33a and 33b are connected to the plurality of Vcc pads 33a and 33b and the bonding pads other than the Vcc pads 33a and 33b as long as they are bonding pads that do not allow high-frequency signals to pass (not input or output). A configuration similar to that of the wiring 36 can be applied.

  In the present embodiment, as described above, the LDMOSFET circuits 31B1, 31B2, corresponding to the amplifier stages of the driver stages of the two power amplifier circuits 102B, 102C for the GSM900 and for the DCS1800 for higher frequency bands are used. 31C1 and 31C2 are formed on the outer peripheral portion of the semiconductor chip 2, a plurality of Vcc pads 33a and 33b are formed on the outer peripheral portion of the semiconductor chip 2, and a wiring 36 connecting the plurality of Vcc pads 33a and 33b is also formed on the semiconductor chip 2. Although formed on the outer peripheral portion, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is connected to the amplification stages 102C1 and 102C2 (LDMOSFET circuits 31C1 and 31C2) of the DCS1800 power amplifier circuit 102C on the outer peripheral portion of the semiconductor chip 2. ) Is provided on the side where it is not arranged. That is, among the amplification stages of the two power amplification circuits 102B and 102C formed on the semiconductor chip 2, the amplification stages 102C1 and 102C2 constituting the power amplification circuit 102C for a higher frequency band (here, for DCS 1800) A wiring 36 for connecting the plurality of Vcc pads 33a and 33b is provided on the outer peripheral portion of the semiconductor chip 2 on the side where it is not disposed. Accordingly, the wiring 36 is formed on the outer peripheral portion of the semiconductor chip 2, but is formed so as not to go around the outer peripheral portion of the semiconductor chip 2, and in the outer peripheral portion of the semiconductor chip 2, the power amplifier circuits 102B and 102C of the two systems Is not formed on the side where the LDMOSFET circuits 31C1 and 31C2 (amplification stages 102C1 and 102C2) constituting the power amplifier circuit 102C for the higher frequency band (DCS1800 in this case) are disposed. A wiring 36 is formed on the side where 31C1 and 31C2 (amplification stages 102C1 and 102C2) are not disposed.

  When the wiring MOSFETs 36 cannot be disposed by avoiding all the LDMOSFET circuits 31B1, 31B2, 31C1, and 31C2 (amplification stages 102B1, 102B2, 102C1, and 102C2) for GSM900 and DCS1800 (for example, as shown in FIG. 20) When the Vcc pads 33a and 33b are formed on the two opposite sides of the semiconductor chip 2, the wirings 36 connecting the plurality of Vcc pads 33a and 33b are LDMOSFET circuits 31C1 and 31C2 (higher than the outer peripheral portion of the semiconductor chip 2). The LDMOSFET circuits 31B1 and 31B2 (lower frequency band amplification stages 102B1 and 102B2) on the outer periphery of the semiconductor chip 2 are disposed without being provided on the side where the frequency band amplification stages 102C1 and 102C2) are disposed. Provide on the side.

  Unlike the present embodiment, the wirings 36 connecting the plurality of Vcc pads 33a and 33b are disposed by the LDMOSFET circuits 31C1 and 31C2 (the amplification stages 102C1 and 102C2 for higher frequency bands) on the outer periphery of the semiconductor chip 2. In the case where it is provided on the opposite side, the wiring 36 connecting the plurality of Vcc pads 33a and 33b and the LDMOSFET circuits 31C1 and 31C2 (the amplification stages 102C1 and 102C2 for higher frequency bands) are close to each other. If the wiring 36 connecting the plurality of Vcc pads 33a and 33b is close to an amplifier circuit (LDMOSFET circuits 31C1 and 31C2) for amplifying a high-frequency signal, high-frequency noise is generated in the wiring 36 due to electromagnetic interference or coupling. However, this phenomenon becomes more remarkable as the frequency of the high-frequency signal amplified by the amplifier circuit is higher. Therefore, when the wiring 36 is provided on the side where the amplification stages 102C1 and 102C2 (LDMOSFET circuits 31C1 and 31C2) for the DCS 1800 are disposed, high-frequency noise is likely to be generated in the wiring 36, and the fixed potential supply terminal 12a of the wiring board 4 is used. When a fixed potential is supplied to any of the plurality of Vcc pads 33 a and 33 b via the bonding wire 8, high frequency noise is added to the supplied fixed potential, and this is added to the control circuit block 32 via the Vcc wiring 34. May cause a malfunction in the operation of the control circuit block 32. In order to prevent high-frequency noise from being generated in the wiring 36, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is connected to the LDMOSFET circuits 31C1 and 31C2 (the amplification stages 102C1 and 102C2 for higher frequency bands). If it is formed at a distant position, the area of the semiconductor chip 2 increases, which may increase the cost of the semiconductor chip 2 and the RF power module using the semiconductor chip 2.

  In contrast, in the present embodiment, two power amplifier circuits 102B and 102C for GSM900 and DCS1800 are provided on the semiconductor chip 2, but the higher frequency of the two power amplifier circuits 102B and 102C. The wiring 36 is provided on the side where the amplification stages 102C1 and 102C2 (LDMOSFET circuits 31C1 and 31C2) constituting the power amplification circuit 102C for the DCS 1800 for amplifying the high frequency signal of the band are not disposed. Therefore, the wiring 36 connecting the plurality of Vcc pads 33a and 33b and the LDMOSFET circuits 31C1 and 31C2 (amplification stages 102C1 and 102C2) for the DCS 1800 do not approach each other.

  In the present embodiment, LDMOSFET circuits 31B1, 31B2, 31C1, and 31C2 (amplification stages 102B1, 102B2, 102C1, and 102C2) for GSM900 and DCS1800 are provided on the outer periphery of the semiconductor chip 2, and a plurality of Vcc pads 33a and 33b are provided. Wirings 36 are provided on the outer peripheral portion of the semiconductor chip 2 and are provided on the outer peripheral portion of the semiconductor chip 2 so as to connect the plurality of Vcc pads 33a and 33b. Of the amplification stages 102B1 and 102B2 (LDMOSFET circuits 31B1 and 31B2) for GSM900 and the amplification stages 102C1 and 102C2 (LDMOSFET circuits 31C1 and 31C2) for DCS1800 formed on the semiconductor chip 2, the surroundings are easily affected by high-frequency noise. These are amplification stages 102C1 and 102C2 (LDMOSFET circuits 31C1 and 31C2) for DCS 1800 that amplify a high-frequency signal in a higher frequency band. For this reason, in the present embodiment, the wiring 36 is provided on the side where the amplification stages 102C1 and 102C2 (LDMOSFET circuits 31C1 and 31C2) for the DCS 1800 are not arranged, so that the wiring 36 and the amplification for the DCS 1800 in the semiconductor chip 2 are provided. The stages 102C1 and 102C2 (LDMOSFET circuits 31C1 and 31C2) are separated from each other without being close to each other. Therefore, even if the high frequency signal is amplified by the amplification stages 102C1 and 102C2 (LDMOSFET circuits 31C1 and 31C2) for the DCS 1800, no high frequency noise is added to the wiring 36 therefrom. As a result, when a fixed potential (ground potential, power supply potential, Vcc) is supplied to any of the plurality of Vcc pads 33a and 33b, it is possible to suppress or prevent high frequency noise from being added to the supplied fixed potential. Since the circuit block 32 can be operated more accurately, the performance of the RF power module can be improved.

  Further, in this embodiment, when all of the LDMOSFET circuits 31B1, 31B2, 31C1, and 31C2 (amplification stages 102B1, 102B2, 102C1, and 102C2) for GSM900 and DCS1800 are avoided and the wiring 36 cannot be disposed, FIG. As shown in FIG. 3, the wiring 36 connecting the plurality of Vcc pads 33a and 33b is on the side where the amplification stages 102C1 and 102C2 (LDMOSFET circuits 31C1 and 31C2) for the DCS 1800 on the outer peripheral portion of the semiconductor chip 2 are arranged. Instead, it is provided on the side where the GSM 900 amplification stages 102B1 and 102B2 (LDMOSFET circuits 31B1 and 31B2) are arranged on the outer periphery of the semiconductor chip 2. That is, among the amplifier circuit for GSM900 (amplification stages 102B1 and 102B2) and the amplifier circuit for DCS1800 (amplification stages 102C1 and 102C2) formed in the semiconductor chip 2, the surroundings are likely to be affected by high-frequency noise (that is, more Avoid the side where the amplifying circuit (amplification stage 102C1, 102C2) for DCS1800 (amplifying high frequency signals in a high frequency band) is placed, and hardly affect the surroundings by high frequency noise (that is, high frequency signals in a lower frequency band) The wiring 36 is provided on the side where the amplification circuit (amplification stages 102B1 and 102B2) for GSM900 is arranged. For this reason, high-frequency noise is less likely to occur in the wiring 36 connecting the plurality of Vcc pads 33a and 33b. As a result, when a fixed potential (ground potential, power supply potential, Vcc) is supplied to any of the plurality of Vcc pads 33a and 33b, it is possible to suppress or prevent high frequency noise from being added to the supplied fixed potential. The circuit block 32 (control circuit 103) can be operated more accurately. Therefore, the performance of the RF power module can be improved. In addition, as compared with the case where the wiring 36 is provided on the side where the amplifier circuit for DCS 1800 (amplification stages 102C1 and 102C2) is disposed, the amplifier circuit for GSM900 (amplification stages 102B1 and 102B2) as shown in FIG. When the wiring 36 is provided on the side where the wiring is disposed, the position of the wiring 36 can be brought closer to the amplifier circuit (here, the amplification stages 102B1 and 102B2) because the high-frequency noise is less likely to be generated in the wiring 36. The area can be further reduced, and the cost of the semiconductor chip 2 and the RF power module using the semiconductor chip 2 can be further reduced.

  In the present embodiment, the amplification stages 102B1 to 102B3 and 102C1 to 102C3 constituting the power amplification circuits 102B and 102C are not constituted by one semiconductor chip, but are constituted by the two semiconductor chips 2 and 3, and the output stage. The amplification stages 102B3 and 102C3 of (final stage) are formed on the semiconductor chip 3, and the amplification stages 102B1, 102B2, 102C1 and 102C2 of driver stages (prior to the final stage) are formed on the semiconductor chip 2.

  Unlike this embodiment, when not only the driver stage amplification stages 102B1, 102B2, 102C1, and 102C2 but also the output stage amplification stages 102B3 and 102C3 are formed by the LDMOSFET circuit formed on the semiconductor chip 2, as described above. If the wiring 36 is provided on the side where the amplifier circuit for GSM900 (amplification stages 102B1, 102B2, 102B3) for amplifying a high frequency signal in a lower frequency band is provided, the output stage (final) of the power amplifier circuit 102B for GSM900 The wiring 36 comes close to the amplification stage 102B3. As compared with the driver stage amplifier stages 102B1, 102B2, 102C1, and 102C2, the output stage amplifier stages 102B3 and 102C3 are more likely to be affected by high frequency noise in the surroundings because a high-frequency signal with higher power flows. For this reason, even if the wiring 36 is provided on the side where the amplification circuit for GSM900 (amplification stages 102B1, 102B2, and 102B3) that amplifies a high frequency signal in a lower frequency band is provided, the influence of high frequency noise on the periphery is given. Since the wiring 36 is close to the amplification stage 102B3 which is easy to output, noise is likely to be generated in the wiring 36 connecting the plurality of Vcc pads 33a and 33b. Further, if the wiring 36 is formed at a position away from the amplification circuit for GSM900 (amplification stages 102B1, 102B2, 102B3) in order to suppress the influence of high-frequency noise from the amplification stage 102B3 to the wiring 36, the semiconductor chip 2 There is a possibility that the cost of the semiconductor chip 2 and the RF power module using the same will increase.

  On the other hand, in the present embodiment, among the amplification stages 102B1 to 102B3 and 102C1 to 102C3 constituting the power amplification circuits 102B and 102C for GSM900 and DCS1800, the amplification stage 102B1 in the driver stage (the stage before the final stage). , 102B2, 102C1, and 102C2 are formed on the semiconductor chip 2, but the amplification stages 102B3 and 102C3 of the output stage (final stage) through which a high-frequency signal with higher power flows are formed on the other semiconductor chip 3. Therefore, the wiring 36 connecting the plurality of Vcc pads 33a and 33b of the semiconductor chip 2 does not come close to the amplification stages 102B3 and 102C3 of the output stages of the power amplification circuits 102B and 102C for GSM900 and DCS1800. Accordingly, the wiring 36 connecting the plurality of Vcc pads 33a and 33b can be accurately prevented from being influenced by high frequency noise from the amplification stages 102B3 and 102C3 of the output stage (final stage). As a result, when a fixed potential is supplied to any of the plurality of Vcc pads 33a and 33b, it is possible to suppress or prevent high frequency noise from being added to the supplied fixed potential, and to operate the control circuit block 32 more accurately. be able to. Moreover, since the wiring 36 can be brought closer to the amplifier circuit for GSM900, the area of the semiconductor chip 2 can be further reduced, and the cost of the semiconductor chip 2 and the RF power module using the semiconductor chip 2 can be further reduced.

  The RF power module 1b according to the present embodiment has the same structure as that of the RF power module 1, 1a of the first embodiment except that two systems of power amplifier circuits are provided and the configuration of the semiconductor chip 2 is as described above. Since the manufacturing process of the RF power module 1b of the present embodiment is the same as the manufacturing process of the RF power modules 1 and 1a of the first embodiment, detailed description thereof is omitted here. To do. Similar to the first embodiment, also in this embodiment, the semiconductor chips 2 and 3 and the passive component 5 are mounted on the upper surface 4a of the wiring substrate 4, and a plurality of electrodes 2a (bonding pads 33) of the semiconductor chips 2 and 3 are mounted. , 3a and a plurality of substrate side terminals 12 of the wiring substrate 4 are electrically connected via a plurality of bonding wires 8, as shown in FIG. 2 (FIG. 17) and FIG. 10 (FIG. 18). 4 is connected to a Vcc pad (bonding pad) close to (closer to) the terminal 12a of the plurality of Vcc pads 33a and 33b of the semiconductor chip 2 through the bonding wire 8. Then, a sealing resin 6 is formed on the upper surface 4a of the wiring board 4 so as to cover the semiconductor chips 2, 3, the passive component 5, and the bonding wire 8, and the RF power module 1b. Is constructed (manufactured). Also in the present embodiment, substantially the same effect as in the first embodiment can be obtained. For example, it is not necessary to change the design of the semiconductor chip 2 even if the position of the terminal 12a of the wiring board 4 used in the RF module is changed, and RF power modules having various specifications can be obtained using the same (common) semiconductor chip 2. The manufacturing cost of the RF power module can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for application to a power amplification module for a mobile phone and its manufacturing technology.

It is a circuit block diagram of the amplifier circuit which comprises the RF power module which is one embodiment of this invention. It is a top view which shows the structure of RF power module. It is sectional drawing of RF power module. It is principal part sectional drawing of the semiconductor chip used for RF power module. It is a top view of the semiconductor chip used for RF power module. It is principal part sectional drawing of the semiconductor chip of FIG. It is principal part sectional drawing of the semiconductor chip of FIG. It is explanatory drawing of a digital mobile telephone. It is explanatory drawing of a digital mobile telephone. It is a top view which shows the structure of RF power module. It is principal part sectional drawing in the manufacturing process of RF power module which is one embodiment of this invention. FIG. 12 is an essential part cross-sectional view of the RF power module during the manufacturing process following FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the RF power module during the manufacturing process following that of FIG. 12; FIG. 14 is an essential part cross-sectional view of the RF power module during the manufacturing process following FIG. 13; FIG. 3 is a plan view of a main part during a manufacturing process of the RF power module of FIG. 2. It is a principal part top view in the manufacturing process of RF power module of FIG. FIG. 16 is a plan view of main parts of the RF power module subsequent to FIG. 15 during the manufacturing process. FIG. 17 is a plan view of main parts of the RF power module subsequent to FIG. 16 during the manufacturing process. It is a circuit block diagram of the amplifier circuit which comprises the RF power module which is other embodiment of this invention. It is a top view of the semiconductor chip used for RF power module which is other embodiments of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 RF power module 1a RF power module 1b RF power module 2 Semiconductor chip 2a Electrode 2b Back surface electrode 3 Semiconductor chip 3a Electrode 4 Wiring board 4a Upper surface 4b Lower surface 5 Passive component 6 Sealing resin 8 Bonding wire 11 Insulator layer 12 Substrate side terminal 12a terminal 13 external connection terminal 13a reference potential supply terminal 14 via hole 14a via hole 15 conductor layer 16 bonding material 17 bonding material 31A1, 31A2 LDMOSFET circuit 31B1, 31B2 LDMOSFET circuit 31C1, 31C2 LDMOSFET circuit 32 control circuit block 33 bonding pads 33a, 33b Vcc pad 34 Vcc wiring 35 wiring 36 wiring 38 guard ring 50a digital cellular phone 50b digital cellular phone 51 motherboard 52 base Command unit 53 base band LSI
54 Microcomputer 55 RF Unit 56 Transmission / Reception Circuit 57 SAW Filter 58 VCO
59 RF power module 60 Vcc line 102, 102B, 102C Power amplifier circuit 102A1, 102A2, 102A3 Amplifier stage 102AM1, 102AM2 Matching circuit 102B1, 102B2, 102B3 Amplifier stage 102BM1, 102BM2 Matching circuit 102C1, 102C2, 102C3 Amplifier stage 102CM1, 102CM2 Matching Circuit 103, 103a Control circuit 104, 104b, 104c Input terminal 105, 105B, 105C Matching circuit 106, 106b, 106c Output terminal 107, 107B, 107C Matching circuit 108, 108B, 108C Low pass filter 110, 110b, 110c Input terminal 151 GaAs Substrate 152 Subcollector layer 153 HBT
154 Collector electrode 155 Collector mesa 156 Base mesa 157 Base electrode 158 Emitter layer 159 Emitter electrode 161 Insulating film 162 Contact hole 163 Collector wiring 164 Insulating film 165 Through hole 166 Emitter wiring 201 Semiconductor substrate 202 Epitaxial layer 203 P-type well 204 Gate insulating film 205 Gate Electrode 206 Side wall spacer 207 n ⁻ type offset drain region 208 n type offset drain region 209 n ⁺ type drain region 210 n ⁻ type source region 211 n ⁺ type source region 212 p type halo region 213 groove 214 p type punching layer 215 p ⁺ -type semiconductor region 221 silicon nitride film 222 a silicon oxide film 223 a contact hole 224 plug 231 lines 231a source electrode 231b drain collector 232 insulation layer 233 through-hole 234 Plug 241 lines 241a source wiring 241b drain wiring 242 surface protective film 251 source backside electrode 261 isolation regions 262 opening

Claims (20)

A power amplifying module for a mobile communication device having a multi-stage power amplifying circuit,
A wiring board;
First and second semiconductor chips mounted on the main surface of the wiring board;
Have
An amplifier circuit at a final stage of the power amplifier circuit is formed on the second semiconductor chip;
An amplifier circuit preceding the final stage of the power amplifier circuit is formed in the first semiconductor chip;
A plurality of pad electrodes are formed on the first semiconductor chip,
The power amplification module, wherein the plurality of pad electrodes include a plurality of first pad electrodes having the same potential and electrically connected by a first wiring of the first semiconductor chip. The power amplification module according to claim 1, wherein
In the first semiconductor chip, the amplifier circuit is disposed on an outer periphery of the first semiconductor chip,
The plurality of first pad electrodes are disposed on an outer periphery of the first semiconductor chip,
The power amplification module, wherein the plurality of first pad electrodes are electrically connected by the first wiring provided on an outer peripheral portion of the first semiconductor chip. The power amplification module according to claim 2, wherein
In the first semiconductor chip, the first wiring that connects the plurality of first pad electrodes is provided on the side of the outer periphery of the first semiconductor chip where the amplifier circuit is not disposed. A power amplification module characterized by that. The power amplification module according to claim 3,
The power amplification module, wherein the plurality of first pad electrodes are respectively disposed on two opposing sides of the first semiconductor chip. The power amplification module according to claim 2, wherein
The power amplification module is a power amplification module for a W-CDMA mobile communication device. The power amplification module according to claim 1, wherein
The power amplification module includes the power amplification circuit of a first system and a second system for a higher frequency band than the first system,
The final stage amplifier circuit of the power amplifier circuit of the first and second systems is formed on the second semiconductor chip,
An amplifier circuit in a stage prior to the final stage of the power amplifier circuits of the first and second systems is formed in the first semiconductor chip;
In the first semiconductor chip, the amplifier circuits of the first and second systems are arranged on the outer periphery of the first semiconductor chip,
The plurality of first pad electrodes are disposed on an outer periphery of the first semiconductor chip,
The power amplification module, wherein the plurality of first pad electrodes are electrically connected by the first wiring provided on an outer peripheral portion of the first semiconductor chip. The power amplification module according to claim 6,
In the first semiconductor chip, the first wiring that connects the plurality of first pad electrodes is on the side of the outer periphery of the first semiconductor chip where the amplification circuit of the second system is not disposed. A power amplifying module characterized in that the power amplifying module is provided. The power amplification module according to claim 6,
In the first semiconductor chip, the first wiring connecting the plurality of first pad electrodes is provided on the side of the outer periphery of the first semiconductor chip on which the amplification circuit of the second system is disposed. Is provided, and is provided on the side of the outer periphery of the first semiconductor chip on the side where the amplifier circuit of the first system is disposed. The power amplification module according to claim 6,
The power amplification module according to claim 1, wherein a transmission frequency band of the power amplification circuit of the first system is a 0.9 GHz band, and a transmission frequency band of the power amplification circuit of the second system is a 1.8 GHz band. The power amplification module according to claim 1, wherein
The power amplification module, wherein the first pad electrode is a pad electrode for supplying a fixed potential. The power amplification module according to claim 1, wherein
In the first semiconductor chip, an active element is not formed immediately below the first wiring connecting the plurality of first pad electrodes. The power amplification module according to claim 1, wherein
In the first semiconductor chip, the first wiring that connects the plurality of first pad electrodes is formed of a conductor layer that is the same layer as a conductor layer constituting the plurality of first pad electrodes. A power amplification module characterized by comprising: The power amplification module according to claim 1, wherein
In the wiring board, a plurality of terminals including a first terminal for supplying a fixed potential are formed on a main surface on which the first and second semiconductor chips are mounted.
The power amplification module, wherein the first terminal of the wiring board is electrically connected to the first pad electrode close to the first terminal among the plurality of first pad electrodes. The power amplification module according to claim 13, wherein
The first terminal of the wiring board is electrically connected to the first pad electrode close to the first terminal among the plurality of first pad electrodes through a bonding wire. Amplification module. The power amplification module according to claim 14, wherein
The power amplification module, wherein a bonding wire is not connected to the first pad electrode far from the first terminal among the plurality of first pad electrodes. The power amplification module according to claim 1, wherein
A power amplification module, wherein a control circuit for controlling the power amplification circuit is formed in the first semiconductor chip. A method of manufacturing a power amplification module for a mobile communication device, having a multistage power amplification circuit,
(A) A step of preparing a wiring board having a plurality of terminals including a first terminal for supplying a fixed potential on its main surface, and first and second semiconductor chips each having a plurality of pad electrodes. ,
(B) mounting the first and second semiconductor chips on the main surface of the wiring board;
(C) electrically connecting the plurality of pad electrodes of the first and second semiconductor chips and the plurality of terminals of the wiring board;
Have
The final stage amplifier circuit of the power amplifier circuit is formed on the second semiconductor chip,
An amplifier circuit in a stage prior to the final stage of the power amplifier circuit is formed in the first semiconductor chip,
The plurality of pad electrodes formed on the first semiconductor chip include a plurality of first pad electrodes of the same potential electrically connected by a first wiring of the first semiconductor chip;
In the step (c), the first pad to be connected to the first terminal of the wiring board from the plurality of first pad electrodes according to the position of the first terminal on the main surface of the wiring board. An electrode is selected, and the selected first pad electrode is electrically connected to the first terminal of the wiring board. A method for manufacturing a power amplification module according to claim 17,
In the step (c), the first pad electrode close to the first terminal of the wiring board is selected from the plurality of first pad electrodes, and the selected first pad electrode and the wiring board are selected. A method for manufacturing a power amplification module, wherein the first terminal is electrically connected. A method for manufacturing a power amplification module according to claim 17,
In the step (c), the selected first pad electrode and the first terminal of the wiring board are electrically connected by a bonding wire. A method for manufacturing a power amplification module according to claim 17,
In the step (c), the first pad electrode close to the first terminal of the wiring board among the plurality of first pad electrodes and the first terminal of the wiring board are electrically connected via a bonding wire. And a bonding wire is not connected to the first pad electrode far from the first terminal among the plurality of first pad electrodes.

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