JP2008118624A - High-frequency power amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small-sized high-frequency high-performance power amplifier, capable of easy adjustment and switching impedance. <P>SOLUTION: The high-frequency power amplifier of a module, or the like, includes a first semiconductor chip including one or more high-frequency amplifying devices, and a second semiconductor chip, including one or more high-frequency matching circuit devices and one or more switching devices. The second semiconductor chip includes a matching circuit for a high-frequency amplifying device. The second semiconductor chip also includes a circuit comprising a capacitance and a switching device connected in series or parallel with the capacitance; and having the switching device switch on or switch off so that the capacitance goes into a connected state or does not go to a connected state, as a part of the matching circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a high-frequency power amplifying apparatus used for mobile communication equipment and the like.

  A high frequency power amplifying device used for a cellular phone or the like includes an amplification element such as a transistor, an input matching circuit for efficiently inputting a high frequency signal to the amplification element, and output matching for efficiently outputting a high frequency signal from the amplification element. It consists of a circuit. These matching circuits are formed of a high-frequency matching element such as a capacitor and an inductor or a microstrip line, and are generally formed by being mounted on a substrate as a chip-mounted component. A semiconductor chip on which a high frequency amplifying element is formed is also mounted on a substrate, and the semiconductor chip including these is configured as a high frequency power amplifier module.

Recently, cellular phones have become more and more multifunctional, and multi-band transmission signals and multi-mode handling different modulation signals have been advanced. In addition, the miniaturization of batteries has led to the miniaturization of mobile phones, and there is a need for higher efficiency of high-frequency power amplifiers to ensure talk time, not only near the maximum output, but also at low power efficiency. There is also a tendency to emphasize. As is well known, in order to optimize the efficiency of the high-frequency power amplifier, it is necessary to match the impedance matching of the input and output under each condition such as frequency and output, as described above. In order to support multiband and multimode, a plurality of high frequency power amplifiers having matching circuits with individually optimized impedances are required.
On the other hand, there is an example using a control element as means corresponding to these. (Patent Document 1)
JP 2001-251202 A

FIG. 19 shows an example of the prior art. The matching circuit on the output side of the final stage amplifying element includes the variable capacitance element 300, the switching diode 302 connected in series with the capacitor 301, the inductor 303, the bypass capacitor 304, and the resistor 305 connected to the control circuit. These elements are included, and the impedance state of the output load circuit 306 is changed by controlling these elements. In the case of such a configuration, for example, when an element such as 300 to 305 is mounted on a substrate with chip components, the entire area of the power amplifier module including the matching circuit and the like as shown in FIG. 20 is increased. When advanced control such as multiband switching and switching according to output power is performed, the area is further increased and the module circuit becomes more complex.
An object of the present invention is to provide a high-frequency power amplifying apparatus that easily adjusts and switches impedance and reduces the area of the entire power amplifier module while ensuring high performance and low cost.

  In order to solve the above problems, a high-frequency power amplifier according to the present invention includes a first semiconductor chip including a main amplification stage having a first high-frequency amplification element, and a second semiconductor chip including a main matching stage having a first switch element. The main amplification stage includes a first output terminal (T1) for outputting a first signal amplified by the first high frequency amplification element, and the main matching stage receives the first signal. It includes a first input terminal (T2) and a first high-frequency matching circuit element that matches the first signal.

  By adopting these configurations, the impedance matching circuit of the power amplifier having a switching function can be integrated on a small-sized semiconductor chip, and complicated switching control is also possible. As a result, it is possible to reduce the size of a high-performance power amplifier module that supports multiband.

  FIG. 1A, FIG. 1B, FIG. 2, FIG. 3, and FIG. 4 are configuration diagrams of a high-frequency power amplifying device in which the present invention is used. The high-frequency power amplifying apparatus according to the present invention uses a high-frequency band, a range from 800 MHz to 3 GHz, and more widely a range from 400 MHz to 5 GHz. The amplified power is about 5 watts. In FIG. 1A, reference numeral 100 denotes the entire high-frequency power amplifier, 101 denotes a first semiconductor chip including an amplifying element (also referred to as a high-frequency amplifying element), and 102 includes a matching circuit element (also referred to as a high-frequency matching circuit element) and a switch element. A second semiconductor chip is shown. 100 high-frequency power amplifying devices (also simply referred to as high-frequency amplifying devices) include first and second semiconductor chips, a substrate 103 formed of a material such as resin or ceramic on which they are mounted, and a sealing resin 104 or cap. These are integrally formed in a form called a module. In the configuration of the present embodiment, two semiconductor chips of blocks 101 and 102 are used in a module, and the high frequency power amplifying apparatus 100 is configured with circuit elements such as microstrip lines formed on a substrate.

  FIG. 1B shows an example of the configuration in a cross-sectional view. A substrate 103 made of a material such as resin or ceramic and a sealing resin 104 are shown. The semiconductor chips 101 and 102 are mounted on the substrate 103 and connected to lands on the substrate by means such as wire bonding. A high-frequency circuit such as a microstrip line can be formed on the substrate 103.

  FIG. 2 is a first block diagram showing the configuration of the high-frequency power amplifier according to the present invention. Reference numeral 105 denotes an input matching circuit block of a two-stage amplifier, 106 denotes a front-stage amplifier circuit block of the two-stage amplifier, 107 denotes an interstage matching circuit block, 108 denotes a rear-stage amplifier circuit block, and 109 denotes an output matching circuit block. The configuration of FIG. 2 is an example in which the output matching circuit 109 includes a switch element, and the matching circuit element and the switch element are formed on the second semiconductor chip 102. Blocks 105, 106, 107, and 108 are formed in a first semiconductor chip including an amplifying element. Blocks 105, 106, 107 and 108 are collectively referred to as the main amplification stage, and block 109 is also referred to as the main matching stage. The main amplification stage is provided upstream of the main matching stage. The main amplification stage includes at least block 108, and blocks 105, 106, and 107 may be omitted. The input matching circuit block 105 and the interstage matching circuit block 107 perform matching processing of a relatively small power signal in the high-frequency power amplifying apparatus, and therefore output matching circuits that perform matching processing of a relatively large power signal to an external impedance circuit. Compared to the block 109, the configuration is simple. The first semiconductor chip 101 has an output terminal T1 that outputs an output signal amplified by the high frequency amplification element, and the second semiconductor chip 102 matches the output signal with the input terminal T2 that receives the output signal of the high frequency amplification element. It has a high-frequency matching circuit element. The high-frequency matching circuit element provided in the second semiconductor chip 102 will be described in detail with reference to FIG. 6A.

FIG. 3 is a second block diagram showing another configuration of the high-frequency power amplifier according to the present invention. In this configuration example, the input matching circuit 105 and the output matching circuit 109 are formed on the second semiconductor chip 102 including the switching element, and the blocks 106, 107, and 108 are formed on the first semiconductor chip including the high frequency amplifying element. ing. Block 105 is also referred to as the pre-match stage, blocks 106, 107, and 108 are collectively referred to as the main amplification stage, and block 109 is also referred to as the main match stage. The main amplification stage is provided on the upstream side of the main matching stage, and the pre-matching stage is provided on the upstream side of the main amplification stage. The main amplification stage includes at least block 108, and blocks 106 and 107 may be omitted. Since the interstage matching circuit block 107 performs matching processing of a relatively small power signal in the high frequency power amplifier, compared to the output matching circuit block 109 that performs matching processing of a relatively large power signal to the external impedance circuit, It has a simple configuration. The first semiconductor chip 101 has an input terminal T4 that receives the original signal amplified by the high-frequency amplifier, and the second semiconductor chip has an output terminal T3 that outputs the original signal and a high-frequency matching circuit element that matches the original signal. Have. The high-frequency matching circuit element provided in the second semiconductor chip 102 will be described in detail with reference to FIG.
The block 109 may be constituted by an individual semiconductor chip separated from the second semiconductor chip 102. In this case, the block 109 may be included in the first semiconductor chip 101.

  FIG. 4 is a third block diagram showing still another configuration of the high-frequency power amplifier according to the present invention. In this configuration example, the input matching circuit 105, the interstage matching circuit 107, and the output matching circuit 109 are formed on the second semiconductor chip 102 including the switch element, and the blocks 106 and 108 include the first semiconductor chip including the amplifier element. 101. Block 105 is also called the pre-match stage, block 106 is also called the pre-amplification stage, block 107 is also called the intermediate match stage, block 108 is also called the main amplification stage, and block 109 is also called the main match stage. The main amplification stage is provided on the upstream side of the main matching stage, the intermediate matching stage is provided on the upstream side of the main amplification stage, the preamplification stage is provided on the upstream side of the intermediate matching stage, and the prealignment stage is the upstream of the preamplification stage. Provided upstream. The first semiconductor chip 101 has a front-stage high-frequency amplifying element (in block 106) and a rear-stage high-frequency amplifying element (in block 108), and an inter-stage signal before matching amplified by the front-stage high-frequency amplifying element. The second semiconductor chip 102 has an input terminal T6 that receives an interstage signal before matching and a high-frequency matching circuit element that matches the interstage signal before matching. Further, the first semiconductor chip 101 has an input terminal T8 that receives an interstage signal after matching, and the second semiconductor chip 102 has an output terminal T7 that outputs an interstage signal after matching. The high-frequency matching circuit element provided in the second semiconductor chip 102 will be described in detail with reference to FIG.

Note that the block 105 and the block 109 may be configured by individual semiconductor chips separated from the second semiconductor chip 102. In this case, the block 105 and / or the block 109 may be included in the first semiconductor chip 101.
Next, description will be given using an actual circuit diagram. FIG. 5 is an example of a circuit diagram of a high frequency power amplifier for explaining the present invention, and shows an example of a two-stage amplifier.
The input matching circuit 105 includes capacitors C1 and C2 and an inductor L1. This configuration is an example, and other configurations may be used.
The preamplifier circuit 106 includes an amplification transistor Tr1, resistors R1 and R2, capacitors C3 and C4, and microstrip lines SL1 and SL2. The terminal 207 is connected to a bias circuit (not shown) that supplies a bias current or voltage to the amplification transistor Tr1. C4 functions as a bypass capacitor. SL2 may be an inductor.

The interstage matching circuit 107 includes a capacitor C5.
The post-stage amplifier circuit 108 includes an amplification transistor Tr2, a resistor R3, a capacitor C6, and a microstrip line SL3. The terminal 208 is connected to a bias circuit (not shown) that supplies a bias current or voltage to the amplification transistor Tr2. C6 functions as a bypass capacitor. SL3 may be an inductor.
The output matching circuit 109 includes capacitors C7, C8, C9 and microstrip lines SL4, SL5, SL6.

  As shown in FIGS. 2, 3, and 4, the high-frequency power amplifying device according to the present invention comprises at least two semiconductor chips, that is, a first semiconductor chip and a second semiconductor chip, and the two semiconductor chips are integrated. It is a precondition that it is formed. The first semiconductor chip includes at least an amplifying element. The amplifying element includes, as an example, a front-stage amplifying element Tr1 and a rear-stage amplifying element Tr2. The amplifying element is, for example, an amplifying transistor. The amplification transistor is formed of, for example, a bipolar transistor. Furthermore, the amplification transistor may be formed of a heterojunction bipolar transistor such as a silicon germanium transistor. An amplifying circuit includes an amplifying element and adjusting resistors and capacitors. The second semiconductor chip includes at least a matching circuit element and a switch element. The matching circuit element includes at least one of a capacitor, an inductor, and a microstrip line. The first semiconductor chip and the second semiconductor chip are integrally formed. Here, the integral formation means that it is formed as a single unit, for example, when the first semiconductor chip and the second semiconductor chip are provided on the same substrate, or molded as an integral object. Say if you are.

  The first semiconductor chip 101 including the amplifying element includes at least a subsequent-stage amplifier circuit block 108, and the second semiconductor chip 102 including the matching circuit element and the switch element includes at least an output matching circuit 109. When comparing the first semiconductor chip 101 and the second semiconductor chip 102, the first semiconductor chip 101 amplifies a signal by an amplifying element such as a bipolar transistor, for example, and the second semiconductor chip 102 is a matching circuit element. The signal is matched by the switch element. Therefore, the manufacturing processes of the two are different, and the first semiconductor chip 101 is more complicated than the second semiconductor chip 102. Further, each element included in the first semiconductor chip 101 requires sufficient performance and accuracy to amplify the signal. For this reason, the chip cost per unit area is relatively high in the case of the first semiconductor chip 101. On the other hand, in the case of the second semiconductor chip 102, the matching circuit element is composed of a passive element that is relatively easy to manufacture, and the switching element does not require performance and accuracy enough to amplify a signal only by switching. Therefore, the chip cost of the second semiconductor chip 102 is lower than that of the first semiconductor chip 101. Further, since the switch element is formed of, for example, a field effect transistor or a heterojunction field effect transistor (HEMT), the manufacturing process of the second semiconductor chip 102 is different from that of the first semiconductor chip 101 mainly including, for example, a bipolar transistor. Quite different.

  As described above, the first semiconductor chip 101 and the second semiconductor chip 102 are different from each other in the manufacturing process, have different required performance and accuracy, and as a result, have different chip costs. In such a case, if each element in the high-frequency power amplifying apparatus 100 is made into a semiconductor chip with a configuration different from that of the first semiconductor chip 101 and the second semiconductor chip 102, not only the manufacturing process becomes complicated, but also the performance. Is difficult to secure, and the yield deteriorates. For this reason, the total cost increases and the size of the high-frequency power amplifying apparatus 100 as a module also increases. In this way, by dividing the high-frequency amplifying device 100 mainly using the first semiconductor chip 101 and the second semiconductor chip 102, the best configuration in terms of cost, manufacturing process, performance, and size. Can be obtained.

(First embodiment)
FIG. 6A is a circuit diagram corresponding to FIG. 2 and is a first configuration diagram showing a configuration of a high-frequency power amplifying device in which the present invention is used. Compared to the circuit of FIG. 5, the output matching circuit 109 is provided with a capacitor C11 and a switch element SW1, which are capacitive elements. Since the capacitor C11 is not connected to the matching circuit as a grounding capacitor when the switch element SW1 is off, the output matching circuit is equivalent to the state shown in FIG. 5, but when the switch element SW1 is turned on, the capacitor C11 is not connected. The element C11 is connected to the matching circuit as a grounding capacitor, and the impedance of the matching circuit is changed from the state of FIG. 5 by the amount of the capacitance of C11. As a result, the matching state seen from the output terminal of the subsequent stage amplifying element changes, and for example, it is possible to perform switching such as optimizing the efficiency with two different output powers or optimizing the efficiency with two different frequencies.
In this configuration, the output side of the transistor Tr2 is directly connected to the output terminal T1 of the first semiconductor chip 101.

  When the high-frequency power amplifying device according to the present invention is used in a mobile phone, a control circuit 603, a frequency detector 600, a power level detector 601, a mode detector are provided as circuits for performing on / off control of the switch element SW1. A container 602 is provided. The frequency detector 600 detects that the transmission / reception frequency and the frequency have changed when the mobile phone is a multi-band compatible device. The power level detector 601 detects the power level of radio waves received by the mobile phone. The mode detector 602 detects whether the mode is a voice call mode or a data communication mode. Control is possible if at least one of the frequency detector 600, the power level detector 601, and the mode detector 602 is provided.

  A control method based on the frequency will be described. When the frequency detector 600 detects that the frequency has changed, the switch element SW1 is turned on or off, and the impedance is changed so as to achieve an optimum matching state at the detected frequency, thereby improving efficiency, for example.

  A control method based on the power level will be described. When the power level detected by the power level detector 601 is greater than or equal to a predetermined value, the control circuit 603 turns on the switch element SW1 to lower the load impedance of the post-stage amplifier circuit 109. When the detected power level falls below a predetermined value, the switch element SW1 is turned off to increase the load impedance. This can increase efficiency.

A control method based on the communication mode will be described. When the mode detector 602 detects the data communication mode, the maximum output increases. In this case, the switch element SW1 is turned on by the control circuit 603, and the load impedance is lowered so as to obtain a large output. On the other hand, when the mode detector 602 detects the voice call mode, the control circuit 603 turns off the switch element SW1 to make matching so as to increase the load impedance and increase the efficiency.
In addition, although the case where the high frequency power amplifier according to the present invention was used in a mobile phone was described, the same control can be performed for other devices in which the high frequency power amplifier is used.

  6B shows a circuit of the impedance Zout viewed from the output terminal of the post-amplifier circuit 108 in FIG. 6A. FIGS. 6C and 6D respectively show the simulation results of Zout when the switch element SW1 is off and when the switch element SW1 is on (capacitor). In this example, the capacitance of C11 is calculated as 0.5 pF. When the switch element SW1 is switched from the off state to the on state, it can be seen that, for example, the impedance at f = 1950 MHz changes in a direction in which the real part is small and the absolute value of the imaginary part is small. When the real part is small and the impedance is low, the maximum output of the high-frequency power amplifying element is large. Therefore, by such switching, characteristics such as efficiency can be optimized in accordance with the output power. In the present embodiment, the switching element SW1 and the capacitor C11 used for switching are formed on the same semiconductor chip 102, so that the switching function can be integrated with a small area.

  Further, as shown in FIG. 6E, when the switch element SW1 is a field effect transistor, it is easy to control on / off by the gate voltage and the loss at the time of on is small, so that the size can be further reduced. In addition, it is easy to form a low-loss switching circuit. Further, it is more effective if the switching element is a heterojunction field effect transistor (HEMT). When the output matching circuit 109 has a switching function as in the present embodiment, consideration must be given to the magnitude of the voltage amplitude of the high-frequency amplified signal at the switch element end. That is, the voltage amplitude becomes large during a large signal operation. For example, if the threshold voltage of the switch element SW1 is exceeded, the off circuit may be turned on and the switching operation may not operate normally. However, when an element such as HEMT is used, a design that easily accommodates a large signal operation can be made by adopting a circuit format such as a plurality of switch elements arranged in multiple stages in series. Even in this case, the loss can be reduced, which is extremely effective.

  In the following embodiments, a case where the switching element is a field effect transistor or a heterojunction field effect transistor will be described as an example.

FIG. 7 is a circuit diagram corresponding to FIG. 3 and is a second configuration diagram of the high-frequency power amplifier according to the present invention. Here, the input matching circuit 105 and the output matching circuit 109 are formed on the same semiconductor chip 102.
In this configuration, the input side of the transistor Tr1 is directly connected to the input terminal T4 of the first semiconductor chip 101.

FIG. 8 is a circuit diagram corresponding to FIG. 4 and is a third configuration diagram of the high-frequency power amplifier according to the present invention. Here, the input matching circuit 105, the interstage matching circuit 107, and the output matching circuit 109 are formed on the same semiconductor chip 102. In the example of FIG. 8, microstrip lines SL4, SL5, and SL6 that are part of the output matching circuit are formed not on the semiconductor chip 102 but outside. In such a case, the microstrip lines SL4, SL5, SL6 are formed on the module substrate 103 and connected to the matching circuit element on the semiconductor chip 102 by means such as wire bonding. With such a configuration, the second semiconductor chip 102 can be reduced in area.
In this configuration, the output side of the transistor Tr1 is directly connected to the output terminal T5 of the first semiconductor chip 101, and the input side of the transistor Tr2 is directly connected to the input terminal T8 of the first semiconductor chip 101. .

  In the above embodiment, the impedance switching circuit by the switch element is formed only in the output matching circuit 109, but of course, it may be formed in the interstage matching circuit 107 or the input matching circuit 105. For example, as shown in FIG. 9, the impedance of the interstage matching circuit 107 can be switched by forming the switch element SW2 and the capacitive element C12 in parallel with the series capacitive element C5 of the interstage matching circuit 107. Thereby, the magnitude of the input power from the pre-stage amplifier circuit 106 to the post-stage amplifier circuit 108 is switched according to the magnitude of the output of the high-frequency power amplifier, or the interstage matching circuit 107 is changed according to the operating frequency of the high-frequency power amplifier. The frequency characteristics can be switched.

  The bias circuits (connected to the terminals 207 and 208) of the amplifier circuits 106 and 108 may be formed on the same first semiconductor chip 101 as the amplifier circuit, or the second circuit provided with the switch element SW1. It may be formed on the semiconductor chip 102. For example, when the amplifying elements Tr1 and Tr2 are bipolar transistors, functions such as temperature compensation and shutdown can be made more accurately and easily if the bias circuit is configured using a circuit of a field effect transistor constituting the switch element SW1. It can be added and the effect is great. The resistor R1 and the capacitor C3 provided in the pre-stage amplifier circuit 106 are a feedback circuit and also function as a part of the matching circuit. Such a circuit provided in the periphery of the amplifying elements Tr1 and Tr2 may be formed on the same first semiconductor chip 101 as the amplifying elements Tr1 and Tr2, or may be formed on the second semiconductor chip 102. It may be good or it may be external to the chip. Similarly, some of the matching circuits 105, 107, and 109 are not necessarily on the second semiconductor chip 102, and some of them may be on the first semiconductor chip 101.

  In addition, at least one of the first semiconductor chip 101 including the amplifier circuit element and the second semiconductor chip 102 including the matching circuit element and the switch element may be divided into a plurality of chips. For example, the first semiconductor chip or the second semiconductor chip may be formed of two or more chips depending on the scale of the amplifier circuit and the switching complexity. Thus, it is more effective if the module layout is optimized (downsized).

  Further, as shown in FIGS. 1 and 2, in the above embodiment, the module of the high-frequency amplification device 100 has a configuration in which only the semiconductor chips 101 and 102 are mounted on the substrate 103. In this case, the resistors R1, R2, capacitors C3, C4, C6, microstrip lines SL1, SL2, SL3, and all or part of the inductors may be included in the semiconductor chip, or may be externally attached. It may be. Further, the amplifier circuit may be a multi-stage having three or more stages. Further, the connection between the circuit element on the semiconductor chip and the substrate is not limited to wire bonding, but may be flip chip bonding.

(Second Embodiment)
Next, an embodiment of a switching circuit using a switching element and a matching circuit element formed in the second semiconductor chip will be described.
10A, 10B, and 10C are circuit block diagrams for explaining a second embodiment of the impedance switching circuit of the present invention. Reference numerals 215, 217, 218, 220, and 221 denote capacitive elements, and 216, 219, and 222 denote switch elements. For example, in FIG. 10A, when the switch element 216 is on, the capacitor element 215 is connected to the circuit as a grounding capacitor. However, when the switch element 216 is off, the capacitor element 215 is open to the ground side and is not connected to the circuit. Connect. Actually, since the parasitic capacitance of the switching element such as HEMT exists, the grounding capacitance is a series combined capacitance of the capacitance element 215 and the parasitic capacitance, but this combined capacitance value is sufficiently smaller than the capacitance element 215. When the circuit of FIG. 10A is used for high-frequency matching, the matching circuit impedance can be changed depending on the difference in capacitance between when the switch element 216 is on and when it is off.

Similarly, in the case of the embodiment of FIG. 10B, the series capacitance value can be switched between the capacitance value of the capacitance element 217 and the total capacitance values of the capacitance elements 217 and 218 by turning on / off the switch element 219.
Further, it is possible to switch the grounding capacitance value as shown in FIG. 10C.

  Further, as shown in FIGS. 11A, 11B, and 11C, the matching circuit element may be an inductor. Further, as described above, since the switch element has a parasitic capacitance, switching using this capacitance value as an element of the matching circuit is also possible. For example, when the HEMT is used, the parasitic capacitance per 1 mm of the gate width is about 0.2 pF, and if the gate length is designed to an appropriate value, 0. A capacitance value of about several pF to several pF can be made variable.

  Next, the fine adjustment switching of the capacitance value using the parasitic capacitance will be described with reference to FIGS. 12A, 12B, 12C, and 12D. For example, if each of the switch elements 231 and 232 connected in series shown in FIG. 12A has an off capacitance of 0.4 pF, when both are off (FIG. 12B), it becomes 0.2 pF, and either one is on. (FIG. 12C) is 0.4 pF. A plurality of them may be arranged in parallel as shown in FIG. 12D. If the circuit of FIG. 12A or FIG. 12D is used as a matching circuit element in series or for grounding, it can be used for fine adjustment of impedance.

  In the present embodiment, the switch element has been described as an example of a single-stage element. In an actual circuit, a switching element such as a HEMT is used. However, as described in the first embodiment, a plurality of switching elements are provided in order to ensure an on / off operation with respect to a voltage value applied to the switching element. A circuit connected in multiple stages may be used. Multi-stage is easy, and it can be applied to a matching circuit with high output power, and the effect is great. In this case, the power supply voltage may be increased instead of being multi-staged. However, in the case of a cellular phone or the like, it is necessary to boost the battery voltage, so that it is less if a booster circuit for that purpose is formed in the second semiconductor chip. It is possible to cope with high output by the number of stages.

(Third embodiment)
Another embodiment of the switching circuit will be described with reference to FIGS. 13A and 13B. Capacitors 237, 239, 241, and 243, which are matching elements, are part of the matching circuit of the amplifying device, respectively, and the control voltage (A) to (D) of the switch elements 238, 240, 242, and 244 are low (L). Alternatively, connection and disconnection to the matching circuit are controlled by high (H) switching. In order to perform these four switching operations, a logic circuit 245 is provided, and L / H switching of the four control voltages (A) to (D) is performed with two control terminals. Four switches are shown in FIG. 13B. If such a logic circuit is formed in the second semiconductor chip of the present invention, it is possible to easily control the switching of a large number of complicated impedances with a small number of interfaces, thereby reducing the chip area and the amplifying device. It is effective for downsizing. In addition, since elements such as HEMT can easily form a logic circuit, these functions can be realized on the second semiconductor chip. Further, in the case of an amplifying device having many functions and a large number of paths, a plurality of chips including switch elements and matching circuit elements may be provided, and a logic circuit may be formed in one or more of them.

(Fourth embodiment)
FIG. 14 is a fifth configuration diagram of the high-frequency power amplifying device according to the present invention, which is also a modification of the high-frequency power amplifying device shown in FIG. 6E. The second semiconductor chip 102 includes a matching circuit element and a switch element. In the present embodiment, a bypass capacitor C4 for the power supply of the former stage amplification element and a bypass capacitor C6 for the power supply of the latter stage amplification element are included. Furthermore, a capacitor C13 and a switch element SW3 connected in parallel with the capacitor C6 are included.

  The bypass capacitors C4, C6, and C13 have values of several tens to several thousand pF in order to eliminate the influence of the impedance on the power supply side on the high frequency amplification operation and to suppress the pass characteristic on the lower frequency side than the amplification frequency range. Designed to have. When such a large-capacity element is formed on a semiconductor chip, the area of the capacitive element is increased, so that the area of the semiconductor chip is increased and the cost is increased. In particular, for example, when the amplifying element is a bipolar transistor, the first semiconductor chip 101 having the amplifying element has a complicated process, so that the chip cost per unit area is high, and the formation of a large-capacity element further increases the chip cost. On the other hand, since the second semiconductor chip 102 including the switch circuit element is lower in cost than the first semiconductor chip, the configuration of the present embodiment is low cost, and the bypass capacitor is also configured on the semiconductor chip. enable.

  When a large capacitance is formed, a high dielectric insulating film may be used. In that case, a process of forming a high dielectric insulating film is further added to the process of forming a semiconductor element. If such an insulating film is formed on the same first semiconductor chip 101 as the semiconductor element having a cross-sectional structure with a large step like a semiconductor element including a bipolar transistor, the entire process becomes complicated and difficult. It is easier and more effective to form such an insulating film on the second semiconductor chip 102 including a switch element having a simple structure with few steps.

Next, the reason why the capacitor C13 and the switch element SW3 are provided will be described.
The bypass capacitor C6 has an effect of reducing noise from the power source and stabilizing the operation of the amplifier. Noise reduction is more effective when bypassing in a wide frequency band, and generally a larger capacitance value is better. On the other hand, when using polar modulation that modulates the amplifier by adding a modulation signal to the power supply voltage, there is a demerit that if the capacitance value of the bypass capacitor is large, the band of the modulation signal is limited. Therefore, for example, when using polar modulation as described above, the switch element SW3 is turned off to reduce the capacitance value. In other cases, the switch element SW3 is turned on, and the capacitance value is increased so as to be the total value of the capacitors C6 and C13, so that the amplifier operates stably.

  Further, the circuit corresponding to the capacitor C13 and the switch element SW3 may be connected in parallel to the bypass capacitor C4 for the power supply of the previous stage amplification element. Moreover, you may form in both the front | former stage and a back | latter stage.

  Note that the second semiconductor chip 102 may include an element or circuit having a memory function or an element or circuit having a trimming function. Furthermore, the first semiconductor chip 101 or the second semiconductor chip 102 may include one or a plurality of via holes that connect the front surface and the back surface of the chip.

(Fifth embodiment)
In the above-described embodiment, the switch element of the impedance switching circuit included in the second semiconductor chip 102 has a capacitor connected to one end. In the fifth embodiment, a switching element in which capacitors are connected to both ends will be described. Furthermore, an example in which a part of the capacitor included in the second semiconductor chip 102 is included in the first semiconductor chip 101 in the above-described embodiment will be described.

  FIG. 15A and FIG. 15B are configuration diagrams of first and second modifications of the high-frequency power amplifier according to the present invention, respectively. 15A and 15B, the first semiconductor chip 101 further includes a capacitor C20 with respect to the semiconductor chip 101 of FIG. One end of the capacitor C20 is inserted between the post-stage amplifier circuit block 108 and the output terminal T1, and the other end is grounded. Microstrip lines SL10 and SL11 are formed on substrate 103.

As described above, the high-frequency amplification device 100 can be obtained by dividing the first semiconductor chip 101 and the second semiconductor chip 102 as main components. In the fifth embodiment, among the elements in the output matching circuit 109, only the input capacitor C7 (shown in FIG. 6A) is transferred to the first semiconductor chip 101 and used as the capacitor C20. As a result, the capacitor C20 can be directly connected to the post-stage amplifier circuit block 108 to effectively match the output without adversely affecting the manufacturing process of the first semiconductor chip 101. Furthermore, the amplifying element included in the post-stage amplifier circuit block 108 has a grounding via hole, and the capacitor C20 can be directly connected to the grounding via hole without going through the wire wiring. For this reason, the high power output of the amplifying element can be effectively passed to the ground. As described above, by using the capacitor C20 to match the output signal of the amplifying element in the first semiconductor chip 101 in advance, the output matching circuit 109 can be reduced in size and the output signal can be reduced in loss and widened. be able to.
The capacitor C20 may be a capacitor C8 (shown in FIG. 6A) or a capacitor C9 (shown in FIG. 6A). Further, the capacitor C20 may include two or more functions among the three capacitors C7, C8, and C9 in FIG. 6A.

  In FIG. 15A, the second semiconductor chip 102 includes a switch SW4 and capacitors C21, C22, C23, C24, and C25. Switch SW4 is inserted between capacitors C24 and C25. As a result, the capacitors C24 and C25 block the direct current flowing through the switch SW4 and prevent the direct current from flowing outside the capacitors C24 and C25, thereby increasing the power consumption and changing the matching characteristics. . The series circuit connected in the order of the capacitor C24, the switch SW4, and the capacitor C25 is connected in parallel to the capacitor C22 inserted in series between the terminal T2 and the terminal 111. In this series circuit, the series impedance of the output matching circuit 109 is reduced or increased by turning on or off the switch SW4 by the control circuit 603 shown in FIG. 6A.

  In FIG. 15B, the second semiconductor chip 102 includes a switch SW5 and capacitors C21, C22, C23, C26, and C27. Switch SW5 is inserted between capacitors C26 and C27. As a result, the capacitors C26 and C27 block the direct current flowing through the switch SW5 and prevent the direct current from flowing outside the capacitors C26 and C27 to increase the power consumption or change the matching characteristics. . In the series circuit connected in the order of the capacitor C26, the switch SW5, and the capacitor C27, one end is inserted between the terminal T2 and the terminal 111, and the other end is grounded. In this series circuit, the parallel impedance of the output matching circuit 109 is decreased or increased by turning on or off the switch SW5 by the control circuit 603 shown in FIG. 6A.

  FIGS. 16A, 16B, and 16C are circuit block diagrams of the impedance switching circuit. FIGS. 10A, 10B, and 10C show the case where the switch element is inserted between both capacitors, respectively. That is, the switch element 251 is inserted between the capacitors 250 and 252, the switch element 255 is inserted between the capacitors 254 and 256, and the switch element 259 is inserted between the capacitors 258 and 260.

  15A and 15B, the microstrip lines SL10 and SL11 are formed on the substrate 103, but may be included in the second semiconductor chip 102. Further, although the second semiconductor chip 102 has been described as a part of the output matching circuit 109, it may include an interstage matching circuit 107.

(Sixth embodiment)
FIG. 17A and FIG. 17B are waveform diagrams showing the time lapse of the power of the output signal in the amplification element. When the output signal of the amplifying element represents a modulated signal modulated by a modulation scheme such as code division multiple access (CDMA) or orthogonal frequency division multiplexing (OFDM), for example, the output The amplitude of the signal varies with time. In FIG. 17A, the peak power PA of the output signal is approximately 4 dB higher than the average power P1, and in FIG. 17B, the peak power PB of the output signal is approximately 2 dB higher than the average power P1.

  For such an amplitude variation type modulation signal, if the distortion rate of the output signal of the amplifying element can be reduced, the signal-to-noise ratio of the matching output signal at the output terminal 111 of the output matching circuit 109 is improved, and out of band. The interference signal is also reduced. For this purpose, it is necessary to amplify the input signal linearly up to the peak power in the post-stage amplifier circuit block 108. However, for example, as shown in FIG. 17A, the post-amplifier circuit block 108 is configured to linearly amplify up to the peak power PA, and if only the peak power PB is used as shown in FIG. Efficiency decreases.

  18A and 18B are characteristic diagrams showing power efficiency when the output signal of the amplification element shown in FIGS. 17A and 17B is generated using the same post-stage amplifier circuit block 108, respectively. In FIG. 18A, an operation curve LA represented by a thick solid line is characterized by an average power P1 and a peak power PA corresponding to the maximum limit power of the linear operation range RLN in the post-stage amplifier circuit block 108. The average power efficiency at the average power P1 is E1, and the peak power efficiency at the peak power PA is EA. In FIG. 18B, an operation curve LB represented by a thick dotted line is characterized by an average power P1 and a peak power PB lower than the peak power PA. The average power efficiency at the average power P1 is E1, and the peak power efficiency at the peak power PB is EB lower than EA. When the post-stage amplifier circuit block 108 is in the state of the operation curve LA, it is called a high peak power mode, and when it is in the state of the operation curve LB, it is called a low peak power mode.

  Thus, in the operation curve LB, since the peak power efficiency EB is lower than EA, the average power efficiency E1 is equivalent to that in the operation curve LA even though the peak power PB of the output signal of the amplification element is low. . Therefore, as shown by an operation curve LC represented by a thick solid line in FIG. 18C, the linear operation range RLN is decreased from the peak power PA or less to the peak power PB or less, and the peak power efficiency at the peak power PB is set to EA. The peak power efficiency at the average power P1 is E2 higher than E1, and higher power efficiency can be achieved in the post-amplifier circuit block 108.

  As described above, according to the sixth embodiment, the switch element included in the second semiconductor chip 102 is switched according to the modes having different peak powers, and the input impedance of the output matching circuit 109 is changed. 6A, 6B, 6E, 7, 8, 9, 10A, 10B, 10C, 11A, 11B, 11C, 12A, 12D, 13A, FIG. 14, any of the switches shown in FIGS. 15A, 15B, 16A, 16B, and 16C may be used. As a result, the input impedance can be optimally adjusted according to the different modes of the peak power, and the power efficiency of the post-amplifier circuit block 108 can be maximized. In the case of applications such as data communication, the peak power may be different in order to increase the transmission rate even if the modulation scheme is the same. Also, in the case of a mobile terminal that supports both W-CDMA (wideband CDMA) and HSDPA (High Speed Downlink Packet Access), the peak power may change considerably due to switching between both systems. is there. In such a case, the sixth embodiment is an effective configuration.

  The present invention can be used for a high frequency power amplifier.

Configuration diagram of a high-frequency power amplifier according to the present invention Sectional drawing of the high frequency power amplifier concerning this invention The block diagram of the 1st example of the high frequency electric power amplifier concerning this invention The block diagram of the 2nd example of the high frequency power amplifier concerning this invention The block diagram of the 3rd example of the high frequency power amplifier concerning this invention The circuit diagram which shows the structure of the high frequency power amplifier for demonstrating this invention First configuration diagram of a high-frequency power amplifier according to the present invention Partial configuration diagram of a high-frequency power amplifier according to the present invention The graph which shows an example of the simulation of the high frequency power amplifier concerning this invention The graph which shows an example of the simulation of the high frequency power amplifier concerning this invention First configuration diagram of a high-frequency power amplifier according to the present invention The 2nd lineblock diagram of the high frequency power amplification device concerning the present invention. Third configuration diagram of the high-frequency power amplifier according to the present invention 4 is a fourth block diagram of the high-frequency power amplifier according to the present invention. The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention Logic table of logic circuit for controlling impedance switching circuit of FIG. 13A The 5th block diagram of the high frequency electric power amplifier concerning this invention The block diagram of the 1st modification of the high frequency power amplifier concerning this invention The block diagram of the 2nd modification of the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The circuit diagram which shows an example of the impedance switching circuit used for the high frequency power amplifier concerning this invention The wave form diagram which shows the operation | movement waveform of the high frequency power amplifier concerning this invention The wave form diagram which shows the operation | movement waveform of the high frequency power amplifier concerning this invention The characteristic view which shows the operating characteristic of the high frequency power amplifier concerning this invention The characteristic view which shows the operating characteristic of the high frequency power amplifier concerning this invention The characteristic view which shows the operating characteristic of the high frequency power amplifier concerning this invention Example of circuit diagram showing conventional configuration Example of configuration diagram showing a conventional module

Explanation of symbols

100, high frequency amplifier (module)
101, semiconductor chip 102 including an amplifier element, semiconductor chip 103 including a matching circuit element and a switch element, a substrate 104, a sealing resin 105, an input matching circuit block 106 of a two-stage amplifier, a pre-stage amplifier element 107 of a two-stage amplifier, an interstage Matching circuit block 108, rear stage amplifying element 109, output matching circuit block 110, amplifier input terminal 111, amplifier output terminals 207 and 208, connection points SL1 to SL6 for biasing the front stage and rear stage amplifying elements, SL10, SL11, microstrip line or inductors C1 to C13, C20 to C27, capacitors SW1 to SW5, switch elements 215, 217, 218, 220, 221, capacitive elements 216, 219, 222, switch elements 223, 225, 226, 228, 229, Induc Elements 224, 227, 230, 231, 232, 233, 234, 235, 236, switch elements 237, 239, 241, 243, 250, 252, 253, 254, 256, 257, 258, 260, capacitors 238, 240 242, 244, 251, 255, 259, switch element 245, logic circuit and control voltage generation circuit 246, semiconductor chip 300 including matching circuit element and switch element, variable capacitor element 301, capacitor element 302, diode 303, inductor element 304, capacitive element 305, resistor 306, output load circuit 600, frequency detector 601, power level detector 602, mode detector

Claims (18)

A first semiconductor chip including a main amplification stage having a first high frequency amplification element;
A second semiconductor chip including a main matching stage having a first switch element,
The main amplification stage includes a first output terminal (T1) for outputting a first signal amplified by the first high-frequency amplification element,
The main alignment stage is:
A first input terminal (T2) for receiving a first signal;
And a first high-frequency matching circuit element for matching the first signal. The second semiconductor chip includes a pre-alignment stage provided on the upstream side of the main amplification stage,
The pre-alignment stage is
A second high-frequency matching circuit element for matching the input second signal;
A second output terminal (T3) for outputting the second signal after matching,
The main amplification stage includes:
A second input terminal (T4) for receiving the second signal after matching;
The high frequency power amplifier according to claim 1, wherein the first high frequency amplifying element amplifies based on the matched second signal. The second semiconductor chip includes an intermediate matching stage provided on the upstream side of the main amplification stage,
The first semiconductor chip includes a preamplification stage provided on the upstream side of the intermediate matching stage,
The preamplification stage comprises:
A second high frequency amplification element;
A second output terminal (T5) for outputting a second signal amplified by the second high-frequency amplification element,
The intermediate alignment stage is
A second input terminal (T6) for receiving a second signal;
A second high-frequency matching circuit element for matching the second signal;
A third output terminal (T7) for outputting the second signal after matching,
The main amplification stage includes a third input terminal (T8) for inputting the second signal after matching,
The high frequency power amplifier according to claim 1, wherein the first high frequency amplifying element amplifies based on the matched second signal.   The high frequency power amplifier according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are integrally formed with each other. further,
A substrate on which the first semiconductor chip and the second semiconductor chip are mounted;
The high frequency power amplifying device according to claim 1, further comprising: a high frequency circuit element formed on the substrate and including a microstrip line. further,
A substrate on which the first semiconductor chip and the second semiconductor chip are mounted;
The high frequency power amplifier according to claim 1, further comprising a passive element mounted on the substrate. The second semiconductor chip includes a capacitor,
The high frequency power amplifying apparatus according to claim 1, wherein the first switch element is connected to the capacitor. The second semiconductor chip includes an inductor,
The high frequency power amplifier according to claim 1, wherein the first switch element is connected to the inductor.   The high frequency power amplifier according to claim 1, wherein the first switch element operates as a capacitor in an off state.   The high frequency power amplifier according to claim 1, wherein the second semiconductor chip includes a logic circuit.   The high-frequency power amplifier according to claim 1, wherein the second semiconductor chip includes a capacitance of 10 pF or more.   The high-frequency power amplifying apparatus according to claim 1, wherein the second semiconductor chip includes at least one of an element or a circuit having a memory function.   The high frequency power amplifier according to claim 1, wherein the second semiconductor chip includes at least one of an element or a circuit having a trimming function.   2. The high-frequency power amplifying apparatus according to claim 1, wherein at least one of the first or second semiconductor chip includes a via hole that connects a front surface and a back surface of the semiconductor chip.   2. The high frequency power amplifier according to claim 1, wherein the first switch element is formed of a field effect transistor or a heterojunction field effect transistor.   The high frequency power amplifying apparatus according to claim 1, wherein the first high frequency amplifying element is formed of a heterogeneous junction bipolar transistor.   The high-frequency power amplifier according to claim 1, wherein the second semiconductor chip includes at least a part of a bias supply circuit that generates a bias signal to be supplied to the first high-frequency amplifier.   2. The high frequency power amplifier according to claim 1, wherein the first semiconductor chip includes a capacitor having one end connected to the first output terminal and the other end grounded.

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