JP2005175560A - High frequency power amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency power amplifier circuit capable of improving its controllability at rising of an output power thereof by decreasing a variation in a rate of change of the output power with respect to an output control voltage and to provide a power module. <P>SOLUTION: In the high frequency power amplifier circuit comprising multi-stage connections of a plurality of power amplifier transistors (Q1 to Q3), an operating voltage (Vdd) of at least the first stage power amplifier transistor (Q1) is changed with a power control voltage (Vapc) by fixing a bias voltage of the gate or the base, and the operating voltage (Vdd) of the final stage power amplifier transistor (Q3) is fixed to change the bias voltage (Vg) of the gate or the base in response to the power control voltage (Vapc). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a high-frequency power amplifier circuit that is used in a wireless communication system such as a cellular phone and amplifies and outputs a high-frequency signal, and a technique that is effective when applied to an electronic component incorporating the high-frequency power amplifier circuit. The present invention relates to a technique for improving controllability at the time of starting up output power of a circuit.

  In general, a transmission unit in a wireless communication device (mobile communication device) such as a mobile phone incorporates a modulation circuit that modulates a transmission signal and a high-frequency power amplification circuit that amplifies the modulated signal. The power of the high-frequency power amplifier circuit of the cellular phone is raised and lowered by a control voltage (Vramp) from a control circuit such as a baseband circuit or a microprocessor during transmission. Specifically, in the GSM standard, the output power is reduced from a level of −25 dBm or less to +33 dBm at the start of transmission, and when the transmission slot is switched, the output power is temporarily reduced from +33 dBm to nearly 0 dBm and then raised to +33 dBm. There is a need. Moreover, the GSM standard stipulates that this slot switching is completed within a short time such as several tens of microseconds.

  Conventional power control methods for mobile phones include a method for controlling the gain of a high-frequency power amplifier circuit while keeping the amplitude of the input signal constant, and a method for changing the amplitude of the input signal while keeping the gain of the high-frequency power amplifier circuit constant. There is. Among these, there are a method of changing the operating voltage and a method of changing the gate bias voltage as a method of controlling the gain of the high-frequency power amplifier circuit while keeping the amplitude of the input signal constant.

In addition, a high-frequency power amplifier circuit in a conventional mobile phone is often configured such that a plurality of power amplification transistors are connected in multiple stages (generally, there are three stages). As shown in FIG. 8, the control of the amplification factor of the high frequency power amplifier circuit by the gate bias method is performed by using the voltages Vg1, Vg2, and Vg3 obtained by dividing the output control voltage Vapc by resistors R11 to R19 at each amplification stage of the high frequency power amplifier circuit. This is performed by applying the voltage to the gate terminals (base terminals in the case of bipolar transistors) of the transistors Q1 to Q3 (see, for example, Patent Document 1). Also, the control of the amplification factor of the high-frequency power amplifier circuit by the operating voltage control method is performed by simultaneously changing the operating voltage (Vdd) of each amplification stage according to the output control voltage Vapc.
JP 2001-7657 A

  Conventionally, in the power start-up / down control in which the power is changed to a desired level in a short time by the control voltage (Vramp) from the baseband circuit as described above, the control voltage (Vramp) output from the baseband circuit is changed. Setting is very difficult, and simply increasing the control voltage causes a problem that the desired time mask is not satisfied. As a result of studying the cause, the present inventors have shown a broken line in FIG. 4 in a system in which the power is controlled by changing the gate bias voltage Vg or the operating voltage Vdd of all three amplification stages. Thus, it has been found that the change in output power change rate (ΔPout / ΔVapc) with respect to the output control voltage is large.

An object of the present invention is to provide a high frequency power amplifier circuit capable of reducing the variation in the rate of change of the output power with respect to the output control voltage and improving the controllability when the output power is raised.
Another object of the present invention is to provide a technique capable of reducing the element size of the power amplification transistor, reducing the occupied area of the high frequency power amplification circuit, and reducing the size of the module.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, in a high-frequency power amplifier circuit (power amplifier and power module) in which a plurality of power amplification transistors are connected in multiple stages, at least the first stage power amplification transistor has its gate or base bias voltage fixed and an operating voltage ( Vdd) is changed according to the power control voltage (Vapc), and the power amplification transistor in the final stage fixes the operating voltage (Vdd) and the gate or base bias voltage (Vg) is changed to the power control voltage (Vapc). It is made to change according to it.

  According to the above-described means, since the rate of change of the output power of the first stage power amplification transistor can be suppressed, the variation in the rate of change of the output power with respect to the output control voltage is reduced over the entire control range and output from the control circuit. The control voltage to be set can be easily set.

  Desirably, the power amplification transistor at least before the final stage is composed of a bipolar transistor having a compound semiconductor chip as a substrate. Thereby, the element size can be reduced, the area occupied by the high-frequency power amplifier circuit can be reduced, and the module can be downsized.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, the control voltage output from the control circuit is improved by reducing the variation in the rate of change of the output power with respect to the output control voltage over the entire control range to improve the controllability when the output power of the high-frequency power amplifier circuit is started There is an effect that it is possible to realize a high-frequency power amplifier circuit that can be easily set.

  Further, according to the present invention, it is possible to reduce the element size of the power amplification transistor, to reduce the occupied area of the high frequency power amplification circuit, and to reduce the size of the module.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of a high frequency power amplifier circuit (hereinafter referred to as a power amplifier) to which the present invention is applied and a bias generation circuit thereof.
In FIG. 1, Q1 is a power amplification transistor constituting the first amplification stage for amplifying the input high-frequency signal Pin, and Q2 is a second amplification connected so that the drain voltage of Q1 is input to the gate terminal. The power amplification transistor constituting the stage, Q3 is the power amplification transistor of the final amplification stage connected so that the drain voltage of Q2 is input to the gate terminal, and L1 to L3 are the power amplification of the power supply voltage terminal and each amplification stage Inductance elements connected between the drain terminals of the transistors Q1 to Q3, MN0 to MN3 are impedance matching circuits connected before and after the power amplification transistor, and CDC1 to CDC4 are capacitive elements that block the DC component.

  In this embodiment, the power amplification transistors Q1 to Q3 are constituted by MOSFETs (insulated gate field effect transistors). A fixed bias voltage Vbias is applied to the gate terminals of the first-stage and second-stage power amplification transistors Q1, Q2 via resistors R1, R2, and the first-stage and second-stage powers. The drain voltage Vdd1 of the power transistor Q4 controlled by the output of the operational amplifier AMP1 is applied to the drain terminals of the amplifying transistors Q1 and Q2 via the inductors L1 and L2. The power supply transistor Q4 is preferably a P-channel MOSFET.

  A voltage obtained by dividing the drain voltage Vdd1 of the power transistor Q4 controlled by the output of the operational amplifier AMP1 with resistors R3 and R4 is applied as a gate bias voltage Vg3 to the gate terminal of the third-stage power amplification transistor Q3. In addition, the power supply voltage Vdd before being converted by the power supply transistor Q4 is applied to the drain terminal of the third-stage power amplification transistor Q3 via the inductor L3.

  In this embodiment, the output control voltage Vapc is input to the non-inverting input terminal of the operational amplifier AMP1, and the drain voltage of the power transistor Q4 is fed back to the inverting input terminal of the operational amplifier AMP1. Thereby, the power transistor Q4 is controlled by the output of the operational amplifier AMP1 so that the drain voltage coincides with the output control voltage Vapc, and output control is performed on the drain terminals of the first and second power amplification transistors Q1 and Q2. A voltage Vdd1 corresponding to the voltage Vapc is applied.

  That is, the gains of the first-stage and second-stage power amplification transistors Q1 and Q2 are controlled by changing the drain voltage according to the output control voltage Vapc while the gate voltage is fixed. The output control voltage Vapc is, for example, an error amplifier that compares the detection signal Vsns of the output Pout with a signal Vramp that indicates an output level supplied from a control circuit such as a baseband circuit and outputs a voltage corresponding to the potential difference. The voltage is output from such a circuit.

  In the circuit as shown in FIG. 8, the gain is controlled by changing the gate voltages Vg1 and Vg2 of the first and second stage power amplification transistors Q1 and Q2 according to the output control voltage Vapc. The output voltage Vout2 of the power amplifying transistor Q2 changes as shown by the broken line in FIG. 2, but the drain voltages of the first and second power amplifying transistors Q1 and Q2 depend on the output control voltage Vapc. In a circuit such as this embodiment in which the gain is controlled by being changed, the output voltage Vout2 of the power amplification transistor Q2 is gradually changed with respect to the output control voltage Vapc as shown by the solid line in FIG. Will be able to.

  On the other hand, in this embodiment, the gate bias voltage Vg3 is changed according to the output control voltage Vapc while the operating voltage (drain voltage) of the third-stage power amplification transistor Q3 is fixed. As a result, the output power Pout of the third-stage power amplification transistor Q3 changes linearly in a region where the output control voltage Vapc is low as shown in FIG. As a result, the power amplifier according to the present embodiment, as shown by a solid line in FIG. 4, determines the variation amount of the output power (ΔPout / ΔVapc) with respect to the output control voltage Vapc as the output power of the conventional circuit of FIG. Can be made smaller than the fluctuation amount of the change rate (broken line in FIG. 4).

  Similarly to the first-stage and second-stage power amplification transistors Q1 and Q2, the third-stage power amplification transistor Q3 is also configured to variably control the operating voltage (drain voltage) by fixing the gate voltage. In this configuration, the current flowing through Q3 is considerably larger than Q1 and Q2, so that the element size (gate width) of the power transistor Q4 becomes large. The transistor Q3 has an advantage that an increase in circuit area can be suppressed by configuring the gate bias voltage Vg3 to change in accordance with the output control voltage Vapc while the operating voltage (drain voltage) is fixed.

  The power amplifier of the present embodiment includes a semiconductor chip on which the first and second power amplification transistors Q1 and Q2 are formed, a semiconductor chip on which the third power amplification transistor Q3 is formed, The semiconductor chip on which the operational amplifier AMP1 and the power transistor Q4 are formed is mounted on an insulating substrate such as a ceramic on which a wiring pattern is formed together with discrete components such as inductors L1 to L3 and DC blocking capacitors CDC1 to CDC4. By doing so, it is configured as a module. The insulating substrate that constitutes the module has printed wiring on the surface and inside, and a plurality of semiconductor chips and components mounted on the substrate are electrically connected by the printed wiring and bonding wires as if one electronic component It can be handled as

  In such a module, the impedance matching circuits MN0 to MN3 can be composed of a transmission line (printed wiring) and a capacitive element connected between a predetermined portion of the transmission line and a ground point. In addition, when the substrate has a multilayer structure in which a plurality of dielectric plates are stacked, the capacitor element can be configured using a capacitor having electrodes as conductive layers formed on the front and back surfaces of any one of the dielectric plates. . For the inductors L1 to L3, a λ / 4 transmission line having an electrical length of ¼ wavelength of the fundamental wave can be used. Therefore, the inductors L1 to L3 can also be elements built in the substrate. Further, L1 of the inductors L1 to L3 can be formed on the same silicon chip as the first-stage power amplification transistor Q1 or the power supply transistor Q4. Alternatively, the first and second stage power amplification transistors Q1 and Q2, the third stage power amplification transistor Q3, the operational amplifier AMP1 and the power transistor Q4 may all be formed on one silicon chip. Is possible.

FIG. 5 shows a second embodiment of a power amplifier to which the present invention is applied and its bias generation circuit.
In this embodiment, a voltage obtained by dividing the voltage Vdd1 generated by the power transistor Q4 by the resistance ratio of the resistors R3 and R4 as in the embodiment of FIG. 1 is the gate terminal of the third-stage power amplification transistor Q3. , A diode-connected transistor Q5 whose gate is connected in common with the third-stage power amplification transistor Q3, a variable current source VC1 for flowing a current according to the output control voltage Vapc, and the variable current source VC1 A current mirror CM1 that folds the current generated by the current mirror CM1 and causes the current of the current mirror CM1 to flow through the transistor Q5 so that an idle current corresponding to the ratio of the gate widths of Q5 and Q3 flows through Q3 to give a bias. It is a thing. A P-channel MOSFET is used for the transistor constituting the current mirror CM1, and an N-channel MOSFET is used for the transistor Q5 through which the current from the current mirror CM1 flows.

  As in the first embodiment, the drain voltage of the third-stage power amplification transistor Q3 is the power supply voltage Vdd before being converted by the power supply transistor Q4. Therefore, in the third-stage power amplification transistor Q3, the gate bias voltage Vg3 is changed according to the output control voltage Vapc while the operating voltage (drain voltage) is fixed. As in the first embodiment, the first and second power amplification transistors Q1 and Q2 have their drain voltages changed according to the output control voltage Vapc while the gate voltage is fixed. The gain is controlled. As described above, also in the power amplifier in which a bias is applied to the third-stage power amplification transistor Q3 by the current mirror method, the same effect as the first embodiment can be obtained. That is, the amount of change in the output power change rate (ΔPout / ΔVapc) with respect to the output control voltage Vapc can be made smaller than the amount of change in the output power change rate of the conventional circuit of FIG.

FIG. 6 shows a third embodiment of a power amplifier to which the present invention is applied and its bias generation circuit.
In this embodiment, HBTs (heterojunction bipolar transistors) are used instead of MOSFETs as the first and second stage power amplification transistors Q1 and Q2 in the first embodiment shown in FIG. . In this embodiment, the same effects as those of the first embodiment can be obtained in terms of circuit, and the HBT has a higher current density and a smaller element size than the MOSFET, so that the power amplifier of the first embodiment can be obtained. There is an advantage that the area occupied by the circuit is smaller than that of the circuit.

  In this embodiment, the HBT formed on the semi-insulating compound semiconductor chip having a higher resistivity than silicon such as GaAs is used as the first and second power amplification transistors Q1 and Q2. Wiring made of a conductive layer formed on a GaAs chip can reduce transmission loss compared to wiring formed on a silicon chip. Therefore, in this embodiment, the first-stage power amplification transistor Q1, the impedance matching circuit MN0, the DC-cut capacitor CDC1 and the resistor R1 are provided on one semiconductor chip CHP1, and the second-stage power amplification transistor. The transistor Q2, the impedance matching circuit MN1, the DC cutting capacitor CDC2 and the resistor R2 can be formed on the other semiconductor chip CHP2, and the module can be reduced in size as compared with the first embodiment. There is an advantage.

  Regarding the third-stage power amplification transistor Q3, the operational amplifier AMP1 and the power supply transistor Q4, as indicated by broken lines CHP3 and CHP4 in FIG. 6, the first-stage and second-stage power amplification transistors Q1 and Q2 May be formed on a separate chip from the chips CHP1 and CHP2 on which the chip is formed, or may be formed on one chip as indicated by a broken line CHP0 in FIG. The first and second power amplification transistors Q1 and Q2, impedance matching circuits MN0 and MN1, DC cut capacitors CDC1 and CDC2, and resistors R1 and R2 are formed on one semiconductor chip CHP1. It is also possible.

  Further, in the present embodiment, the first and second stage power amplification transistors Q1 and Q2 are composed of HBTs, and the third stage power amplification transistor Q3 is composed of MOSFETs. The power amplification transistors Q1 to Q3 in the second stage are all configured by HBT, or, contrary to FIG. 6, the power amplification transistors Q1 and Q2 in the first and second stages are configured by MOSFETs, and the third stage The power amplifying transistor Q3 may be composed of an HBT. Furthermore, it is also possible to use a bipolar transistor using SiGe as a substrate instead of the HBT. When bipolar transistors having SiGe as a substrate are used as the first and second stage power amplification transistors Q1 and Q2, a third stage power amplification transistor Q3 comprising these transistors Q1 and Q2 and a MOSFET is used. Can be easily formed on one chip.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiments, the present invention is applied to a power amplifier having a three-stage configuration, but the present invention can also be applied to a power amplifier having a two-stage configuration. Even in such a case, the first stage power amplification transistor is configured such that the drain voltage is changed according to the output control voltage Vapc while the gate voltage is fixed, so that the gain is controlled. The amplification transistor may be configured such that the gain is controlled by changing the gate voltage in accordance with the output control voltage Vapc while the drain voltage is fixed.

  In the embodiment, the second-stage power amplifying transistor Q2 has a fixed gate bias so that the drain voltage Vdd1 is changed according to the output control voltage Vapc, like the first-stage power amplifying transistor Q1. However, the second-stage power amplifying transistor Q2 has a fixed drain voltage so that the gate bias voltage is changed according to the output control voltage Vapc, like the third-stage power amplifying transistor Q3. It may be configured as follows.

  Further, in the above embodiment, the operating voltage Vdd1 of the first and second stage power amplification transistors Q1 and Q2 is applied from the common power supply transistor Q3, but another pair of operational amplifier and power supply transistor is provided. It is also possible to provide an operating voltage separately.

  In the above description, the case where the invention made mainly by the present inventor is applied to the power amplifier and power module constituting the mobile phone capable of transmission / reception by the GSM method, which is the field of use behind it, has been described. Is not limited to this, but a mobile phone capable of transmission / reception by other communication methods such as CDMA (Code Division Multiple Access), or by a plurality of communication methods such as GMS, DCS (Digital Cellular System) and PCS (Personal Communications System). It can be used for power amplifiers and power modules that constitute wireless communication systems such as mobile phones.

1 is a block diagram showing a first embodiment of a high-frequency power amplifier circuit (power amplifier) to which the present invention is applied and its bias generation circuit; FIG. FIG. 10 is a characteristic diagram showing the relationship between the output voltage Vout2 and the output control voltage Vapc of the second-stage power amplification transistor in the high-frequency power amplifier circuit of the example and the conventional high-frequency power amplifier circuit (FIG. 8). FIG. 10 is a characteristic diagram showing the relationship between the output power Pout of the third stage power amplification transistor and the output control voltage Vapc in the high frequency power amplifier circuit of the example and the conventional high frequency power amplifier circuit (FIG. 8). It is a characteristic view which shows the relationship between the output power Pout of the power amplification transistor of the 3rd stage in the high frequency power amplifier circuit of an Example, and the conventional high frequency power amplifier circuit (FIG. 8), and the change rate (slope) of output power. It is a block diagram which shows the 2nd Example of the high frequency power amplifier circuit to which this invention is applied, and its bias production | generation circuit. It is a block diagram which shows the 3rd Example of the high frequency power amplifier circuit to which this invention is applied, and its bias production | generation circuit. It is a block diagram which shows the modification of the Example of the high frequency power amplifier circuit to which this invention is applied. It is a block diagram which shows the structural example of the conventional high frequency power amplifier circuit and its bias generation circuit.

Explanation of symbols

Q1 First stage power amplification transistor Q2 Second stage power amplification transistor Q3 Third stage power amplification transistor Q4 Power supply transistor Vapc Output power control voltage

Claims (10)

  A plurality of power amplification transistors are connected in multiple stages, and a variable operation voltage generation circuit that generates a voltage whose level is controlled in accordance with the power control voltage is provided. At least the first stage power amplification transistor has its gate or base bias A voltage generated by the variable operating voltage generation circuit is supplied as an operating voltage in a state where the voltage is fixed, and an amplification operation is performed, and the power amplifying transistor in the final stage has the variable operating voltage in a state where the operating voltage is fixed A high frequency power amplifier circuit which performs an amplification operation by supplying a voltage generated by a generation circuit as a bias voltage of a gate or a base.   Three power amplifying transistors are connected in multiple stages, and the second stage power amplifying transistor operates with the voltage generated by the variable operating voltage generating circuit with its gate or base bias voltage fixed. The high-frequency power amplifier circuit according to claim 1, wherein the amplifier operates by being supplied as a voltage.   Three power amplification transistors are connected in multiple stages, and the voltage generated by the variable operation voltage generation circuit is the gate or base bias of the second stage power amplification transistor with its operation voltage fixed. The high-frequency power amplifier circuit according to claim 1, wherein the amplifier operates by being supplied as a voltage.   4. The high frequency power amplifier circuit according to claim 1, wherein the first stage power amplification transistor is a bipolar transistor.   5. The high frequency power amplifier circuit according to claim 1, wherein the final stage power amplification transistor is an insulated gate field effect transistor.   5. The high frequency power amplifier circuit according to claim 4, wherein the first stage power amplification transistor is a heterojunction bipolar transistor.   Between the input terminal to which a high frequency signal to be amplified is input and the gate terminal or the base terminal of the first stage power amplification transistor, a capacitor element and an impedance matching circuit for blocking a direct current component are provided, and the first stage power is provided. 7. The high frequency power amplifier circuit according to claim 6, wherein the amplifying transistor, the capacitive element, and the impedance matching circuit are formed on the same compound semiconductor chip.   The variable operating voltage generation circuit and the final-stage power amplification transistor are respectively formed on a semiconductor chip separate from the first-stage power amplification transistor and the semiconductor chip on which the capacitance element and the impedance matching circuit are formed. The high frequency power amplifier circuit according to claim 7, wherein the high frequency power amplifier circuit is provided.   The variable operating voltage generation circuit and the final-stage power amplification transistor are formed on the same semiconductor chip separate from the first-stage power amplification transistor and the semiconductor chip on which the capacitive element and the impedance matching circuit are formed. The high frequency power amplifier circuit according to claim 7, wherein the high frequency power amplifier circuit is provided.   Between the input terminal to which a high frequency signal to be amplified is input and the gate terminal or the base terminal of the first stage power amplification transistor, a capacitor element and an impedance matching circuit for blocking a direct current component are provided, and the first stage power is provided. The amplifying transistor and the final stage power amplifying transistor are formed on a semiconductor chip, and the semiconductor chip, the capacitor element, and the elements constituting the impedance matching circuit are mounted on the same insulating substrate. The high frequency power amplifier circuit according to claim 6.

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