JPWO2004073063A1 - Electronic device and semiconductor device - Google Patents

Electronic device and semiconductor device Download PDF

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Publication number
JPWO2004073063A1
JPWO2004073063A1 JP2004568182A JP2004568182A JPWO2004073063A1 JP WO2004073063 A1 JPWO2004073063 A1 JP WO2004073063A1 JP 2004568182 A JP2004568182 A JP 2004568182A JP 2004568182 A JP2004568182 A JP 2004568182A JP WO2004073063 A1 JPWO2004073063 A1 JP WO2004073063A1
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Prior art keywords
tab
lead
electrode terminal
circuit unit
electronic device
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Granted
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JP2004568182A
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Japanese (ja)
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JP4137059B2 (en
Inventor
団野　忠敏
忠敏 団野
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Renesas Technology Corp
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Renesas Technology Corp
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract

低雑音増幅器を含む高周波部アナログ信号処理ＩＣが組み込まれた高周波パワーモジュール（１）の実装構造であり、タブ（４）と、複数のリード（７）と、複数の電極端子および回路部を有する半導体チップ（３）と、前記複数の電極端子とリード（７）とを接続する複数のワイヤ（１０）と、前記複数の電極端子とタブ（４）とを接続する複数のワイヤ（１０）とを有する高周波パワーモジュール（１）と、複数のスルーホール（８４）により低インダクタンス化されたグランド電位をタブ（４）に供給可能な実装基板（８０）とからなり、前記回路部に入力信号を送る信号配線の両側に固定電位の配線が配置され、かつ複数のスルーホール（８４）によって低インダクタンス化されたグランド電位を実装基板（８０）からタブ（４）に供給することにより、１系統の通信システムを使用中の他の系統の通信システムとの間でのクロストークが発生しなくなり、携帯電話機などの電子装置において良好な通話が可能になる。A mounting structure of a high-frequency power module (1) incorporating a high-frequency section analog signal processing IC including a low-noise amplifier, and includes a tab (4), a plurality of leads (7), a plurality of electrode terminals, and a circuit section. A plurality of wires (10) for connecting the semiconductor chip (3), the plurality of electrode terminals and the leads (7), and a plurality of wires (10) for connecting the plurality of electrode terminals and the tab (4); And a mounting board (80) capable of supplying a ground potential reduced in inductance by a plurality of through holes (84) to the tab (4), and an input signal is supplied to the circuit unit. The fixed potential wiring is arranged on both sides of the signal wiring to be sent, and the ground potential reduced in inductance by the plurality of through holes (84) is transferred from the mounting board (80) to the tab (4). By feeding, 1 crosstalk between other strains communication systems in use systematic communication system is not generated, allowing a good call in an electronic device such as a mobile phone.

Description

本発明は、電子装置および半導体装置に関し、特に、微弱な信号を増幅する低雑音増幅器（ＬＮＡ：Ｌｏｗ Ｎｏｉｓｅ Ａｍｐｌｉｆｉｅｒ）を含む高周波部アナログ信号処理ＩＣを組み込んだ無線通信装置（電子装置）および高周波パワーモジュール（半導体装置）に適用して有効な技術に関する。  The present invention relates to an electronic device and a semiconductor device, and in particular, a wireless communication device (electronic device) incorporating a high-frequency unit analog signal processing IC including a low noise amplifier (LNA) that amplifies a weak signal and a high-frequency power. The present invention relates to a technology effective when applied to a module (semiconductor device).

携帯電話機などの移動体通信機（移動端末）は、複数の通信システムに対応できるような構成になっている。すなわち、携帯電話機の送受信機（フロントエンド）には複数の通信システムの送受信を行うように、複数の回路系が組み込まれている。例えば、通信方式（システム）の異なる携帯電話（例えばセルラー電話機）間での通話を可能とする方式としてデュアルバンド通信方式が知られている。
デュアルバンド方式については、例えば、搬送周波数帯が８８０〜９１５ＭＨｚのＧＳＭ（Ｇｌｏｂａｌ Ｓｙｓｔｅｍ ｆｏｒ Ｍｏｂｉｌｅ Ｃｏｍｍｕｎｉｃａｔｉｏｎｓ）と、搬送周波数帯が１７１０〜１７８５ＭＨｚのＤＣＳ−１８００（Ｄｉｇｉｔａｌ Ｃｅｌｌｕｌａｒ Ｓｙｓｔｅｍ １８００）によるデュアルバンド方式およびデュアルバンド用高周波電力増幅器について知られている。
また、特開平１１−１８６９２１号公報には、ＰＣＮ（Ｐｅｒｓｏｎａｌ Ｃｏｍｍｕｎｉｃａｔｉｏｎｓ Ｎｅｔｗｏｒｋ：ＤＣＳ−１８００）、ＰＣＳ（Ｐｅｒｓｏｎａｌ Ｃｏｍｍｕｎｉｃａｔｉｏｎｓ Ｓｅｒｖｉｃｅ：ＤＣＳ−１９００）およびＧＳＭなどの携帯電話システムに利用できる多バンド移動体通信装置が開示されている。
また、携帯電話機のフロントエンドでは、ＧＳＭ用の高周波部アナログ信号処理回路のモジュール化が図られている。例えば、ＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ−Ｅｆｆｅｃｔ−Ｔｒａｎｓｉｓｔｏｒ）によるデュアルバンドまたはトリプルバンドのＧＳＭ用ＲＦ（Ｒａｄｉｏ Ｆｒｅｑｕｅｎｃｙ）パワーモジュールが有る。
デュアルバンド方式はＧＳＭおよびＤＣＳ１８００方式などの二つの通信系の信号を処理するものであり、トリプルバンド方式はＧＳＭおよびＤＣＳ（Ｄｉｇｉｔａｌ Ｃｅｌｌｕｌａｒ Ｓｙｓｔｅｍ）１８００並びにＰＣＳ１９００方式などの三つの通信系の信号を処理するものである。ＧＳＭとしては、ＧＳＭ９００あるいはＧＳＭ８５０が組み込まれる。
また、高周波パワーモジュールは、ＬＮＡ、ミキサ、ＰＬＬ（Ｐｈａｓｅ−Ｌｏｃｋｅｄ Ｌｏｏｐ）シンセサイザ、オートキャリブレーション付ＰＧＡ（Ｐｒｏｇｒａｍｍａｂｌｅ Ｇａｉｎ Ａｍｐｌｉｆｉｅｒ）、ＩＱ変調器／復調器、オフセットＰＬＬ、ＶＣＯ（Ｖｏｌｔａｇｅ−Ｃｏｎｔｒｏｌｌｅｄ Ｏｓｃｉｌｌａｔｏｒ）などをモノリシックに集積したワンチップの半導体素子が組み込まれている。
一方、携帯電話機は、その持ち運びが便利なように小型・軽量化が要請されている。この結果、高周波パワーモジュールなどの半導体装置もより小型・軽量化が望まれている。
半導体装置は、そのパッケージの形態によって種々のものがあるが、その一つとして、絶縁性樹脂の封止体（パッケージ）の裏面（実装面）にリード（外部電極端子）を露出させ、封止体の側面に長くリードを突出させないノンリード型半導体装置が知られている。
ノンリード型半導体装置としては、封止体の裏面の対向する２辺に沿ってリードを露出させるＳＯＮ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｎｏｎ−Ｌｅａｄｅｄ Ｐａｃｋａｇｅ）や、封止体の裏面の４辺側にリードを露出させるＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎ−Ｌｅａｄｅｄ Ｐａｃｋａｇｅ）がある。小型でリード曲がりが発生しないノンリード型半導体装置については、例えば特開２００１−３１３３６３号公報に記載されている。
この文献に記載されている樹脂封止型半導体装置は、半導体チップを固定するダイパッドとワイヤを接続するワイヤボンディング部とを有するアイランドがあり、ダイパッド上に半導体チップが固定され、半導体チップの各電極端子は、リードやアイランドのワイヤボンディング部に接続される構造になっている。ダイパッドとワイヤボンディング部との間に空隙部を設けて熱ストレスによるボンディングされたワイヤの外れや切断を防止している。このような構造では、半導体チップのアース端子とアイランドをワイヤで接続することによって、アイランドをアースリードとしてプリント基板などに接続できる。
また、特開平１１−２５１４９４号公報には、半導体素子搭載部をグランドとする携帯電話機などに用いられるリード構造がガルウィング型となる高周波デバイスについて記載されている。この技術では、半導体素子の電極とリードをワイヤで接続する以外に、ダイパッドをグランド電極として利用するため、半導体素子の電極と半導体素子搭載部とをワイヤで接続している（以降、この接続をダウンボンディングと呼ぶ）。ダウンボンディングするため、半導体素子搭載部は半導体素子よりも大きく、また実装状態では、半導体素子の外側に半導体素子搭載部の周縁部分が突出し、この部分にワイヤが接続される構造になっている。
他方、本出願人においては、高周波パワーモジュールをノンリード型半導体装置に組み込み、かつグランド電位の安定化のために、高周波パワーモジュールを構成する各回路部のグランド端子をワイヤを介してタブに電気的に接続する手法の採用を検討した。ダウンボンディングを採用することにより、外部電極端子の数を少なくでき、パッケージの小型化が図れ、最終的には半導体装置の小型化が図れる。
しかし、無線通信系（通信システム）を用途とする高周波パワーモジュールでは、以下のような問題が発生することが判明した。
携帯電話機の受信系では、アンテナで捕らえた信号は低雑音増幅器（ＬＮＡ）で増幅されるが、入力信号は極めて微弱である。このため、各回路部、特に周期的に動作する発振器の動作に応じて共通端子であるタブの電位、すなわちグランド電位が変動し、これに起因して一部の回路部との間でクロストークが発生し、出力が変動して良好な通話ができなくなる。
特に、リード間クロストークによる誘起電流、またはグランド電位の変動による信号波形の歪みが通信システムから出力され、この出力信号が使用中の通信システムに入ってしまい雑音となる。
このようなグランド電位の変動、およびクロストークの影響を受け易い回路部は、低雑音増幅器（ＬＮＡ）以外では、例えば、高周波を扱うＲＦＶＣＯ（高周波電圧制御発振器）などがある。
つまり、低雑音増幅器（ＬＮＡ）や高周波電圧制御発振器（ＲＦＶＣＯ）は、グランド電位の変動、およびクロストークの影響などを受け易く、これによって、高周波パワーモジュールを搭載した携帯電話機などの電子装置の高周波特性が損ねることが問題である。
本発明の目的は、無線通信装置などを用途とする高周波パワーモジュールが搭載された電子装置において、高周波特性を向上させる電子装置を提供することにある。
本発明の他の目的は、信頼性の向上を図る電子装置（無線通信装置）を提供することにある。
本発明の他の目的は、低雑音増幅器や高周波電圧制御発振器などの回路部が、他の回路部のグランド電位の変動によるクロストークの影響を受け難くできる半導体装置を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。Mobile communication devices (mobile terminals) such as mobile phones are configured to be compatible with a plurality of communication systems. That is, a plurality of circuit systems are incorporated in a transceiver (front end) of a mobile phone so as to perform transmission / reception of a plurality of communication systems. For example, a dual-band communication system is known as a system that enables a call between mobile phones (for example, cellular phones) having different communication systems (systems).
As for the dual band method, for example, a dual band method and a dual band by GSM (Global System for Mobile Communications) having a carrier frequency band of 880 to 915 MHz and DCS-1800 (Digital Cellular System 1800) having a carrier frequency band of 1710 to 1785 MHz. High frequency power amplifiers are known.
Japanese Patent Application Laid-Open No. 11-186922 discloses a multiband mobile communication device that can be used for a mobile phone system such as PCN (Personal Communications Network: DCS-1800), PCS (Personal Communications Service: DCS-1900), and GSM. It is disclosed.
Further, at the front end of a mobile phone, a high frequency analog signal processing circuit for GSM is modularized. For example, there is a dual-band or triple-band RF (Radio Frequency) power module for GSM using a MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor).
The dual-band method processes signals of two communication systems such as GSM and DCS1800, and the triple-band method processes signals of three communication systems such as GSM, DCS (Digital Cellular System) 1800 and PCS1900. Is. GSM900 or GSM850 is incorporated as GSM.
The high-frequency power module includes an LNA, a mixer, a PLL (Phase-Locked Loop) synthesizer, a PGA (Programmable Gain Amplifier) with auto calibration, an IQ modulator / demodulator, an offset PLL, a VCO (Voltage-Controlled Oscillator), and the like. One-chip semiconductor elements monolithically integrated are incorporated.
On the other hand, mobile phones are required to be small and light so that they can be easily carried. As a result, semiconductor devices such as high-frequency power modules are also desired to be smaller and lighter.
There are various types of semiconductor devices depending on the form of the package, and as one of them, the lead (external electrode terminal) is exposed on the back surface (mounting surface) of the sealing body (package) of insulating resin and sealed. 2. Description of the Related Art Non-lead type semiconductor devices are known in which a lead does not protrude long on the side of a body.
As a non-lead type semiconductor device, SON (Small Outline Non-Leaded Package) that exposes leads along two opposite sides of the back surface of the sealing body, or QFN that exposes leads on the four sides of the back surface of the sealing body. (Quad Flat Non-Leaded Package). A non-lead type semiconductor device which is small and does not generate lead bending is described in, for example, Japanese Patent Application Laid-Open No. 2001-313363.
The resin-encapsulated semiconductor device described in this document has an island having a die pad for fixing a semiconductor chip and a wire bonding portion for connecting a wire. The semiconductor chip is fixed on the die pad, and each electrode of the semiconductor chip The terminal is structured to be connected to the wire bonding portion of the lead or island. An air gap is provided between the die pad and the wire bonding portion to prevent the bonded wire from being disconnected or cut due to thermal stress. In such a structure, by connecting the ground terminal of the semiconductor chip and the island with a wire, the island can be connected to a printed circuit board or the like as a ground lead.
Japanese Laid-Open Patent Publication No. 11-251494 describes a high-frequency device in which a lead structure used in a mobile phone or the like having a semiconductor element mounting portion as a ground is a gull wing type. In this technology, in addition to connecting the electrode of the semiconductor element and the lead with a wire, in order to use the die pad as a ground electrode, the electrode of the semiconductor element and the semiconductor element mounting portion are connected with a wire (hereinafter, this connection is referred to as “connection”). Called down bonding). In order to down bond, the semiconductor element mounting portion is larger than the semiconductor element, and in the mounted state, the peripheral portion of the semiconductor element mounting portion protrudes outside the semiconductor element, and a wire is connected to this portion.
On the other hand, in the present applicant, the high-frequency power module is incorporated in the non-lead type semiconductor device, and the ground terminal of each circuit unit constituting the high-frequency power module is electrically connected to the tab via the wire in order to stabilize the ground potential. We considered the adoption of a method to connect to. By adopting down bonding, the number of external electrode terminals can be reduced, the size of the package can be reduced, and finally the size of the semiconductor device can be reduced.
However, it has been found that the following problems occur in a high-frequency power module that uses a wireless communication system (communication system).
In a mobile phone reception system, a signal captured by an antenna is amplified by a low noise amplifier (LNA), but the input signal is extremely weak. For this reason, the potential of the tab, which is a common terminal, that is, the ground potential, fluctuates according to the operation of each circuit unit, particularly an oscillator that operates periodically, and this causes crosstalk between some circuit units. Occurs and the output fluctuates, making it impossible to make a good call.
In particular, an induced current due to crosstalk between leads or a distortion of a signal waveform due to a change in ground potential is output from the communication system, and this output signal enters the communication system in use and causes noise.
Examples of such a circuit unit that is easily affected by fluctuations in ground potential and crosstalk include an RFVCO (High Frequency Voltage Controlled Oscillator) that handles high frequencies, other than a low noise amplifier (LNA).
In other words, the low noise amplifier (LNA) and the high frequency voltage controlled oscillator (RFVCO) are easily affected by fluctuations in the ground potential and crosstalk, thereby causing the high frequency of an electronic device such as a mobile phone equipped with a high frequency power module. The problem is that the characteristics are impaired.
An object of the present invention is to provide an electronic device that improves high-frequency characteristics in an electronic device equipped with a high-frequency power module for use in a wireless communication device or the like.
Another object of the present invention is to provide an electronic device (wireless communication device) that improves reliability.
Another object of the present invention is to provide a semiconductor device in which circuit portions such as a low noise amplifier and a high-frequency voltage controlled oscillator are hardly affected by crosstalk due to a change in ground potential of other circuit portions.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を簡単に説明すれば、下記のとおりである。
本発明は、複数のリードと、主面および裏面を有するタブと、複数の電極端子およびそれぞれが複数の半導体素子によって構成される複数の回路部を有する半導体チップと、前記複数の電極端子と前記リードとを接続する複数の導電性のワイヤと、前記複数の電極端子と前記タブの主面とを接続して前記複数の電極端子に第１の電位を供給する複数の導電性のワイヤとを有する半導体装置と、前記半導体装置が実装され、第１の配線層と第２の配線層とを備えており、前記第１の配線層と第２の配線層とに開口する複数の貫通孔に配置されてそれぞれの前記配線層の配線を接続する共通配線が設けられた配線基板とを有し、前記半導体チップは前記タブの主面に固定されており、前記回路部は、前記リードを介して外部信号が入力される第１の回路部と、前記タブと前記導電性のワイヤを介して接続される第２の回路部とを含んでおり、前記複数の電極端子は、前記第１の回路部に前記外部信号を入力する第１の電極端子と、前記第１の回路部に固定電位を供給する第２の電極端子とを有しており、前記複数のリードは、前記外部信号を伝達する第１のリードと、前記第１のリードの両側に配置された第２のリードとを含んでおり、前記第１のリードと前記第１の電極端子とを接続する前記導電性のワイヤの両側に前記第２のリードと前記第２の電極端子とを接続する前記導電性のワイヤが配置されており、前記タブと前記配線基板の前記共通配線とが接続されている。
また、本発明は、絶縁性樹脂からなる封止体と、前記封止体の周囲に沿って配置され、前記封止体の内外に亘って設けられた複数のリードと、主面および裏面を有するタブと、主面および裏面を有しており、その主面上に複数の電極端子と、それぞれが複数の半導体素子によって構成される複数の回路部とを有する半導体チップと、前記複数の電極端子と前記リードとを接続する複数の導電性のワイヤと、前記複数の電極端子と前記タブの主面とを接続して前記複数の電極端子に第１の電位を供給する複数の導電性のワイヤとを有し、前記半導体チップは前記タブの主面に固定されており、前記回路部は、前記リードを介して外部信号が入力される第１の回路部と、前記タブと前記導電性のワイヤを介して接続される第２の回路部とを含んでおり、前記複数の電極端子は、前記第１の回路部に前記外部信号を入力する第１の電極端子と、前記第１の回路部に固定電位を供給する第２の電極端子とを有しており、前記複数のリードは、前記外部信号を伝達する第１のリードと、前記第１のリードの両側に配置された第２のリードとを含んでおり、前記第１のリードと前記第１の電極端子とを接続する前記導電性のワイヤの両側に前記第２のリードと前記第２の電極端子とを接続する前記導電性のワイヤが配置されている。The following is a brief description of an outline of typical inventions disclosed in the present application.
The present invention includes a plurality of leads, a tab having a main surface and a back surface, a plurality of electrode terminals and a semiconductor chip having a plurality of circuit portions each constituted by a plurality of semiconductor elements, the plurality of electrode terminals, A plurality of conductive wires connecting leads, and a plurality of conductive wires connecting the plurality of electrode terminals and the main surface of the tab to supply a first potential to the plurality of electrode terminals. A semiconductor device having the first wiring layer and the second wiring layer, the plurality of through-holes opening in the first wiring layer and the second wiring layer. And a wiring board provided with a common wiring for connecting the wirings of the respective wiring layers, the semiconductor chip is fixed to the main surface of the tab, and the circuit portion is connected via the leads. The first external signal is input A plurality of electrode terminals for inputting the external signal to the first circuit unit; and a second circuit unit connected to the tab and the conductive wire. 1 electrode terminal and a second electrode terminal for supplying a fixed potential to the first circuit portion, wherein the plurality of leads include a first lead for transmitting the external signal, Second leads disposed on both sides of one lead, and the second leads and the two sides on both sides of the conductive wire connecting the first lead and the first electrode terminal. The conductive wire connecting the second electrode terminal is disposed, and the tab and the common wiring of the wiring board are connected.
Further, the present invention includes a sealing body made of an insulating resin, a plurality of leads arranged along the periphery of the sealing body, and provided over the inside and outside of the sealing body, and a main surface and a back surface. A semiconductor chip having a tab having a main surface and a back surface, a plurality of electrode terminals on the main surface, and a plurality of circuit portions each composed of a plurality of semiconductor elements, and the plurality of electrodes A plurality of conductive wires connecting the terminals and the leads, a plurality of conductive wires connecting the plurality of electrode terminals and the main surface of the tab to supply a first potential to the plurality of electrode terminals; The semiconductor chip is fixed to the main surface of the tab, and the circuit portion includes a first circuit portion to which an external signal is input through the lead, the tab, and the conductive material. Including a second circuit portion connected via a wire The plurality of electrode terminals include a first electrode terminal that inputs the external signal to the first circuit portion, and a second electrode terminal that supplies a fixed potential to the first circuit portion. The plurality of leads include a first lead for transmitting the external signal, and second leads disposed on both sides of the first lead, and the first lead and the first lead The conductive wire that connects the second lead and the second electrode terminal is disposed on both sides of the conductive wire that connects one electrode terminal.

図１は本発明の実施の形態１の半導体装置の一例である高周波パワーモジュールの構造を封止体の一部を切り欠いて示す平面図、図２は図１に示す高周波パワーモジュールの構造を示す断面図、図３は図１に示す高周波パワーモジュールの構造を示す平面図、図４は図１に示す高周波パワーモジュールに組み込まれる半導体チップにおける回路構成の一例をブロック的に示す平面図、図５は図１に示す高周波パワーモジュールにおける外部電極端子と半導体チップの低雑音増幅器などの各回路部との結線状態の一例を示す平面図、図６は図１に示す高周波パワーモジュールの組み立て手順の一例を示す製造プロセスフロー図、図７は図１に示す高周波パワーモジュールの製造で使用するリードフレームの構造の一例を示す平面図、図８は図７に示すリードフレームにおける単位リードフレームパターンの一例を示す部分拡大平面図、図９は図１に示す高周波パワーモジュールの組み立てにおけるダイボンディング状態の一例を示す部分断面図、図１０は図１に示す高周波パワーモジュールの組み立てにおけるワイヤボンディング状態の一例を示す部分断面図、図１１は図１に示す高周波パワーモジュールの組み立てにおける樹脂封止後の構造の一例を示す部分断面図、図１２は図１に示す高周波パワーモジュールが組み込まれた電子装置の一例である携帯電話機の回路構成を示すブロック図、図１３は図１に示す高周波パワーモジュールの携帯電話機（電子装置）における実装構造の一例を示す部分断面図、図１４は本発明の電子装置に組み込まれる配線基板のモジュール実装部の端子パターンの一例を示す部分平面図、図１５は図１４に示す配線基板に高周波パワーモジュールを搭載した際のＡ−Ａ断面の構造の一例を示す断面図、図１６は図１５に示す実装構造の封止体の一部を切り欠いて示す平面図、図１７は変形例の配線基板に高周波パワーモジュールを実装した際の実装構造を示す断面図、図１８は他の変形例の配線基板のモジュール実装部の端子パターンを示す部分平面図、図１９は図１８に示す配線基板に高周波パワーモジュールを搭載した際のＢ−Ｂ断面の構造を示す断面図、図２０は本発明の他の実施の形態（実施の形態２）である高周波パワーモジュールの構造を封止体の一部を切り欠いて示す平面図、図２１は本発明の他の実施の形態（実施の形態３）である高周波パワーモジュールの構造を封止体の一部を切り欠いて示す平面図、図２２は本発明の他の実施の形態（実施の形態４）である高周波パワーモジュールの構造を封止体の一部を切り欠いて示す平面図、図２３は図２２に示す高周波パワーモジュールの構造を示す断面図、図２４は実施の形態４の高周波パワーモジュールの変形例の構造を示す断面図、図２５は本発明の他の実施の形態（実施の形態５）である高周波パワーモジュールの構造を封止体の一部を切り欠いて示す平面図、図２６は本発明の変形例の電子装置の構造を示す模式構成図である。  FIG. 1 is a plan view showing a structure of a high-frequency power module as an example of a semiconductor device according to Embodiment 1 of the present invention, with a part of a sealing body cut away, and FIG. 2 shows the structure of the high-frequency power module shown in FIG. FIG. 3 is a plan view showing the structure of the high-frequency power module shown in FIG. 1. FIG. 4 is a plan view showing in block form an example of the circuit configuration of the semiconductor chip incorporated in the high-frequency power module shown in FIG. 5 is a plan view showing an example of a connection state between the external electrode terminal and each circuit unit such as a low-noise amplifier of the semiconductor chip in the high-frequency power module shown in FIG. 1, and FIG. 6 is an assembly procedure of the high-frequency power module shown in FIG. FIG. 7 is a plan view showing an example of the structure of a lead frame used in manufacturing the high-frequency power module shown in FIG. 1, and FIG. 9 is a partially enlarged plan view showing an example of a unit lead frame pattern in the lead frame shown, FIG. 9 is a partial sectional view showing an example of a die bonding state in the assembly of the high frequency power module shown in FIG. 1, and FIG. 10 is a high frequency power shown in FIG. FIG. 11 is a partial sectional view showing an example of a wire bonding state in the assembly of the module, FIG. 11 is a partial sectional view showing an example of the structure after resin sealing in the assembly of the high frequency power module shown in FIG. 1, and FIG. FIG. 13 is a partial cross-sectional view showing an example of the mounting structure of the high-frequency power module shown in FIG. 1 in the mobile phone (electronic device); FIG. 14 shows a module mounting portion of a wiring board incorporated in the electronic device of the present invention. FIG. 15 is a partial plan view showing an example of a child pattern, FIG. 15 is a cross-sectional view showing an example of the AA cross-section structure when the high-frequency power module is mounted on the wiring board shown in FIG. 14, and FIG. 16 is a mounting structure shown in FIG. FIG. 17 is a cross-sectional view showing a mounting structure when a high-frequency power module is mounted on a wiring board of a modification, and FIG. 18 is a wiring board of another modification. 19 is a partial plan view showing a terminal pattern of the module mounting portion, FIG. 19 is a cross-sectional view showing the structure of the BB cross section when the high frequency power module is mounted on the wiring board shown in FIG. 18, and FIG. 20 is another embodiment of the present invention. FIG. 21 is a plan view showing a structure of a high-frequency power module according to another embodiment (Embodiment 2) with a part of the sealing body cut away, and FIG. 21 shows a high-frequency power as another embodiment (Embodiment 3) of the present invention. Power module structure sealed FIG. 22 is a plan view showing a structure of a high-frequency power module according to another embodiment (Embodiment 4) of the present invention, with a part of the sealing body cut out. 23 is a cross-sectional view showing the structure of the high-frequency power module shown in FIG. 22, FIG. 24 is a cross-sectional view showing the structure of a modified example of the high-frequency power module of Embodiment 4, and FIG. 25 is another embodiment of the present invention ( FIG. 26 is a schematic configuration diagram showing a structure of an electronic device according to a modification of the present invention. FIG.

以下、図面を参照して本発明の実施の形態を詳細に説明する。なお、発明の実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
（実施の形態１）
図１〜図１９は本発明の実施の形態１の半導体装置の一例である高周波パワーモジュールおよびその高周波パワーモジュールを組み込んだ無線通信装置に係わる図である。図１〜図５は高周波パワーモジュールに係わる図であり、図６〜図１１は高周波パワーモジュールの製造方法に係わる図であり、図１２〜図１９は無線通信装置に係わる図である。
本実施の形態１では、四角形状の封止体（パッケージ）の裏面の実装面に、タブおよびこのタブに連なるタブ吊りリードならびにリード（外部電極端子）が露出するＱＦＮ型の半導体装置に本発明を適用した例について説明する。さらに、前記半導体装置の一例として、例えば、高周波パワーモジュール１を取り上げて説明する。
ＱＦＮ型の高周波パワーモジュール１は、図１および図２に示すように、偏平の四角形状の絶縁性樹脂で形成される封止体（パッケージ）２を有している。この封止体２の内部には四角形状の半導体素子（半導体チップ：チップ）３が埋め込まれている。前記半導体チップ３は四角形状のタブ４のタブ表面（主面）に接着剤５によって固定されている（図２参照）。封止体２の裏面（下面）は実装される面側（実装面）となる。
封止体２の裏面にはタブ４およびタブ４を支持するタブ吊りリード６ならびにリード７（外部電極端子）７の一面（実装面７ａ）が露出する構造となっている。これらタブ４およびタブ吊りリード６ならびにリード７は、高周波パワーモジュール１の製造において、パターニングした一枚の金属製（例えば、銅製）のリードフレームで形成され、その後切断されて形成される。
従って、本実施の形態１ではこれらタブ４およびタブ吊りリード６ならびにリード７の厚さは同じになっている。しかし、リード７においては、内端部分は裏面を一定の深さエッチングして薄く形成しておくので、この薄いリード部分の下側には封止体２を構成する樹脂が入り込む構造になっている。これにより、リード７は封止体２から脱落し難くなる。
タブ４は、その４隅が細いタブ吊りリード６によって支持される。これらタブ吊りリード６は四角形状の封止体２の対角線上に位置し、四角形状の封止体２の各隅部に外端を臨ませている。封止体２は偏平の四角形体となり、角部（隅部）は面取り加工が施されて斜面２ａとなっている（図１参照）。タブ吊りリード６の外端はこの面取り部分に０．１ｍｍ以下と僅かに突出している。この突出長さは、リードフレーム状態のタブ吊りリードを切断するときのプレス機械の切断型によって決まり、例えば、０．１ｍｍ以下が選択される。
また、図１に示すように、タブ４の周辺には、内端をタブ４に対面させるリード７が四角形の封止体２の各辺に沿って所定間隔で複数配置されている。タブ吊りリード６およびリード７の外端は封止体２の周縁にまで延在している。すなわち、リード７およびタブ吊りリード６は封止体２の内外に亘って延在することになる。リード７の封止体２からの突出長さは、前記タブ吊りリード６と同様にリードフレーム状態のリードを切断するときのプレス機械の切断型によって決まり、例えば、０．１ｍｍ以下と僅かに突出する。
また、封止体２の側面は傾斜面２ｂとなっている（図２参照）。この傾斜面２ｂは、リードフレームの一面に片面モールドして封止体２を形勢した後、モールド金型のキャビティから封止体２を抜き取る際、抜き取りを容易にするためにキャビティの側面を傾斜面にした結果によるものである。なお、図１は、封止体２の上部を切り欠いてタブ４、タブ吊りリード６、リード７、半導体チップ３などが見えるようにした模式図である。
また、図１および図４に示すように、半導体チップ３の露出する主面には電極端子９が設けられている。電極端子９は、半導体チップ３の主面において、四角形の各辺に沿ってほぼ所定ピッチに設けられている。この電極端子９は導電性のワイヤ１０を介してリード７の内端側に接続されている。
タブ４は半導体チップ３に比較して大きく形成され、図８に示すように、その主面の中央に半導体素子固定領域である半導体素子搭載部４ａを有するとともに、この半導体素子搭載部４ａの外側、すなわちタブ４の周縁部分にワイヤ接続領域４ｂを有している。そして、この半導体素子搭載部４ａに半導体チップ３が固定される。また、ワイヤ接続領域４ｂには、一端が半導体チップ３の電極端子９に接続される導電性のワイヤ１０の他端が接続されている。特に、タブ４に接続されるワイヤ１０をダウンボンディングワイヤ１０ａと呼称する。ワイヤボンディング装置によって電極端子９とリード７との間のワイヤボンディングおよび電極端子９とタブ４との間のワイヤボンディングを行うことから、ワイヤ１０もダウンボンディングワイヤ１０ａも同じ材質のものである。
ダウンボンディング構造の採用の目的は、一般的にはタブ４を利用した半導体チップ内の各回路部のグランド電位（第１の電位）の共通化である。タブ４を共通のグランド端子とし、このタブ４と、グランド電極端子となる多くの電極端子９とをワイヤ１０を介して接続することによって、封止体２の周囲に沿って並ぶ外部電極端子であるリード７（ピン）の数を少なくし、リード数低減による封止体２の小型化を図ることができる。これは半導体装置である高周波パワーモジュール１の小型化に繋がる。
次に、本実施の形態１の高周波パワーモジュール１に搭載される半導体チップ３の回路構成について説明する。図４は、半導体チップ３における各回路部の配置を示す模式的レイアウト図である。半導体チップ３の主面には、辺に沿って電極端子（パッド）９が配置されている。そして、これら電極端子９の内側に領域を分けて各回路部が配置されている。図４に示すように、半導体チップ３の中央にはＡＤＣ／ＤＡＣ＆ＤＣオフセット用制御論理回路部３５が配置され、その左側にはミキサ２６，６４と３個のＬＮＡ（低雑音増幅器）２４が並び、上側にはＲＦＶＣＯ（第２の回路部）４４が位置し、右側には上から下に掛けてＲＦシンセサイザ（第２の回路部）４１、ＶＣＸＯ（第２の回路部）５０、ＩＦシンセサイザ（第２の回路部）４２、ＩＦＶＣＯ４５が並び、下側にはＴＸＶＣＯ（第２の回路部）６７が位置している。
また、図５は、各回路部（第１の回路部および第２の回路部）とその電極端子９との関係、電極端子９とリード７のワイヤ１０による結線状態を示す。ワイヤ１０は電極端子９とリード７を結線するワイヤ１０と、電極端子９とタブ４を結線するダウンボンディングワイヤ１０ａが示されている。
特定回路部１１（第１の回路部）である３個のＬＮＡ２４に着目すると、外付け部品である帯域通過フィルタ２３（図１２参照）と繋がる予定のリード７、すなわちＳｉｇｎａｌと左側に記載されたリード（第１のリード）７と、ＬＮＡ２４の信号用の電極端子（第１の電極端子）９とがワイヤ１０を介して接続されている。電極端子９からワイヤ１０を介してリード７に至る信号配線は１つのＬＮＡ２４に対して２本ずつ設けられ、この２本の信号配線の両側は、特定回路部１１であるＬＮＡ２４のグランド用の電極端子（第２の電極端子）９がワイヤ１０を介してグランド用のリード７（第２のリードであり、図中ＧＮＤと左側に記載されたリード７）に接続されてグランド配線が形成されている。
その際、本実施の形態１の高周波パワーモジュール１では、２本の信号配線の両側のグランド用のリード（第２のリード）７は、固定電位が供給されるものであり、前記固定電位の一例としてグランド電位の場合を表している。
これにより、隣接する他のＶＣＯなどの第２の回路部のリード７とＬＮＡ２４のリード７の間が固定電位（ここでは、固定されたグランド電位）のリード７によって電磁シールドされる。また、隣接するＬＮＡ２４同士も固定電位のリード７によって電磁シールドされる。
また、図１２に示すように、アンテナ２０から入ってくる微弱信号を増幅するＬＮＡ２４に比較して、ベースバンドチップ２２から出力される電気信号を処理する送信系の各回路部（例えば、オフセットＰＬＬ、ＴＸＶＣＯ６７など）においては、その電気信号が前記微弱信号に比較して大きいために、グランド電位の変動やクロストークによるノイズにより強いという特性を持つ。そこで、送信系の回路部へのグランド電位の供給は、各ＶＣＯなどとタブ４を介して共通にすることにより、リード７の数を減らす事ができ、高周波パワーモジュール１（半導体装置）の小型化を図ることができる。
さらに、ＬＮＡ２４は、半導体チップ３の主面上に形成された配線間でのクロストークによる信号の劣化を防ぐために、例えば、ＰＧＡ２８（図１２参照）など、ＬＮＡ２４によって増幅された信号を扱う回路、または送信系の回路などと比較して前記配線の長さが短くなる様に、電極端子９のより近くに配置するのが好ましい。
次に、本実施の形態１の高周波パワーモジュール１は、図３に示すように、各リード７とリード７の間、およびリード７とタブ吊りリード６との間には封止体２を形成する際発生するレジンバリが存在している。このレジンバリ部分は、高周波パワーモジュール１の製造において、図７に示すリードフレーム１３の一面に片面モールドして封止体２を形成する際発生するものである。
モールド後、不要リードフレーム部分を切断するが、この際のリード７やタブ吊りリード６の切断時に同時にレジンバリも切断されるため、レジンバリの外縁はリード７の縁やタブ吊りリード６の縁と一緒になり、一部のレジンバリが各リード７とリード７の間、およびリード７とタブ吊りリード６との間に残留することになる。
また、本実施の形態１では封止体２の裏面はタブ４、タブ吊りリード６およびリード７の裏面（実装面）よりも引っ込んだ構造になっている。これは、トランスファモールドにおける片面モールドにおいて、モールド金型の上下型間に樹脂製のシートを張り、このシートにリードフレーム１３の一面が接触するようにしてモールドを行うことから、シートがリードフレーム１３の隙間で食い込むようになるため、封止体２の裏面は引っ込む形になる。
また、トランスファモールドによる片面モールド後、リードフレーム１３の表面に表面実装用のメッキ膜を形成する。このため、高周波パワーモジュール１の封止体２の裏面に露出するタブ４、タブ吊りリード６およびリード７の表面は、図示はしないがメッキ膜を有することになる。
このようにリード７やタブ吊りリード６の裏面である実装面が突出し、封止体２の裏面が引っ込むオフセット構造では、実装基板８０（図１３参照）などの配線基板に高周波パワーモジュール１を表面実装する場合、半田８３の濡れ領域が特定されるため半田実装が良好となる特長がある。
次に、本実施の形態１の高周波パワーモジュール１の製造方法について、図６〜図１１を参照しながら説明する。図６のフローチャートに示すように、高周波パワーモジュール１は、リードフレーム準備（Ｓ１０１）、チップボンディング（Ｓ１０２）、ワイヤボンディング（Ｓ１０３）、封止（モールド：Ｓ１０４）、メッキ処理（Ｓ１０５）、不要リードフレーム切断除去（Ｓ１０６）の各工程を経て製造される。
図７は本実施の形態１によるＱＦＮ型の高周波パワーモジュール１を製造する際使用するマトリクス構成のリードフレーム１３の模式的平面図である。
このリードフレーム１３は、単位リードフレームパターン１４がＸ方向に沿って２０行、Ｙ方向に沿って４列配置され、１枚のリードフレーム１３から８０個の高周波パワーモジュール１を製造することができる。リードフレーム１３の両側には、リードフレーム１３の搬送や位置決めなどに使用するガイド孔１５ａ，１５ｂ，１５ｃが設けられている。
また、各列の左側には、トランスファモールド時、ランナーが位置する。そこでランナー硬化レジンをエジェクターピンの突き出しによってリードフレーム１３から引き剥がすため、エジェクターピンが貫通できるエジェクターピン孔１６が設けられている。また、このランナーから分岐し、キャビティに流れるゲート部分で硬化したゲート硬化レジンをエジェクターピンの突き出しによってリードフレーム１３から引き剥がすため、エジェクターピンが貫通できるエジェクターピン孔１７が設けられている。
図８は単位リードフレームパターン１４の一部を示す平面図である。単位リードフレームパターン１４は、実際に製造するパターンであることから、模式図である図１や図２などとは必ずしも一致しない部分が有る。
単位リードフレームパターン１４は矩形枠状の枠部１８を有している。この枠部１８の４隅からタブ吊りリード６が延在し、中央のタブ４を支持するパターンとなっている。枠部１８の各辺の内側から内方に向かって複数のリード７が延在し、その内端はタブ４の外周縁に近接している。タブ４およびリード７の主面には、チップボンディングやワイヤボンディングのために図示しないメッキ膜が設けられている。
また、リード７はその先端側裏面は、ハーフエッチングされて薄くなっている（図２参照）。なお、リード７やタブ４などは、その周縁が、主面の幅が裏面の幅よりも広くなるような斜めの面とし、逆台形断面に形成して封止体２から抜け難くする構造としてもよい。これは、エッチングやプレスによっても製造することができる。
また、図８に示すように、タブ４の主面において、中央の四角形領域は半導体素子搭載部４ａ（二点鎖線枠で囲まれる領域）となり、その外側の領域はワイヤ接続領域４ｂとなる。
このようなリードフレーム１３を準備した後、図９に示すように、各単位リードフレームパターン１４のタブ４の半導体素子搭載部４ａに接着剤５を介して半導体チップ３を固定（チップボンディング）する（Ｓ１０２）。
その後、図１０に示すように、ワイヤボンディングを行い、半導体チップ３の電極端子９とリード７の先端を導電性のワイヤ１０で接続するとともに、所定の電極端子９とタブ４のワイヤ接続領域４ｂとを導電性のダウンボンディングワイヤ１０ａで接続する（Ｓ１０３）。ワイヤ１０やダウンボンディングワイヤ１０ａは、例えば金線を使用する。
ワイヤボンディング後、常用のトランスファモールドによる片面モールドを行い、リードフレーム１３の主面に図１１に示す絶縁性樹脂による封止体２を形成する（Ｓ１０４）。封止体２はリードフレーム１３の主面側の半導体チップ３、リード７などを被う。図８において、二点鎖線枠で示す部分が封止体２が形成される領域である。
その後、図示はしないが、メッキ処理を行う（Ｓ１０５）。この結果、リードフレーム１３の裏面には図示しないメッキ膜が形成される。このメッキ膜は、高周波パワーモジュール１の表面実装時の接合材として使用されるものであり、例えば、半田メッキ膜である。前記メッキ膜を形成する工程に代えて、予めリードフレーム１３の表面全面にＰｄメッキが施された物を使用しても良く、その際、特にＰｄメッキされたリードフレーム１３を用いる場合には前記封止後のメッキ工程を省略することができ、製造工程の簡略化をし、製造コストを削減することができる。
その後、不要なリードフレーム部分を切断除去し（Ｓ１０６）、図１に示すような高周波パワーモジュール１を製造する。図８に示す二点鎖線枠の封止体２の僅か外側で、図示しないプレス機械の切断型によってリード７およびタブ吊りリード６を切断する。切断型の構造により、リード７およびタブ吊りリード６は封止体２から僅か外れた位置で切断するが、この外れた位置の封止体２からの距離は、例えば０．１ｍｍ以下とされる。リード７およびタブ吊りリード６の封止体２からの突出長さは、引っ掛かり防止などの点では短い程よい。この突出長さはプレス機械の切断型の変更で０．１ｍｍ以上では自由に選択できる。
ここで、高周波パワーモジュール１の各部の寸法の一例を挙げる。リードフレーム１３（タブ４、タブ吊りリード６、リード７）の厚さは０．２ｍｍ、半導体チップ３の厚さは０．２８ｍｍ、高周波パワーモジュール１の厚さは１．０ｍｍ、リード７の幅は０．２ｍｍ、リード７の長さは０．５ｍｍ、タブ４のワイヤ接続箇所（点）は搭載された半導体チップ３の端から１．０ｍｍ、また、タブ４とリード７のとの間隔は０．２ｍｍである。
なお、従来の高周波パワーモジュールでは、発振器などの高周波信号を出力する回路部で、先に説明したようにグランド電位の変動によってクロストークが発生し、それぞれの回路部での出力変動や信号波形の歪みが発生するおそれがある。また、デュアルバンドやトリプルバンドなど複数の通信回路を有する高周波パワーモジュールにおいては、動作中の通信回路の影響で動作させていない通信回路に誘起電流が発生し、この誘起電流が雑音として動作中の通信回路に入り込むおそれがある。
さらに、入力信号配線同士のクロストークによってもそれぞれの回路部での出力変動や信号波形の歪みが発生するおそれがあり、特に入力信号の小さいアンテナからの外部信号入力用リードにおいては、隣接するリード間でのクロストークの影響を極力避ける必要が有る。
そこで、本実施の形態１の高周波パワーモジュール１では、図５に示すように、第１の回路部である特定回路部１１に外部信号を伝達する導電性のワイヤ１０の両側に、例えばグランド電位などの固定電位が供給される導電性のワイヤ１０が配置されている。
すなわち、図５に示す高周波パワーモジュール１において、ＬＮＡ（低雑音増幅器）２４の電極端子９からワイヤ１０を介してリード７に至る信号配線は、その両側にグランド電位などの固定電位が供給される導電性のワイヤ１０が配置されており、これによって、ＬＮＡ２４の信号配線は電磁シールドされ、その結果、前記信号配線はクロストークを受け難くなる。なお、固定電位は、グランド電位に限定されるものではなく、固定された電位であればよい。
ここで、本実施の形態１における高周波パワーモジュール１は、例えば、携帯電話機のトリプルバンド用の高周波パワーモジュールであることから、図５に示すように特定回路部１１はＬＮＡ（低雑音増幅器）２４であり、かつトリプルバンドであることから、アンテナ２０（図１２参照）に繋がるＬＮＡ２４も３個配置されている。
単一のＬＮＡ２４が本発明で言う狭義の特定回路部１１となる。すなわち、各ＬＮＡ２４のアンテナ２０からの入力信号配線は、図５に示すように、それぞれ２本となっている。そして、この２本の信号配線を電磁シールドするために、２本の信号用リードと他の信号用リードとの間、好ましくは２本の信号用リードの両側にそれぞれ固定電位（本実施の形態１ではグランド電位）のリード７（ワイヤ１０）を配置している。
なお、入力信号配線を２本にして差動入力構成にすると、入力信号配線の２本に同程度のクロストークによる影響が出てノイズ（クロストーク）を相殺（キャンセル）することができる。ここでは、図５に示すように、３個のＬＮＡ２４を囲んだ矩形枠部分を広義の特定回路部１１とする。
この特定回路部１１では、半導体チップ３において、他の回路部から絶縁分離された領域に各ＬＮＡ２４が形成されている。そして、各ＬＮＡ２４のグランド電位は共通になっている。これは、デュアル通信システム、トリプル通信システムでは、一つの通信システム（通信系）を使用している間、残りの通信システムはアイドリング状態となっていることから、アイドリング状態になっている通信システムに属するＬＮＡ２４によるグランド電位に対する影響が小さいため、各々別個の通信システムに属するＬＮＡ同士のグランド電極およびグランド配線を共通化しても、お互いに及ぼす悪影響が小さいからである。しかし、必要ならば、各ＬＮＡごとにアイソレーションを施して、各ＬＮＡのグランド電位を独立とさせる構成でもよい。
次に、本実施の形態１の電子装置の構造について説明する。本実施の形態１の電子装置は、本実施の形態１の高周波パワーモジュール１が搭載された実装構造を含むものであり、例えば、携帯電話機などの無線通信装置６９である。
図１３は本実施の形態１の半導体装置（高周波パワーモジュール）１の携帯電話機における実装状態の基本構造を示す模式的断面図である。
無線通信装置６９（図１２参照）である携帯電話機の実装基板（配線基板）８０の主面には高周波パワーモジュール１を搭載するために、高周波パワーモジュール１のリード７およびタブ４に対応して配線に連なるランド８１およびタブ接続用端子であるタブ固定部８２が設けられている。そこで、高周波パワーモジュール１のリード７およびタブ４が前記ランド８１およびタブ固定部８２に一致して重なるように高周波パワーモジュール１を位置決めして載置する。そして、この状態で高周波パワーモジュール１のリード７およびタブ４の裏面に予め形成しておいた半田メッキ膜を一時的に溶融（リフロー）してリード７およびタブ４を半田８３で接続（実装）する。
ここで、トリプルバンド構成の携帯電話機の回路構成（機能構成）について図１２を参照しながら簡単に説明する。すなわち、この携帯電話機は、例えば、９００ＭＨｚ帯のＧＳＭ通信方式と、１８００ＭＨｚ帯のＤＣＳ１８００通信方式と、１９００ＭＨｚ帯のＰＣＳ１９００通信方式の信号処理を行うことができる。
図１２のブロック図では、アンテナ２０にアンテナスイッチ２１を介して接続する送信系と、受信系とを示しており、送信系および受信系はいずれもベースバンドチップ２２に接続されるものである。
受信系は、アンテナ２０、アンテナスイッチ２１，このアンテナスイッチ２１に並列に接続される３個の帯域通過フィルタ２３、前記帯域通過フィルタ２３にそれぞれ接続される低雑音増幅器（ＬＮＡ）２４、前記３個のＬＮＡ２４に接続されかつ並列に接続される可変増幅器２５を有する。この２つの可変増幅器２５には、それぞれミキサ２６、ローパスフィルタ２７、ＰＧＡ２８、ローパスフィルタ２９、ＰＧＡ３０、ローパスフィルタ３１、ＰＧＡ３２、ローパスフィルタ３３、復調器３４が接続される。ＰＧＡ２８、ＰＧＡ３０、ＰＧＡ３２はＡＤＣ／ＤＡＣ＆ＤＣオフセット用制御論理回路部３５によって制御される。また、２つのミキサ２６は９０度位相変換器４０で位相制御される。
図１２において、９０度位相変換器４０および２つのミキサ２６によって構成されるＩ／Ｑ変調器は、各バンド帯域に対応するために、３つのＬＮＡ２４に対応してそれぞれ設けられるが、図１２においては、簡略化のために１つにまとめて書いてある。
半導体チップ３には、信号処理ＩＣとしてＲＦシンセサイザ４１およびＩＦ（Ｉｎｔｅｒｍｅｄｉａｔｅ）シンセサイザ４２からなるシンセサイザが設けられている。ＲＦシンセサイザ４１はバッファ４３を介してＲＦＶＣＯ４４に接続され、ＲＦＶＣＯ４４がＲＦローカル信号を出力するように制御する。バッファ４３には、直列に２つのローカル信号用分周器３７，３８が接続され、それぞれの出力端にはスイッチ４８，４９が接続されている。ＲＦＶＣＯ４４から出されたＲＦローカル信号はスイッチ４８の切替えによって９０度位相変換器４０に入力される。このＲＦローカル信号によって９０度位相変換器４０はミキサ２６を制御する。
ＲＦＶＣＯ４４の信号出力モードはＲｘモードの場合、ＧＳＭでは３７８０〜３８４０ＭＨｚ、ＤＣＳでは３６１０〜３７６０ＭＨｚ、ＰＣＳでは３８６０〜３９８０ＭＨｚである。またＴｘモードはＧＳＭでは３８４０〜３９８０ＭＨｚ、ＤＣＳでは３５８０〜３７３０ＭＨｚ、ＰＣＳでは３８６０〜３９８０ＭＨｚである。
ＩＦシンセサイザ４２は分周器４６を介してＩＦＶＣＯ（中間波電圧制御発振器）４５に接続され、ＩＦＶＣＯ４５がＩＦローカル信号を出力するように制御する。ＩＦＶＣＯ４５による出力信号の周波数は各通信方式共に６４０ＭＨｚである。また、ＲＦシンセサイザ４１およびＩＦシンセサイザ４２によってＶＣＸＯ（電圧制御水晶発振器）５０を制御し、基準信号を出力し、ベースバンドチップ２２に送る。
受信系ではシンセサイザおよびＡＤＣ／ＤＡＣ＆ＤＣオフセット用制御論理回路部３５によってＩＦ信号を制御し、復調器３４によってベースバンドチップ信号（Ｉ，Ｑ信号）に変換してベースバンドチップ２２に送る。
送信系は、ベースバンドチップ２２から出力されるＩ，Ｑ信号を入力信号とする２つのミキサ６１と、この２つのミキサ６１の位相を制御する９０度位相変換器６２と、２つのミキサ６１の出力を加算する加算器６３と、加算器６３の出力をいずれも入力とするミキサ６４およびＤＰＤ（デジタルフェーズディテクタ）６５と、ミキサ６４およびＤＰＤ６５の出力を共に入力とするループフィルタ６６と、ループフィルタ６６の出力を共に入力とする二つのＴＸＶＣＯ（送信波電圧制御発信器）６７と、２つのＴＸＶＣＯ６７の出力を共に入力とするＰＡモジュール６８と、アンテナスイッチ２１とからなっている。ループフィルタ６６は外付け部品である。
ミキサ６１、９０度位相変換器６２および加算器６３によって直交変調器を構成する。９０度位相変換器６２は分周器４６に分周器４７を介して接続され、ＩＦＶＣＯ４５から出力されるＩＦローカル信号によって制御される。
２つのＴＸＶＣＯ６７の出力はカプラー７０によって電流を検出される。この検出信号は増幅器７１を介してミキサ７２に入力される。ミキサ７２はスイッチ４９を介してＲＦＶＣＯ４４から出力されるＲＦローカル信号を入力する。ミキサ７２の出力信号は加算器６３の出力信号とともにミキサ６４およびＤＰＤ６５に入力される。ミキサ６４とＤＰＤ６５によってオフセットＰＬＬ（Ｐｈａｓｅ−Ｌｏｃｋｅｄ Ｌｏｏｐ）を構成する。ミキサ７２による出力信号の周波数は各通信方式共に８０ＭＨｚである。
２つのＴＸＶＣＯ６７のうちの一方のＴＸＶＣＯ６７はＧＳＭ通信方式用であり、出力信号の周波数は８８０〜９１５ＭＨｚである。また、他のＴＸＶＣＯ６７はＤＣＳ・ＰＣＳ通信方式用であり、出力信号の周波数は１７１０〜１７８５ＭＨｚ、または１８５０〜１９１０ＭＨｚである。ＰＡモジュール６８は低周波用パワーモジュールと高周波用パワーモジュールを内蔵し、低周波用パワーモジュールは８８０〜９１５ＭＨｚの信号を出力するＴＸＶＣＯ６７からの信号を受けて増幅処理し、高周波用パワーモジュールは１７１０〜１７８５ＭＨｚ、または１８５０〜１９１０ＭＨｚの信号を出力するＴＸＶＣＯ６７からの信号を受けて増幅処理し、アンテナスイッチ２１に送る。
本実施の形態１の高周波パワーモジュール１にはロジック回路６０もモノリシックに形成され、出力信号をベースバンドチップ２２に送る。
本実施の形態１の高周波パワーモジュール１は、図１２において太線で囲った部分の各回路部がモノリシックに形成されていることになる。そして、３個のＬＮＡ２４の部分が、本実施の形態１における特定回路部１１になる（図４、図５参照）。これら各回路部を模式的に一部示したものが、図４および図５の半導体チップ３のブロック平面図である。
アンテナ２０で受信された無線信号（電波）は電気信号に変換され、受信系の各素子で順次処理されてベースバンドチップ２２に送られる。また、ベースバンドチップ２２から出力された電気信号は、送信系の各素子で順次処理されてアンテナ２０から電波として放射される。
図１４〜図１６は本実施の形態１の高周波パワーモジュール１の携帯電話機における実装構造の詳細を示す図である。
図１４は高周波パワーモジュール１が実装される実装基板８０の端子パターンを示すものであり、実装基板８０の主面には、タブ接続用端子であるタブ固定部８２が形成され、さらに、タブ固定部８２の外側の周囲に、高周波パワーモジュール１の各リード７と接続される複数のランド８１が形成され、図１５に示すように、実装基板８０の主面の高周波パワーモジュール１と接続する箇所以外は、絶縁膜であるソルダレジスト９１によって覆われている。
実装基板８０には、主面の第１の配線層８６（タブ固定部８２やランド８１など）や内層の第２の配線層８７や第３の配線層８８などが形成されており、スルーホール８４は、何れかの配線層同士を接続するように所望の配線層に開口する貫通孔に導体が配置されて形成されたものであり、前記導体はメッキなどで形成される場合が多い。
図１４において、チップ３内の回路の構成が省略されているが、チップ３内の回路の構成および接続するリード７の配置は図５に記載された構成に該当するものであり、ＬＮＡ２４に接地電位を供給するリード７が（固定電位）として示されており、また、ＬＮＡ２４へ信号を入力するためのリード７がＳｉｇｎａｌとして示されているものである。
図１５に示す実装基板８０では、主面にタブ固定部８２やランド８１などの第１の配線層が形成され、さらに、第２の配線層８７として内層ＧＮＤ８９、第３の配線層８８として内層Ｖｃｃ９０などの各配線層が内部に形成されており、第１の配線層のタブ固定部８２と第２の配線層８７の内層ＧＮＤ８９とが多数のスルーホール８４によって接続されている。
なお、図１４および図１５に示す構造では、タブ固定部８２には、その各辺に沿って複数の共通配線であるスルーホール８４が配置されて接続されている。すなわち、タブ固定部８２の裏面側にその各辺にほぼ沿って並んだ状態で複数のスルーホール８４が配置されて各スルーホール８４がタブ固定部８２に接続されており、したがって、タブ固定部８２には多数のスルーホール８４を介して内層ＧＮＤ８９と同電位の共通のグランド電位（第１の電位）が供給される。
さらに、高周波パワーモジュール１のＬＮＡ（第１の回路部）２４に固定電位のグランド電位を供給するリード接続用のランド８１もスルーホール８４を介して内層ＧＮＤ８９と接続しているため、図１６に示すように、実装基板８０に高周波パワーモジュール１を搭載した際には、ＬＮＡ２４には、タブ固定部８２からタブ４を介して供給されるグランド電位と共通の同じグランド電位が固定電位としてリード７およびワイヤ１０を介して供給されることになる。
ただし、ＬＮＡ２４に供給されるグランド電位については、固定電位が供給されるリード７および電極端子９（第２の電極端子）とは異なった別のリード７からワイヤ１０および別の電極端子９（第３の電極端子）を介して供給してもよいし、タブ４に接続したダウンボンディングワイヤ１０ａを介して供給してもよい。さらに、ＬＮＡ２４に、リード７およびワイヤ１０を介して供給されるグランド電位は、タブ４に供給される第１の電位であるグランド電位とは分離させた（接続していない）別のグランド電位であってもよい。
すなわち、実装基板８０上において、タブ固定部８２に供給する第１の電位であるグランド電位とは接続していない別のグランド電位を供給可能な構造としておき、高周波パワーモジュール１の動作時にはタブ固定部８２に供給するグランド電位とは別のグランド電位を、ＬＮＡ２４にリード７およびワイヤ１０を介して供給してもよい。いずれの場合においても、ＬＮＡ２４などの特定回路部１１のグランドと他の残りの回路部のグランドは、図示はしないが、半導体チップ３内の配線においても層間絶縁膜などによって絶縁分離しておくのが好ましい。これは、チップ３内の配線が、実装基板８０上の配線やリードなどと比較してインダクタンスが高いために、チップ３内の配線によってＬＮＡ２４などの特定回路部１１と、他の電源ノイズ源となりうる回路部とを接続すると、電源ノイズの影響によってＬＮＡ２４の高周波特性が損なわれる可能性があるからである。
なお、高周波パワーモジュール１においてはその封止体２の実装面（裏面）にタブ４および各リード７が露出しており、実装基板８０の各ランド８１とこれに対応する各リード７とが、さらに、タブ４と実装基板８０のタブ接続用端子であるタブ固定部８２とが半田８３を介して電気的に接続されている。
したがって、このような実装構造の無線通信装置６９において、実装基板８０の内層ＧＮＤ８９と多数のスルーホール８４およびタブ固定部８２を介して半田接続されたタブ４は、そのグランド電位が十分に低インダクタンス化され、その安定化が図られている。
これにより、ＬＮＡ２４以外のタブ４にダウンボンディングされた第２の回路部を有する発振器などの各電子部品に対して、十分に低インダクタンス化されたグランド電位がダウンボンディングワイヤ１０ａを介して供給されるため、ＬＮＡ２４などの第１の回路部に供給されるグランド電位に与える影響、およびＬＮＡ２４などへの入力信号に与える影響を極めて小さくすることができる。
すなわち、実装基板８０のスルーホール８４は、その１本１本はインダクタンスが大きい。その理由は、スルーホール８４はスルーホール内の導電材（例えば銅）がコイルと同様に働き、実装基板８０の主面上に形成した配線９４，９５，９６に比較して、そのインダクタンスが大きくなるからである。これは、一般的に実装基板８０に形成されたスルーホール８４（導電性のプラグ）において、貫通孔の半径に比較して、その内部に形成される導体の膜厚が小さいために、スルーホール８４の内部が中空になるためである。こうした問題を解決するために、実装基板８０の製造工程において、スルーホール８４の内部を導体で充填する技術があるが、こうした技術は実装基板８０の製造工程における負荷が大きく、実装基板８０のコストを上昇させるため好ましくない。
このように、中空のスルーホール８４を有する実装基板８０を採用する場合、内層ＧＮＤ８９とタブ固定部８２とが１つのスルーホール８４でしか接続されていないと、タブ４に供給されるグランド電位が十分に低インダクタンス化されず、不安定な状態となり、第２の回路部を有する高周波の発振器のＯＮ／ＯＦＦなどの切り換えなどによって第１の回路部に影響を及ぼすことになる。さらに、ＬＮＡ（低雑音増幅器）２４は微弱な信号を増幅するため、グランド電位の変動は低雑音増幅器２４の出力の変動となるとともに、信号波形の歪みにもつながる。
これに対して、本実施の形態１の無線通信装置６９では、高周波パワーモジュール１が実装される実装基板８０において、タブ固定部８２と内層ＧＮＤ８９とがタブ固定部８２の近傍で多数のスルーホール８４で接続されているため、タブ４に供給されるグランド電位が十分に低インダクタンス化される。
さらに、高周波パワーモジュール１において、第１の回路部を有するＬＮＡ（低雑音増幅器）２４の電極端子９からワイヤ１０を介してリード７に至る信号配線は、その両側にグランド電位などの固定電位が供給される導電性のワイヤ１０が配置されているため、ＬＮＡ２４の信号配線は電磁シールドされ、これにより、前記信号配線はクロストークを受け難くい。
したがって、無線通信装置６９の高周波特性を向上させることができる。
また、タブ４に供給されるグランド電位を十分に低インダクタンス化することにより、グランド電位が十分に安定するため、図１４に記載のように、ＬＮＡ２４にグランド電位（ＧＮＤ）を供給するランド８１と接続する配線９４を、タブ固定部８２と接続してもよい。特に、前記配線９４を接続するランド８１より内側に配置することにより、ランド８１より外側の領域を、その他の配線９５や部品を配置する領域として有効に利用することができる。
特に、ＬＮＡ２４へ入力される信号の高周波特性を改善するために、前記ＬＮＡ２４に信号（Ｓｉｇｎａｌ）を入力するランド８１と接続するコイル（Ｌ）、容量素子（Ｃ）もしくは抵抗素子（Ｒ）などの受動素子を配置する場合に、前記のようにグランド電位（ＧＮＤ）を供給するランド８１からの配線９４を内側に引き込むことによって、前記様々な素子をより信号（Ｓｉｇｎａｌ）入力用のランド８１の近くに配置することができ、高周波特性の改善をより効果的に達成することができる。例えば図１４に記載されている例においては、コイル（Ｌ）および容量素子（Ｃ）を信号（Ｓｉｇｎａｌ）入力用のランド８１の非常に近くに配置することによって、各受動素子と、ランド８１との間の配線９６の長さを短くすることができるために、損失の小さいインピーダンス整合を達成することができる。
なお、図１７は、変形例の実装基板８０を用いた場合である。図１７に示す実装基板８０は、第１の配線層と第２の配線層８７のそれぞれの配線を接続する共通配線が、実装基板８０の裏面までは到達していないブラインドビア８５を採用した例である。
ブラインドビア８５を採用した場合、スルーホール８４ではスルーホール８４内にはんだが流れ込みはんだ不足等の問題をおこすおそれがあるが、ブラインドビア８５にすることによりはんだ量を制御しやすくなるという効果を得ることができる。
また、ブラインドビア８５が形成された実装基板８０に高周波パワーモジュール１を実装した場合であっても、前記スルーホール８４の実装基板８０の場合と同様の効果を得ることができる。
また、図１８に示す変形例の実装基板８０は、そのタブ固定部８２の全体に亘ってブラインドビア８５を設けた場合であり、図１９は図１８に示す実装基板８０上に高周波パワーモジュール１を実装した構造を示すものである。図１９に示す実装構造によれば、ブラインドビア８５（スルーホール８４でもよい）をタブ固定部８２の全体に亘って配置したことにより、タブ固定部８２と半田接続されるタブ４に供給されるグランド電位をさらに低インダクタンス化することができ、無線通信装置６９の高周波特性もさらに向上させることができる。
本実施の形態１によれば、高周波パワーモジュール１などの半導体装置において、ＬＮＡ（低雑音増幅器）２４などの第１の回路部に外部信号を伝達する導電性のワイヤ１０の両側に、グランド電位などの固定電位が供給される導電性のワイヤ１０が配置され、かつシンセサイザやＶＣＯなどの第２の回路部とタブ４とを接続して前記第２の回路部にグランド電位（第１の電位）を供給する複数の導電性のダウンボンディングワイヤ１０ａが設けられており、さらに、この半導体装置を実装する構造において、タブ４と実装基板８０の複数のスルーホール８４（共通配線）とが面積の大きなタブ固定部８２上で半田８３を介して接続されていることにより、タブ４は十分にグランド電位が低インダクタンス化された状態となる。
これによって、前記第２の回路部のタブ４におけるグランド電位も安定した状態となり、タブ４におけるグランド電位の変動を低減することができる。例えば、周期的に動作する発振器などの第２の回路部の動作に応じたグランド電位の変動を低減でき、これに起因したクロストークの発生も防ぐことができる。
また、前記第１の回路部に外部信号を伝達する導電性のワイヤ１０の両側に、固定電位が供給される導電性のワイヤ１０が配置されるため、外部信号を伝達する導電性のワイヤ１０の電位が固定電位の導電性のワイヤ１０によって電磁シールドされた状態を形成できる。これによって、前記第２の回路部でグランド電位の変動が起こったとしても、前記第１の回路部は、前記第２の回路部のグランド電位の変動の影響を受け難い。
その結果、本実施の形態１のように、高周波パワーモジュール１などの半導体装置が組み込まれた携帯電話機などの無線通信装置６９（電子装置）において、ＬＮＡ（低雑音増幅器）２４などの回路部への電源ノイズおよび信号ノイズの入力を減らすことができ、これにより、無線通信装置６９の高周波特性を向上させることができる。
また、ＬＮＡ２４などの回路部への電源ノイズおよび信号ノイズの入力を減らすことができるため、無線通信装置６９の信頼性および品質を向上させることができる。
すなわち、無線通信装置６９において出力変動や歪みのない良好な通話が可能になる。
また、半導体装置である高周波パワーモジュール１において、ＬＮＡ（低雑音増幅器）２４の電極端子９からワイヤ１０を介してリード７に至る信号配線はその両側にグランド配線が配置されて電磁シールドされていることから、他の回路部の信号の入出力によるクロストークを受け難くすることができる。
さらに、高周波パワーモジュール１は、タブ４が封止体２の裏面に露出していることから、半導体チップ３で発生した熱をタブ固定部８２を介して効果的に実装基板８０に放散することができる。これにより、この高周波パワーモジュール１を組み込んだ無線通信装置６９の動作の安定化を図ることができる。
また、高周波パワーモジュール１は、タブ４およびリード７が封止体２の裏面に露出するノンリード型半導体装置であることから、高周波パワーモジュール１の小型・薄型化が可能になり、軽量化も図れる。したがって、この高周波パワーモジュール１を組み込んだ無線通信装置６９の小型・軽量化も可能になる。
また、高周波パワーモジュール１は、半導体チップ３の電極端子９とリード（ピン）７とをワイヤ１０で接続するとともに、第１の電位であるグランド電位となるタブ４と半導体チップ３の電極端子（グランド電極端子）９とをダウンボンディングワイヤ１０ａで接続するダウンボンディング構造となっていることから、外部電極端子となるグランド用のリード７を少なくすることができる。
その結果、ピン数低減による封止体２の小型化が可能になり、高周波パワーモジュール１の小型化が達成できる。
（実施の形態２）
図２０は本発明の他の実施の形態（実施の形態２）である高周波パワーモジュールの構造を封止体の一部を切り欠いて示す平面図である。
本実施の形態２では、無線通信装置６９（図１２参照）などの電子装置に搭載される高周波パワーモジュール１に関して、実施の形態１の高周波パワーモジュール１において特定回路部１１として３個のＬＮＡ（低雑音増幅器）２４を有する場合を説明したのに対して、３個のＬＮＡ（低雑音増幅器）２４に加えて、ＶＣＯのうち、高周波を扱うＲＦＶＣＯ４４も特定回路部１１としたものである。したがって、ＲＦＶＣＯ４４の全てのグランド用の電極端子９がワイヤ１０を介してリード（グランド用のリード）７に接続され、タブ４にはワイヤを介して接続しないものである。
さらに、半導体チップ３の電極端子９からワイヤ１０を介してリード７に至る配線において、ＲＦＶＣＯ４４の２本の信号配線（Ｓｉｇｎａｌ）の両側に固定電位のグランド配線が配置され、実施の形態１の高周波パワーモジュール１と同様に信号配線の電磁シールドがなされている。
なお、３個のＬＮＡ２４についても実施の形態１と同様に、それぞれ２本の信号配線（Ｓｉｇｎａｌ）の両側に固定電位のグランド配線が配置されている。
これにより、ＬＮＡ２４（低雑音増幅器）に加えてＲＦＶＣＯ４４（高周波電圧制御発振器）も含めた高周波信号を取り扱う特定回路部１１のグランド電位が他の回路部のグランド電位から影響を受け難くなり、高周波パワーモジュール１を搭載した携帯電話機などの無線通信装置６９（電子装置）の高周波特性の向上を図ることができる。
（実施の形態３）
図２１は本発明の他の実施の形態（実施の形態３）である高周波パワーモジュールの封止体の一部を切り欠いて示す平面図である。
本実施の形態３では、無線通信装置６９（図１２参照）などの電子装置に搭載される高周波パワーモジュール１において、ＲＦＶＣＯ４４を外付け部品とし、半導体チップ３にはモノリシックに形成しない例である。このデュアルバンド通信方式では、低雑音増幅器、ミキサ、ＶＣＯ、シンセサイザ、ＩＱ変調器／復調器、分周器、直交変調器など各回路部をモノリシックに形成したものである。
受信系の二つのミキサはそれぞれ分周器７３によって制御され、またこの分周器７３は外付け部品であるＲＦＶＣＯ４４から出力された高周波の信号を、より低周波の信号に変換するための周波数変換回路である。
したがって、本実施の形態３では、図２１に示すように、高周波パワーモジュール１の外側にＲＦＶＣＯ４４が存在し、ＲＦＶＣＯ４４の信号配線（Ｓｉｇｎａｌ）が２本高周波パワーモジュール１のリード７に接続される。そして、ＲＦＶＣＯ４４に接続される２つのリード７からワイヤ１０を介して半導体チップ３の電極端子９に至る２本の信号配線の両側の電極端子９とリード７とはワイヤ１０を介して接続されている。この２本の信号配線の両側の電極端子９は固定電位のグランド用の電極端子９であり、したがって、このグランド用の電極端子９にワイヤ１０を介して接続されるリード７も固定電位のグランド用のリード７となっている。これにより、実施の形態２の場合と同様に高周波信号を扱う信号配線も電磁シールドされるとともに、半導体チップ３における他の回路部とはグランド電位が独立した構成になっている。
なお、実施の形態２と同様に、３個のＬＮＡ２４についてもそれぞれ２本の信号配線（Ｓｉｇｎａｌ）の両側に固定電位のグランド配線が配置されている。
その結果、本実施の形態３においても、実施の形態２と同様に、ＲＦＶＣＯ４４のグランド電位の変動に伴う障害は発生しなくなり、したがって、高周波パワーモジュール１を搭載した携帯電話機などの無線通信装置６９の高周波特性の向上を図ることができる。
（実施の形態４）
図２２および図２３は本発明の他の実施の形態（実施の形態４）である高周波パワーモジュールに係わる図であり、図２２は高周波パワーモジュールの封止体の一部を切り欠いて示す平面図、図２３は図２２に示す高周波パワーモジュールの断面図、図２４は実施の形態４の高周波パワーモジュールの変形例を示す断面図である。
本実施の形態４は、図２２および図２３に示すように、共通のグランド端子となるタブ４と、グランド電位とされるリード７を導電性のワイヤ１０ｂで電気的に接続し、リード７をもグランド外部電極端子とするものである。本実施の形態４の高周波パワーモジュール１では、タブ４の裏面が封止体２の裏面（実装面）から露出するため、タブ４をグランド用の外部電極端子として使用できるとともに、タブ４にワイヤ１０ｂを介して接続されたリード７もグランド用の外部電極端子としても使用することができる。
また、本実施の形態４の変形例である図２４に示す構造では、タブ４の裏面側をハーフエッチングして薄くしてあることから、片面モールド時、タブ４の裏面側にも封止用樹脂が回り込み、これにより、タブ４はその裏面も封止体２から露出することなく、完全に封止体２内に埋没する。
このような構造では、タブ４は封止体２の裏面に露出しないため、タブ４と図１３に示す実装基板８０のタブ固定部８２とを直接半田を介して接続することができない。そこで、実装基板８０において、タブ４にグランド電位を供給するリード７と接続されるランド８１に複数のスルーホール８４を接続してグランド電位の低インダクタンス化を図っておき、このランド８１に接続するリード７とタブ４とを１リード当たり複数のワイヤ１０ｂによって接続し、リード−タブ間のグランド低インダクタンス化を図る。
あるいは、グランド低インダクタンス化されたリード７とタブ４とを直接リードフレーム上のリード材によって繋げた構造とし、これによって、前記同様、リード−タブ間のグランド低インダクタンス化を図る。
このように、タブ４を封止体内に埋め込んだ構造の高周波パワーモジュール１であっても、この高周波パワーモジュール１を搭載した携帯電話機などの無線通信装置６９の高周波特性を向上させることができる。
また、図２４に示す構造の場合、タブ４がワイヤ１０ｂを介してリード７に接続されていることから、このリード７をグランド用の外部電極端子として使用することができる。なお、タブ４を封止体２内に埋没させる別の構造としては、タブ吊りリードの途中で一段高く階段状に折り曲げる構造としてもよい。
図２４に示す変形例の構造においては、ワイヤ１０ａを介してタブ４に接続するグランド電位供給用の電極端子９の数に比較して、ワイヤ１０ｂを介してタブと接続するリード７の数を少なくすることにより、封止体２の周囲に沿って配列されるリード７の本数を少なくし、半導体装置を小型化することができるとともに、タブ４の裏面が封止体２によって覆われているために、本実施の形態４における高周波パワーモジュール１などの半導体装置を実装基板８０（図１３参照）上に実装した際に高周波パワーモジュール１の下の領域も実装基板８０上の配線を配置するための領域として利用できるという利点がある。したがって、本実施の形態４においては、高周波パワーモジュール１の小型化に併せて、実装基板８０などの配線基板上の実装密度を向上できるという利点がある。
（実施の形態５）
図２５は本発明の他の実施の形態（実施の形態５）である高周波パワーモジュールの構造を封止体の一部を切り欠いて示す平面図である。
本実施の形態５の高周波パワーモジュール１は、実施の形態１で説明した高周波パワーモジュール１においてＬＮＡ２４へのグランド電位（第１の電位）の供給を、タブ４とワイヤ１０ａで接続された第３の電極端子である電極端子９を介して行うものである。
すなわち、本実施の形態５の高周波パワーモジュール１では、これに搭載された半導体チップ３が、ＬＮＡ２４にグランド電位（第１の電位）を供給する電極端子９（第３の電極端子）を有しており、この電極端子９（第３の電極端子）とタブ４とが導電性のワイヤ１０ａによって接続されている。
したがって、本実施の形態５の高周波パワーモジュール１では、ＬＮＡ２４へのグランド電位（第１の電位）の供給が、信号配線（Ｓｉｇｎａｌ）の両側の固定電位のリード７を介して行われるのではなく、実装基板８０の複数のスルーホール８４と接続させることによって、電源供給配線を低インダクタンス化したタブ４を介して行われる。
なお、本実施の形態５の高周波パワーモジュール１においても、ＬＮＡ２４の信号配線（Ｓｉｇｎａｌ）の両側には、タブ４のグランド電位とは別の固定電位のリード７およびワイヤ１０が配置されており、ＬＮＡ２４の信号配線は、実施の形態１の高周波パワーモジュール１と同様に電磁シールドされている。
したがって、本実施の形態５の高周波パワーモジュール１を搭載した携帯電話機などの無線通信装置６９においても、その高周波特性の向上を図ることができる。
さらに、本実施の形態５の高周波パワーモジュール１において、電極端子９（第３の電極端子）とタブ４とを接続する導電性のワイヤ１０ａは、信号配線（Ｓｉｇｎａｌ）用の電極端子９（第１の電極端子）とリード７（第１のリード）とを接続する導電性のワイヤ１０に比較してその長さを非常に短くすることができる。
これにより、ＬＮＡ２４への供給用の電源のワイヤ長が短くなるため、この配線のインピーダンスを小さくすることができ、高周波パワーモジュール１の特性をさらに向上させることができる。
したがって、本実施の形態５の高周波パワーモジュール１を搭載した携帯電話機などの無線通信装置６９においてさらにその高周波特性の向上を図ることができる。
以上本発明者によってなされた発明を実施形態に基づき具体的に説明したが、本発明は上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
前記実施の形態１〜５では、共通化した電源電位についてグランド電位についてのみ記載したが、本発明の適用の範囲はグランド電位とそれに関連する構成についてのみに限られる物ではなく、発明を適用する上で適当な電源電位（第１の電位）、例えば電極の共通化をすることによりリード７の数を少なくすることができる電源電位に着目し、その電源電位を供給するための電極端子９やリード７の構成に対して本発明を適用しても良い。
また、前記実施の形態１〜５では、ＱＦＮ型の半導体装置の製造に本発明を適用した例について説明したが、例えば、ＳＯＮ型半導体装置の製造に対しても本発明を同様に適用でき、同様の効果を有することができる。さらに、本発明の半導体装置、あるいは電子装置に搭載される半導体装置はノンリード型半導体装置に限定されることなく、例えば、封止体２の周囲に沿って、ガルウイング形状に折り曲げられたリードが突出するＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）やＳＯＰ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）と呼ばれる半導体装置についても同様に適用することができるが、前記ＱＦＰやＳＯＰに比較して、封止体２の周囲におけるリードの突出量が小さいＱＦＮ型の構造を採用した方が、半導体装置の小型化を達成する上ではより好ましい。
また、前記実施の形態１〜５では、半導体装置が搭載された携帯電話機などの無線通信装置（電子装置）が、予めその本体にアンテナ２０が取り付けられた無線通信装置６９の場合を取り上げて説明したが、本発明の電子装置は、図２６の変形例に示すように、例えば、テレビジョン、セットトップボックスまたはカーナビゲーション装置などのアンテナ９２を後から各本体に取り付けるようなアンテナ外付け装置９３であってもよく、このアンテナ外付け装置９３においても、実施の形態１〜５で説明した高周波パワーモジュール１を組み込むことにより、その高周波特性の向上を図ることができる。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.
(Embodiment 1)
1 to 19 are diagrams relating to a high-frequency power module, which is an example of a semiconductor device according to the first embodiment of the present invention, and a wireless communication device incorporating the high-frequency power module. 1 to 5 are diagrams related to a high-frequency power module, FIGS. 6 to 11 are diagrams related to a manufacturing method of the high-frequency power module, and FIGS. 12 to 19 are diagrams related to a wireless communication apparatus.
In the first embodiment, the present invention is applied to a QFN type semiconductor device in which a tab, a tab suspension lead connected to the tab, and a lead (external electrode terminal) are exposed on a mounting surface on the back surface of a rectangular sealing body (package). An example to which is applied will be described. Further, as an example of the semiconductor device, for example, a high frequency power module 1 will be described.
As shown in FIGS. 1 and 2, the QFN type high frequency power module 1 has a sealing body (package) 2 formed of a flat, rectangular insulating resin. A rectangular semiconductor element (semiconductor chip: chip) 3 is embedded in the sealing body 2. The semiconductor chip 3 is fixed to the tab surface (main surface) of the rectangular tab 4 with an adhesive 5 (see FIG. 2). The back surface (lower surface) of the sealing body 2 is the surface side (mounting surface) to be mounted.
The back surface of the sealing body 2 has a structure in which the tab 4 and the tab suspension lead 6 that supports the tab 4 and one surface (mounting surface 7a) of the lead 7 (external electrode terminal) 7 are exposed. The tab 4, the tab suspension lead 6, and the lead 7 are formed of a single metal (for example, copper) lead frame that is patterned in the manufacture of the high-frequency power module 1, and then cut and formed.
Therefore, in the first embodiment, the thicknesses of the tab 4, the tab suspension lead 6 and the lead 7 are the same. However, in the lead 7, the inner end portion is formed thin by etching the back surface to a certain depth, so that the resin constituting the sealing body 2 enters under the thin lead portion. Yes. This makes it difficult for the lead 7 to fall off the sealing body 2.
The tab 4 is supported by tab suspension leads 6 whose four corners are thin. These tab suspension leads 6 are positioned on diagonal lines of the quadrangular sealing body 2, and have their outer ends facing each corner of the quadrangular sealing body 2. The sealing body 2 is a flat rectangular body, and the corner (corner) is chamfered to form a slope 2a (see FIG. 1). The outer end of the tab suspension lead 6 protrudes slightly to 0.1 mm or less in this chamfered portion. This protrusion length is determined by the cutting die of the press machine when cutting the tab suspension lead in the lead frame state, and for example, 0.1 mm or less is selected.
As shown in FIG. 1, around the tab 4, a plurality of leads 7 whose inner ends are opposed to the tab 4 are arranged at predetermined intervals along each side of the rectangular sealing body 2. The outer ends of the tab suspension lead 6 and the lead 7 extend to the periphery of the sealing body 2. That is, the lead 7 and the tab suspension lead 6 extend over the inside and outside of the sealing body 2. The protruding length of the lead 7 from the sealing body 2 is determined by the cutting die of the press machine when cutting the lead in the lead frame state as in the case of the tab suspension lead 6, and is slightly protruding, for example, 0.1 mm or less. To do.
Further, the side surface of the sealing body 2 is an inclined surface 2b (see FIG. 2). The inclined surface 2b is formed on one surface of the lead frame and molded to form the sealing body 2. Then, when the sealing body 2 is extracted from the mold mold cavity, the side surface of the cavity is inclined to facilitate extraction. This is due to the results of the surface. FIG. 1 is a schematic view in which the upper portion of the sealing body 2 is cut away so that the tab 4, the tab suspension lead 6, the lead 7, the semiconductor chip 3 and the like can be seen.
As shown in FIGS. 1 and 4, an electrode terminal 9 is provided on the exposed main surface of the semiconductor chip 3. The electrode terminals 9 are provided on the main surface of the semiconductor chip 3 at a substantially predetermined pitch along each side of the rectangle. The electrode terminal 9 is connected to the inner end side of the lead 7 via a conductive wire 10.
The tab 4 is formed larger than the semiconductor chip 3, and has a semiconductor element mounting portion 4a which is a semiconductor element fixing region at the center of the main surface thereof as shown in FIG. 8, and the outside of the semiconductor element mounting portion 4a. That is, the wire connection region 4b is provided at the peripheral portion of the tab 4. The semiconductor chip 3 is fixed to the semiconductor element mounting portion 4a. Further, the other end of the conductive wire 10 whose one end is connected to the electrode terminal 9 of the semiconductor chip 3 is connected to the wire connection region 4b. In particular, the wire 10 connected to the tab 4 is referred to as a down bonding wire 10a. Since wire bonding between the electrode terminal 9 and the lead 7 and wire bonding between the electrode terminal 9 and the tab 4 are performed by a wire bonding apparatus, the wire 10 and the down bonding wire 10a are made of the same material.
The purpose of adopting the down bonding structure is to commonly use the ground potential (first potential) of each circuit unit in the semiconductor chip using the tab 4. By using the tab 4 as a common ground terminal and connecting the tab 4 and many electrode terminals 9 serving as ground electrode terminals via wires 10, external electrode terminals arranged along the periphery of the sealing body 2 The number of leads 7 (pins) can be reduced, and the sealing body 2 can be downsized by reducing the number of leads. This leads to miniaturization of the high frequency power module 1 which is a semiconductor device.
Next, the circuit configuration of the semiconductor chip 3 mounted on the high frequency power module 1 of the first embodiment will be described. FIG. 4 is a schematic layout diagram showing the arrangement of each circuit unit in the semiconductor chip 3. On the main surface of the semiconductor chip 3, electrode terminals (pads) 9 are arranged along the sides. And each circuit part is arrange | positioned dividing the area | region inside these electrode terminals 9. FIG. As shown in FIG. 4, an ADC / DAC & DC offset control logic circuit unit 35 is disposed at the center of the semiconductor chip 3, and mixers 26 and 64 and three LNAs (low noise amplifiers) 24 are arranged on the left side thereof. An RFVCO (second circuit unit) 44 is located on the upper side, and an RF synthesizer (second circuit unit) 41, a VCXO (second circuit unit) 50, and an IF synthesizer (second circuit unit) are placed on the right side from top to bottom. 2) and the IFVCO 45 are arranged, and a TXVCO (second circuit part) 67 is located on the lower side.
FIG. 5 shows the relationship between each circuit unit (first circuit unit and second circuit unit) and the electrode terminal 9, and the connection state of the electrode terminal 9 and the lead 7 with the wire 10. As for the wire 10, the wire 10 which connects the electrode terminal 9 and the lead 7 and the down bonding wire 10a which connects the electrode terminal 9 and the tab 4 are shown.
Focusing on the three LNAs 24 that are the specific circuit unit 11 (first circuit unit), the lead 7 that is to be connected to the bandpass filter 23 (see FIG. 12) that is an external component, that is, the Signal, is described on the left side. A lead (first lead) 7 and a signal electrode terminal (first electrode terminal) 9 of the LNA 24 are connected via a wire 10. Two signal wirings extending from the electrode terminal 9 to the lead 7 via the wire 10 are provided for each LNA 24, and both sides of the two signal wirings are ground electrodes of the LNA 24 that is the specific circuit unit 11. A terminal (second electrode terminal) 9 is connected to a ground lead 7 (second lead, that is, a lead 7 described on the left side of GND in the drawing) via a wire 10 to form a ground wiring. Yes.
At that time, in the high frequency power module 1 of the first embodiment, the ground leads (second leads) 7 on both sides of the two signal wirings are supplied with a fixed potential, As an example, the case of the ground potential is shown.
As a result, the lead 7 of the second circuit unit such as another adjacent VCO and the lead 7 of the LNA 24 are electromagnetically shielded by the lead 7 having a fixed potential (here, a fixed ground potential). Adjacent LNAs 24 are also electromagnetically shielded by leads 7 having a fixed potential.
Also, as shown in FIG. 12, each circuit unit (for example, offset PLL) of the transmission system that processes the electrical signal output from the baseband chip 22 as compared with the LNA 24 that amplifies the weak signal coming from the antenna 20. , TXVCO 67, etc.) have a characteristic that the electric signal is larger than the weak signal, and is therefore more resistant to ground potential fluctuations and noise due to crosstalk. Therefore, the supply of the ground potential to the circuit section of the transmission system is made common with each VCO or the like via the tab 4, so that the number of leads 7 can be reduced, and the high-frequency power module 1 (semiconductor device) can be reduced in size. Can be achieved.
Furthermore, the LNA 24 is a circuit that handles signals amplified by the LNA 24, such as PGA 28 (see FIG. 12), in order to prevent signal degradation due to crosstalk between wirings formed on the main surface of the semiconductor chip 3, for example. Alternatively, it is preferable that the wiring is disposed closer to the electrode terminal 9 so that the length of the wiring is shorter than that of a transmission circuit or the like.
Next, in the high frequency power module 1 according to the first embodiment, as shown in FIG. 3, the sealing body 2 is formed between each lead 7 and the lead 7 and between the lead 7 and the tab suspension lead 6. Resin burrs that are generated during the process are present. This resin burr portion is generated when the sealing body 2 is formed by single-side molding on one surface of the lead frame 13 shown in FIG.
After molding, the unnecessary lead frame portion is cut. However, since the resin burr is cut simultaneously with the cutting of the lead 7 and the tab suspension lead 6 at this time, the outer edge of the resin burr is together with the edge of the lead 7 and the tab suspension lead 6. Thus, a part of the resin burr remains between each lead 7 and the lead 7 and between the lead 7 and the tab suspension lead 6.
In the first embodiment, the back surface of the sealing body 2 has a structure in which the back surface (mounting surface) of the tab 4, the tab suspension lead 6 and the lead 7 is retracted. This is because, in a single-sided mold in a transfer mold, a resin sheet is stretched between the upper and lower molds of the mold, and molding is performed such that one surface of the lead frame 13 is in contact with the sheet. Therefore, the back surface of the sealing body 2 is retracted.
Further, after one-side molding by transfer molding, a plating film for surface mounting is formed on the surface of the lead frame 13. For this reason, the surface of the tab 4, the tab suspension lead 6 and the lead 7 exposed on the back surface of the sealing body 2 of the high-frequency power module 1 has a plating film (not shown).
Thus, in the offset structure in which the mounting surface which is the back surface of the lead 7 and the tab suspension lead 6 protrudes and the back surface of the sealing body 2 retracts, the high frequency power module 1 is placed on the surface of the wiring substrate such as the mounting substrate 80 (see FIG. 13). In the case of mounting, since the wet area of the solder 83 is specified, there is a feature that the solder mounting is good.
Next, a method for manufacturing the high-frequency power module 1 according to the first embodiment will be described with reference to FIGS. As shown in the flowchart of FIG. 6, the high-frequency power module 1 includes lead frame preparation (S101), chip bonding (S102), wire bonding (S103), sealing (mold: S104), plating treatment (S105), and unnecessary leads. It is manufactured through each step of frame cutting and removal (S106).
FIG. 7 is a schematic plan view of a lead frame 13 having a matrix configuration used when manufacturing the QFN type high frequency power module 1 according to the first embodiment.
In this lead frame 13, unit lead frame patterns 14 are arranged in 20 rows along the X direction and 4 columns along the Y direction, and 80 high frequency power modules 1 can be manufactured from one lead frame 13. . On both sides of the lead frame 13, guide holes 15a, 15b, and 15c used for conveying and positioning the lead frame 13 are provided.
In addition, a runner is located on the left side of each row during transfer molding. Therefore, in order to peel off the runner curing resin from the lead frame 13 by ejecting the ejector pin, an ejector pin hole 16 through which the ejector pin can penetrate is provided. In addition, an ejector pin hole 17 through which the ejector pin can pass is provided in order to peel off the gate-cured resin, which is branched from the runner and hardened at the gate portion flowing into the cavity, from the lead frame 13 by the protrusion of the ejector pin.
FIG. 8 is a plan view showing a part of the unit lead frame pattern 14. Since the unit lead frame pattern 14 is a pattern that is actually manufactured, there are portions that do not necessarily match the schematic diagrams of FIGS.
The unit lead frame pattern 14 has a frame portion 18 having a rectangular frame shape. The tab suspension leads 6 extend from the four corners of the frame portion 18 so as to support the central tab 4. A plurality of leads 7 extend inward from the inside of each side of the frame portion 18, and the inner ends thereof are close to the outer peripheral edge of the tab 4. On the main surface of the tab 4 and the lead 7, a plating film (not shown) is provided for chip bonding and wire bonding.
Further, the lead 7 has its back surface at the front end side thinned by half etching (see FIG. 2). In addition, the lead 7 and the tab 4 have a structure in which the peripheral edge thereof is an inclined surface whose main surface is wider than the width of the back surface, and is formed in an inverted trapezoidal cross section so that it is difficult to be removed from the sealing body 2. Also good. This can also be produced by etching or pressing.
Further, as shown in FIG. 8, on the main surface of the tab 4, the central square region is the semiconductor element mounting portion 4a (region surrounded by a two-dot chain line frame), and the outer region is the wire connection region 4b.
After preparing such a lead frame 13, as shown in FIG. 9, the semiconductor chip 3 is fixed to the semiconductor element mounting portion 4a of the tab 4 of each unit lead frame pattern 14 via the adhesive 5 (chip bonding). (S102).
Thereafter, as shown in FIG. 10, wire bonding is performed to connect the electrode terminal 9 of the semiconductor chip 3 and the tip of the lead 7 with the conductive wire 10, and the wire connection region 4 b of the predetermined electrode terminal 9 and the tab 4. Are connected by a conductive down-bonding wire 10a (S103). As the wire 10 and the down bonding wire 10a, for example, a gold wire is used.
After the wire bonding, one-side molding is performed by a normal transfer mold, and the sealing body 2 made of an insulating resin shown in FIG. 11 is formed on the main surface of the lead frame 13 (S104). The sealing body 2 covers the semiconductor chip 3 and the leads 7 on the main surface side of the lead frame 13. In FIG. 8, a portion indicated by a two-dot chain line frame is a region where the sealing body 2 is formed.
Thereafter, although not shown, a plating process is performed (S105). As a result, a plating film (not shown) is formed on the back surface of the lead frame 13. This plating film is used as a bonding material at the time of surface mounting of the high-frequency power module 1, and is, for example, a solder plating film. In place of the step of forming the plating film, a material in which the entire surface of the lead frame 13 is previously plated with Pd may be used. In this case, particularly when the lead frame 13 plated with Pd is used, The plating process after sealing can be omitted, the manufacturing process can be simplified, and the manufacturing cost can be reduced.
Thereafter, unnecessary lead frame portions are cut and removed (S106), and the high-frequency power module 1 as shown in FIG. 1 is manufactured. The lead 7 and the tab suspension lead 6 are cut by a cutting die of a press machine (not shown) just outside the sealing body 2 of the two-dot chain line frame shown in FIG. Due to the cutting type structure, the lead 7 and the tab suspension lead 6 are cut at a position slightly deviated from the sealing body 2, and the distance from the sealing body 2 at the deviated position is, for example, 0.1 mm or less. . The projecting length of the lead 7 and the tab suspension lead 6 from the sealing body 2 is preferably as short as possible in terms of prevention of catching. This protrusion length can be freely selected at 0.1 mm or more by changing the cutting die of the press machine.
Here, an example of the dimension of each part of the high frequency power module 1 is given. The lead frame 13 (tab 4, tab suspension lead 6, lead 7) has a thickness of 0.2 mm, the semiconductor chip 3 has a thickness of 0.28 mm, the high frequency power module 1 has a thickness of 1.0 mm, and the width of the lead 7. Is 0.2 mm, the length of the lead 7 is 0.5 mm, the wire connection point (point) of the tab 4 is 1.0 mm from the end of the mounted semiconductor chip 3, and the distance between the tab 4 and the lead 7 is 0.2 mm.
In a conventional high-frequency power module, crosstalk occurs due to a change in ground potential in a circuit unit that outputs a high-frequency signal such as an oscillator as described above, and output fluctuations and signal waveforms in each circuit unit are generated. There is a risk of distortion. Moreover, in a high frequency power module having a plurality of communication circuits such as dual band and triple band, an induced current is generated in a communication circuit that is not operated due to the influence of the operating communication circuit, and this induced current is operating as noise. There is a risk of entering the communication circuit.
Furthermore, crosstalk between input signal wirings may cause output fluctuations and signal waveform distortion in each circuit part. Especially in the case of external signal input leads from antennas with small input signals, adjacent leads It is necessary to avoid the influence of crosstalk between them as much as possible.
Therefore, in the high frequency power module 1 according to the first embodiment, as shown in FIG. 5, for example, a ground potential is provided on both sides of the conductive wire 10 that transmits an external signal to the specific circuit unit 11 that is the first circuit unit. A conductive wire 10 to which a fixed potential is supplied is disposed.
That is, in the high-frequency power module 1 shown in FIG. 5, the signal wiring from the electrode terminal 9 of the LNA (low noise amplifier) 24 to the lead 7 via the wire 10 is supplied with a fixed potential such as a ground potential on both sides. The conductive wire 10 is disposed, whereby the signal wiring of the LNA 24 is electromagnetically shielded, and as a result, the signal wiring is less susceptible to crosstalk. Note that the fixed potential is not limited to the ground potential, and may be any fixed potential.
Here, since the high-frequency power module 1 according to the first embodiment is, for example, a triple-band high-frequency power module for a mobile phone, the specific circuit unit 11 has an LNA (low noise amplifier) 24 as shown in FIG. In addition, since it is a triple band, three LNAs 24 connected to the antenna 20 (see FIG. 12) are also arranged.
The single LNA 24 is the specific circuit section 11 in the narrow sense in the present invention. That is, there are two input signal lines from the antenna 20 of each LNA 24 as shown in FIG. In order to electromagnetically shield the two signal wirings, a fixed potential (in this embodiment) is provided between the two signal leads and the other signal leads, preferably on both sides of the two signal leads. In FIG. 1, a lead 7 (wire 10) having a ground potential is disposed.
Note that when the differential input configuration is made with two input signal wirings, the influence of the same degree of crosstalk is exerted on the two input signal wirings, and noise (crosstalk) can be canceled (cancelled). Here, as shown in FIG. 5, the rectangular frame portion surrounding the three LNAs 24 is defined as the specific circuit unit 11 in a broad sense.
In the specific circuit unit 11, each LNA 24 is formed in a region isolated from the other circuit units in the semiconductor chip 3. The ground potential of each LNA 24 is common. This is because in the dual communication system and the triple communication system, the remaining communication system is in an idling state while one communication system (communication system) is used. This is because the influence of the LNA 24 belonging to the LNA 24 on the ground potential is small, and even if the ground electrodes and the ground wirings of the LNAs belonging to different communication systems are shared, the adverse effect on each other is small. However, if necessary, the configuration may be such that isolation is performed for each LNA so that the ground potential of each LNA is independent.
Next, the structure of the electronic device according to the first embodiment will be described. The electronic device according to the first embodiment includes a mounting structure on which the high-frequency power module 1 according to the first embodiment is mounted. For example, the electronic device is a wireless communication device 69 such as a mobile phone.
FIG. 13 is a schematic cross-sectional view showing the basic structure of the semiconductor device (high frequency power module) 1 according to the first embodiment mounted in a mobile phone.
In order to mount the high frequency power module 1 on the main surface of the mounting substrate (wiring substrate) 80 of the mobile phone which is the wireless communication device 69 (see FIG. 12), it corresponds to the lead 7 and the tab 4 of the high frequency power module 1. A land 81 connected to the wiring and a tab fixing portion 82 which is a tab connection terminal are provided. Therefore, the high frequency power module 1 is positioned and placed so that the lead 7 and the tab 4 of the high frequency power module 1 coincide with and overlap the land 81 and the tab fixing portion 82. In this state, the solder plating film previously formed on the back surface of the lead 7 and the tab 4 of the high-frequency power module 1 is temporarily melted (reflowed), and the lead 7 and the tab 4 are connected (mounted) with the solder 83. To do.
Here, a circuit configuration (functional configuration) of a mobile phone having a triple band configuration will be briefly described with reference to FIG. That is, this mobile phone can perform signal processing of, for example, a 900 MHz band GSM communication system, a 1800 MHz band DCS1800 communication system, and a 1900 MHz band PCS1900 communication system.
The block diagram of FIG. 12 shows a transmission system and a reception system connected to the antenna 20 via the antenna switch 21, and both the transmission system and the reception system are connected to the baseband chip 22.
The receiving system includes an antenna 20, an antenna switch 21, three band pass filters 23 connected in parallel to the antenna switch 21, a low noise amplifier (LNA) 24 connected to the band pass filter 23, and the three pieces. And a variable amplifier 25 connected to the LNA 24 in parallel. A mixer 26, a low-pass filter 27, a PGA 28, a low-pass filter 29, a PGA 30, a low-pass filter 31, a PGA 32, a low-pass filter 33, and a demodulator 34 are connected to the two variable amplifiers 25, respectively. The PGA 28, PGA 30, and PGA 32 are controlled by an ADC / DAC & DC offset control logic circuit unit 35. The two mixers 26 are phase-controlled by a 90-degree phase converter 40.
In FIG. 12, an I / Q modulator constituted by a 90-degree phase converter 40 and two mixers 26 is provided corresponding to three LNAs 24 in order to correspond to each band band. Are grouped together for simplicity.
The semiconductor chip 3 is provided with a synthesizer including an RF synthesizer 41 and an IF (Intermediate) synthesizer 42 as a signal processing IC. The RF synthesizer 41 is connected to the RFVCO 44 via the buffer 43 and controls the RFVCO 44 to output an RF local signal. Two local signal frequency dividers 37 and 38 are connected to the buffer 43 in series, and switches 48 and 49 are connected to respective output terminals. The RF local signal output from the RFVCO 44 is input to the 90-degree phase converter 40 by switching the switch 48. The 90-degree phase converter 40 controls the mixer 26 by this RF local signal.
In the Rx mode, the signal output mode of the RFVCO 44 is 3780 to 3840 MHz for GSM, 3610 to 3760 MHz for DCS, and 3860 to 3980 MHz for PCS. The Tx mode is 3840 to 3980 MHz for GSM, 3580 to 3730 MHz for DCS, and 3860 to 3980 MHz for PCS.
The IF synthesizer 42 is connected to an IFVCO (Intermediate Wave Voltage Controlled Oscillator) 45 via a frequency divider 46, and controls the IFVCO 45 to output an IF local signal. The frequency of the output signal from the IFVCO 45 is 640 MHz for each communication method. Further, a VCXO (voltage controlled crystal oscillator) 50 is controlled by the RF synthesizer 41 and the IF synthesizer 42 to output a reference signal and send it to the baseband chip 22.
In the receiving system, the IF signal is controlled by the synthesizer and the ADC / DAC & DC offset control logic circuit unit 35, converted into a baseband chip signal (I, Q signal) by the demodulator 34, and sent to the baseband chip 22.
The transmission system includes two mixers 61 having I and Q signals output from the baseband chip 22 as input signals, a 90-degree phase converter 62 for controlling the phases of the two mixers 61, and two mixers 61 An adder 63 for adding outputs; a mixer 64 and DPD (digital phase detector) 65 that receive the outputs of the adder 63; a loop filter 66 that receives both outputs of the mixer 64 and DPD 65; and a loop filter It consists of two TXVCOs (transmission wave voltage controlled oscillators) 67 that receive the outputs of 66, a PA module 68 that receives the outputs of the two TXVCOs 67, and the antenna switch 21. The loop filter 66 is an external part.
The mixer 61, the 90-degree phase converter 62, and the adder 63 constitute an orthogonal modulator. The 90-degree phase converter 62 is connected to the frequency divider 46 via the frequency divider 47 and is controlled by the IF local signal output from the IFVCO 45.
The outputs of the two TXVCOs 67 are detected by a coupler 70. This detection signal is input to the mixer 72 via the amplifier 71. The mixer 72 inputs an RF local signal output from the RFVCO 44 via the switch 49. The output signal of the mixer 72 is input to the mixer 64 and the DPD 65 together with the output signal of the adder 63. The mixer 64 and the DPD 65 constitute an offset PLL (Phase-Locked Loop). The frequency of the output signal from the mixer 72 is 80 MHz for each communication method.
One of the two TXVCOs 67 is for the GSM communication system, and the frequency of the output signal is 880 to 915 MHz. The other TXVCO 67 is for the DCS / PCS communication system, and the frequency of the output signal is 1710 to 1785 MHz or 1850 to 1910 MHz. The PA module 68 includes a low-frequency power module and a high-frequency power module. The low-frequency power module receives and amplifies the signal from the TXVCO 67 that outputs a signal of 880 to 915 MHz. The high-frequency power module 1710 A signal from the TXVCO 67 that outputs a signal of 1785 MHz or 1850 to 1910 MHz is received, amplified, and sent to the antenna switch 21.
In the high-frequency power module 1 according to the first embodiment, the logic circuit 60 is also monolithically formed and sends an output signal to the baseband chip 22.
In the high-frequency power module 1 according to the first embodiment, each circuit portion surrounded by a thick line in FIG. 12 is monolithically formed. The portions of the three LNAs 24 become the specific circuit unit 11 in the first embodiment (see FIGS. 4 and 5). FIG. 4 and FIG. 5 are block plan views showing a part of each circuit part schematically.
A radio signal (radio wave) received by the antenna 20 is converted into an electric signal, sequentially processed by each element of the receiving system, and sent to the baseband chip 22. The electric signal output from the baseband chip 22 is sequentially processed by each element of the transmission system and is radiated as a radio wave from the antenna 20.
14-16 is a figure which shows the detail of the mounting structure in the mobile telephone of the high frequency power module 1 of this Embodiment 1. FIG.
FIG. 14 shows a terminal pattern of the mounting substrate 80 on which the high-frequency power module 1 is mounted. A tab fixing portion 82 that is a tab connection terminal is formed on the main surface of the mounting substrate 80, and tab fixing is further performed. A plurality of lands 81 connected to the leads 7 of the high-frequency power module 1 are formed around the outside of the portion 82, and as shown in FIG. 15, places where the main surface of the mounting substrate 80 is connected to the high-frequency power module 1. Other than the above, it is covered with a solder resist 91 which is an insulating film.
The mounting substrate 80 is provided with a first wiring layer 86 (such as a tab fixing portion 82 and a land 81) on the main surface, a second wiring layer 87 and a third wiring layer 88 on the inner layer, and the like. 84 is formed by arranging a conductor in a through-hole opened in a desired wiring layer so as to connect any of the wiring layers, and the conductor is often formed by plating or the like.
In FIG. 14, the circuit configuration in the chip 3 is omitted, but the circuit configuration in the chip 3 and the arrangement of the leads 7 to be connected correspond to the configuration described in FIG. 5, and the LNA 24 is grounded. A lead 7 for supplying a potential is shown as (fixed potential), and a lead 7 for inputting a signal to the LNA 24 is shown as Signal.
In the mounting substrate 80 shown in FIG. 15, the first wiring layer such as the tab fixing portion 82 and the land 81 is formed on the main surface, the inner layer GND 89 as the second wiring layer 87, and the inner layer as the third wiring layer 88. Each wiring layer such as Vcc 90 is formed inside, and the tab fixing portion 82 of the first wiring layer and the inner layer GND 89 of the second wiring layer 87 are connected by a large number of through holes 84.
In the structure shown in FIGS. 14 and 15, the tab fixing portion 82 is connected to a plurality of through holes 84 that are common wirings along each side. That is, a plurality of through holes 84 are arranged on the back surface side of the tab fixing portion 82 so as to be substantially aligned along each side thereof, and each through hole 84 is connected to the tab fixing portion 82. A common ground potential (first potential) having the same potential as that of the inner layer GND 89 is supplied to 82 through a large number of through holes 84.
Further, since the land 81 for lead connection for supplying a fixed ground potential to the LNA (first circuit portion) 24 of the high frequency power module 1 is also connected to the inner layer GND 89 through the through hole 84, FIG. As shown, when the high frequency power module 1 is mounted on the mounting substrate 80, the LNA 24 has the same ground potential that is common to the ground potential supplied from the tab fixing portion 82 via the tab 4 as a fixed potential. And supplied via the wire 10.
However, the ground potential supplied to the LNA 24 is different from the lead 7 and the electrode terminal 9 (second electrode terminal) to which the fixed potential is supplied from another wire 7 and another electrode terminal 9 (first electrode). 3 may be supplied via a down bonding wire 10 a connected to the tab 4. Further, the ground potential supplied to the LNA 24 via the lead 7 and the wire 10 is a different ground potential that is separated (not connected) from the ground potential that is the first potential supplied to the tab 4. There may be.
That is, on the mounting substrate 80, a structure that can supply another ground potential that is not connected to the ground potential that is the first potential supplied to the tab fixing portion 82 is provided, and the tab is fixed when the high-frequency power module 1 is in operation. A ground potential different from the ground potential supplied to the unit 82 may be supplied to the LNA 24 via the lead 7 and the wire 10. In any case, the ground of the specific circuit unit 11 such as the LNA 24 and the grounds of the other circuit units are not illustrated, but the wiring in the semiconductor chip 3 is also insulated and separated by an interlayer insulating film or the like. Is preferred. This is because the wiring in the chip 3 has a higher inductance than the wiring and leads on the mounting substrate 80, so that the wiring in the chip 3 becomes a specific circuit unit 11 such as the LNA 24 and other power source noise sources. This is because the high frequency characteristics of the LNA 24 may be impaired due to the influence of power supply noise.
In the high-frequency power module 1, the tab 4 and each lead 7 are exposed on the mounting surface (back surface) of the sealing body 2, and each land 81 of the mounting substrate 80 and each corresponding lead 7 are Further, the tab 4 and the tab fixing portion 82 which is a tab connection terminal of the mounting substrate 80 are electrically connected via the solder 83.
Therefore, in the wireless communication device 69 having such a mounting structure, the tab 4 soldered to the inner layer GND 89 of the mounting substrate 80 via the numerous through holes 84 and the tab fixing portions 82 has a sufficiently low ground potential. To stabilize it.
As a result, a sufficiently low inductance ground potential is supplied via the down bonding wire 10a to each electronic component such as an oscillator having the second circuit portion down bonded to the tab 4 other than the LNA 24. Therefore, the influence on the ground potential supplied to the first circuit unit such as the LNA 24 and the influence on the input signal to the LNA 24 can be extremely reduced.
That is, each of the through holes 84 of the mounting substrate 80 has a large inductance. The reason is that the through hole 84 has a conductive material (for example, copper) in the through hole that works in the same manner as the coil, and has a larger inductance than the wirings 94, 95, and 96 formed on the main surface of the mounting substrate 80. Because it becomes. This is because the thickness of the conductor formed in the through hole 84 (conductive plug) generally formed in the mounting substrate 80 is smaller than the radius of the through hole. This is because the interior of 84 becomes hollow. In order to solve such a problem, there is a technique of filling the inside of the through hole 84 with a conductor in the manufacturing process of the mounting board 80. However, this technique places a heavy load on the manufacturing process of the mounting board 80, and the cost of the mounting board 80 is high. Is not preferable.
As described above, when the mounting substrate 80 having the hollow through hole 84 is employed, if the inner layer GND 89 and the tab fixing portion 82 are connected by only one through hole 84, the ground potential supplied to the tab 4 is The inductance is not sufficiently reduced and becomes unstable, and the first circuit portion is affected by switching on / off of a high-frequency oscillator having the second circuit portion. Further, since the LNA (low noise amplifier) 24 amplifies a weak signal, the fluctuation of the ground potential becomes the fluctuation of the output of the low noise amplifier 24 and leads to distortion of the signal waveform.
On the other hand, in the wireless communication device 69 of the first embodiment, in the mounting substrate 80 on which the high frequency power module 1 is mounted, the tab fixing portion 82 and the inner layer GND 89 are many through holes in the vicinity of the tab fixing portion 82. Therefore, the ground potential supplied to the tab 4 is sufficiently reduced in inductance.
Further, in the high frequency power module 1, the signal wiring from the electrode terminal 9 of the LNA (low noise amplifier) 24 having the first circuit portion to the lead 7 through the wire 10 has a fixed potential such as a ground potential on both sides thereof. Since the conductive wire 10 to be supplied is disposed, the signal wiring of the LNA 24 is electromagnetically shielded, so that the signal wiring is not easily subjected to crosstalk.
Therefore, the high frequency characteristics of the wireless communication device 69 can be improved.
Moreover, since the ground potential is sufficiently stabilized by sufficiently reducing the inductance of the ground potential supplied to the tab 4, as shown in FIG. 14, the land 81 for supplying the ground potential (GND) to the LNA 24 and The wiring 94 to be connected may be connected to the tab fixing portion 82. In particular, by arranging the wiring 94 inside the land 81 to which the wiring 94 is connected, the region outside the land 81 can be effectively used as a region for arranging other wiring 95 and components.
In particular, in order to improve the high frequency characteristics of a signal input to the LNA 24, a coil (L), a capacitor element (C), a resistance element (R), etc. connected to a land 81 for inputting a signal (Signal) to the LNA When a passive element is arranged, the wiring 94 from the land 81 for supplying the ground potential (GND) is drawn inward as described above, thereby making the various elements closer to the signal (Signal) input land 81. The high frequency characteristics can be improved more effectively. For example, in the example described in FIG. 14, the coil (L) and the capacitive element (C) are arranged very close to the land 81 for signal (Signal) input. Since the length of the wiring 96 between the terminals can be shortened, impedance matching with low loss can be achieved.
FIG. 17 shows a case where a modified mounting board 80 is used. The mounting board 80 shown in FIG. 17 employs a blind via 85 in which the common wiring connecting the wirings of the first wiring layer and the second wiring layer 87 does not reach the back surface of the mounting board 80. It is.
When the blind via 85 is adopted, the solder may flow into the through hole 84 in the through hole 84 and cause problems such as insufficient solder. However, the use of the blind via 85 provides an effect that the amount of solder can be easily controlled. be able to.
Further, even when the high-frequency power module 1 is mounted on the mounting substrate 80 in which the blind via 85 is formed, the same effect as that of the mounting substrate 80 of the through hole 84 can be obtained.
18 is a case where a blind via 85 is provided over the entire tab fixing portion 82, and FIG. 19 shows the high-frequency power module 1 on the mounting substrate 80 shown in FIG. The structure which mounted is shown. According to the mounting structure shown in FIG. 19, the blind via 85 (which may be the through hole 84) is arranged over the entire tab fixing portion 82, so that it is supplied to the tab 4 soldered to the tab fixing portion 82. The ground potential can be further reduced, and the high-frequency characteristics of the wireless communication device 69 can be further improved.
According to the first embodiment, in a semiconductor device such as the high-frequency power module 1, a ground potential is applied to both sides of the conductive wire 10 that transmits an external signal to a first circuit unit such as an LNA (low noise amplifier) 24. A conductive wire 10 to which a fixed potential is supplied is disposed, and a second circuit unit such as a synthesizer or a VCO is connected to the tab 4 to connect the ground potential (first potential) to the second circuit unit. In the structure for mounting the semiconductor device, the tab 4 and the plurality of through holes 84 (common wiring) of the mounting substrate 80 have an area. Since the large tab fixing portion 82 is connected via the solder 83, the tab 4 is in a state where the ground potential is sufficiently reduced in inductance.
As a result, the ground potential at the tab 4 of the second circuit section is also stabilized, and the fluctuation of the ground potential at the tab 4 can be reduced. For example, the fluctuation of the ground potential according to the operation of the second circuit unit such as an oscillator that operates periodically can be reduced, and the occurrence of crosstalk due to this can be prevented.
In addition, since the conductive wire 10 to which a fixed potential is supplied is disposed on both sides of the conductive wire 10 that transmits an external signal to the first circuit portion, the conductive wire 10 that transmits an external signal. Can be formed as an electromagnetic shield by the conductive wire 10 having a fixed potential. As a result, even if the ground potential fluctuates in the second circuit portion, the first circuit portion is hardly affected by the ground potential variation of the second circuit portion.
As a result, as in the first embodiment, in a wireless communication device 69 (electronic device) such as a cellular phone in which a semiconductor device such as the high frequency power module 1 is incorporated, to a circuit unit such as an LNA (low noise amplifier) 24. Thus, the input of power supply noise and signal noise can be reduced, whereby the high frequency characteristics of the wireless communication device 69 can be improved.
In addition, since the input of power supply noise and signal noise to the circuit unit such as the LNA 24 can be reduced, the reliability and quality of the wireless communication device 69 can be improved.
That is, the wireless communication device 69 can perform a good call without output fluctuation or distortion.
Further, in the high frequency power module 1 which is a semiconductor device, the signal wiring from the electrode terminal 9 of the LNA (low noise amplifier) 24 to the lead 7 through the wire 10 is grounded on both sides thereof and is electromagnetically shielded. Therefore, it is possible to make it difficult to receive crosstalk due to input / output of signals of other circuit portions.
Furthermore, since the tab 4 is exposed on the back surface of the sealing body 2, the high frequency power module 1 effectively dissipates the heat generated in the semiconductor chip 3 to the mounting substrate 80 via the tab fixing portion 82. Can do. Thereby, stabilization of operation | movement of the radio | wireless communication apparatus 69 incorporating this high frequency power module 1 can be aimed at.
In addition, since the high frequency power module 1 is a non-lead type semiconductor device in which the tab 4 and the lead 7 are exposed on the back surface of the sealing body 2, the high frequency power module 1 can be reduced in size and thickness and can be reduced in weight. . Therefore, the wireless communication device 69 incorporating the high frequency power module 1 can be reduced in size and weight.
The high-frequency power module 1 connects the electrode terminal 9 of the semiconductor chip 3 and the lead (pin) 7 with a wire 10, and the tab 4 serving as the first potential and the electrode terminal ( Since it has a down-bonding structure in which the ground electrode terminal) 9 is connected by the down-bonding wire 10a, the number of ground leads 7 serving as external electrode terminals can be reduced.
As a result, the sealing body 2 can be reduced in size by reducing the number of pins, and the high-frequency power module 1 can be reduced in size.
(Embodiment 2)
FIG. 20 is a plan view showing the structure of a high-frequency power module according to another embodiment (Embodiment 2) of the present invention, with a part of the sealing body cut away.
In the second embodiment, regarding the high-frequency power module 1 mounted on an electronic device such as the wireless communication device 69 (see FIG. 12), three LNAs (specific circuit units 11) in the high-frequency power module 1 of the first embodiment are used. The case where the low-noise amplifier) 24 is described has been described. In addition to the three LNAs (low-noise amplifiers) 24, the RFVCO 44 that handles high frequencies among the VCOs is also the specific circuit unit 11. Accordingly, all the ground electrode terminals 9 of the RFVCO 44 are connected to the leads (ground leads) 7 via the wires 10 and are not connected to the tabs 4 via the wires.
Further, in the wiring extending from the electrode terminal 9 of the semiconductor chip 3 to the lead 7 via the wire 10, a ground wiring having a fixed potential is arranged on both sides of the two signal wirings (Signals) of the RFVCO 44, and the high frequency according to the first embodiment. Similar to the power module 1, the signal wiring is electromagnetically shielded.
Similarly to the first embodiment, the three LNAs 24 are each provided with fixed potential ground lines on both sides of the two signal lines (Signals).
As a result, the ground potential of the specific circuit section 11 that handles high-frequency signals including the RFVCO 44 (high-frequency voltage controlled oscillator) in addition to the LNA 24 (low-noise amplifier) is less affected by the ground potential of other circuit sections. The high frequency characteristics of a wireless communication device 69 (electronic device) such as a mobile phone equipped with the module 1 can be improved.
(Embodiment 3)
FIG. 21 is a plan view showing a cutout part of a sealing body of a high-frequency power module according to another embodiment (Embodiment 3) of the present invention.
In the third embodiment, in the high-frequency power module 1 mounted on an electronic device such as the wireless communication device 69 (see FIG. 12), the RFVCO 44 is an external component and the semiconductor chip 3 is not formed monolithically. In this dual band communication system, each circuit unit such as a low noise amplifier, a mixer, a VCO, a synthesizer, an IQ modulator / demodulator, a frequency divider, and a quadrature modulator is monolithically formed.
The two mixers in the receiving system are each controlled by a frequency divider 73, and the frequency divider 73 converts a high frequency signal output from the RFVCO 44, which is an external component, into a lower frequency signal. Circuit.
Therefore, in the third embodiment, as shown in FIG. 21, the RFVCO 44 exists outside the high-frequency power module 1, and the signal wiring (Signal) of the RFVCO 44 is connected to the lead 7 of the high-frequency power module 1. The electrode terminals 9 on both sides of the two signal wirings extending from the two leads 7 connected to the RFVCO 44 to the electrode terminals 9 of the semiconductor chip 3 via the wires 10 are connected via the wires 10. Yes. The electrode terminals 9 on both sides of the two signal wires are fixed potential ground electrode terminals 9, and therefore the lead 7 connected to the ground electrode terminal 9 via the wire 10 is also fixed potential ground. It is lead 7 for. As a result, similarly to the second embodiment, the signal wiring for handling the high-frequency signal is also electromagnetically shielded, and the ground potential is independent from the other circuit portions in the semiconductor chip 3.
As in the second embodiment, the fixed potential ground lines are arranged on both sides of the two signal lines (Signals) in the three LNAs 24, respectively.
As a result, also in the present third embodiment, as in the second embodiment, a failure due to the fluctuation of the ground potential of the RFVCO 44 does not occur. Therefore, a wireless communication device 69 such as a mobile phone on which the high frequency power module 1 is mounted. The high frequency characteristics can be improved.
(Embodiment 4)
22 and 23 are diagrams related to a high-frequency power module according to another embodiment (Embodiment 4) of the present invention, and FIG. 22 is a plan view in which a part of the sealing body of the high-frequency power module is cut away. 23 is a cross-sectional view of the high-frequency power module shown in FIG. 22, and FIG. 24 is a cross-sectional view showing a modification of the high-frequency power module according to the fourth embodiment.
In the fourth embodiment, as shown in FIG. 22 and FIG. 23, the tab 4 serving as a common ground terminal and the lead 7 that is set to the ground potential are electrically connected by the conductive wire 10b. Are also ground external electrode terminals. In the high frequency power module 1 according to the fourth embodiment, since the back surface of the tab 4 is exposed from the back surface (mounting surface) of the sealing body 2, the tab 4 can be used as an external electrode terminal for grounding, and the tab 4 can be wired. The lead 7 connected via 10b can also be used as an external electrode terminal for ground.
Further, in the structure shown in FIG. 24 which is a modification of the fourth embodiment, the back side of the tab 4 is half-etched to be thinned. The resin wraps around, whereby the tab 4 is completely buried in the sealing body 2 without exposing the back surface of the tab 4 from the sealing body 2.
In such a structure, since the tab 4 is not exposed on the back surface of the sealing body 2, the tab 4 and the tab fixing portion 82 of the mounting substrate 80 shown in FIG. 13 cannot be directly connected via solder. Therefore, in the mounting substrate 80, a plurality of through holes 84 are connected to the lands 81 connected to the leads 7 for supplying the ground potential to the tab 4 to reduce the inductance of the ground potential, and the land 81 is connected. The lead 7 and the tab 4 are connected by a plurality of wires 10b per lead to reduce the ground between the lead and the tab.
Alternatively, the lead 7 and the tab 4 having a low ground inductance are directly connected by the lead material on the lead frame, thereby reducing the ground inductance between the lead and the tab as described above.
Thus, even with the high-frequency power module 1 having a structure in which the tab 4 is embedded in the sealed body, the high-frequency characteristics of the wireless communication device 69 such as a mobile phone equipped with the high-frequency power module 1 can be improved.
In the case of the structure shown in FIG. 24, since the tab 4 is connected to the lead 7 via the wire 10b, the lead 7 can be used as an external electrode terminal for ground. In addition, as another structure which embeds the tab 4 in the sealing body 2, it is good also as a structure bent one step higher in the middle of a tab suspension lead.
In the structure of the modified example shown in FIG. 24, the number of leads 7 connected to the tab via the wire 10b is smaller than the number of ground potential supply electrode terminals 9 connected to the tab 4 via the wire 10a. By reducing the number, the number of leads 7 arranged along the periphery of the sealing body 2 can be reduced, the semiconductor device can be downsized, and the back surface of the tab 4 is covered with the sealing body 2. Therefore, when a semiconductor device such as the high-frequency power module 1 according to the fourth embodiment is mounted on the mounting substrate 80 (see FIG. 13), wiring on the mounting substrate 80 is also arranged in the region below the high-frequency power module 1. There is an advantage that it can be used as an area for. Therefore, the fourth embodiment has an advantage that the mounting density on the wiring board such as the mounting board 80 can be improved along with the miniaturization of the high-frequency power module 1.
(Embodiment 5)
FIG. 25 is a plan view showing the structure of a high-frequency power module according to another embodiment (Embodiment 5) of the present invention, with a part of the sealing body cut away.
The high-frequency power module 1 according to the fifth embodiment has a third configuration in which the supply of the ground potential (first potential) to the LNA 24 in the high-frequency power module 1 described in the first embodiment is connected to the tab 4 and the wire 10a. This is performed through the electrode terminal 9 which is an electrode terminal of the above.
That is, in the high frequency power module 1 according to the fifth embodiment, the semiconductor chip 3 mounted on the high frequency power module 1 has the electrode terminal 9 (third electrode terminal) for supplying the ground potential (first potential) to the LNA 24. The electrode terminal 9 (third electrode terminal) and the tab 4 are connected by a conductive wire 10a.
Therefore, in the high-frequency power module 1 according to the fifth embodiment, the supply of the ground potential (first potential) to the LNA 24 is not performed via the fixed potential leads 7 on both sides of the signal wiring (Signal). By connecting to the plurality of through holes 84 of the mounting substrate 80, the power supply wiring is performed via the tab 4 with a reduced inductance.
Also in the high frequency power module 1 of the fifth embodiment, leads 7 and wires 10 having a fixed potential different from the ground potential of the tab 4 are arranged on both sides of the signal wiring (Signal) of the LNA 24. The signal wiring of the LNA 24 is electromagnetically shielded similarly to the high frequency power module 1 of the first embodiment.
Therefore, also in the wireless communication device 69 such as a mobile phone equipped with the high frequency power module 1 of the fifth embodiment, the high frequency characteristics can be improved.
Furthermore, in the high frequency power module 1 of the fifth embodiment, the conductive wire 10a that connects the electrode terminal 9 (third electrode terminal) and the tab 4 is the electrode terminal 9 (signal first) for signal wiring (Signal). Compared with the conductive wire 10 connecting the first electrode terminal) and the lead 7 (first lead), the length thereof can be made very short.
Thereby, since the wire length of the power supply for supply to LNA24 becomes short, the impedance of this wiring can be made small and the characteristic of the high frequency power module 1 can be improved further.
Therefore, it is possible to further improve the high frequency characteristics of the wireless communication device 69 such as a mobile phone equipped with the high frequency power module 1 of the fifth embodiment.
Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment described above, and various modifications can be made without departing from the scope of the invention. Nor.
In the first to fifth embodiments, only the ground potential is described as the common power supply potential. However, the scope of application of the present invention is not limited to only the ground potential and related configurations, and the invention is applied. Focusing on an appropriate power source potential (first potential), for example, a power source potential that can reduce the number of leads 7 by making electrodes common, an electrode terminal 9 for supplying the power source potential, The present invention may be applied to the configuration of the lead 7.
In the first to fifth embodiments, the example in which the present invention is applied to the manufacture of a QFN type semiconductor device has been described. For example, the present invention can also be applied to the manufacture of a SON type semiconductor device. It can have a similar effect. Further, the semiconductor device mounted on the semiconductor device or the electronic device of the present invention is not limited to the non-lead type semiconductor device, but, for example, a lead bent into a gull wing shape protrudes along the periphery of the sealing body 2. It can also be applied to a semiconductor device called QFP (Quad Flat Package) or SOP (Small Outline Package), but the amount of protrusion of the lead around the sealing body 2 is larger than that of the QFP or SOP. It is more preferable to adopt a small QFN type structure in order to achieve miniaturization of the semiconductor device.
In the first to fifth embodiments, a case where a wireless communication device (electronic device) such as a mobile phone equipped with a semiconductor device is a wireless communication device 69 in which an antenna 20 is attached in advance to the main body will be described. However, as shown in the modification of FIG. 26, the electronic device of the present invention has an antenna external device 93 in which an antenna 92 such as a television, a set top box, or a car navigation device is attached to each main body later. In this antenna external device 93, the high-frequency characteristics can be improved by incorporating the high-frequency power module 1 described in the first to fifth embodiments.

以上のように、本発明の電子装置および半導体装置は携帯電話機などの無線通信装置に使用される。特に、通信システムが複数系統の携帯電話機において、低雑音増幅器のような入力信号が極めて微弱な信号を処理する回路部に前記入力信号を送る信号配線の両側に固定電位の配線を配置するとともに、この半導体装置が実装される配線基板において複数の共通配線により低インダクタンス化されたグランド電位を半導体装置のタブに供給する実装構造を有することにより、１系統の通信システムを使用中、他の系統の通信システムとの間でのクロストークが発生しなくなり、良好な通話が可能な電子装置および半導体装置を提供することができる。  As described above, the electronic device and the semiconductor device of the present invention are used for a wireless communication device such as a mobile phone. In particular, in a mobile phone having a plurality of communication systems, a fixed potential wiring is arranged on both sides of a signal wiring for sending the input signal to a circuit unit that processes a very weak input signal such as a low noise amplifier, In the wiring board on which the semiconductor device is mounted, a mounting structure for supplying a ground potential reduced in inductance by a plurality of common wirings to the tab of the semiconductor device is used. It is possible to provide an electronic device and a semiconductor device in which crosstalk with a communication system does not occur and good communication is possible.

Claims (15)

複数のリードと、主面および裏面を有するタブと、複数の電極端子およびそれぞれが複数の半導体素子によって構成される複数の回路部を有する半導体チップと、前記複数の電極端子と前記リードとを接続する複数の導電性のワイヤと、前記複数の電極端子と前記タブの主面とを接続して前記複数の電極端子に第１の電位を供給する複数の導電性のワイヤとを有する半導体装置と、
前記半導体装置が実装され、第１の配線層と第２の配線層とを備えており、前記第１の配線層と第２の配線層とに開口する複数の貫通孔に配置されてそれぞれの前記配線層の配線を接続する共通配線が設けられた配線基板とを有する電子装置であって、
前記半導体チップは前記タブの主面に固定されており、
前記回路部は、前記リードを介して外部信号が入力される第１の回路部と、前記タブと前記導電性のワイヤを介して接続される第２の回路部とを含んでおり、
前記複数の電極端子は、前記第１の回路部に前記外部信号を入力する第１の電極端子と、前記第１の回路部に固定電位を供給する第２の電極端子とを有しており、
前記複数のリードは、前記外部信号を伝達する第１のリードと、前記第１のリードの両側に配置された第２のリードとを含んでおり、
前記第１のリードと前記第１の電極端子とを接続する前記導電性のワイヤの両側に前記第２のリードと前記第２の電極端子とを接続する前記導電性のワイヤが配置されており、
前記タブと前記配線基板の前記共通配線とが接続されていることを特徴とする電子装置。Connecting a plurality of leads, a tab having a main surface and a back surface, a plurality of electrode terminals and a semiconductor chip having a plurality of circuit portions each composed of a plurality of semiconductor elements, and the plurality of electrode terminals and the leads A plurality of conductive wires, and a plurality of conductive wires that connect the plurality of electrode terminals and the main surface of the tab to supply a first potential to the plurality of electrode terminals; ,
The semiconductor device is mounted, and includes a first wiring layer and a second wiring layer, and each of the semiconductor devices is disposed in a plurality of through holes opened in the first wiring layer and the second wiring layer. An electronic device having a wiring board provided with a common wiring for connecting wirings of the wiring layer,
The semiconductor chip is fixed to the main surface of the tab,
The circuit unit includes a first circuit unit to which an external signal is input through the lead, and a second circuit unit connected to the tab through the conductive wire,
The plurality of electrode terminals include a first electrode terminal that inputs the external signal to the first circuit unit, and a second electrode terminal that supplies a fixed potential to the first circuit unit. ,
The plurality of leads include a first lead for transmitting the external signal, and second leads disposed on both sides of the first lead,
The conductive wire for connecting the second lead and the second electrode terminal is disposed on both sides of the conductive wire for connecting the first lead and the first electrode terminal. ,
The electronic device, wherein the tab and the common wiring of the wiring board are connected. 請求の範囲第１項記載の電子装置であって、前記共通配線と接続されたタブ接続用端子が、半田を介して前記タブと接続されていることを特徴とする電子装置。The electronic device according to claim 1, wherein a tab connection terminal connected to the common wiring is connected to the tab via solder. 請求の範囲第２項記載の電子装置であって、前記複数の共通配線が前記タブ接続用端子の辺に沿って設けられていることを特徴とする電子装置。3. The electronic device according to claim 2, wherein the plurality of common wires are provided along a side of the tab connection terminal. 請求の範囲第１項記載の電子装置であって、前記複数の電極端子は、前記第１の回路部に前記第１の電位を供給する第３の電極端子を有しており、前記第３の電極端子と前記タブとが前記導電性のワイヤによって接続されていることを特徴とする電子装置。The electronic device according to claim 1, wherein the plurality of electrode terminals include a third electrode terminal that supplies the first potential to the first circuit unit, and The electrode terminal and the tab are connected by the conductive wire. 請求の範囲第４項記載の電子装置であって、前記第３の電極端子と前記タブとを接続する前記導電性のワイヤは、前記第１の電極端子と前記第１のリードとを接続する前記導電性のワイヤより短いことを特徴とする電子装置。5. The electronic device according to claim 4, wherein the conductive wire that connects the third electrode terminal and the tab connects the first electrode terminal and the first lead. An electronic device characterized by being shorter than the conductive wire. 請求の範囲第１項記載の電子装置であって、前記複数の電極端子は、前記第１の回路部に前記第１の電位を供給する第３の電極端子を有しており、前記第３の電極端子と前記リードとが前記導電性のワイヤによって接続されていることを特徴とする電子装置。The electronic device according to claim 1, wherein the plurality of electrode terminals include a third electrode terminal that supplies the first potential to the first circuit unit, and An electronic device, wherein the electrode terminal and the lead are connected by the conductive wire. 請求の範囲第１項記載の電子装置であって、前記第２の電極端子を介して前記第１の回路部に供給される前記固定電位が前記第１の電位であることを特徴とする電子装置。2. The electronic device according to claim 1, wherein the fixed potential supplied to the first circuit portion through the second electrode terminal is the first potential. apparatus. 請求の範囲第１項記載の電子装置であって、前記第１の回路部は、前記リードを介して入力される前記外部信号を増幅する増幅回路であることを特徴とする電子装置。2. The electronic device according to claim 1, wherein the first circuit unit is an amplifier circuit that amplifies the external signal input through the lead. 請求の範囲第１項記載の電子装置であって、前記第２の回路部は、前記第１の回路部によって増幅された信号を処理する機能の少なくとも一部を有することを特徴とする電子装置。2. The electronic device according to claim 1, wherein the second circuit unit has at least a part of a function of processing a signal amplified by the first circuit unit. . 請求の範囲第１項記載の電子装置であって、前記半導体装置は、絶縁性樹脂からなる封止体を有しており、前記封止体には、前記半導体装置を前記配線基板に実装した際に前記配線基板の主面と対向する実装面が形成されており、前記複数のリードは、前記実装面に露出していることを特徴とする電子装置。The electronic device according to claim 1, wherein the semiconductor device has a sealing body made of an insulating resin, and the semiconductor device is mounted on the wiring board in the sealing body. In this case, a mounting surface facing the main surface of the wiring board is formed, and the plurality of leads are exposed to the mounting surface. 請求の範囲第１０項記載の電子装置であって、前記封止体の前記実装面に前記タブが露出しており、前記配線基板の前記共通配線と接続されたタブ接続用端子が、半田を介して前記タブと接続されていることを特徴とする電子装置。11. The electronic device according to claim 10, wherein the tab is exposed on the mounting surface of the sealing body, and the tab connection terminal connected to the common wiring of the wiring board is soldered. And an electronic device connected to the tab. 請求の範囲第１項記載の電子装置であって、前記第１の回路部は、無線信号がアンテナを介して変換された電気信号を増幅するための回路であることを特徴とする電子装置。2. The electronic apparatus according to claim 1, wherein the first circuit unit is a circuit for amplifying an electric signal obtained by converting a radio signal through an antenna. 絶縁性樹脂からなる封止体と、
前記封止体の周囲に沿って配置され、前記封止体の内外に亘って設けられた複数のリードと、
主面および裏面を有するタブと、
主面および裏面を有しており、その主面上に複数の電極端子と、それぞれが複数の半導体素子によって構成される複数の回路部とを有する半導体チップと、
前記複数の電極端子と前記リードとを接続する複数の導電性のワイヤと、
前記複数の電極端子と前記タブの主面とを接続して前記複数の電極端子に第１の電位を供給する複数の導電性のワイヤとを有する半導体装置であって、
前記半導体チップは前記タブの主面に固定されており、
前記回路部は、前記リードを介して外部信号が入力される第１の回路部と、前記タブと前記導電性のワイヤを介して接続される第２の回路部とを含んでおり、
前記複数の電極端子は、前記第１の回路部に前記外部信号を入力する第１の電極端子と、前記第１の回路部に固定電位を供給する第２の電極端子とを有しており、
前記複数のリードは、前記外部信号を伝達する第１のリードと、前記第１のリードの両側に配置された第２のリードとを含んでおり、
前記第１のリードと前記第１の電極端子とを接続する前記導電性のワイヤの両側に前記第２のリードと前記第２の電極端子とを接続する前記導電性のワイヤが配置されていることを特徴とする半導体装置。A sealing body made of an insulating resin;
A plurality of leads disposed along the periphery of the sealing body and provided inside and outside the sealing body;
A tab having a main surface and a back surface;
A semiconductor chip having a main surface and a back surface, a plurality of electrode terminals on the main surface, and a plurality of circuit units each constituted by a plurality of semiconductor elements;
A plurality of conductive wires connecting the plurality of electrode terminals and the leads;
A semiconductor device comprising: a plurality of conductive wires that connect the plurality of electrode terminals and a main surface of the tab and supply a first potential to the plurality of electrode terminals;
The semiconductor chip is fixed to the main surface of the tab,
The circuit unit includes a first circuit unit to which an external signal is input through the lead, and a second circuit unit connected to the tab through the conductive wire,
The plurality of electrode terminals include a first electrode terminal that inputs the external signal to the first circuit unit, and a second electrode terminal that supplies a fixed potential to the first circuit unit. ,
The plurality of leads include a first lead for transmitting the external signal, and second leads disposed on both sides of the first lead,
The conductive wire for connecting the second lead and the second electrode terminal is disposed on both sides of the conductive wire for connecting the first lead and the first electrode terminal. A semiconductor device. 請求の範囲第１３項記載の半導体装置であって、前記複数の電極端子は、前記第１の回路部に前記第１の電位を供給する第３の電極端子を有しており、前記第３の電極端子と前記タブとが前記導電性のワイヤによって接続されていることを特徴とする半導体装置。14. The semiconductor device according to claim 13, wherein the plurality of electrode terminals include a third electrode terminal that supplies the first potential to the first circuit portion. The electrode terminal and the tab are connected by the conductive wire. 請求の範囲第１３項記載の半導体装置であって、前記複数の電極端子は、前記第１の回路部に前記第１の電位を供給する第３の電極端子を有しており、前記第３の電極端子と前記リードとが前記導電性のワイヤによって接続されていることを特徴とする半導体装置。14. The semiconductor device according to claim 13, wherein the plurality of electrode terminals include a third electrode terminal that supplies the first potential to the first circuit portion. An electrode terminal and the lead are connected by the conductive wire.
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