WO2003094236A1 - Semiconductor device and radio communication apparatus - Google Patents

Semiconductor device and radio communication apparatus Download PDF

Info

Publication number
WO2003094236A1
WO2003094236A1 PCT/JP2002/004339 JP0204339W WO03094236A1 WO 2003094236 A1 WO2003094236 A1 WO 2003094236A1 JP 0204339 W JP0204339 W JP 0204339W WO 03094236 A1 WO03094236 A1 WO 03094236A1
Authority
WO
WIPO (PCT)
Prior art keywords
lead
semiconductor device
tab
circuit
sealing body
Prior art date
Application number
PCT/JP2002/004339
Other languages
French (fr)
Japanese (ja)
Inventor
Tadatoshi Danno
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2002/004339 priority Critical patent/WO2003094236A1/en
Priority to KR1020087009552A priority patent/KR100993579B1/en
Priority to CNB038096366A priority patent/CN100380651C/en
Priority to KR1020087009547A priority patent/KR100993277B1/en
Priority to CNA2009101340438A priority patent/CN101515579A/en
Priority to US10/512,459 priority patent/US7425756B2/en
Priority to CNB2007101273468A priority patent/CN100536123C/en
Priority to CNA2009101340423A priority patent/CN101515578A/en
Priority to JP2004502352A priority patent/JP4351150B2/en
Priority to AU2003235967A priority patent/AU2003235967A1/en
Priority to KR1020047017429A priority patent/KR100993276B1/en
Priority to PCT/JP2003/005475 priority patent/WO2003094232A1/en
Publication of WO2003094236A1 publication Critical patent/WO2003094236A1/en
Priority to US11/455,157 priority patent/US7312511B2/en
Priority to US11/455,171 priority patent/US20060237831A1/en
Priority to US12/032,690 priority patent/US7937105B2/en
Priority to US12/033,061 priority patent/US7777309B2/en
Priority to JP2009142145A priority patent/JP5080532B2/en
Priority to US13/094,383 priority patent/US8126501B2/en
Priority to JP2012128107A priority patent/JP5473026B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801—Structure
    • H01L2224/48011—Length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a semiconductor device and an electronic device.
  • the present invention relates to a high-frequency power module (semiconductor device) incorporating a high-frequency unit analog signal processing IC including a low noise amplifier (LNA) for amplifying a weak signal.
  • LNA low noise amplifier
  • wireless communication devices electronic devices
  • Mobile communication devices such as mobile phones are configured to be compatible with multiple communication systems. That is, a plurality of circuit systems are incorporated in a transceiver (front end) of a mobile phone so as to transmit and receive a plurality of communication systems.
  • a dual-band communication method is known as a method that enables communication between mobile phones (for example, cellular telephones) using different communication methods (systems).
  • GSM Global System for Mobile Communications
  • DCS with a carrier frequency band of 170 to 1785 MHz
  • the dual-band system using the 1800 (Digital Cellular System 1800) and the high-frequency power amplifier for the dual band.
  • RF Radio Frequency
  • MOS FET Metal Oxide Semiconductor Field-Effect-Transistor
  • the dual-band system processes signals of two communication systems, such as GSM and DCS 180, and the triple-band system uses GSM and DCS (Digital Cellular System) 180, and PCS 190. It processes signals of three communication systems such as the 00 system.
  • GSM Global System for Mobile Communications
  • GSM900 or GSM850 is incorporated.
  • the high-frequency power module includes an LNA, mixer, PLL (Phase-Locked Loop) synthesizer, PGA (Programmable Gain Amplifier) with auto-calibration, IQ modulator / demodulator, offset PLL, It incorporates a one-chip semiconductor device that monolithically integrates VC0 (Voltage-Controlled Oscillator) and the like.
  • S 0 N Small Outline Non-Leaded Package
  • QFN Quad Flat Non-Leaded Package
  • the resin-encapsulated semiconductor device described in this document has an island having a die pad for fixing a semiconductor chip and a wire bonding portion for connecting wires, and the semiconductor chip is fixed on the die pad.
  • Each of the electrode terminals of the semiconductor chip is connected to a wire bonding part of a lead or an island.
  • An air gap is provided between the die pad and the wire bonding part to prevent the bonded wire from coming off or cutting due to heat stress.
  • the island can be connected to a printed board or the like as a ground lead.
  • Japanese Patent Application Laid-Open No. H11-251514 describes a high-frequency device in which a lead structure used in a mobile phone or the like having a semiconductor element mounting portion as a ground is a gull-wing type. .
  • the electrode of the semiconductor element and the semiconductor element mounting portion are connected with a wire in order to use the die pad as a ground electrode ( Down bonding). Due to down bonding, the semiconductor element mounting part is larger than the semiconductor element, and in the mounted state, the periphery of the semiconductor element mounting part protrudes outside the semiconductor element, and a wire is connected to this part. Has become.
  • a high-frequency power module is incorporated in a non-lead type semiconductor device, and a ground terminal of each circuit part constituting a high-frequency power module is connected to a wire in order to stabilize a ground potential.
  • a method of electrical connection to the evening via the Internet By using down bonding, the number of external electrode terminals can be reduced and the package The size of the semiconductor device can be reduced eventually.
  • the signal captured by the antenna is amplified by a low noise amplifier (LNA), but the input signal is extremely weak.
  • LNA low noise amplifier
  • the potential of the common terminal that is, the ground potential fluctuates in accordance with the operation of each circuit section, especially the oscillator that operates periodically, and as a result, there is a possibility that the circuit section and the circuit section may be partially connected.
  • Crosstalk occurs and the output fluctuates, preventing good calls.
  • signal waveform distortion due to induced current due to inter-lead crosstalk or fluctuation in ground potential is output from the communication system, and this output signal enters the communication system in use and becomes noise.
  • Circuits that are susceptible to such fluctuations in ground potential and crosstalk include RF VCOs (high-frequency voltage controlled oscillators) that handle high frequencies in addition to low noise amplifiers (LNA).
  • RF VCOs high-frequency voltage controlled oscillators
  • LNA low noise amplifier
  • the present inventor has proposed that in a low-noise amplifier or RFVC0, among the electrode terminals of a semiconductor element, the ground terminal is not connected to a tab serving as a common terminal via a wire, but is connected to an independent lead terminal (external electrode).
  • the present invention has been made with the idea that the influence of the fluctuation of the ground potential at the time of turning on and off other circuit parts is reduced by connecting the terminal to the terminal via a wire.
  • An object of the present invention is to provide a down-bonded semiconductor device in which a ground potential in a specific circuit portion of a circuit formed in a semiconductor element is hardly affected by a ground potential in the remaining circuit portion. It is to provide a semiconductor device that can be used.
  • Another object of the present invention is to provide a high-frequency power module in which a circuit section such as a low-noise amplifier or RFVC0 is less likely to be affected by crosstalk due to fluctuations in the ground potential of other circuit sections in the high-frequency power module. To is there.
  • Another object of the present invention is to provide a wireless communication device capable of making a good call with less noise in a wireless communication system.
  • Another object of the present invention is to provide a wireless communication device capable of performing a good call with less noise in a wireless communication system having a plurality of communication systems.
  • a plurality of leads provided along the periphery of the sealing body and inside and outside the sealing body;
  • a tab having a main surface and a back surface
  • a semiconductor chip having a main surface and a back surface, a plurality of electrode terminals on the main surface, and a plurality of circuit portions each including a plurality of semiconductor elements;
  • a semiconductor device including a plurality of conductive wires connecting the plurality of electrode terminals and the main surface of the tab (for example, a non-leaded device) Semiconductor device)
  • the back surface of the semiconductor chip is fixed on the main surface of the tab,
  • the plurality of circuit units include a first circuit unit (specific circuit unit) and a second circuit unit,
  • the plurality of electrode terminals are a first electrode terminal for inputting an external signal to the first circuit unit, and a first potential (ground potential) for supplying the first circuit unit with the first potential.
  • the plurality of leads include a first lead (a signal lead), a second lead (a signal lead), and a third lead disposed between the first lead and the second lead.
  • the first electrode terminal is connected to the first lead via a conductive wire
  • the second electrode terminal is connected to the third lead via a conductive wire
  • the third electrode terminal is connected to the second lead via a conductive wire
  • the fourth electrode terminal is connected to a common ground via a conductive wire, as described above.
  • the third lead and the tab are electrically separated from each other
  • the first circuit unit is an amplifier circuit (low-noise amplifier: LAN) for amplifying an external signal input through the first lead and the first electrode terminal. This is a circuit for amplifying the electric signal converted through the circuit.
  • LAN low-noise amplifier
  • the second circuit unit processes the signal amplified by the first circuit unit. It has at least some of the functions to manage.
  • a plurality of communication circuits are formed in the high-frequency power module so as to be compatible with a plurality of communication systems.
  • Such a high-frequency power module is incorporated in a wireless communication device.
  • the electrode terminal of the semiconductor element is connected (down-bonded) to a tab serving as a common ground in addition to being connected to a lead via a wire.
  • the ground electrode terminal (electrode terminal of the semiconductor element) of the low-noise amplifier (specific circuit part) that amplifies a weak signal is not connected to the tab, but is connected to an independent lead terminal (lead for ground).
  • the ground potential is independent from other circuit sections, and the ground potential does not easily fluctuate even when the power of the other circuit section is turned on and off. Output fluctuations of the low-noise amplifier and distortion of the signal waveform are less likely to occur, and if incorporated in a wireless communication device, a good call without output fluctuations and distortion becomes possible.
  • the high-frequency power module is a bonded semiconductor device with a down-bonded structure that can be small, thin, and lightweight, and has a heat dissipation property because the tab is exposed on the back surface of the sealing body. Is good, and stable operation is possible. Therefore, by incorporating this high-frequency power module, it is possible to provide a small-sized and light-weight mobile phone having good call performance.
  • FIG. 1 is a schematic plan view in which a part of a sealed body of a high-frequency power module according to an embodiment (Embodiment 1) of the present invention is partially cut away.
  • FIG. 2 is a cross-sectional view of the high-frequency power module according to the first embodiment.
  • FIG. 3 is a schematic plan view of the high-frequency power module according to the first embodiment.
  • FIG. 4 is a schematic plan view schematically illustrating a circuit configuration of a semiconductor chip incorporated in the high-frequency power module according to the first embodiment.
  • FIG. 5 is a schematic plan view showing a connection state between external electrode terminals and respective circuit units such as a low-noise amplifier and a synthesizer of a semiconductor chip in the high-frequency power module of the first embodiment.
  • FIG. 6 is a flowchart showing a method of manufacturing the high-frequency power module according to the first embodiment.
  • FIG. 7 is a plan view of a lead frame used in manufacturing the high-frequency power module of the first embodiment.
  • FIG. 8 is a schematic plan view showing a unit lead frame pattern in the lead frame.
  • FIG. 9 is a schematic sectional view showing the lead frame on which a semiconductor chip is mounted.
  • FIG. 10 is a schematic sectional view showing the lead frame after wire bonding has been completed.
  • FIG. 11 is a schematic cross-sectional view showing the lead frame on which a sealing body is formed.
  • FIG. 12 is a block diagram showing a circuit configuration of a mobile phone in which the high-frequency power module of the first embodiment is incorporated.
  • FIG. 13 is a schematic cross-sectional view showing a mounting state of the high-frequency power module of the first embodiment in a mobile phone.
  • FIG. 14 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 2) of the present invention, in which a part of a sealing body is cut away.
  • FIG. 15 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 3) of the present invention, in which a sealing body is partially cut away.
  • FIG. 16 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 4) of the present invention, in which a part of a sealing body is cut away.
  • FIG. 17 is a schematic sectional view of the high-frequency power module according to the fourth embodiment.
  • FIG. 18 is a schematic cross-sectional view showing a modification of the high-frequency power module of the fourth embodiment.
  • FIGS. 1 to 13 are diagrams related to a semiconductor device (high-frequency power module) according to an embodiment (Embodiment 1) of the present invention and a wireless communication device incorporating the high-frequency power module.
  • 1 to 5 are diagrams relating to the high-frequency power module
  • FIGS. 6 to 11 are high-frequency power modules.
  • FIGS. 12 and 13 are diagrams relating to the wireless communication device.
  • the semiconductor device 1 constitutes, for example, a high-frequency power module.o
  • the QFN type semiconductor device 1 has a sealing body (package) 2 formed of a flat rectangular insulating resin.
  • a rectangular semiconductor element (semiconductor chip: chip) 3 is embedded in the sealing body 2.
  • the semiconductor chip 3 is fixed to the surface (principal surface) of the square cup 4 with an adhesive 5 (see FIG. 2).
  • the back surface (lower surface) of the sealing body 2 is the mounting surface side (mounting surface).
  • the tab 4 and the tab suspension lead 6 supporting the tab 4 and one surface (mounting surface 7a) of the lead (external electrode terminal) 7 are exposed.
  • the tab 4, the tab suspension lead 6 and the lead 7 are formed by a patterned metal (for example, copper) lead frame in the manufacture of the semiconductor device 1, and then cut and formed. You. Therefore, in the first embodiment, the tabs 4, the tab suspension leads 6, and the leads 7 have the same thickness. However, in the lead 7, since the inner end portion is formed thin by etching the back surface to a certain depth, the resin constituting the sealing body 2 enters under the thin lead portion. It is. This makes it difficult for the lead 7 to fall off the sealing body 2.
  • a patterned metal for example, copper
  • the tab 4 is supported by a tab suspension lead 6 having four narrow corners.
  • These evening suspension leads 6 are located on a diagonal line of the rectangular sealing body 2, and the outer end faces each corner of the rectangular sealing body 2.
  • Seal 2 is a flat square
  • the corners (corners) are chamfered to form slopes 2a (see Fig. 1).
  • the outer end of the evening suspension lead 6 slightly protrudes from this chamfered portion to 0.1 mm or less.
  • the protruding length is determined by the cutting type of the press machine used to cut the suspension lead in the lead frame state. For example, 0.1 mm or less is selected.
  • a plurality of leads 7 having an inner end facing the tab 4 are arranged at predetermined intervals along each side of the rectangular sealing body 2. .
  • the outer ends of the evening suspension leads 6 and 7 extend to the periphery of the sealing body 2. That is, the lead 7 and the tab suspension lead 6 extend inside and outside the sealing body 2.
  • the protruding length of the lead 7 from the sealing body 2 is determined by the cutting die of the press machine when cutting the lead in the state of the lead frame as in the case of the above-mentioned hanging suspension 6, for example, 0 Projects slightly less than 1 mm.
  • the side surface of the sealing body 2 is an inclined surface 2b (see FIG. 2).
  • the inclined surface 2b is formed on one surface of the lead frame to form the sealing body 2 on one side thereof, and then to facilitate removal when the sealing body 2 is removed from the mold mold cavity. This is due to the fact that the side surface of the cavity is inclined.
  • FIG. 1 is a schematic diagram in which the upper portion of the sealing body 2 is cut out so that the tab 4, the tab suspension lead 6, the lead 7, the semiconductor chip 3, and the like can be seen.
  • the exposed main surface of the semiconductor chip 3 is provided with an electrode terminal 9.
  • the electrode terminals 9 are provided on the main surface of the semiconductor chip 3 at substantially a predetermined pitch along each side of the square.
  • the electrode terminal 9 is connected to the inner end of the lead 7 via a conductive wire 10.
  • the head 4 is formed larger than the semiconductor chip 3, and the center of the main surface is formed.
  • a wire connection region is provided outside the semiconductor element fixing region, that is, on the peripheral portion of the tab 4.
  • the semiconductor chip 3 is fixed to the semiconductor element fixing region.
  • the other end of the conductive wire 10 whose one end is connected to the electrode terminal 9 of the semiconductor chip 3 is connected to the wire connection region.
  • the wire 10 connected to the tab 4 is called a down-bonding wire 10a. Since the wire bonding device performs wire bonding between the electrode terminal 9 and the lead 7 and wire bonding between the electrode terminal 9 and the tab 4, the wire 10 is also a down bonding wire 10a. Are also of the same material.
  • the purpose of adopting the down-bonding structure is to commonly use the tab to share the ground potential of each circuit section in the semiconductor chip.
  • the spark plug as a common ground terminal and connecting the spark plug and a number of electrode terminals to be the ground electrode terminals via wires, the external electrode terminals are lined up along the periphery of the sealing body.
  • the number of leads (pins) can be reduced, and the size of the sealing body can be reduced by reducing the number of leads. This leads to downsizing of the semiconductor device.
  • the sealing body 2 is provided between each lead 7 and the lead 7 and between the lead 7 and the tab suspension lead 6.
  • resin burrs generated during the formation. This resin burr portion is generated when the encapsulant 2 is formed in one side mode on one surface of the lead frame in the manufacture of the semiconductor device 1. After molding, the unnecessary lead frame is cut off, but when cutting the lead or tab hanging lead, the resin glue is also cut at the same time. Along with the edge of the lead 6, some resin burrs will remain between each lead 7 and the lead 7, and between the lead 7 and the tab suspension lead 6.
  • the back surface of the sealing body 2 has a structure that is recessed from the back surface (mounting surface) of the tab 4, the evening hanger lead 6, and the lead 7. This is because in a one-sided transfer molding mode, a resin sheet is placed between the upper and lower mold dies, and the mold is placed so that one side of the lead frame contacts this sheet. As a result, the sheet bites into the gap between the lead frames, so that the back surface of the sealing body 2 is retracted.
  • a plating film for surface mounting is formed on the surface of the lead frame. Therefore, the surfaces of the tab 4, the tab suspension lead 6, and the lead 7 exposed on the back surface of the sealing body 2 of the semiconductor device 1 have a plating film (not shown).
  • the back surface of the sealing body 2 is recessed, when the semiconductor device 1 is surface-mounted on a wiring board such as a mounting board, The feature is that the solder wet area is specified and the solder mounting is good.
  • the semiconductor device 1 includes a lead frame preparation (S101), a chip bonding (S102), a wire bonding (S103), and a sealing (S103). Mold: Manufactured through the following steps: S104), key processing (S105), and unnecessary lead frame cutting and removal (S106).
  • FIG. 7 is a schematic plan view of a lead frame 13 having a matrix configuration used when manufacturing the QFN type semiconductor device 1 according to the first embodiment.
  • unit read frame patterns 14 are arranged in 20 rows in the X direction and 4 columns in the Y direction, and one read frame 13 to 80 Semiconductor devices 1 can be manufactured.
  • Lee dofre Guide holes 15 a to 15 c used for transporting and positioning the lead frame 13 are provided on both sides of the frame 13.
  • an ejector pin hole 16 through which an ejector pin can be inserted is provided to separate the runner cured resin from the lead frame 13 by protruding the ejector bin.
  • the gate-hardened resin that has branched from this runner and hardened at the gate portion flowing into the cavity is peeled off from the lead frame 13 by protruding the ejector bin, the ejector pin hole 1 through which the ejector pin can penetrate 7 are provided.
  • FIG. 10 is a plan view showing a part of the unit lead frame pattern 14.
  • the unit lead frame pattern 14 is a pattern to be actually manufactured. May not always match.
  • the unit lead frame pattern 14 has a rectangular frame 18, and the tab suspension leads 6 extend from the four corners of the frame 18 to support the center tab 4. It has become.
  • a plurality of leads 7 extend inward from the inside of each side of the frame 18, and the inner ends thereof are close to the outer peripheral edge of the tab 4.
  • a plating film (not shown) is provided on the main surfaces of the tab 4 and the lead 7 for chip bonding and wire bonding.
  • the lead 7 has its backside on the tip side half-etched and thinned (see Fig. 2).
  • the leads 7 and the tabs 4 have a structure in which the periphery is formed so that the width of the main surface is wider than the width of the back surface, and is formed into an inverted trapezoidal cross section so that it is difficult to fall out of the sealing body 2. May be. It can also be manufactured by etching press.
  • -Also as shown in FIG. 10, on the main surface of the tab 4, the central rectangular area becomes the semiconductor element mounting portion 4a (the area surrounded by the two-dot chain line frame).
  • the outer area is the wire connection area 4b.
  • the semiconductor chip 3 is connected to the semiconductor element mounting portion 4 a of the unit 4 of the unit lead frame pattern 14 via the adhesive 5.
  • wire bonding is performed, and the electrode terminal of the semiconductor chip 3 and the tip of the lead 7 are connected with a conductive wire 10 while the predetermined electrode terminal and the tab 4 are connected.
  • the wire connection region 4b is connected by a conductive wire 10 (S103).
  • the wire connecting the electrode terminal and the wire connection area 4b of the tab 4 is particularly called a down-bonding wire 1Oa.
  • As the wire for example, a gold wire is used.
  • a sealing body 2 made of an insulating resin is formed on the main surface of the lead frame 13 (S104).
  • the sealing body 2 covers the semiconductor chip 3, the lead 7, and the like on the main surface side of the lead frame 13.
  • a portion indicated by a two-dot chain line frame is a region where the sealing body 2 is formed.
  • a masking process is performed (S105).
  • a plating film (not shown) is formed on the back surface of the lead frame 13.
  • This solder film is used as a bonding material when the semiconductor device 1 is surface-mounted, and is, for example, a solder plating film.
  • a Pd plating may be used on the entire surface of the lead frame 13 in advance, and in particular, a Pd plating lead frame 1 may be used.
  • the plating step after the sealing can be omitted, and the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • an unnecessary lead frame portion is cut and removed (S106), and a semiconductor device 1 as shown in FIG. 1 is manufactured.
  • the thickness of the lead frame (evening 4, tab hanging lead 6, lead 7) is 0.2 mm, the thickness of chip 3 is 0.28 mm, and the thickness of semiconductor device 1 is 1.0 mm.
  • the width of the lead 7 is 0.2 mm, the length of the lead 7 is 0.5 mm, and the wire connection point (point) of the tab 4 is 1.0 mm from the end of the mounted chip 3.
  • the distance between lead and lead 7 is 0.2 mm.
  • the ground of the specific circuit portion is taken out as a ground electrode terminal, and connected to the lead via a wire. It is separated from the ground of the rest of the circuit.
  • the remaining circuit sections are connected to the common ground via wires as necessary, and are connected to leads as necessary.
  • the ground of the specific circuit portion and the ground of the other circuit portions are also insulated and separated from each other in the wiring in the semiconductor chip 3 by an interlayer insulating film or the like.
  • the crosstalk is caused by the fluctuation of the ground potential. This may cause output fluctuations and signal waveform distortions in the respective circuit sections.
  • high-frequency circuits with multiple communication circuits such as dual band and triple band
  • an induced current is generated in a communication circuit that is not operating in an operating communication circuit, and this induced current may enter the operating communication circuit as noise. Therefore, in the first embodiment, the ground electrode terminal (ground electrode terminal) of the specific circuit section is connected to an independent lead (ground lead) via a wire without being connected to the terminal.
  • crosstalk between input signal wirings may cause output fluctuations and signal waveform distortion in the respective circuit sections, especially in external signal input leads from antennas with small input signals. It is necessary to minimize the effects of crosstalk with the leads.
  • the semiconductor device 1 is a high-frequency power module for a triple band of a mobile phone.
  • L N A Because it is a triple band, three low-noise amplifiers (LNA) connected to the antenna are also arranged.
  • LNA low-noise amplifier
  • a single LNA is a specific circuit unit in a narrow sense in the present invention. That is, as shown in FIG. 5, there are two input signal wires from each LNA antenna. Then, in order to electromagnetically shield the two signal wires, the two signal leads are preferably placed between two signal leads and another signal lead, preferably on both sides of the two signal leads. Each has a ground lead.
  • each extended LNA is formed in a region of the semiconductor chip that is insulated and separated from other circuit sections.
  • the ground potential of each LNA is common.
  • FIG. 13 is a schematic cross-sectional view showing a mounting state of the semiconductor device (high-frequency power module) 1 of Embodiment 1 in a mobile phone.
  • the land 81 and the tab connected to the wiring correspond to the lead 7 and the tab 4 of the semiconductor device 1.
  • a fixed portion 82 is provided. Therefore, the semiconductor device 1 is positioned and mounted such that the leads 7 and the leads 4 of the semiconductor device 1 coincide with the land 81 and the fixed portion 82 and overlap with each other. Then, in this state, the solder plating film previously formed on the back surface of the lead 7 and the tab 4 of the semiconductor device 1 is temporarily melted (reflowed), and the lead 7 and the tab 4 are soldered with the solder 83. Connect (implement).
  • this mobile phone has a 900 MHz GSM communication system, a 800 MHz DCS 180 communication system, and a 900 MHz PCS 190 MHz communication system. 0 Signal processing of the communication system can be performed.
  • the block diagram in FIG. 12 shows the transmission system and the reception system connected to the antenna 20 via the antenna switch 21. Both the transmission system and the reception system are baseband chip chips. It is connected to 2 2.
  • the receiving system is composed of an antenna 20, an antenna switch 21, three band-pass filters 23 connected in parallel to the antenna switch 21, and the above-mentioned band-pass filter 23. Each has a low noise amplifier (LNA) 24 connected thereto, and a variable amplifier 25 connected to the three LNAs 24 and connected in parallel.
  • Each of these two variable amplifiers 25 has a mixer 26, a rover filter 27, a PGA 28, a one-pass filter 29, a PGA 30 and a one-pass filter 3, respectively.
  • 1, PGA 32, mouth-to-pass filter 33, and demodulator 34 are connected.
  • PGA 28, PGA 30, and PGA 32 are controlled by a control logic circuit section 35 for ADC / DAC & DC offset.
  • the two mixers 26 are controlled in phase by a 90-degree phase converter 40.
  • the I / Q modulator composed of the 90-degree phase converter 40 and the two mixers 26 corresponds to three LNAs in order to correspond to each band band. Each is provided, but in Figure 12 they are grouped together for simplicity.
  • the semiconductor chip 3 is provided with a synthesizer including an RF synthesizer 41 and an IF (Intermediate) synthesizer 42 as a signal processing IC.
  • the RF synthesizer 41 is connected to 11? 044 via a buffer 43, and controls the RFVC044 to output an RF local signal.
  • Two frequency dividers 37, 38 for the oral signal are connected in series to the knocker 43, and switches 48, 49 are connected to their output terminals. .
  • the RF local signal output from RFVC 04 is input to the 90-degree phase converter 40 by switching the switch 48.
  • the 90-degree phase converter 40 controls the mixer 26 by the RF signal.
  • the signal output mode of the RFVC044 When the signal output mode of the RFVC044 is in the Rx mode, it is 3780 to 3840 MHz for GSM, 3610 to 3760 MHz for DCS, and 3860 MHz for PCS. ⁇ 3980 MHz.
  • Tx mode is GSM It is 380 to 380 MHz, 380 to 3730 MHz for DCS, and 380 to 3980 MHz for PCS.
  • IF synthesizer 42 is connected to IFVC O (intermediate wave voltage controlled oscillator) 45 via frequency divider 46, and controls IFVC045 to output an IF local signal.
  • the frequency of the output signal according to IFVC045 is 640 MHz for each communication method.
  • the RF synthesizer 41 and the IF synthesizer 42 control VCXO (voltage controlled crystal oscillator) 50, output a reference signal, and send it to the baseband chip chip 22.
  • VCXO voltage controlled crystal oscillator
  • the IF signal is controlled by the synthesizer and the control logic circuit section 35 for ADCZ DAC & DC offset, and converted to baseband chip signals (I and Q signals) by the demodulator 34 and sent to the baseband chip 22.
  • the transmission system includes two mixers 61 that use the I and Q signals output from the baseband chip 22 as input signals, a 90-degree phase converter 62 that controls the phases of the two mixers 61, and An adder 63 that adds the outputs of the two mixers 61, a mixer 64 and a DPD (digital phase detector) 65 that both receive the output of the adder 63, and a mixer 64 and a DPD 65 that The output of the loop filter 66 and the output of the loop filter 66 and the two TXV COs (transmission voltage control oscillators) 67 and the outputs of the two TXV C06 7 It comprises a power module 68 and an antenna switch 21 both of which are inputs. Loop fill 6 6 is an external component.
  • a quadrature modulator is constituted by the mixers 61, 90-degree phase converter 62 and the adder 63.
  • the 90-degree phase converter 62 is connected to the frequency divider 46 via the frequency divider 47, and is controlled by the IF local signal output from the IFVC 045.
  • the outputs of the two TXVCs 067 are current sensed by the coupler 70. This detection signal is input to the mixer 72 via the amplifier 71.
  • the mixer 72 inputs the RF local signal output from the RFVC 044 via the switch 49.
  • the output signal of the mixer 72 is input to the mixer 64 and the DPD 65 together with the output signal of the adder 63.
  • the offset PLL Phase-Locked Loop
  • the frequency of the output signal from the mixer 72 is 80 MHz for each communication system.
  • the frequency of the output signal is 880 to 915 MHz.
  • the other TXVC 067 is for the DCS'PCS communication system, and the frequency of the output signal is 1710 to 1785 MHz, or 1850 to 1910 MHz.
  • the power module 68 incorporates a low-frequency power module and a high-frequency power module, and the low-frequency power module outputs a signal of 880 to 915 MHz.
  • the high-frequency power module receives a signal from the TXVC 067, which outputs a signal of 1710 to 1785 MHz or 1850 to 1910 MHz.
  • the signal is amplified and sent to antenna switch 21.
  • the logic circuit 60 is also formed monolithically in the semiconductor device 1 of the first embodiment, and sends an output signal to the paceband chip 22.
  • each circuit portion surrounded by a thick line in FIG. 12 is monolithically formed. Then, the three LNA 24 portions become the specific circuit portion 11 in the first embodiment (see FIGS. 4 and 5).
  • FIG. 4 and FIG. 5 are block plan views of the semiconductor chip 3 schematically showing part of each of these circuit portions.
  • Radio signals (radio waves) received by antenna 20 are converted into electrical signals, The signals are sequentially processed by each element of the receiving system and sent to the baseband chip 22.
  • the electric signal output from the baseband chip 22 is sequentially processed by each element of the transmission system and radiated from the antenna 20 as a radio wave.
  • FIG. 4 is a schematic layout diagram showing an arrangement of each circuit unit in the semiconductor chip 3.
  • electrode terminals (pads) 9 are arranged along the sides. Each circuit portion is arranged inside the electrode terminal 9 with a region divided.
  • a control logic circuit section 35 for ADC / DAC & DC offset is arranged in the center of the semiconductor chip 3, and mixers 26, 64 and three LNAs 24 are located on the left side thereof.
  • RFVC 044 is located on the upper side
  • RF synthesizers 41, VCX 050, IF synthesizer 42, IFV C045 are arranged on the right side from top to bottom
  • TXVC 06 7 is located on the lower side .
  • FIG. 5 shows the relationship between each circuit section (the first circuit section and the second circuit section) and its electrode terminal 9, and the connection state of the electrode terminal 9 and the lead 7 with the wire 10.
  • Wire 10 shows wire 10 connecting electrode terminal 9 and lead 7, and down-bonding wire 10a connecting electrode terminal 9 and tab 4.
  • Specific circuit section 1 1 first circuit Focusing on the three LNAs 24, the lead 7 to be connected to the bandpass filter 23, which is an external component, that is, the lead 7 described on the left with Signal, and the LNA 24 Signal electrode terminal 9 is connected via wire 10.
  • Two signal wirings from the electrode terminal 9 to the lead 7 via the wire 10 are provided, and on both sides of the two signal wirings, the ground electrode terminal 9 of the LNA 24, which is the specific circuit section 11, is provided.
  • a ground wire is formed by connecting to a ground lead 7 (GND and a lead 7 described on the left side in the figure) via a wire 10.
  • the other circuit section, at least the ground of each VC ⁇ and the ground of LNA 24 are insulated and separated, and the lead of other adjacent circuit section and LN 24 are separated. Electromagnetic shield between the leads of A24 is provided by ground lead 7. Adjacent LNAs 24 are also electromagnetically shielded by ground leads 7.
  • each circuit part of the transmission system that processes the electric signal output from the base chip chip 22 (for example, offset PLL, TXVC 0 67)), since the electrical signal is larger than the weak signal, it has a characteristic that it is more resistant to fluctuations in the ground potential and noise due to crosstalk. Therefore, the supply of the ground potential to the circuit section of the transmission system is made common to each VC ⁇ and the like via the tab 4, so that the number of leads 7 can be reduced. The size of the device can be reduced.
  • the LNA is a circuit that handles signals amplified by the LNA, such as a PGA, or a transmission circuit, for example, in order to prevent signal deterioration due to crosstalk between wirings formed on the main surface of the semiconductor chip 3. It is preferable to dispose it closer to the electrode terminal 9 so that the length of the wiring is shorter than that of the above.
  • the electrode terminal 9 of the semiconductor element (semiconductor chip) 3 is connected not only to the lead 7 via the wire 10 but also to the chip 4 ( Down-bonding).
  • the tab 4 becomes a common ground, so that the ground electrode terminal (electrode terminal of the semiconductor element) of the low-noise amplifier 24 which is the specific circuit section 11 is connected to the tab 4. Not connected, but connected to an independent lead terminal (ground lead).
  • the low-noise amplifier 24 Since the low-noise amplifier 24 amplifies a weak signal, the fluctuation of the ground potential causes the fluctuation of the output of the low-noise amplifier 24 and the signal waveform is distorted, but the ground of the low-noise amplifier 24 Circuit section of Since this is separated from the ground, fluctuations in the output of the low noise amplifier 24 and distortion in the signal waveform can be suppressed. As a result, by incorporating the wireless communication device into a wireless communication device, it is possible to perform a favorable call without output fluctuation or distortion.
  • the signal wiring from the electrode terminal 9 of the low-noise amplifier 24 to the lead 7 via the wire 10 is grounded on both sides thereof and is electromagnetically shielded. Therefore, the signal wiring is less susceptible to crosstalk.
  • the wireless communication device incorporating the high-frequency power module 1 can operate stably.
  • the high-frequency power module 1 is a non-lead type semiconductor device in which the lug 4 and the lead 7 are exposed on the back surface of the sealing body 2, the high-frequency power module 1 can be reduced in size and thickness. And lighter weight. Therefore, the wireless communication device incorporating the high-frequency power module 1 can be reduced in size and weight.
  • the high frequency power module 1 is connected to the electrode terminals 9 of the semiconductor chip 3. Down bonding where lead (pin) 7 is connected with wire 10 and tab 4 which is the ground potential and electrode terminal (ground electrode terminal) 9 of semiconductor chip 3 are connected with down bonding wire 10a. Because of this structure, the number of ground leads that become the external electrode terminals 7 can be reduced, the size of the sealing body 2 can be reduced by reducing the number of pins, and the size of the high-frequency power module 1 can be reduced. Can be achieved.
  • FIG. 14 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 2) of the present invention, in which a sealing body is partially cut away.
  • the RFVC044 that handles high frequencies is also a specific circuit unit 1 1 Therefore, all the ground electrode terminals 9 of the RFVC 04 4 are connected to the lead (ground lead) 7 via the wire 10, and are not connected to the tab 4 via the wire.
  • LNAs low-noise amplifiers
  • ground wiring is arranged on both sides of the two signal wirings of the RFVC044, and the signal wiring is shielded electromagnetically. I have.
  • the ground potential of the specific circuit unit 11 handling the high-frequency signal is insulated and separated from the ground potentials of the other circuit units, so that crosstalk does not occur.
  • FIG. 15 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 3) of the present invention, in which a sealing body is partially cut away.
  • the third embodiment is an example in which the RFVC044 is an external component and is not formed monolithically on the semiconductor chip 3.
  • This dual-band communication method In the formula, the low noise amplifier, mixer, VCO, synthesizer, IQ modulator / demodulator, frequency divider, quadrature modulator, and other circuit sections are monolithically formed.
  • Each of the two mixers in the receiving system is controlled by a frequency divider, and this frequency divider converts the high-frequency signal output from the external component RFVC0 into a lower-frequency signal. It is a frequency conversion circuit.
  • the RFVC044 exists outside the semiconductor device 1, and the signal wiring of the RFVC044 is connected to the lead 7 of the two semiconductor devices 1. Is done. Then, the electrode terminals 9 on both sides of the two signal wires from the two leads 7 connected to the RFVC 0 4 to the electrode terminals 9 of the semiconductor chip 3 via the wires 10 and the leads 7 are connected to the wires 1 Connected via 0.
  • the electrode terminals 9 on both sides of the two signal wirings are ground electrode terminals, and the leads 7 connected to the ground electrode terminals via the wires 10 are also ground leads.
  • the signal wiring for handling the high-frequency signal is electromagnetically shielded, and the ground potential is independent of other circuit portions in the semiconductor chip 3. I have.
  • FIGS. 16 and 1 ⁇ relate to a high-frequency power module according to another embodiment (Embodiment 4) of the present invention.
  • FIG. 16 shows a part of a sealed body of the high-frequency power module.
  • FIG. 17 is a schematic cross-sectional view of the high-frequency power module.
  • a tab 4 serving as a common ground terminal and a lead 7 serving as a ground potential are electrically connected by a conductive wire 10b.
  • a conductive wire 10b are also used as ground external electrode terminals.
  • the tab 4 since the back surface of the tab 4 is exposed from the back surface (mounting surface) of the sealing body 2, the tab 4 can be used as an external electrode terminal for ground, and the wire 4 is connected to the tab 4.
  • the lead 7 connected via Ob can also be used as the ground external electrode terminal.
  • FIG. 18 shows a modification of the fourth embodiment. That is, in this modification, the back surface of the tab 4 is half-etched to be thin, so that the resin also wraps around the back surface of the tab 4 during the single-sided molding, as shown in FIG.
  • the backing 4 is completely buried in the sealing body 2 without its back surface also being exposed from the sealing body.
  • the lead 7 can be used as a ground external electrode terminal.
  • a structure in which the tab is embedded in the sealing body a structure in which the tab is bent one step higher in the middle of the tab suspension lead may be used.
  • the connection to the tab via the wire 10b is made.
  • the semiconductor device 1 in the present embodiment is mounted on the wiring board, the area under the semiconductor device 1 is also used for arranging the wiring on the wiring board because the semiconductor device 1 in this embodiment is covered with the sealing body 2. There is an advantage that it can be used as an area. Therefore, in the present embodiment, there is an advantage that the mounting density on the wiring board can be improved along with the miniaturization of the semiconductor device 1.
  • the present invention focuses on a power supply potential (first potential) suitable for applying the invention, for example, a power supply potential that can reduce the number of leads 7 by using a common electrode.
  • the present invention may be applied to the configuration of the electrode terminal 9 or the lead 7 for supplying the power supply potential.
  • the present invention is not limited to a non-lead type semiconductor device.
  • a QFP Quad Flat Package
  • SOP Silicon-Input Packet
  • a lead bent into a gull-wing shape protrudes along the periphery of the sealing body 2.
  • the same can be applied to a semiconductor device called (Small Outline Package) .However, compared to the QFP or SOP, a QFN type structure with a smaller lead protrusion around the encapsulation 2 is adopted. It is more preferable to achieve miniaturization of the equipment.
  • the semiconductor device of the present invention is used for a wireless communication device such as a mobile phone.
  • a wireless communication device such as a mobile phone.
  • the ground electrode terminal of the circuit section that processes an extremely weak input signal such as a low-noise amplifier is not connected to the common ground potential.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Amplifiers (AREA)

Abstract

A high frequency power module (semiconductor device) to be built in a cellular telephone and having a built-in high frequency analog signal processing IC including a low noise amplifier for amplifying a weak signal. The semiconductor device includes a capsule made from an insulating resin, a plurality of leads provided to extend inside and outside the capsule, a tub provided in the capsule and having a semiconductor element fixed region and a wire connection region on its main surface, a semiconductor element fixed to the semiconductor element fixed region and having an electrode terminal on an exposed main surface, a conductive wire connecting the electrode terminal of the semiconductor element to the lead, and a conductive wire connecting the electrode terminal of the semiconductor element to the wire connection region of the tab. A circuit monolithically formed on the semiconductor element consists of a plurality of circuit blocks and in a particular circuit block (low noise amplifier), all the ground electrode terminals among the electrode terminals of the semiconductor element are connected to the lead via the wire without being connected to the tab via the wire.

Description

明 細 書 半導体装置及び電子装置 技術分野  Description Semiconductor device and electronic device Technical field
本発明は半導体装置及び電子装置に係わり、 例えば、 微弱な信号を増 幅する低雑音増幅器 （ L N A ： Low Noise Amplifier) を含む高周波部ァ ナ口グ信号処理 I Cを組み込んだ高周波パワーモジュール（半導体装置） 及び無線通信装置 （電子装置） に適用して有効な技術に関する。 背景技術  The present invention relates to a semiconductor device and an electronic device. For example, the present invention relates to a high-frequency power module (semiconductor device) incorporating a high-frequency unit analog signal processing IC including a low noise amplifier (LNA) for amplifying a weak signal. ) And wireless communication devices (electronic devices). Background art
携帯電話機等の移動体通信機 （移動端末） は、 複数の通信システムに 対応できるような構成になっている。 即ち、 携帯電話機の送受信機 （フ ロン トエン ド） には複数の通信システムの送受信を行うように、 複数の 回路系が組み込まれている。 例えば、 通信方式 （システム） の異なる携 帯電話 （例えばセルラー電話機） 間での通話を可能とする方式としてデ ユアルバン ド通信方式が知られている。デュアルバン ド方式については、 例えば、 搬送周波数帯が 8 8 0〜 9 1 5 MH zのG S M (Global System for Mobile Communications) と、 搬送周波数帯が 1 7 1 0〜 1 7 8 5 M H zの D C S— 1800 (Digital Cellular System 1800) によるデュアル バン ド方式およびデュアルバン ド用高周波電力増幅器について知られて いる。  Mobile communication devices (mobile terminals) such as mobile phones are configured to be compatible with multiple communication systems. That is, a plurality of circuit systems are incorporated in a transceiver (front end) of a mobile phone so as to transmit and receive a plurality of communication systems. For example, a dual-band communication method is known as a method that enables communication between mobile phones (for example, cellular telephones) using different communication methods (systems). For the dual-band system, for example, GSM (Global System for Mobile Communications) with a carrier frequency band of 880 to 915 MHz and DCS with a carrier frequency band of 170 to 1785 MHz — It is known about the dual-band system using the 1800 (Digital Cellular System 1800) and the high-frequency power amplifier for the dual band.
また、特開平 1 1 — 1 8 6 9 2 1号（ 1 9 9 9年 7月 9 曰公開）には、 P C N ( Personal Communications Network： D C S - 1800) , P C S (Personal Communications Service： D C S - 1900) および G S Mなど の携帯電話システムに利用できる多バン ド移動体通信装置が開示されて いる。 In addition, Japanese Patent Application Laid-Open No. 11-186692 (published July 9, 1999) discloses PCN (Personal Communications Network: DCS-1800), PCS (Personal Communications Service: DCS-1900) And multi-band mobile communication devices that can be used for mobile phone systems such as GSM I have.
また、 携帯電話機のフロン トエン ドでは、 G S M用の高周波部アナ口 グ信号処理回路のモジュール化が図られている。 例えば、 MO S F E T ( Metal Oxide Semiconductor Field-Effect-Transistor) によるデュア ルノ ン ドまたは ト リプルバン ドの G S M用 R F (Radio Frequency) ノ、。ヮ 一モジュールが有る。  At the front end of mobile phones, high-frequency analog signal processing circuits for GSM have been modularized. For example, RF (Radio Frequency) for GSM in dual or triple band with Metal Oxide Semiconductor Field-Effect-Transistor (MOS FET).ヮ There is one module.
デュアルバン ド方式は G S M及び D C S 1 8 0 0方式等の二つの通信 系の信号を処理するものであり、 ト リ プルバン ド方式は G S M及び D C S (Digital Cellular System) 1 8 0 0並びに P C S 1 9 0 0方式等の 三つの通信系の信号を処理するものである。 G S Mとしては、 G S M 9 0 0あるいは G S M 8 5 0が組み込まれる。  The dual-band system processes signals of two communication systems, such as GSM and DCS 180, and the triple-band system uses GSM and DCS (Digital Cellular System) 180, and PCS 190. It processes signals of three communication systems such as the 00 system. As GSM, GSM900 or GSM850 is incorporated.
ま た、 高周波パ ワーモジ ュ ールは、 L N A ， ミ キサ ， P L L (Phase-Locked Loop) シンセサイザ， オー トキャ リ ブレーション付 P G A (Programmable Gain Amplifier), I Q変調器/復調器， オフセ ヅ ト P L L , V C 0 (Voltage-Controlled Oscillator) 等をモノ リシックに 集積したワンチップの半導体素子が組み込まれている。  The high-frequency power module includes an LNA, mixer, PLL (Phase-Locked Loop) synthesizer, PGA (Programmable Gain Amplifier) with auto-calibration, IQ modulator / demodulator, offset PLL, It incorporates a one-chip semiconductor device that monolithically integrates VC0 (Voltage-Controlled Oscillator) and the like.
一方、 携帯電話機は、 その持ち運びが便利なように小型 · 軽量化が要 請されている。 この結果、 高周波パワーモジュール等の電子部品もよ り 小型 · 軽量化が望まれている。  On the other hand, mobile phones are required to be small and light so that they can be easily carried. As a result, electronic components such as high-frequency power modules are also desired to be smaller and lighter.
半導体装置は、 そのパヅケージの形態によって種々のものがあるが、 その一つと して、 絶縁性樹脂の封止体 （パッケージ） の裏面 （実装面） にリー ド （外部電極端子） を露出させ、 封止体の側面に長く リー ドを突 出させないノ ンリー ド型半導体装置が知られている。  There are various types of semiconductor devices depending on the form of the package. One of them is that a lead (external electrode terminal) is exposed on a back surface (mounting surface) of a sealing body (package) of an insulating resin. There has been known a non-lead type semiconductor device which does not protrude a long lead on a side surface of a sealing body.
ノ ンリー ド型半導体装置と しては、 封止体の裏面の対面する 2辺に沿 つて リー ドを露出させる S 0 N (Small Outline Non-Leaded Package) や、 封止体の裏面の 4辺側に リ ー ドを露出させる Q F N ( Quad Flat Non-Leaded Package ) がある。 小型で リー ド曲がりが発生しないノ ンリ 一ド型半導体装置については、 例えば特開 2 0 0 1 — 3 1 3 3 6 3号公 報に記載されている。 As a non-lead type semiconductor device, S 0 N (Small Outline Non-Leaded Package) that exposes leads along two opposite sides of the back surface of the sealing body, and four sides of the back surface of the sealing body QFN (Quad Flat Non-Leaded Package). A small, non-leaded semiconductor device that does not cause lead bending is described in, for example, Japanese Patent Application Laid-Open No. 2001-313336.
この文献に記載されている樹脂封止型半導体装置は、 半導体チップを 固定するダイパッ ドとワイヤを接続するワイヤボンディ ング部とを有す るアイラン ドがあり、 ダイパッ ド上に半導体チップが固定され、 半導体 チップの各電極端子は、 リー ドやアイ ラン ドのワイヤボンディ ング部に 接続される構造になっている。 ダイパッ ドとワイヤボンディ ング部との 間に空隙部を設けて熱ス ト レスによるボンディ ングされたワイヤの外れ や切断を防止している。 このような構造では、 半導体チップのアース端 子とアイラン ドをワイヤで接続することによって、 アイラン ドをアース リー ドとしてプリ ン ト基板などに接続できる。  The resin-encapsulated semiconductor device described in this document has an island having a die pad for fixing a semiconductor chip and a wire bonding portion for connecting wires, and the semiconductor chip is fixed on the die pad. Each of the electrode terminals of the semiconductor chip is connected to a wire bonding part of a lead or an island. An air gap is provided between the die pad and the wire bonding part to prevent the bonded wire from coming off or cutting due to heat stress. In such a structure, by connecting the ground terminal of the semiconductor chip and the island with a wire, the island can be connected to a printed board or the like as a ground lead.
また、 特開平 1 1 — 2 5 1 4 9 4号公報には、 半導体素子搭載部をグ ラン ドとする携帯電話機などに用いられる リー ド構造がガルウイ ング型 となる高周波デバイスについて記載されている。 この技術では、 半導体 素子の電極と リー ドをワイヤで接続する以外に、 ダイパッ ドをグラン ド 電極として利用するため、 半導体素子の電極と半導体素子搭載部とをヮ ィャで接続している （ダウンボンディ ング）。 ダウンボンディ ングするた め、 半導体素子搭載部は半導体素子よ り も大き く、 また実装状態では、 半導体素子の外側に半導体素子搭載部の周縁部分が突出し、 この部分に ワイャが接続される構造になっている。  Also, Japanese Patent Application Laid-Open No. H11-251514 describes a high-frequency device in which a lead structure used in a mobile phone or the like having a semiconductor element mounting portion as a ground is a gull-wing type. . In this technology, in addition to connecting the lead and the electrode of the semiconductor element with a wire, the electrode of the semiconductor element and the semiconductor element mounting portion are connected with a wire in order to use the die pad as a ground electrode ( Down bonding). Due to down bonding, the semiconductor element mounting part is larger than the semiconductor element, and in the mounted state, the periphery of the semiconductor element mounting part protrudes outside the semiconductor element, and a wire is connected to this part. Has become.
他方、 本出願人においては、 高周波パワーモジュールをノ ンリー ド型 半導体装置に組み込み、 かつグラン ド電位の安定化のために、 高周波パ ヮ一モジユールを構成する各回路部のグラン ド端子をワイヤを介して夕 ブに電気的に接続する手法の採用を検討した。 ダウンボンディ ングを採 用することによ り、 外部電極端子の数を少なくでき、 パッケージの小型 化が図れ、 最終的には半導体装置の小型化が図れる。 On the other hand, in the present applicant, a high-frequency power module is incorporated in a non-lead type semiconductor device, and a ground terminal of each circuit part constituting a high-frequency power module is connected to a wire in order to stabilize a ground potential. Considering the use of a method of electrical connection to the evening via the Internet. By using down bonding, the number of external electrode terminals can be reduced and the package The size of the semiconductor device can be reduced eventually.
しかし、 無線通信系 （通信システム） を用途とする高周波パワーモジ ユールでは、 以下のような問題が発生することが判明した。  However, it has been found that the following problems occur in high-frequency power modules used for wireless communication systems (communication systems).
携帯電話機の受信系では、アンテナで捕らえた信号は低雑音増幅器（ L N A ) で増幅されるが、 入力信号は極めて微弱である。 このため、 各回 路部、 特に周期的に動作する発振器の動作に応じて共通端子である夕ブ の電位、 即ちグラン ド電位が変動し、 これに起因して一部の回路部との 間でクロス トークが発生し出力が変動して良好な通話ができなくなる。 特に、 リー ド間クロス トークによる誘起電流、 またはグラン ド電位の 変動による信号波形の歪みが通信システムから出力され、 この出力信号 が使用中の通信システムに入ってしまい雑音となる。  In the receiving system of a mobile phone, the signal captured by the antenna is amplified by a low noise amplifier (LNA), but the input signal is extremely weak. For this reason, the potential of the common terminal, that is, the ground potential fluctuates in accordance with the operation of each circuit section, especially the oscillator that operates periodically, and as a result, there is a possibility that the circuit section and the circuit section may be partially connected. Crosstalk occurs and the output fluctuates, preventing good calls. In particular, signal waveform distortion due to induced current due to inter-lead crosstalk or fluctuation in ground potential is output from the communication system, and this output signal enters the communication system in use and becomes noise.
このようなグラン ド電位の変動、 およびクロス トークの影響を受けや すい回路部は、 低雑音増幅器 （ L N A ) 以外では、 高周波を扱う R F V C O (高周波電圧制御発振器） 等がある。  Circuits that are susceptible to such fluctuations in ground potential and crosstalk include RF VCOs (high-frequency voltage controlled oscillators) that handle high frequencies in addition to low noise amplifiers (LNA).
そこで、 本発明者は、 低雑音増幅器や R F V C 0では、 半導体素子の 電極端子のうちグラン ド端子は共通端子となるタブにワイヤを介して接 続することなく、 独立したリー ド端子 （外部電極端子） にワイヤを介し て接続させ、 他の回路部のオン ' オフ時等のグラン ド電位の変動の影響 を少なく させることを思い立ち本発明をなした。  In view of this, the present inventor has proposed that in a low-noise amplifier or RFVC0, among the electrode terminals of a semiconductor element, the ground terminal is not connected to a tab serving as a common terminal via a wire, but is connected to an independent lead terminal (external electrode). The present invention has been made with the idea that the influence of the fluctuation of the ground potential at the time of turning on and off other circuit parts is reduced by connecting the terminal to the terminal via a wire.
本発明の目的は、 ダウンボンディ ング構造の半導体装置において、 半 導体素子に形成された回路のうち、 特定の回路部におけるグラ ン ド電位 が残りの回路部のグラ ン ド電位の影響を受け難くできる半導体装置を提 供することにある。  An object of the present invention is to provide a down-bonded semiconductor device in which a ground potential in a specific circuit portion of a circuit formed in a semiconductor element is hardly affected by a ground potential in the remaining circuit portion. It is to provide a semiconductor device that can be used.
本発明の他の目的は、 高周波パワーモジュールにおいて低雑音増幅器 や R F V C 0等の回路部が、 他の回路部のグラン ド電位の変動によるク ロス トークの影響を受け難い高周波パワーモジュールを提供することに ある。 Another object of the present invention is to provide a high-frequency power module in which a circuit section such as a low-noise amplifier or RFVC0 is less likely to be affected by crosstalk due to fluctuations in the ground potential of other circuit sections in the high-frequency power module. To is there.
本発明の他の目的は、 無線通信システムにおいて雑音の少ない良好な 通話が可能となる無線通信装置を提供することにある。  Another object of the present invention is to provide a wireless communication device capable of making a good call with less noise in a wireless communication system.
本発明の他の目的は、 複数の通信システムを有する無線通信システム において、 雑音の少ない良好な通話が可能となる無線通信装置を提供す ることにある。  Another object of the present invention is to provide a wireless communication device capable of performing a good call with less noise in a wireless communication system having a plurality of communication systems.
本発明の前記ならびにそのほかの目的と新規な特徴は、 本明細書の記 述および添付図面からあきらかになるであろう。 発明の開示  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention
本願において開示される発明のうち代表的なものの概要を簡単に説明 すれば、 下記のとおりである。  The outline of typical inventions disclosed in the present application is briefly described as follows.
( 1 ) 本発明の半導体装置は、  (1) The semiconductor device of the present invention
絶縁性樹脂からなる封止体と、  A sealing body made of an insulating resin;
前記封止体の周囲に沿って、 前記封止体の内外に亘つて設けられる複数 のリー ドと、 A plurality of leads provided along the periphery of the sealing body and inside and outside the sealing body;
主面および裏面を有するタブと、  A tab having a main surface and a back surface;
主面および裏面を有しており、 その主面上に複数の電極端子と、 それ それが複数の半導体素子によって構成される複数の回路部とを有する半 導体チップと、  A semiconductor chip having a main surface and a back surface, a plurality of electrode terminals on the main surface, and a plurality of circuit portions each including a plurality of semiconductor elements;
前記複数の電極端子と前記リ一ドとを接続する複数の導電性のワイヤ と、  A plurality of conductive wires connecting the plurality of electrode terminals and the lead;
前記複数の電極端子に第 1の電位を供給するために、 前記複数の電極 端子と前記タブの主面とを接続する複数の導電性のワイヤとを有する半 導体装置 （例えば、 ノ ン リー ド型半導体装置） であって、  In order to supply a first potential to the plurality of electrode terminals, a semiconductor device including a plurality of conductive wires connecting the plurality of electrode terminals and the main surface of the tab (for example, a non-leaded device) Semiconductor device)
前記半導体チップの裏面は前記タブの主面上に固定されており、 前記複数の回路部は、 第 1の回路部 （特定回路部）、 第 2の回路部を含ん でおり、 The back surface of the semiconductor chip is fixed on the main surface of the tab, The plurality of circuit units include a first circuit unit (specific circuit unit) and a second circuit unit,
前記複数の電極端子は、 前記第 1の回路部に外部信号を入力するため の第 1の電極端子と、 前記第 1の回路部に前記第 1の電位 （グラン ド電 位） を供給するための第 2の電極端子と、 前記第 2の回路部と接続する 第 3の電極端子と、 前記第 2の回路部に前記第 1の電位を供給するため の第 4の電極端子とを有しており、  The plurality of electrode terminals are a first electrode terminal for inputting an external signal to the first circuit unit, and a first potential (ground potential) for supplying the first circuit unit with the first potential. A second electrode terminal, a third electrode terminal connected to the second circuit portion, and a fourth electrode terminal for supplying the first potential to the second circuit portion. And
前記複数のリードは、 第 1のリード （信号用リード） と、 第 2のリ一 ド （信号用リード） と、 前記第 1のリードと第 2のリー ドの間に配置さ れた第 3のリード （グラン ド用リード） とを含んでおり、  The plurality of leads include a first lead (a signal lead), a second lead (a signal lead), and a third lead disposed between the first lead and the second lead. Lead (ground lead)
前記第 1の電極端子は導電性のワイャを介して前記第 1のリードと接 続しており、  The first electrode terminal is connected to the first lead via a conductive wire,
前記第 2の電極端子は導電性のワイャを介して前記第 3のリードと接 続しており、  The second electrode terminal is connected to the third lead via a conductive wire,
前記第 3の電極端子は導電性のワイャを介して前記第 2のリードと接 続しており、  The third electrode terminal is connected to the second lead via a conductive wire,
前記第 4の電極端子は導電性のワイャを介して共通グラン ドとなる前 記夕ブと接続しており、  The fourth electrode terminal is connected to a common ground via a conductive wire, as described above.
前記第 3のリードと前記タブは電気的に分離されていることを特徴と し、  The third lead and the tab are electrically separated from each other,
高周波モジュールを構成している。 This constitutes a high-frequency module.
前記第 1の回路部は前記第 1のリー ド、 および前記第 1の電極端子を 介して入力される外部信号を増幅するための増幅回路 （低雑音増幅器 ： L A N ) であり、 無線信号がアンテナを介して変換された電気信号を増 幅するための回路である。  The first circuit unit is an amplifier circuit (low-noise amplifier: LAN) for amplifying an external signal input through the first lead and the first electrode terminal. This is a circuit for amplifying the electric signal converted through the circuit.
前記第 2の回路部は、 前記第 1の回路部によって増幅された信号を処 理する機能の少なく とも一部を有する。 The second circuit unit processes the signal amplified by the first circuit unit. It has at least some of the functions to manage.
また、 高周波パワーモジュールには複数の通信方式に対応できるよう に複数の通信回路が形成されている。 このような高周波パワーモジユ ー ルは無線通信装置に組み込まれている。  In addition, a plurality of communication circuits are formed in the high-frequency power module so as to be compatible with a plurality of communication systems. Such a high-frequency power module is incorporated in a wireless communication device.
前記 （ 1 ) の手段によれば、 （ a ) 半導体素子の電極端子はワイヤを介 して リードに接続される以外に共通グラン ドとなるタブにも接続 （ダウ ンボンディ ング） される。 微弱な信号を増幅する低雑音増幅器 （特定回 路部） のグラン ド電極端子 （半導体素子の電極端子） は、 タブには接続 されず、 独立したリード端子 （グラン ド用リー ド） に接続されるため、 他の回路部との間でグラン ド電位が独立することになり、 他の回路部の 電源のオン · オフ時にもグラン ド電位変動が起き難く なり、 グラン ド電 位の変動に伴う低雑音増幅器の出力変動や信号波形の歪みも発生し難く なり、 無線通信装置に組み込めば、 出力変動や歪みのない良好な通話が 可能になる。  According to the means (1), (a) the electrode terminal of the semiconductor element is connected (down-bonded) to a tab serving as a common ground in addition to being connected to a lead via a wire. The ground electrode terminal (electrode terminal of the semiconductor element) of the low-noise amplifier (specific circuit part) that amplifies a weak signal is not connected to the tab, but is connected to an independent lead terminal (lead for ground). As a result, the ground potential is independent from other circuit sections, and the ground potential does not easily fluctuate even when the power of the other circuit section is turned on and off. Output fluctuations of the low-noise amplifier and distortion of the signal waveform are less likely to occur, and if incorporated in a wireless communication device, a good call without output fluctuations and distortion becomes possible.
( b ) 複数の通信回路を有する高周波パワーモジュールにおいては、 タブを利用する共通グラン ドの場合、 グラン ド電位の変動に伴い使用し ていない通信回路に誘起電流が発生し、 この誘起電流に起因する雑音が 使用中 （動作中） の通信回路に入り込む、 いわゆるクロス トークが発生 するが、 本発明の高周波パワーモジュールでは、 各通信回路の低雑音増 幅器は他の回路部のグラン ドと分離されていることから、 低雑音増幅器 の出力の変動や信号波形の歪みを抑制できる。 この結果、 複数の通信回 路を有する無線通信装置においても出力変動や歪みのない良好な通話が 可能になる。  (b) In a high-frequency power module with multiple communication circuits, in the case of a common ground that uses tabs, induced currents are generated in unused communication circuits due to fluctuations in the ground potential. In the high-frequency power module of the present invention, the low-noise amplifier of each communication circuit is separated from the ground of the other circuit sections, although the generated noise enters the communication circuit in use (during operation). Therefore, fluctuations in the output of the low-noise amplifier and distortion of the signal waveform can be suppressed. As a result, even in a wireless communication device having a plurality of communication circuits, it is possible to perform a good call without output fluctuation or distortion.
( c ) 低雑音増幅器の電極端子からワイヤを介して リー ドに至る信号 配線はその両側にグラン ド配線が配置されて電磁シール ドされているこ とから、 信号配線間のクロス トークを低減する事ができる。 ( d ) 高周波パワーモジュールはダウンボンディ ング構造のノ ンリ一 ド型の半導体装置であり、 小型 · 薄型 · 軽量化が図れるとともに、 タブ が封止体の裏面に露出していることから、 放熱性が良好であり、 安定動 作が可能になる。 従って、 この高周波パワーモジュールの組み込みによ つて通話性能が良好な小型 '軽量の携帯電話機を提供することができる。 図面の簡単な説明 (c) Since the signal wiring from the electrode terminals of the low-noise amplifier to the leads via the wires is grounded on both sides and grounded electromagnetically, crosstalk between the signal wiring is reduced. Can do things. (d) The high-frequency power module is a bonded semiconductor device with a down-bonded structure that can be small, thin, and lightweight, and has a heat dissipation property because the tab is exposed on the back surface of the sealing body. Is good, and stable operation is possible. Therefore, by incorporating this high-frequency power module, it is possible to provide a small-sized and light-weight mobile phone having good call performance. BRIEF DESCRIPTION OF THE FIGURES
図 1は本発明の一実施形態 （実施形態 1 ) である高周波パワーモジュ —ルの封止体の一部を切り欠いた模式的平面図である。  FIG. 1 is a schematic plan view in which a part of a sealed body of a high-frequency power module according to an embodiment (Embodiment 1) of the present invention is partially cut away.
図 2は本実施形態 1の高周波パワーモジュールの断面図である。  FIG. 2 is a cross-sectional view of the high-frequency power module according to the first embodiment.
図 3は本実施形態 1の高周波パワーモジュールの模式的平面図である, 図 4は本実施形態 1の高周波パワーモジュールに組み込まれる半導体 チップにおける回路構成をプロック的に示す模式的平面図である。  FIG. 3 is a schematic plan view of the high-frequency power module according to the first embodiment. FIG. 4 is a schematic plan view schematically illustrating a circuit configuration of a semiconductor chip incorporated in the high-frequency power module according to the first embodiment.
図 5は本実施形態 1の高周波パワーモジュールにおける外部電極端子 と半導体チップの低雑音増幅器やシンセサイザ等の各回路部との結線状 態を示す模式的平面図である。  FIG. 5 is a schematic plan view showing a connection state between external electrode terminals and respective circuit units such as a low-noise amplifier and a synthesizer of a semiconductor chip in the high-frequency power module of the first embodiment.
図 6は本実施形態 1の高周波パワーモジュールの製造方法を示すフロ 一チヤ一トである。  FIG. 6 is a flowchart showing a method of manufacturing the high-frequency power module according to the first embodiment.
図 7は本実施形態 1の高周波パワーモジュールの製造において使用す る リー ドフレームの平面図である。  FIG. 7 is a plan view of a lead frame used in manufacturing the high-frequency power module of the first embodiment.
図 8は前記リー ドフレームにおける単位リー ドフレームパターンを示 す模式的平面図である。  FIG. 8 is a schematic plan view showing a unit lead frame pattern in the lead frame.
図 9は半導体チップを搭載した前記リー ドフレームを示す模式的断面 図である。  FIG. 9 is a schematic sectional view showing the lead frame on which a semiconductor chip is mounted.
図 1 0はワイヤボンディ ングが終了した前記リー ドフレームを示す模 式的断面図である。 図 1 1は封止体が形成された前記リー ドフ レームを示す模式的断面図 である。 FIG. 10 is a schematic sectional view showing the lead frame after wire bonding has been completed. FIG. 11 is a schematic cross-sectional view showing the lead frame on which a sealing body is formed.
図 1 2は本実施形態 1の高周波パワーモジュールが組み込まれた携帯 電話機の回路構成を示すプロ ック図である。  FIG. 12 is a block diagram showing a circuit configuration of a mobile phone in which the high-frequency power module of the first embodiment is incorporated.
図 1 3は本実施形態 1の高周波パワーモジュールの携帯電話機におけ る実装状態を示す模式的断面図である。  FIG. 13 is a schematic cross-sectional view showing a mounting state of the high-frequency power module of the first embodiment in a mobile phone.
図 1 4は本発明の他の実施形態 （実施形態 2 ) である高周波パワーモ ジュールの封止体の一部を切り欠いた模式的平面図である。  FIG. 14 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 2) of the present invention, in which a part of a sealing body is cut away.
図 1 5は本発明の他の実施形態 （実施形態 3 ) である高周波パワーモ ジュールの封止体の一部を切り欠いた模式的平面図である。  FIG. 15 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 3) of the present invention, in which a sealing body is partially cut away.
図 1 6は本発明の他の実施形態 （実施形態 4 ) である高周波パワーモ ジュールの封止体の一部を切り欠いた模式的平面図である。  FIG. 16 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 4) of the present invention, in which a part of a sealing body is cut away.
図 1 7は本実施形態 4の高周波パワーモジュールの模式的断面図であ る。  FIG. 17 is a schematic sectional view of the high-frequency power module according to the fourth embodiment.
図 1 8は本実施形態 4の高周波パワーモジュールの変形例を示す模式 的断面図である。 発明を実施するための最良の形態  FIG. 18 is a schematic cross-sectional view showing a modification of the high-frequency power module of the fourth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 図面を参照して本発明の実施の形態を詳細に説明する。 なお、 発明の実施の形態を説明するための全図において、 同一機能を有するも のは同一符号を付け、 その繰り返しの説明は省略する。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.
(実施形態 1 )  (Embodiment 1)
図 1乃至図 1 3は本発明の一実施形態 （実施形態 1 ) である半導体装 置 （高周波パワーモジュール） 及びその高周波パワーモジュールを組み 込んだ無線通信装置に係わる図である。 図 1乃至図 5は高周波パワーモ ジュールに係わる図であり、 図 6乃至図 1 1は高周波パワーモジュール の製造方法に係わる図であ り、 図 1 2及び図 1 3は無線通信装置に係わ る図である。 FIGS. 1 to 13 are diagrams related to a semiconductor device (high-frequency power module) according to an embodiment (Embodiment 1) of the present invention and a wireless communication device incorporating the high-frequency power module. 1 to 5 are diagrams relating to the high-frequency power module, and FIGS. 6 to 11 are high-frequency power modules. FIGS. 12 and 13 are diagrams relating to the wireless communication device.
本実施形態 1では、 四角形状の封止体 （パッケージ） の裏面の実装面 に、 夕ブ及びこの夕ブに連なるタブ吊 り リード並びにリ一ド （外部電極 端子） が露出する Q F N型の半導体装置に本発明を適用した例について 説明する。 半導体装置 1は、 例えば高周波パワーモジュールを構成して いる o  In the first embodiment, a QFN type semiconductor in which the tab, the tab suspension lead and the lead (external electrode terminal) connected to the tab are exposed on the mounting surface on the back surface of the rectangular sealing body (package). An example in which the present invention is applied to an apparatus will be described. The semiconductor device 1 constitutes, for example, a high-frequency power module.o
Q F N型の半導体装置 1 は、 図 1及び図 2に示すように、 偏平の四角 形状の絶縁性樹脂で形成される封止体 （パッケージ） 2 を有している。 この封止体 2の内部には四角形状の半導体素子（半導体チップ：チップ） 3が埋め込まれている。 前記半導体チップ 3は四角形状の夕プ 4の夕ブ 表面 （主面） に接着剤 5によって固定されている （図 2参照）。 図 2に示 すように、 封止体 2の裏面 （下面） は実装される面側 （実装面） となる。 封止体 2の裏面にはタブ 4及びタブ 4を支持するタブ吊り リー ド 6並 びに リー ド （外部電極端子） 7の一面 （実装面 7 a ) が露出する構造と なっている。 これらタブ 4及びタブ吊 り リー ド 6並びにリー ド 7は、 半 導体装置 1の製造において、 パターニングした一枚の金属製 （例えば、 銅製） のリー ドフレームで形成され、 その後切断されて形成される。 従って、 本実施形態 1ではこれらタブ 4及びタブ吊 り リー ド 6並びに リー ド 7の厚さは同じになっている。 しかし、 リー ド 7 においては、 内 端部分は裏面を一定の深さエッチングして薄く形成しておくので、 この 薄いリー ド部分の下側には封止体 2 を構成する樹脂が入り込む構造にな つている。 これによ り、 リード 7は封止体 2から脱落し難く なる。  As shown in FIGS. 1 and 2, the QFN type semiconductor device 1 has a sealing body (package) 2 formed of a flat rectangular insulating resin. A rectangular semiconductor element (semiconductor chip: chip) 3 is embedded in the sealing body 2. The semiconductor chip 3 is fixed to the surface (principal surface) of the square cup 4 with an adhesive 5 (see FIG. 2). As shown in FIG. 2, the back surface (lower surface) of the sealing body 2 is the mounting surface side (mounting surface). On the back surface of the sealing body 2, the tab 4 and the tab suspension lead 6 supporting the tab 4 and one surface (mounting surface 7a) of the lead (external electrode terminal) 7 are exposed. The tab 4, the tab suspension lead 6 and the lead 7 are formed by a patterned metal (for example, copper) lead frame in the manufacture of the semiconductor device 1, and then cut and formed. You. Therefore, in the first embodiment, the tabs 4, the tab suspension leads 6, and the leads 7 have the same thickness. However, in the lead 7, since the inner end portion is formed thin by etching the back surface to a certain depth, the resin constituting the sealing body 2 enters under the thin lead portion. It is. This makes it difficult for the lead 7 to fall off the sealing body 2.
タブ 4は、 その 4隅が細いタブ吊 り リー ド 6によって支持される。 こ れら夕ブ吊 り リー ド 6は四角形状の封止体 2の対角線上に位置し、 四角 形状の封止体 2の各隅部に外端を臨ませている。 封止体 2は偏平の四角 形体となり、 角部 （隅部） は面取り加工が施されて斜面 2 aとなってい る （図 1参照）。 夕ブ吊 り リード 6 の外端はこの面取り部分に 0 . 1 m m 以下と僅かに突出している。 この突出長さは、 リー ドフ レーム状態の夕 ブ吊り リードを切断するときのプレス機械の切断型によって決ま り、 例 えば、 0 . 1 m m以下が選択される。 The tab 4 is supported by a tab suspension lead 6 having four narrow corners. These evening suspension leads 6 are located on a diagonal line of the rectangular sealing body 2, and the outer end faces each corner of the rectangular sealing body 2. Seal 2 is a flat square The corners (corners) are chamfered to form slopes 2a (see Fig. 1). The outer end of the evening suspension lead 6 slightly protrudes from this chamfered portion to 0.1 mm or less. The protruding length is determined by the cutting type of the press machine used to cut the suspension lead in the lead frame state. For example, 0.1 mm or less is selected.
また、 図 1 に示すように、 タブ 4の周辺には、 内端をタブ 4に対面さ せる リー ド 7が四角形の封止体 2の各辺に沿って所定間隔で複数配置さ れている。 夕ブ吊 り リー ド 6及びリー ド 7の外端は封止体 2の周縁にま で延在している。 即ち、 リード 7及びタブ吊り リー ド 6は封止体 2の内 外に亘つて延在することになる。リー ド 7の封止体 2からの突出長さは、 前記夕ブ吊り リー ド 6 と同様にリー ドフレーム状態のリ一ドを切断する ときのプレス機械の切断型によって決ま り、 例えば、 0 . 1 m m以下と 僅かに突出する。  Further, as shown in FIG. 1, around the tab 4, a plurality of leads 7 having an inner end facing the tab 4 are arranged at predetermined intervals along each side of the rectangular sealing body 2. . The outer ends of the evening suspension leads 6 and 7 extend to the periphery of the sealing body 2. That is, the lead 7 and the tab suspension lead 6 extend inside and outside the sealing body 2. The protruding length of the lead 7 from the sealing body 2 is determined by the cutting die of the press machine when cutting the lead in the state of the lead frame as in the case of the above-mentioned hanging suspension 6, for example, 0 Projects slightly less than 1 mm.
また、 封止体 2の側面は傾斜面 2 b となっている （図 2参照）。 この傾 斜面 2 bは、 リー ドフ レームの一面に片面モール ドして封止体 2 を形勢 した後、 モール ド金型のキヤビティから封止体 2 を抜き取る際、 抜き取 り を容易にするためにキヤビティの側面を傾斜面にした結果によるもの である。 なお、 図 1は、 封止体 2の上部を切り欠いてタブ 4 , タ ブ吊 り リー ド 6 , リー ド 7， 半導体チップ 3等が見えるようにした模式図であ る。  The side surface of the sealing body 2 is an inclined surface 2b (see FIG. 2). The inclined surface 2b is formed on one surface of the lead frame to form the sealing body 2 on one side thereof, and then to facilitate removal when the sealing body 2 is removed from the mold mold cavity. This is due to the fact that the side surface of the cavity is inclined. FIG. 1 is a schematic diagram in which the upper portion of the sealing body 2 is cut out so that the tab 4, the tab suspension lead 6, the lead 7, the semiconductor chip 3, and the like can be seen.
また、 図 1及び図 4に示すように、 半導体チップ 3の露出する主面に は電極端子 9が設けられている。 電極端子 9 は、 半導体チップ 3の主面 において、 四角形の各辺に沿ってほぼ所定ピッチに設けられている。 こ の電極端子 9は導電性のヮィャ 1 0 を介して リー ド 7の内端側に接続さ れている。  Further, as shown in FIGS. 1 and 4, the exposed main surface of the semiconductor chip 3 is provided with an electrode terminal 9. The electrode terminals 9 are provided on the main surface of the semiconductor chip 3 at substantially a predetermined pitch along each side of the square. The electrode terminal 9 is connected to the inner end of the lead 7 via a conductive wire 10.
夕ブ 4は半導体チップ 3に比較して大き く形成され、 その主面の中央 に半導体素子固定領域を有するとともに、 この半導体素子固定領域の外 側、 即ちタブ 4の周縁部分にワイヤ接続領域を有している。 そして、 こ の半導体素子固定領域に半導体チップ 3が固定される。 また、 ワイヤ接 続領域には、 一端が半導体チップ 3の電極端子 9 に接続される導電性の ワイヤ 1 0の他端が接続されている。 特に、 タブ 4に接続されるワイヤ 1 0 をダウンボンディ ングワイヤ 1 0 aと呼称する。 ワイヤボンディ ン グ装置によって電極端子 9 と リー ド 7 との間のワイヤボンディ ング及び 電極端子 9 とタブ 4 との間のワイヤボンディ ングを行うことから、 ワイ ャ 1 0 もダウンボンディ ングワイヤ 1 0 aも同じ材質のものである。 The head 4 is formed larger than the semiconductor chip 3, and the center of the main surface is formed. In addition to the semiconductor element fixing region, a wire connection region is provided outside the semiconductor element fixing region, that is, on the peripheral portion of the tab 4. Then, the semiconductor chip 3 is fixed to the semiconductor element fixing region. The other end of the conductive wire 10 whose one end is connected to the electrode terminal 9 of the semiconductor chip 3 is connected to the wire connection region. In particular, the wire 10 connected to the tab 4 is called a down-bonding wire 10a. Since the wire bonding device performs wire bonding between the electrode terminal 9 and the lead 7 and wire bonding between the electrode terminal 9 and the tab 4, the wire 10 is also a down bonding wire 10a. Are also of the same material.
ダウンボンディ ング構造の採用の目的は、 一般的にはタブを利用した 半導体チップ内の各回路部のグラン ド電位の共通化である。 夕プを共通 のグラン ド端子とし、 この夕プとグラン ド電極端子となる多くの電極端 子をワイヤを介して接続することによって、 封止体の周囲に沿って並ぶ 外部電極端子である リー ド （ピン） の数を少なく し、 リード数低減によ る封止体の小型化を図ることができる。 これは半導体装置の小型化に繋 がる。  The purpose of adopting the down-bonding structure is to commonly use the tab to share the ground potential of each circuit section in the semiconductor chip. By using the spark plug as a common ground terminal and connecting the spark plug and a number of electrode terminals to be the ground electrode terminals via wires, the external electrode terminals are lined up along the periphery of the sealing body. The number of leads (pins) can be reduced, and the size of the sealing body can be reduced by reducing the number of leads. This leads to downsizing of the semiconductor device.
また、 本実施形態 1の半導体装置 1 は、 図 3に示すように、 各リー ド 7 と リード 7の間、 及びリー ド 7 とタブ吊 り リー ド 6 との間には封止体 2 を形成する際発生するレジンバリが存在している。 このレジンバリ部 分は、 半導体装置 1の製造において、 リー ドフレームの一面に片面モー ル ド して封止体 2 を形成する際発生するものである。 モール ド後、 不要 リー ドフレーム部分を切断するが、 この際のリー ドやタブ吊 り リー ドの 切断時に同時にレジンノ リ も切断されるため、 レジンバリの外縁はリー ド 7の縁や夕ブ吊り リー ド 6の縁と一緒になり、 一部のレジンバリが各 リー ド 7 と リー ド 7の間、 及びリー ド 7 とタブ吊り リード 6 との間に残 留することになる。 また、 本実施形態 1では封止体 2の裏面はタブ 4 , 夕ブ吊り リー ド 6 及びリー ド 7の裏面 （実装面） よ り も引っ込んだ構造になっている。 こ れは、 トランスファモール ドにおける片面モ一ル ドにおいて、 モール ド 金型の上下型間に樹脂製のシー トを張り、 このシー トにリー ドフ レーム の一面が接触するようにしてモール ドを行うことから、 シー トがリー ド フ レームの隙間で食い込むようになるため、 封止体 2 の裏面は引っ込む 形になる。 Further, in the semiconductor device 1 of the first embodiment, as shown in FIG. 3, the sealing body 2 is provided between each lead 7 and the lead 7 and between the lead 7 and the tab suspension lead 6. There are resin burrs generated during the formation. This resin burr portion is generated when the encapsulant 2 is formed in one side mode on one surface of the lead frame in the manufacture of the semiconductor device 1. After molding, the unnecessary lead frame is cut off, but when cutting the lead or tab hanging lead, the resin glue is also cut at the same time. Along with the edge of the lead 6, some resin burrs will remain between each lead 7 and the lead 7, and between the lead 7 and the tab suspension lead 6. Further, in the first embodiment, the back surface of the sealing body 2 has a structure that is recessed from the back surface (mounting surface) of the tab 4, the evening hanger lead 6, and the lead 7. This is because in a one-sided transfer molding mode, a resin sheet is placed between the upper and lower mold dies, and the mold is placed so that one side of the lead frame contacts this sheet. As a result, the sheet bites into the gap between the lead frames, so that the back surface of the sealing body 2 is retracted.
また、 トランスファモール ドによる片面モール ド後、 リー ドフレーム の表面に表面実装用のメ ツキ膜を形成する。 このため、 半導体装置 1の 封止体 2の裏面に露出するタブ 4， タブ吊 り リード 6及びリー ド 7の表 面は、 図示はしないがメ ツキ膜を有することになる。  After the transfer molding is performed on one side, a plating film for surface mounting is formed on the surface of the lead frame. Therefore, the surfaces of the tab 4, the tab suspension lead 6, and the lead 7 exposed on the back surface of the sealing body 2 of the semiconductor device 1 have a plating film (not shown).
このよう に リー ド 7やタブ吊り リー ド 6の裏面である実装面が突出し. 封止体 2の裏面が引っ込むオフセッ ト構造では、 実装基板等の配線基板 に半導体装置 1 を表面実装する場合、 半田の濡れ領域が特定されるため 半田実装が良好となる特長がある。  In this way, the mounting surface that is the back surface of the lead 7 and the tab suspension lead 6 protrudes. In the offset structure where the back surface of the sealing body 2 is recessed, when the semiconductor device 1 is surface-mounted on a wiring board such as a mounting board, The feature is that the solder wet area is specified and the solder mounting is good.
ここで、 本実施形態 1の半導体装置 1の製造方法について、 図 6乃至 図 1 1 を参照しながら説明する。 図 6のフローチャー ト に示すように、 半導体装置 1 は、 リー ドフ レーム準備 （ S 1 0 1 )， チップボンディ ング ( S 1 0 2 ) , ワイヤボンディ ング （ S 1 0 3 )， 封止 （モール ド ： S 1 0 4 ) , メ ヅキ処理 （ S 1 0 5 ) , 不要リー ドフ レーム切断除去 （ S 1 0 6 ) の各工程を経て製造される。  Here, a method of manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to FIGS. As shown in the flowchart of FIG. 6, the semiconductor device 1 includes a lead frame preparation (S101), a chip bonding (S102), a wire bonding (S103), and a sealing (S103). Mold: Manufactured through the following steps: S104), key processing (S105), and unnecessary lead frame cutting and removal (S106).
図 7は本実施形態 1 による Q F N型の半導体装置 1 を製造する際使用 するマ ト リクス構成のリー ドフ レーム 1 3の模式的平面図である。  FIG. 7 is a schematic plan view of a lead frame 13 having a matrix configuration used when manufacturing the QFN type semiconductor device 1 according to the first embodiment.
このリー ドフ レーム 1 3は、 単位リー ドフ レームパターン 1 4が X方 向に沿って 2 0行、 Y方向に沿って 4列配置され、 1枚のリ ー ド フ レー ム 1 3から 8 0個の半導体装置 1 を製造することができる。 リー ドフ レ ーム 1 3の両側には、 リー ドフ レーム 1 3の搬送や位置決め等に使用す るガイ ド孔 1 5 a ~ 1 5 cが設けられている。 In this lead frame 13, unit read frame patterns 14 are arranged in 20 rows in the X direction and 4 columns in the Y direction, and one read frame 13 to 80 Semiconductor devices 1 can be manufactured. Lee dofre Guide holes 15 a to 15 c used for transporting and positioning the lead frame 13 are provided on both sides of the frame 13.
また、 各列の左側には、 ト ラ ンスフ ァモール ド時、 ランナーが位置す る。 そこでランナー硬化レジンをェジェクタ一ビンの突き出しによって リー ドフ レーム 1 3から引き剥がすため、 ェジェクターピンが貫通でき るェジェクタ一ピン孔 1 6が設けられている。 また、 このランナーから 分岐し、 キヤビティ に流れるゲー ト部分で硬化したゲー ト硬化レジンを ェジヱクタ一ビンの突き出しによって リー ドフ レーム 1 3から引き剥が すため、 ェジェクタ一ピンが貫通できるェジェクタ一ピン孔 1 7が設け られている。  On the left side of each row, a runner is located during the transfer molding. Therefore, an ejector pin hole 16 through which an ejector pin can be inserted is provided to separate the runner cured resin from the lead frame 13 by protruding the ejector bin. In addition, since the gate-hardened resin that has branched from this runner and hardened at the gate portion flowing into the cavity is peeled off from the lead frame 13 by protruding the ejector bin, the ejector pin hole 1 through which the ejector pin can penetrate 7 are provided.
図 1 0は単位リー ドフ レームパターン 1 4の一部を示す平面図である , 単位リードフ レームパターン 1 4は、 実際に製造するパターンであるこ とから、模式図である図 1や図 2等とは必ずしも一致しない部分が有る。 単位リー ドフ レームパターン 1 4は矩形枠状の枠部 1 8を有している , この枠部 1 8の 4隅からタブ吊り リー ド 6が延在し、 中央のタブ 4を支 持するパターンとなっている。 枠部 1 8の各辺の内側から内方に向かつ て複数のリー ド 7が延在し、その内端はタブ 4の外周縁に近接している。 タブ 4及びリー ド 7の主面には、 チップボンディ ングゃワイヤボンディ ングのために図示しないメ ツキ膜が設けられている。  FIG. 10 is a plan view showing a part of the unit lead frame pattern 14.The unit lead frame pattern 14 is a pattern to be actually manufactured. May not always match. The unit lead frame pattern 14 has a rectangular frame 18, and the tab suspension leads 6 extend from the four corners of the frame 18 to support the center tab 4. It has become. A plurality of leads 7 extend inward from the inside of each side of the frame 18, and the inner ends thereof are close to the outer peripheral edge of the tab 4. A plating film (not shown) is provided on the main surfaces of the tab 4 and the lead 7 for chip bonding and wire bonding.
また、 リー ド 7はその先端側裏面は、 ハーフエッチングされて薄く な つている （図 2参照）。 なお、 リー ド 7やタブ 4等は、 その周縁が主面の 幅が裏面の幅よ り も広く なるような斜面と し、 逆台形断面に形成して封 止体 2から抜け難く する構造と してもよい。 これは、 エッチングゃプレ スによっても製造することができる。 - また、 図 1 0に示すように、 タブ 4の主面において、 中央の四角形領 域は半導体素子搭載部 4 a (二点鎖線枠で囲まれる領域） となり、 その 外側の領域はワイャ接続領域 4 bとなる。 Also, the lead 7 has its backside on the tip side half-etched and thinned (see Fig. 2). The leads 7 and the tabs 4 have a structure in which the periphery is formed so that the width of the main surface is wider than the width of the back surface, and is formed into an inverted trapezoidal cross section so that it is difficult to fall out of the sealing body 2. May be. It can also be manufactured by etching press. -Also, as shown in FIG. 10, on the main surface of the tab 4, the central rectangular area becomes the semiconductor element mounting portion 4a (the area surrounded by the two-dot chain line frame). The outer area is the wire connection area 4b.
このようなリー ドフ レーム 1 3を準備した後、 図 9 に示すように、 各 単位リー ドフ レームパターン 1 4の夕ブ 4の半導体素子搭載部 4 aに接 着剤 5 を介して半導体チップ 3 を固定 （チップボンディ ング） する （ S 1 0 2 ) ο  After preparing such a lead frame 13, as shown in FIG. 9, the semiconductor chip 3 is connected to the semiconductor element mounting portion 4 a of the unit 4 of the unit lead frame pattern 14 via the adhesive 5. Fix (chip bonding) (S102) ο
つぎに、 図 1 0に示すように、 ワイヤボンディ ングを行い、 半導体チ ヅプ 3の電極端子と リー ド 7の先端を導電性のワイヤ 1 0で接続すると ともに、 所定の電極端子とタブ 4のワイヤ接続領域 4 bを導電性のヮィ ャ 1 0で接続する （ S 1 0 3 )。電極端子とタブ 4のワイャ接続領域 4 b を接続したワイヤを特にダウンボンディ ングワイヤ 1 O aと呼称する。 ワイヤは例えば金線を使用する。  Next, as shown in FIG. 10, wire bonding is performed, and the electrode terminal of the semiconductor chip 3 and the tip of the lead 7 are connected with a conductive wire 10 while the predetermined electrode terminal and the tab 4 are connected. The wire connection region 4b is connected by a conductive wire 10 (S103). The wire connecting the electrode terminal and the wire connection area 4b of the tab 4 is particularly called a down-bonding wire 1Oa. As the wire, for example, a gold wire is used.
つぎに、 常用の ト ランスフ ァモ一ル ドによる片面モール ドを行い、 リ ー ドフ レーム 1 3の主面に絶縁性樹脂による封止体 2 を形成する （ S 1 0 4 )。封止体 2はリー ドフ レーム 1 3の主面側の半導体チップ 3 , リー ド 7等を被う。 図 8 において、 二点鎖線枠で示す部分が封止体 2が形成 される領域である。  Next, single-sided molding is performed using a conventional transfer mold, and a sealing body 2 made of an insulating resin is formed on the main surface of the lead frame 13 (S104). The sealing body 2 covers the semiconductor chip 3, the lead 7, and the like on the main surface side of the lead frame 13. In FIG. 8, a portion indicated by a two-dot chain line frame is a region where the sealing body 2 is formed.
つぎに、 図示はしないが、 メ ツキ処理を行う （ S 1 0 5 )。 この結果、 リー ドフ レーム 1 3の裏面には図示しないメ ツキ膜が形成される。 この メ ッキ膜は、 半導体装置 1の表面実装時の接合材と して使用されるもの であり、 例えば、 半田メ ツキ膜である。 前記メ ツキ膜を形成する工程に 代えて、 あらかじめリー ドフ レーム 1 3の表面全面に P dメ ツキが施さ れた物を使用しても良い、 また特に P dメ ツキされた リー ドフ レーム 1 3を用いる場合には前記封止後のメ ツキ工程を省略する事ができ、 製造 工程の簡略化をし、 製造コス トを削減する事ができる。  Next, although not shown, a masking process is performed (S105). As a result, a plating film (not shown) is formed on the back surface of the lead frame 13. This solder film is used as a bonding material when the semiconductor device 1 is surface-mounted, and is, for example, a solder plating film. Instead of the step of forming the plating film, a Pd plating may be used on the entire surface of the lead frame 13 in advance, and in particular, a Pd plating lead frame 1 may be used. When 3 is used, the plating step after the sealing can be omitted, and the manufacturing process can be simplified and the manufacturing cost can be reduced.
つぎに、 不要なリ一 ドフ レーム部分を切断除去し （ S 1 0 6 )、 図 1 に 示すような半導体装置 1 を製造する。 図 8 に示す二点鎖線枠の封止体 2 の僅か外側で、 図示しないプレス機械の切断型でリード 7及びタブ吊り リー ド 6が切断される。 切断型の構造によ り、 リー ド 7及び夕ブ吊り リ ード 6は封止体 2から僅か外れた位置で切断するが、 この外れた位置の 封止体 2からの距離は、 例えば 0 . 1 m m以下とされる。 リー ド 7及び タブ吊り リー ド 6の封止体 2からの突出長さは、 引っ掛かり防止等の点 では短い程よい。 この突出長さはプレス機械の切断型の変更で 0 . l m m以上では自由に選択できる。 Next, an unnecessary lead frame portion is cut and removed (S106), and a semiconductor device 1 as shown in FIG. 1 is manufactured. Sealed body 2 with a two-dot chain line frame shown in Fig. 8 Slightly outside, the lead 7 and the tab suspension lead 6 are cut by a cutting die of a press machine (not shown). Due to the cutting type structure, the lead 7 and the evening suspension lead 6 are cut at a position slightly deviated from the sealing body 2, and the distance from the sealing body 2 at the deviated position is, for example, 0. . 1 mm or less. The shorter the lead 7 and the tab suspension lead 6 protrude from the sealing body 2, the better in terms of prevention of catching and the like. This protruding length can be freely selected above 0.1 mm by changing the cutting die of the press machine.
ここで、 半導体装置 1の各部の寸法の一例を挙げる。 リー ドフレーム (夕プ 4， タブ吊り リー ド 6 ， リー ド 7 ) の厚さは 0 . 2 m m、 チップ 3の厚さは 0 . 2 8 m m、 半導体装置 1の厚さは 1 . 0 m m、 リード 7 の幅は 0 . 2 m m、 リー ド 7の長さは 0 . 5 m m、 タブ 4のワイヤ接続 箇所 （点） は搭載されたチヅプ 3の端から 1 . 0 m m、 また、 タブ 4 と リー ド 7のとの間隔は 0 . 2 m mである。  Here, an example of the dimensions of each part of the semiconductor device 1 will be described. The thickness of the lead frame (evening 4, tab hanging lead 6, lead 7) is 0.2 mm, the thickness of chip 3 is 0.28 mm, and the thickness of semiconductor device 1 is 1.0 mm. The width of the lead 7 is 0.2 mm, the length of the lead 7 is 0.5 mm, and the wire connection point (point) of the tab 4 is 1.0 mm from the end of the mounted chip 3. The distance between lead and lead 7 is 0.2 mm.
一方、 これが本発明の特徴の一つであるが、 半導体チップ 3内の回路 の一部、即ち特定回路部のグラン ドはグラン ド電極端子として取り出し、 かつリー ドにワイヤを介して接続し、 残りの回路部のグラン ドとは分離 するものである。 残りの各回路部は必要に応じて共通グラン ドとなる夕 ブにワイヤを介して接続するとともに、 必要に応じて リー ドにワイヤを 介して接続するものである。 また、 特定回路部のグラン ドと他の残りの 回路部のグラン ドは、 図示はしないが、 半導体チップ 3内の配線におい ても層間絶縁膜等によって絶縁分離されているものである。  On the other hand, this is one of the features of the present invention. Part of the circuit in the semiconductor chip 3, that is, the ground of the specific circuit portion is taken out as a ground electrode terminal, and connected to the lead via a wire. It is separated from the ground of the rest of the circuit. The remaining circuit sections are connected to the common ground via wires as necessary, and are connected to leads as necessary. Although not shown, the ground of the specific circuit portion and the ground of the other circuit portions are also insulated and separated from each other in the wiring in the semiconductor chip 3 by an interlayer insulating film or the like.
本実施形態 1で適用した高周波パワーモジュールでは、 単一の半導体 チップ内に形成された各回路部全てをグラン ド共通化にすると、 先に説 明したようにグラン ド電位の変動によってクロス トークが発生し、 それ それの回路部での出力変動や信号波形の歪みが発生するおそれがある。 また、 デュアルバン ドゃ ト リプルバン ド等複数の通信回路を有する高周 波パワーモジュールにおいては、 動作中の通信回路に動作させていない 通信回路に誘起電流が発生し、 この誘起電流が雑音と して動作中の通信 回路に入り込むおそれがある。 そこで、 本実施形態 1では特定回路部の グラン ド用の電極端子（グラン ド電極端子）は夕ブに接続することなく、 独立したリー ド （グラン ドリー ド） にワイヤを介して接続することとす る。 In the high-frequency power module applied in the first embodiment, if all the circuit units formed in a single semiconductor chip are made to have a common ground, as described above, the crosstalk is caused by the fluctuation of the ground potential. This may cause output fluctuations and signal waveform distortions in the respective circuit sections. In addition, high-frequency circuits with multiple communication circuits such as dual band and triple band In a wave power module, an induced current is generated in a communication circuit that is not operating in an operating communication circuit, and this induced current may enter the operating communication circuit as noise. Therefore, in the first embodiment, the ground electrode terminal (ground electrode terminal) of the specific circuit section is connected to an independent lead (ground lead) via a wire without being connected to the terminal. You.
また、 入力信号配線同士のクロス トークによってもそれそれの回路部 での出力変動や信号波形の歪みが発生するおそれがあり、 特に入力信号 の小さいアンテナからの外部信号入力用リードにおいては、 隣接する リ ー ドとのクロス トークの影響を極力避ける必要が有る。  In addition, crosstalk between input signal wirings may cause output fluctuations and signal waveform distortion in the respective circuit sections, especially in external signal input leads from antennas with small input signals. It is necessary to minimize the effects of crosstalk with the leads.
本実施形態 1 において半導体装置 1 は携帯電話機の ト リプルバン ド用 の高周波パワーモジュールであることから、 特定回路部は低雑音増幅器 In the first embodiment, the semiconductor device 1 is a high-frequency power module for a triple band of a mobile phone.
( L N A ) である。 卜 リ プルバン ドであることから、 アンテナに繋がる 低雑音増幅器 （ L N A ) も 3個配置されている。 (L N A). Because it is a triple band, three low-noise amplifiers (LNA) connected to the antenna are also arranged.
単一の L N Aが本発明で言う狭義の特定回路部となる。 即ち、 図 5 に 示すように、 各 L N Aのアンテナからの入力信号配線は 2本となってい る。 そして、 この 2本の信号配線を電磁シール ドするために、 2本の信 号用 リ一ドと他の信号用リ一ドとの間、 好ま しくは 2本の信号用リ一ド の両側にそれぞれグラン ド用リー ドを配置している。  A single LNA is a specific circuit unit in a narrow sense in the present invention. That is, as shown in FIG. 5, there are two input signal wires from each LNA antenna. Then, in order to electromagnetically shield the two signal wires, the two signal leads are preferably placed between two signal leads and another signal lead, preferably on both sides of the two signal leads. Each has a ground lead.
入力信号配線を 2本にして差動入力構成にすると、 入力信号配線の 2 本に同程度のクロス トークによる影響が出てノイズ （クロス 卜一ク） を 相殺 （キャンセル） することができる。 なお、 図 5 に示すように、 3個 の L N Aを囲んだ矩形枠部分を広義の特定回路部 1 1 とする。 この特定 回路部 1 1では、 半導体チップにおいて、 他の回路部から絶縁分離され た領域に各延 L N Aが形成されている。 そして、 各 L N Aのグラン ド電 位は共通になっている。 これは、 デュアル通信システム、 ト リプル通信 システムでは、 一つの通信システム （通信系） を使用している間、 残り の通信システムはアイ ド リ ング状態となっていることから、 アイ ド リ ン グ状態になっている通信システムに属する L NAによるグラン ド電位に 対する影響が小さいため、 各々別個の通信システムに属する L N A同士 のグラン ド電極およびグラン ド配線を共通化しても、 お互いに及ぼす悪 影響が小さいからである。 しかし、 必要ならば、 各 L NAごとにァイ ソ レ一シヨンを施して、 各 L NAのグラン ド電位を独立とさせる構成でも よい。 If two input signal lines are used to form a differential input configuration, the two input signal lines will be affected by the same degree of crosstalk, thereby canceling (cancelling) noise (crosstalk). Note that, as shown in FIG. 5, a rectangular frame portion surrounding three LNAs is a broadly defined specific circuit unit 11. In the specific circuit section 11, each extended LNA is formed in a region of the semiconductor chip that is insulated and separated from other circuit sections. The ground potential of each LNA is common. This is a dual communication system, triple communication In the system, while one communication system (communication system) is used, the remaining communication systems are in the idling state, so that the L belonging to the communication system in the idle state is used. This is because the influence of the NA on the ground potential is small, and even if the ground electrode and the ground wiring of the LNAs belonging to different communication systems are shared, the adverse effect on each other is small. However, if necessary, a configuration may be adopted in which isolation is applied to each LNA so that the ground potential of each LNA is independent.
図 1 3は本実施形態 1の半導体装置 （高周波パワーモジュール） 1の 携帯電話機における実装状態を示す模式的断面図である。  FIG. 13 is a schematic cross-sectional view showing a mounting state of the semiconductor device (high-frequency power module) 1 of Embodiment 1 in a mobile phone.
携帯電話機の実装基板 （配線基板） 8 0の主面には半導体装置 1 を搭 載するために、 半導体装置 1のリー ド 7及びタブ 4に対応して配線に連 なるラン ド 8 1及びタブ固定部 8 2が設けられている。 そこで、 半導体 装置 1のリード 7及び夕ブ 4が前記ラン ド 8 1及び固定部 8 2 に一致し て重なるように半導体装置 1 を位置決め載置する。 そして、 この状態で 半導体装置 1のリー ド 7及びタブ 4の裏面に予め形成しておいた半田メ ヅキ膜を一時的に溶融 （ リ フロー） して リー ド 7及びタブ 4を半田 8 3 で接続 （実装） する。  In order to mount the semiconductor device 1 on the main surface of the mounting substrate (wiring substrate) 80 of the mobile phone, the land 81 and the tab connected to the wiring correspond to the lead 7 and the tab 4 of the semiconductor device 1. A fixed portion 82 is provided. Therefore, the semiconductor device 1 is positioned and mounted such that the leads 7 and the leads 4 of the semiconductor device 1 coincide with the land 81 and the fixed portion 82 and overlap with each other. Then, in this state, the solder plating film previously formed on the back surface of the lead 7 and the tab 4 of the semiconductor device 1 is temporarily melted (reflowed), and the lead 7 and the tab 4 are soldered with the solder 83. Connect (implement).
ここで、 ト リプルバン ド構成の携帯電話機の回路構成 （機能構成） に ついて図 1 2を参照しながら簡単に説明する。即ち、この携帯電話機は、 例えば、 9 0 0 M H z帯の G S M通信方式と、 1 8 0 0 MH z帯の D C S 1 8 0 0通信方式と、 1 9 0 0 MH z帯の P C S 1 9 0 0通信方式の 信号処理を行うことができる。  Here, the circuit configuration (functional configuration) of a triple-band mobile phone will be briefly described with reference to FIGS. That is, for example, this mobile phone has a 900 MHz GSM communication system, a 800 MHz DCS 180 communication system, and a 900 MHz PCS 190 MHz communication system. 0 Signal processing of the communication system can be performed.
図 1 2のブロ ック図では、 アンテナ 2 0にアンテナスイ ッチ 2 1 を介 して接続する送信系と、 受信系とを示してあり、 送信系及び受信系はい ずれもベースバン ドチップチップ 2 2 に接続されるものである。 受信系は、 アンテナ 2 0， アンテナスィ ッチ 2 1 , このアンテナスィ ツチ 2 1に並列に接続される 3個の帯域通過フ ィ ル夕 2 3、 前記帯域通 過フ ィ ル夕 2 3にそれそれ接続される低雑音増幅器 （ L N A) 2 4、 前 記 3個の L NA 2 4に接続されかつ並列に接続される可変増幅器 2 5を 有する。 この二つの可変増幅器 2 5には、 それそれミキサ 2 6， ローバ スフ ィ ル夕 2 7， P GA 2 8 , 口一パスフ ィ ゾレ夕 2 9 , P G A 3 0 , 口 一パスフ ィ ル夕 3 1 , P GA 3 2 , 口一パスフ ィ ル夕 3 3 , 復調器 3 4 が接続される。 P GA 2 8， P G A 3 0 , P GA 3 2は AD C/D A C &D Cオフセッ ト用制御論理回路部 3 5によって制御される。 また、 二 つのミキサ 2 6は 9 0度位相変換器 4 0で位相制御される。 The block diagram in FIG. 12 shows the transmission system and the reception system connected to the antenna 20 via the antenna switch 21. Both the transmission system and the reception system are baseband chip chips. It is connected to 2 2. The receiving system is composed of an antenna 20, an antenna switch 21, three band-pass filters 23 connected in parallel to the antenna switch 21, and the above-mentioned band-pass filter 23. Each has a low noise amplifier (LNA) 24 connected thereto, and a variable amplifier 25 connected to the three LNAs 24 and connected in parallel. Each of these two variable amplifiers 25 has a mixer 26, a rover filter 27, a PGA 28, a one-pass filter 29, a PGA 30 and a one-pass filter 3, respectively. 1, PGA 32, mouth-to-pass filter 33, and demodulator 34 are connected. PGA 28, PGA 30, and PGA 32 are controlled by a control logic circuit section 35 for ADC / DAC & DC offset. The two mixers 26 are controlled in phase by a 90-degree phase converter 40.
図 1 2において、 9 0度位相変換器 4 0および 2つのミキサ 2 6によ つて構成される I /Q変調器は、 各バン ド帯域に対応するために、 3つ の L N Aに対応してそれそれ設けられるが、 図 1 2においては、 簡略化 のために 1つにまとめて書いてある。  In Fig. 12, the I / Q modulator composed of the 90-degree phase converter 40 and the two mixers 26 corresponds to three LNAs in order to correspond to each band band. Each is provided, but in Figure 12 they are grouped together for simplicity.
半導体チップ 3には、 信号処理 I Cとして R Fシンセサイザ 4 1及び I F ( Intermediate) シンセサイザ 4 2からなるシンセサイザが設けら れている。 R Fシンセサイザ 4 1はバッファ 4 3を介して11 ? ¥〇 04 4に接続され、 R F V C 04 4が R Fローカル信号を出力するように制 御する。 ノ ッ フ ァ 4 3には、 直列に 2つの口一カル信号用分周器 3 7 , 3 8が接続され、 それそれの出力端にはスイ ッチ 4 8， 4 9が接続され ている。 R F V C 04 4から出された R F口一カル信号はスィ ッチ 4 8 の切替えによって 9 0度位相変換器 4 0に入力される。 この R Fロー力 ル信号によって 9 0度位相変換器 4 0はミキサ 2 6を制御する。  The semiconductor chip 3 is provided with a synthesizer including an RF synthesizer 41 and an IF (Intermediate) synthesizer 42 as a signal processing IC. The RF synthesizer 41 is connected to 11? 044 via a buffer 43, and controls the RFVC044 to output an RF local signal. Two frequency dividers 37, 38 for the oral signal are connected in series to the knocker 43, and switches 48, 49 are connected to their output terminals. . The RF local signal output from RFVC 04 is input to the 90-degree phase converter 40 by switching the switch 48. The 90-degree phase converter 40 controls the mixer 26 by the RF signal.
R F V C 04 4の信号出力モー ドは R xモー ドの場合、 G S Mでは 3 7 8 0〜 3 8 4 0 MH z、 D C Sでは 3 6 1 0〜 3 7 6 0 MH z、 P C Sでは 3 8 6 0〜 3 9 8 0 MH zである。 また T xモー ドは G S Mでは 3 84 0〜 3 9 8 0 MH z、 D C Sでは 3 5 8 0〜 37 30MH z、 P C Sでは 3 8 6 0〜 3 9 80 MH zである。 When the signal output mode of the RFVC044 is in the Rx mode, it is 3780 to 3840 MHz for GSM, 3610 to 3760 MHz for DCS, and 3860 MHz for PCS. ~ 3980 MHz. And Tx mode is GSM It is 380 to 380 MHz, 380 to 3730 MHz for DCS, and 380 to 3980 MHz for PCS.
I Fシンセサイザ 42は分周器 4 6を介して I FVC O (中間波電圧 制御発振器） 4 5に接続され、 I F V C 04 5が I Fローカル信号を出 力するように制御する。 I F V C 04 5による出力信号の周波数は各通 信方式共に 6 4 0 MH zである。 また、 R Fシンセサイザ 4 1及ぴ I F シンセサイザ 4 2によって VCXO (電圧制御水晶発振器） 5 0を制御 し、 基準信号を出力し、 ベースバン ドチップチップ 2 2に送る。  IF synthesizer 42 is connected to IFVC O (intermediate wave voltage controlled oscillator) 45 via frequency divider 46, and controls IFVC045 to output an IF local signal. The frequency of the output signal according to IFVC045 is 640 MHz for each communication method. The RF synthesizer 41 and the IF synthesizer 42 control VCXO (voltage controlled crystal oscillator) 50, output a reference signal, and send it to the baseband chip chip 22.
受信系ではシンセサイザ及び A D C Z D A C & D Cオフセッ ト用制御 論理回路部 3 5によって I F信号を制御し、 復調器 34によってベース バン ドチップ信号 （ I , Q信号） に変換してベースバン ドチップ 2 2に 送る。  In the receiving system, the IF signal is controlled by the synthesizer and the control logic circuit section 35 for ADCZ DAC & DC offset, and converted to baseband chip signals (I and Q signals) by the demodulator 34 and sent to the baseband chip 22.
送信系は、 ベースバン ドチップ 2 2から出力される I , Q信号を入力 信号とする二つのミキサ 6 1と、 この二つのミキサ 6 1の位相を制御す る 9 0度位相変換器 6 2と、 二つのミキサ 6 1の出力を加算する加算器 63と、 加算器 6 3の出力をいずれも入力とする ミキサ 64及び D PD (デジタルフェーズディテクタ） 6 5 と、 ミキサ 6 4及び D PD 6 5の 出力を共に入力とするループフィル夕 6 6と、 ループフィル夕 6 6の出 力を共に入力とする二つの TXV C O (送信波電圧制御発信器） 6 7と、 二つの TXV C06 7の出力を共に入力とするパワーモジュール 6 8と- アンテナスィ ツチ 2 1とからなっている。 ループフィル夕 6 6は外付け 部品である。  The transmission system includes two mixers 61 that use the I and Q signals output from the baseband chip 22 as input signals, a 90-degree phase converter 62 that controls the phases of the two mixers 61, and An adder 63 that adds the outputs of the two mixers 61, a mixer 64 and a DPD (digital phase detector) 65 that both receive the output of the adder 63, and a mixer 64 and a DPD 65 that The output of the loop filter 66 and the output of the loop filter 66 and the two TXV COs (transmission voltage control oscillators) 67 and the outputs of the two TXV C06 7 It comprises a power module 68 and an antenna switch 21 both of which are inputs. Loop fill 6 6 is an external component.
ミキサ 6 1 , 9 0度位相変換器 6 2及び加算器 6 3によって直交変調 器を構成する。 9 0度位相変換器 6 2は分周器 4 6に分周器 47を介レ て接続され、 I FVC 04 5から出力される I Fローカル信号によって 制御される。 二つの T XV C 06 7の出力はカプラー 7 0によって電流を検出され る。 この検出信号は増幅器 7 1 を介してミキサ 7 2に入力される。 ミキ サ 7 2はスィ ツチ 4 9を介して R F V C 04 4から出力される R Fロー カル信号を入力する。 ミキサ 7 2の出力信号は加算器 6 3の出力信号と 共にミキサ 6 4及び D P D 6 5に入力される。 ミキサ 6 4と D P D 6 5 によってオフセッ ト P L L (Phase-Locked Loop) を構成する。 ミキサ 7 2による出力信号の周波数は各通信方式共に 8 0 MH zである。 A quadrature modulator is constituted by the mixers 61, 90-degree phase converter 62 and the adder 63. The 90-degree phase converter 62 is connected to the frequency divider 46 via the frequency divider 47, and is controlled by the IF local signal output from the IFVC 045. The outputs of the two TXVCs 067 are current sensed by the coupler 70. This detection signal is input to the mixer 72 via the amplifier 71. The mixer 72 inputs the RF local signal output from the RFVC 044 via the switch 49. The output signal of the mixer 72 is input to the mixer 64 and the DPD 65 together with the output signal of the adder 63. The offset PLL (Phase-Locked Loop) is configured by the mixer 64 and the DPD 65. The frequency of the output signal from the mixer 72 is 80 MHz for each communication system.
二つの T XV C 0 6 7のうちの一方の T XV C O 6 7は G S M通信方 式用であり、 出力信号の周波数は 8 8 0〜 9 1 5 MH zである。 また、 他の T X V C 0 6 7は D C S ' P C S通信方式用であり、 出力信号の周 波数は 1 7 1 0〜 1 7 8 5 MH z、 または 1 8 5 0〜 1 9 1 0 MH zで ある。 パワーモジュール 6 8は低周波用パワーモジュールと高周波用パ ヮ一モジュールを内蔵し、 低周波用パワーモジュールは 8 8 0〜 9 1 5 MH zの信号を出力する T XV C 0 6 7からの信号を受けて増幅処理し. 高周波用パワーモジュールは 1 7 1 0〜 1 7 8 5 MH z、 または 1 8 5 0〜 1 9 1 0 MH zの信号を出力する T X V C 0 6 7からの信号を受け て増幅処理し、 アンテナスィ ッチ 2 1に送る。  One of the two TXVC067s is for the GSM communication method, and the frequency of the output signal is 880 to 915 MHz. The other TXVC 067 is for the DCS'PCS communication system, and the frequency of the output signal is 1710 to 1785 MHz, or 1850 to 1910 MHz. . The power module 68 incorporates a low-frequency power module and a high-frequency power module, and the low-frequency power module outputs a signal of 880 to 915 MHz. The high-frequency power module receives a signal from the TXVC 067, which outputs a signal of 1710 to 1785 MHz or 1850 to 1910 MHz. The signal is amplified and sent to antenna switch 21.
本実施形態 1の半導体装置 1にはロジック回路 6 0もモノ リシックに 形成され、 出力信号をペースバン ドチップ 2 2に送る。  The logic circuit 60 is also formed monolithically in the semiconductor device 1 of the first embodiment, and sends an output signal to the paceband chip 22.
本実施形態 1の半導体装置 （高周波パワーモジュール） 1は、 図 1 2 において太線で囲った部分の各回路部がモノ リシックに形成されている ことになる。 そして、 3個の L NA 2 4の部分が、 本実施形態 1におけ る特定回路部 1 1になる （図 4， 図 5参照）。 これら各回路部を模式的に 一部示したものが、 図 4及び図 5の半導体チップ 3のプロ ック平面図で ある。  In the semiconductor device (high-frequency power module) 1 according to the first embodiment, each circuit portion surrounded by a thick line in FIG. 12 is monolithically formed. Then, the three LNA 24 portions become the specific circuit portion 11 in the first embodiment (see FIGS. 4 and 5). FIG. 4 and FIG. 5 are block plan views of the semiconductor chip 3 schematically showing part of each of these circuit portions.
アンテナ 2 0で受信された無線信号 （電波） は電気信号に変換され、 受信系の各素子で順次処理されてベースバン ドチップ 2 2に送られる。 また、 ベースバン ドチップ 2 2から出力された電気信号は、 送信系の各 素子で順次処理されてアンテナ 2 0から電波と して放射される。 Radio signals (radio waves) received by antenna 20 are converted into electrical signals, The signals are sequentially processed by each element of the receiving system and sent to the baseband chip 22. The electric signal output from the baseband chip 22 is sequentially processed by each element of the transmission system and radiated from the antenna 20 as a radio wave.
図 4は、 半導体チップ 3における各回路部の配置を示す模式的レイァ ゥ ト図である。 半導体チップ 3の主面には、 辺に沿って電極端子 （パッ ド） 9が配置されている。 そして、 これら電極端子 9の内側に領域を分 けて各回路部が配置されている。 図 4に示すように、 半導体チップ 3中 央には AD C/DAC&D Cオフセッ ト用制御論理回路部 3 5が配置さ れ、 その左側にはミキサ 2 6 , 64と 3個の L N A 2 4が並び、 上側に は R F V C 044位置し、 右側には上から下に掛けて R Fシンセサイザ 4 1 , V C X 05 0 , I Fシンセサイザ 42 , I FV C045が並び、 下側には T X V C 06 7が位置している。  FIG. 4 is a schematic layout diagram showing an arrangement of each circuit unit in the semiconductor chip 3. On the main surface of the semiconductor chip 3, electrode terminals (pads) 9 are arranged along the sides. Each circuit portion is arranged inside the electrode terminal 9 with a region divided. As shown in Fig. 4, a control logic circuit section 35 for ADC / DAC & DC offset is arranged in the center of the semiconductor chip 3, and mixers 26, 64 and three LNAs 24 are located on the left side thereof. RFVC 044 is located on the upper side, RF synthesizers 41, VCX 050, IF synthesizer 42, IFV C045 are arranged on the right side from top to bottom, and TXVC 06 7 is located on the lower side .
図 5には各回路部 （第 1の回路部及び第 2の回路部） とその電極端子 9との関係、電極端子 9と リー ド 7のワイヤ 1 0による結線状態を示す。 ワイヤ 1 0は電極端子 9と リー ド 7を結線するワイヤ 1 0と、 電極端子 9とタブ 4を結線するダウンボンディ ングワイヤ 1 0 aが示されている , 特定回路部 1 1 (第 1の回路部） である 3個の LNA 24に着目する と、 外付け部品である帯域通過フィルタ 2 3と繋がる予定のリー ド 7、 即ち S i g n a lと左側に記載された リー ド 7と、 L NA 24の信号電 極端子 9がワイヤ 1 0を介して接続されている。 電極端子 9からワイヤ 1 0を介して リー ド 7に至る信号配線は 2本設けられ、 この 2本の信号 配線の両側は、 特定回路部 1 1である L N A 2 4のグラン ド電極端子 9 がワイヤ 1 0を介してグラン ド リー ド 7 (図中 G N Dと左側に記載され たリード 7 ) に接続されてグラン ド配線が形成されている。  FIG. 5 shows the relationship between each circuit section (the first circuit section and the second circuit section) and its electrode terminal 9, and the connection state of the electrode terminal 9 and the lead 7 with the wire 10. Wire 10 shows wire 10 connecting electrode terminal 9 and lead 7, and down-bonding wire 10a connecting electrode terminal 9 and tab 4.Specific circuit section 1 1 (first circuit Focusing on the three LNAs 24, the lead 7 to be connected to the bandpass filter 23, which is an external component, that is, the lead 7 described on the left with Signal, and the LNA 24 Signal electrode terminal 9 is connected via wire 10. Two signal wirings from the electrode terminal 9 to the lead 7 via the wire 10 are provided, and on both sides of the two signal wirings, the ground electrode terminal 9 of the LNA 24, which is the specific circuit section 11, is provided. A ground wire is formed by connecting to a ground lead 7 (GND and a lead 7 described on the left side in the figure) via a wire 10.
これによ り、 他の回路部、 少なく とも各 V C〇のグラン ドと LNA 2 4 のグラン ドは絶縁分離され、 かつ、 隣接する他の回路部のリー ドと L N A 2 4のリー ドの間がグラン ド リー ド 7によって電磁シール ドされてい る。 また、 隣接する L N A 2 4同士もグラン ド リー ド 7 によって電磁シ —ル ドされている。 As a result, the other circuit section, at least the ground of each VC〇 and the ground of LNA 24 are insulated and separated, and the lead of other adjacent circuit section and LN 24 are separated. Electromagnetic shield between the leads of A24 is provided by ground lead 7. Adjacent LNAs 24 are also electromagnetically shielded by ground leads 7.
アンテナから入って く る微弱信号を増幅する L N A 2 4に比較して、 ベ —スパン ドチップチップ 2 2から出力される電気信号を処理する送信系 の各回路部 （例えばオフセッ ト P L L、 T X V C 0 6 7など） において は、 その電気信号が前記微弱信号に比較して大きいために、 グラン ド電 位の変動やクロス トークによるノイズによ り強いという特性を持つ。 そ こで、 送信系の回路部へのグラン ド電位の供給は、 各 V C〇などとタブ 4を介して共通にする事によ り、 リー ド 7の数を減らす事ができ、 半導 体装置の小型化をする事ができる。 Compared to the LNA 24 which amplifies the weak signal coming from the antenna, each circuit part of the transmission system that processes the electric signal output from the base chip chip 22 (for example, offset PLL, TXVC 0 67)), since the electrical signal is larger than the weak signal, it has a characteristic that it is more resistant to fluctuations in the ground potential and noise due to crosstalk. Therefore, the supply of the ground potential to the circuit section of the transmission system is made common to each VC〇 and the like via the tab 4, so that the number of leads 7 can be reduced. The size of the device can be reduced.
L N Aは、 半導体チップ 3主面上に形成された配線間でのクロス トーク による信号の劣化を防ぐために、 例えば P G Aなど、 前記 L N Aによつ て増幅された信号を扱う回路、 または送信系の回路などと比較して前記 配線の長さが短くなる様に、 電極端子 9のよ り近く に配置するのが好ま しい。  The LNA is a circuit that handles signals amplified by the LNA, such as a PGA, or a transmission circuit, for example, in order to prevent signal deterioration due to crosstalk between wirings formed on the main surface of the semiconductor chip 3. It is preferable to dispose it closer to the electrode terminal 9 so that the length of the wiring is shorter than that of the above.
本実施形態 1 によれば、 以下の効果を有する。  According to the first embodiment, the following effects are obtained.
( 1 ) 半導体装置 1、 即ち高周波パワーモジュール 1 においては、 半 導体素子 （半導体チップ） 3の電極端子 9はワイヤ 1 0を介して リー ド 7に接続される以外に夕プ 4にも接続 （ダウンボンディ ング） される。 そして、 このダウンボンディ ングはタブ 4が共通グラン ドとなることか ら、 特定回路部 1 1である低雑音増幅器 2 4のグラン ド電極端子 （半導 体素子の電極端子） はタブ 4 には接続されず、 独立したリー ド端子 （グ ラ ン ド リー ド） に接続される。 低雑音増幅器 2 4は微弱な信号を増幅す るため、 グラン ド電位の変動は低雑音増幅器 2 4の出力の変動となると ともに、 信号波形も歪むが、 低雑音増幅器 2 4のグラン ドは他の回路部 のグラン ドと分離されていることから、 低雑音増幅器 2 4の出力の変動 や信号波形の歪みを抑制できる。 この結果、 無線通信装置に組み込むこ とによって出力変動や歪みのない良好な通話が可能になる。 (1) In the semiconductor device 1, that is, in the high-frequency power module 1, the electrode terminal 9 of the semiconductor element (semiconductor chip) 3 is connected not only to the lead 7 via the wire 10 but also to the chip 4 ( Down-bonding). In this down-bonding, the tab 4 becomes a common ground, so that the ground electrode terminal (electrode terminal of the semiconductor element) of the low-noise amplifier 24 which is the specific circuit section 11 is connected to the tab 4. Not connected, but connected to an independent lead terminal (ground lead). Since the low-noise amplifier 24 amplifies a weak signal, the fluctuation of the ground potential causes the fluctuation of the output of the low-noise amplifier 24 and the signal waveform is distorted, but the ground of the low-noise amplifier 24 Circuit section of Since this is separated from the ground, fluctuations in the output of the low noise amplifier 24 and distortion in the signal waveform can be suppressed. As a result, by incorporating the wireless communication device into a wireless communication device, it is possible to perform a favorable call without output fluctuation or distortion.
( 2 ) 複数の通信回路を有する高周波パワーモジュールにおいては、 タブ 4を利用する共通グラン ドの場合、 グラン ド電位の変動に伴い使用 していない通信回路に誘起電流が発生し、 この誘起電流に起因する雑音 が使用中 （動作中） の通信回路に入り込む、 いわゆるクロス トークが発 生するが、 本発明の高周波パワーモジュール 1では、 各通信回路の低雑 音増幅器 2 4は他の回路部のグラン ドと分離されていることから、 低雑 音増幅器 2 4の出力の変動や信号波形の歪みを抑制できる。 この結果、 複数の通信回路を有する無線通信装置においても出力変動や歪みのない 良好な通話が可能になる。  (2) In a high-frequency power module having a plurality of communication circuits, in the case of a common ground using the tab 4, an induced current is generated in an unused communication circuit due to fluctuations in the ground potential, and this induced current is The resulting noise enters the communication circuit in use (during operation), so-called crosstalk occurs. In the high-frequency power module 1 of the present invention, the low-noise amplifier 24 of each communication circuit is connected to the other circuit sections. Since it is separated from the ground, fluctuations in the output of the low-noise amplifier 24 and distortion of the signal waveform can be suppressed. As a result, even in a wireless communication device having a plurality of communication circuits, it is possible to perform a good call without output fluctuation or distortion.
( 3 ) 高周波パワーモジュール 1 において、 低雑音増幅器 2 4の電極 端子 9からワイヤ 1 0を介して リー ド 7に至る信号配線はその両側にグ ラン ド配線が配置されて電磁シール ドされていることから、 信号配線は クロス トークを受け難く なる。  (3) In the high-frequency power module 1, the signal wiring from the electrode terminal 9 of the low-noise amplifier 24 to the lead 7 via the wire 10 is grounded on both sides thereof and is electromagnetically shielded. Therefore, the signal wiring is less susceptible to crosstalk.
( 4 ) 高周波パワーモジュール 1 は、 タブ 4が封止体 2の裏面に露出 していることから、 半導体チップ 3で発生した熱を効果的に実装基板 8 0に放散することができる。 従って、 この高周波パワーモジュール 1 を 組み込んだ無線通信装置は安定動作が可能になる。  (4) In the high-frequency power module 1, since the tab 4 is exposed on the back surface of the sealing body 2, heat generated in the semiconductor chip 3 can be effectively dissipated to the mounting board 80. Therefore, the wireless communication device incorporating the high-frequency power module 1 can operate stably.
( 5 ) 高周波パワーモジュール 1 は、 夕ブ 4及びリー ド 7が封止体 2 の裏面に露出するノン リー ド型半導体装置であることから、 高周波パヮ 一モジュール 1の小型 ·薄型化が可能になり、軽量化も図れる。従って、 この高周波パワーモジュール 1 を組み込んだ無線通信装置の小型 · 軽量 ィ匕も可能になる。  (5) Since the high-frequency power module 1 is a non-lead type semiconductor device in which the lug 4 and the lead 7 are exposed on the back surface of the sealing body 2, the high-frequency power module 1 can be reduced in size and thickness. And lighter weight. Therefore, the wireless communication device incorporating the high-frequency power module 1 can be reduced in size and weight.
( 6 ) 高周波パヮ一モジュール 1 は、 半導体チップ 3の電極端子 9 と リー ド （ピン） 7をワイヤ 1 0で接続するとともに、 グラン ド電位とな るタブ 4 と半導体チップ 3の電極端子 （グラン ド電極端子） 9をダウン ボンディ ングワイヤ 1 0 aで接続するダウンボンディ ング構造となって いることから、 外部電極端子 7 となるグラン ド リー ドを少なくすること ができ、 ピン数低減による封止体 2の小型化が可能にな り、 高周波パヮ 一モジュール 1の小型化が達成できる。 (6) The high frequency power module 1 is connected to the electrode terminals 9 of the semiconductor chip 3. Down bonding where lead (pin) 7 is connected with wire 10 and tab 4 which is the ground potential and electrode terminal (ground electrode terminal) 9 of semiconductor chip 3 are connected with down bonding wire 10a. Because of this structure, the number of ground leads that become the external electrode terminals 7 can be reduced, the size of the sealing body 2 can be reduced by reducing the number of pins, and the size of the high-frequency power module 1 can be reduced. Can be achieved.
(実施形態 2 )  (Embodiment 2)
図 1 4は本発明の他の実施形態 （実施形態 2 ) である高周波パワーモ ジユールの封止体の一部を切り欠いた模式的平面図である。  FIG. 14 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 2) of the present invention, in which a sealing body is partially cut away.
本実施形態 2では、 実施形態 1において、 特定回路部 1 1 として 3個 の低雑音増幅器 （ L N A) 2 4を有する回路部以外に、 V C 0のうち、 高周波を扱う R F V C 04 4も特定回路部 1 1 としたものである。 従つ て、 R F V C 04 4の全てのグラン ド電極端子 9がワイヤ 1 0を介して リー ド （グラン ド リー ド） 7に接続され、 タブ 4にはワイヤを介して接 続しないものである。  In the second embodiment, in addition to the circuit unit having three low-noise amplifiers (LNAs) 24 as the specific circuit unit 11 in the first embodiment, among the VC 0s, the RFVC044 that handles high frequencies is also a specific circuit unit 1 1 Therefore, all the ground electrode terminals 9 of the RFVC 04 4 are connected to the lead (ground lead) 7 via the wire 10, and are not connected to the tab 4 via the wire.
半導体チップ 3の電極端子 9からワイヤ 1 0を介して リー ド 7に至る 配線において、 R F V C 04 4の 2本の信号配線の両側にグラン ド配線 が配置され、 信号配線の電磁シール ドがなされている。  In the wiring from the electrode terminal 9 of the semiconductor chip 3 to the lead 7 via the wire 10, ground wiring is arranged on both sides of the two signal wirings of the RFVC044, and the signal wiring is shielded electromagnetically. I have.
これによ り、 高周波信号を取り扱う特定回路部 1 1のグラン ド電位が 他の回路部のグラン ド電位から絶縁分離されることによ り、 クロス トー クが発生しなく なる。  As a result, the ground potential of the specific circuit unit 11 handling the high-frequency signal is insulated and separated from the ground potentials of the other circuit units, so that crosstalk does not occur.
(実施形態 3 )  (Embodiment 3)
図 1 5は本発明の他の実施形態 （実施形態 3 ) である高周波パワーモ ジュールの封止体の一部を切り欠いた模式的平面図である。  FIG. 15 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 3) of the present invention, in which a sealing body is partially cut away.
本実施形態 3では、 R F V C 04 4を外付け部品と し、 半導体チップ 3にはモノ リシックに形成しない例である。 このデュアルバン ド通信方 式では、 低雑音増幅器， ミキサ， V C O， シンセサイザ， I Q変調器/ 復調器， 分周器、 直交変調器等各回路部をモノ リシックに形成したもの である。 The third embodiment is an example in which the RFVC044 is an external component and is not formed monolithically on the semiconductor chip 3. This dual-band communication method In the formula, the low noise amplifier, mixer, VCO, synthesizer, IQ modulator / demodulator, frequency divider, quadrature modulator, and other circuit sections are monolithically formed.
受信系の二つのミキサはそれぞれ分周器によつて制御され、 またこの 分周器は外付け部品である R F V C 0から出力された高周波の信号を、 よ り低周波の信号に変換するための周波数変換回路である。  Each of the two mixers in the receiving system is controlled by a frequency divider, and this frequency divider converts the high-frequency signal output from the external component RFVC0 into a lower-frequency signal. It is a frequency conversion circuit.
従って、 本実施形態 3では、 図 1 5 に示すように、 半導体装置 1の外 側に R F V C 0 4 4が存在し、 R F V C 0 4 4の信号配線が 2本半導体 装置 1のリー ド 7に接続される。 そして、 R F V C 0 4 4に接続される 二つのリー ド 7からワイヤ 1 0 を介して半導体チップ 3の電極端子 9に 至る 2本の信号配線の両側の電極端子 9 と リー ド 7 とはワイヤ 1 0を介 して接続されている。 この 2本の信号配線の両側の電極端子 9はグラン ド電極端子であり、 このグラン ド電極端子にワイヤ 1 0 を介して接続さ れる リー ド 7 もグラン ド リー ドとなっている。 これによ り、 実施形態 2 の場合と同様に高周波信号を扱う信号配線も電磁シール ドされるととも に、 半導体チップ 3における他の回路部とはグラン ド電位が独立した構 成になっている。  Therefore, in the third embodiment, as shown in FIG. 15, the RFVC044 exists outside the semiconductor device 1, and the signal wiring of the RFVC044 is connected to the lead 7 of the two semiconductor devices 1. Is done. Then, the electrode terminals 9 on both sides of the two signal wires from the two leads 7 connected to the RFVC 0 4 to the electrode terminals 9 of the semiconductor chip 3 via the wires 10 and the leads 7 are connected to the wires 1 Connected via 0. The electrode terminals 9 on both sides of the two signal wirings are ground electrode terminals, and the leads 7 connected to the ground electrode terminals via the wires 10 are also ground leads. As a result, similarly to the case of the second embodiment, the signal wiring for handling the high-frequency signal is electromagnetically shielded, and the ground potential is independent of other circuit portions in the semiconductor chip 3. I have.
本実施形態 3においても、 実施形態 2 と同様に、 R F V C 0 4 4のグ ラン ド電位の変動に伴う障害は発生しなくなる。  In the third embodiment as well, as in the second embodiment, no trouble occurs due to the fluctuation of the ground potential of the RFVC04.
(実施形態 4 )  (Embodiment 4)
図 1 6及び図 1 Ίは本発明の他の実施形態 （実施形態 4 ) である高周 波パワーモジュールに係わる図であり、 図 1 6は高周波パワーモジュ一 ルの封止体の一部を切り欠いた模式的平面図、 図 1 7は高周波パワーモ ジュールの模式的断面図である。  FIGS. 16 and 1Ί relate to a high-frequency power module according to another embodiment (Embodiment 4) of the present invention. FIG. 16 shows a part of a sealed body of the high-frequency power module. FIG. 17 is a schematic cross-sectional view of the high-frequency power module.
本実施形態 4は、 共通のグラン ド端子となるタブ 4 と、 グラン ド電位 とされる リー ド 7を導電性のヮィャ 1 0 bで電気的に接続し、 リー ド 7 をもグラン ド外部電極端子とするものである。 本実施形態 4の半導体装 置 1では、 タブ 4の裏面が封止体 2の裏面（実装面）から露出するため、 タブ 4をグラン ド用外部電極端子として使用できるとともに、 タブ 4に ワイヤ 1 O bを介して接続されたリー ド 7 もグラン ド用外部電極端子と しても使用することができる。 In the fourth embodiment, a tab 4 serving as a common ground terminal and a lead 7 serving as a ground potential are electrically connected by a conductive wire 10b. Are also used as ground external electrode terminals. In the semiconductor device 1 according to the fourth embodiment, since the back surface of the tab 4 is exposed from the back surface (mounting surface) of the sealing body 2, the tab 4 can be used as an external electrode terminal for ground, and the wire 4 is connected to the tab 4. The lead 7 connected via Ob can also be used as the ground external electrode terminal.
図 1 8は本実施形態 4の変形例である。 即ち、 この変形例では、 タブ 4 の裏面側をハーフエッチングして薄く してあることから、 片面モール ド 時、タブ 4の裏面側にも樹脂が回り込むことから、図 1 8に示すように、 夕プ 4はその裏面も封止体から露出することなく、 完全に封止体 2内に 埋没する。 このような構造の場合、 タブ 4がワイヤ 1 O bを介して リー ド 7に接続されていることから、 このリード 7をグラン ド用外部電極端 子として使用することができる。 なお、 タブを封止体内に埋没させる別 の構造としては、 タブ吊り リー ドの途中で一段高く階段状に折り曲げる 構造でもよい。 FIG. 18 shows a modification of the fourth embodiment. That is, in this modification, the back surface of the tab 4 is half-etched to be thin, so that the resin also wraps around the back surface of the tab 4 during the single-sided molding, as shown in FIG. The backing 4 is completely buried in the sealing body 2 without its back surface also being exposed from the sealing body. In the case of such a structure, since the tab 4 is connected to the lead 7 via the wire 1 Ob, the lead 7 can be used as a ground external electrode terminal. As another structure in which the tab is embedded in the sealing body, a structure in which the tab is bent one step higher in the middle of the tab suspension lead may be used.
図 1 8に記載の構成においては、 ワイヤ 1 0 aを介してタブ 4に接続す るグラン ド電位供給用の電極端子 9の数に比較して、 ワイヤ 1 0 bを介 してタブと接続する リー ド 7の数を少なくする事によ り、 封止体 2の周 囲に沿って配列される リード 7の本数を少なく し、 装置を小型化するこ とができるとともに、 タブ 4の裏面が封止体 2によって覆われているた めに、 本実施例における半導体装置 1 を配線基板上に実装した際に半導 体装置 1の下の領域も配線基板上の配線を配置するための領域として利 用できるという利点がある。 従って、 本実施例においては、 半導体装置 1の小型化に併せて、 配線基板上の実装密度を向上できるという利点が ある。 In the configuration shown in Fig. 18, compared to the number of electrode terminals 9 for supplying the ground potential connected to the tab 4 via the wire 10a, the connection to the tab via the wire 10b is made. By reducing the number of leads 7, the number of leads 7 arranged along the periphery of the sealing body 2 can be reduced, the device can be downsized, and the back surface of the tab 4 can be reduced. Since the semiconductor device 1 in the present embodiment is mounted on the wiring board, the area under the semiconductor device 1 is also used for arranging the wiring on the wiring board because the semiconductor device 1 in this embodiment is covered with the sealing body 2. There is an advantage that it can be used as an area. Therefore, in the present embodiment, there is an advantage that the mounting density on the wiring board can be improved along with the miniaturization of the semiconductor device 1.
以上本発明者によってなされた発明を実施形態に基づき具体的に説 明したが、 本発明は上記実施形態に限定されるものではなく、 その要旨 を逸脱しない範囲で種々変更可能であることはいうまでもない。 Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and the gist thereof is as follows. It goes without saying that various changes can be made without departing from the scope of the present invention.
前記実施の形態では、 共通化し、 または分離する電源電位につい てグラ ン ド電位についてのみ記載したが、 本発明の適用の範囲はグ ラ ン ド電位とそれに関連する構成についてのみに限られる物ではな く、 発明を適用する上で適当な電源電位 （第 1の電位）、 例えば電極 の共通化をする事によって よ り リー ド 7の数を少な く する事ができ る電源電位に着目 し、 その電源電位を供給するための電極端子 9や リ一 ド 7の構成に対して本発明を適用 しても良い。  In the above-described embodiment, only the ground potential is described as the power supply potential to be shared or separated. However, the scope of the present invention is limited to only the ground potential and the configuration related thereto. Instead, the present invention focuses on a power supply potential (first potential) suitable for applying the invention, for example, a power supply potential that can reduce the number of leads 7 by using a common electrode. The present invention may be applied to the configuration of the electrode terminal 9 or the lead 7 for supplying the power supply potential.
前記実施形態では、 Q F N型の半導体装置の製造に本発明を適用した 例について説明したが、 例えば、 S 0 N型半導体装置の製造に対しても 本発明を同様に適用でき、 同様の効果を有することができる。 さらに、 本発明はノ ンリー ド型半導体装置に限定されることなく、 例えば、 封止 体 2の周囲に沿って、 ガルウィ ング形状に折り曲げられたリー ドが突出 する Q F P (Quad Flat Package)や S O P (Small Outline Package)と呼 ばれる半導体装置についても同様に適用する事ができるが、 前記 Q F P や S O Pに比較して、 封止体 2の周囲における リー ドの突出量が小さい Q F N型の構造を採用した方が、 装置の小型化を達成する上ではよ り好 ましい。  In the above-described embodiment, an example in which the present invention is applied to the manufacture of a QFN type semiconductor device has been described. However, for example, the present invention can be similarly applied to the manufacture of an SON type semiconductor device, and the same effects can be obtained. Can have. Further, the present invention is not limited to a non-lead type semiconductor device. For example, a QFP (Quad Flat Package) or SOP in which a lead bent into a gull-wing shape protrudes along the periphery of the sealing body 2. The same can be applied to a semiconductor device called (Small Outline Package) .However, compared to the QFP or SOP, a QFN type structure with a smaller lead protrusion around the encapsulation 2 is adopted. It is more preferable to achieve miniaturization of the equipment.
本願において開示される発明のう ち代表的なものによって得られる 効果を簡単に説明すれば、 下記のとおりである。  The effects obtained by the representative inventions disclosed in the present application will be briefly described as follows.
( 1 ) クロス トークが起き難いダウンボンディ ング構造の半導体装置 を提供することができる。  (1) It is possible to provide a semiconductor device having a down-bonding structure in which crosstalk hardly occurs.
( 2 ) 低雑音増幅器や R F V C 0等の特定回路部におけるグラン ド電 位が残りの回路部のグラン ド電位の影響を受け難い、 低雑音増幅器， ミ キサ， V CO, シンセサイザ， I Q変調器/復調器， 直交変調器等各回 路部をモノ リシックに形成した半導体素子を組み込んだ高周波パワーモ ジュールを提供することができる。 (2) The ground potential in a specific circuit section such as a low-noise amplifier or RFVC0 is not easily affected by the ground potential in the remaining circuit sections. A high-frequency power module incorporating a semiconductor device, such as a demodulator and a quadrature modulator, in which each circuit is monolithically formed. Joules can be provided.
( 3 ) 低雑音増幅器や R F V C 0等の特定回路部におけるグラン ド電 位が残りの回路部のグラン ド電位の影響を受け難い、 低雑音増幅器， ミ キサ， V C O， シンセサイザ， I Q変調器/復調器， 直交変調器等各回 路部をモノ リ シックに形成した半導体素子を組み込んだダウンボンディ ング構造でかつノ ンリー ド型の高周波パワーモジュールを提供すること ができる。  (3) The ground potential in a specific circuit such as a low-noise amplifier or RFVC0 is not easily affected by the ground potential in the remaining circuits. Low-noise amplifiers, mixers, VCOs, synthesizers, IQ modulators / demodulators It is possible to provide a non-bonded high-frequency power module with a down-bonded structure incorporating a semiconductor element in which each circuit section such as a modulator and a quadrature modulator is formed monolithically.
( 4 ) 低雑音増幅器や R F V C 0等の特定回路部におけるグラン ド電 位が残りの回路部のグラン ド電位の影響を受け難い、 低雑音増幅器， ミ キサ， V C O， シンセサイザ， I Q変調器/復調器， 直交変調器等各回 路部をモノ リシックに形成した半導体素子を組み込んだ小型 · 軽量の高 周波パワーモジュールを提供することができる。  (4) The ground potential in a specific circuit such as a low-noise amplifier or RFVC0 is not easily affected by the ground potential in the remaining circuits. Low-noise amplifiers, mixers, VCOs, synthesizers, IQ modulators / demodulators It is possible to provide a compact and lightweight high-frequency power module incorporating a semiconductor device in which each circuit section such as a modulator and a quadrature modulator is monolithically formed.
( 5 ) 雑音の少ない良好な通話が可能となる無線通信装置を提供する ことができる。  (5) It is possible to provide a wireless communication device capable of making a good call with little noise.
( 6 ) 雑音の少ない良好な通話が可能となる複数の通信方式に対処で きる無線通信装置を提供することができる。 産業上の利用可能性  (6) It is possible to provide a wireless communication device that can cope with a plurality of communication systems that enable good communication with little noise. Industrial applicability
以上のように、 本発明の半導体装置は携帯電話機等の無線通信装置に 使用される。 特に、 通信システムが複数系統の携帯電話機において、 低 雑音増幅器のような入力信号が極めて微弱な信号を処理する回路部のグ ラン ド電極端子を共通グラン ド電位となる夕ブに接続することなく、 全 て独立したリー ドに接続してあることから、 一系統の通信システムを使 用中、 他の系統の通信システムとの間でのクロス トークが発生しなくな り、 良好な通話が可能を高周波パワーモジュールを提供することができ る。  As described above, the semiconductor device of the present invention is used for a wireless communication device such as a mobile phone. In particular, in a mobile phone having a plurality of communication systems, the ground electrode terminal of the circuit section that processes an extremely weak input signal such as a low-noise amplifier is not connected to the common ground potential. , Because all are connected to independent leads, when using one communication system, there is no cross talk with other communication systems and good communication is possible Thus, a high-frequency power module can be provided.

Claims

請 求 の 範 囲 The scope of the claims
1 . 絶縁性樹脂からなる封止体と、 1. a sealing body made of an insulating resin;
前記封止体の周囲に沿って、 前記封止体の内外に亘つて設けられる複数 のリードと、 A plurality of leads provided along the periphery of the sealing body, inside and outside the sealing body,
主面および裏面を有するタブと、 A tab having a main surface and a back surface;
主面および裏面を有しており、 その主面上に複数の電極端子と、 それそ れが複数の半導体素子によって構成される複数の回路部とを有する半導 体チップと、 A semiconductor chip having a main surface and a back surface, having a plurality of electrode terminals on the main surface, and a plurality of circuit portions each including a plurality of semiconductor elements;
前記複数の電極端子と前記リ一ドとを接続する複数の導電性のワイャと. 前記複数の電極端子に第 1の電位を供給するために、 前記複数の電極端 子と前記タブの主面とを接続する複数の導電性のワイヤとを有する半導 体装置であって、 A plurality of conductive wires for connecting the plurality of electrode terminals and the lead; and a main surface of the plurality of electrode terminals and the tab for supplying a first potential to the plurality of electrode terminals. And a plurality of conductive wires for connecting
前記半導体チップの裏面は前記タブの主面上に固定されており、 前記複数の回路部は、 第 1の回路部、 第 2の回路部を含んでおり、 前記複数の電極端子は、 前記第 1の回路部に外部信号を入力するための 第 1の電極端子と、 前記第 1の回路部に前記第 1の電位を供給するため の第 2の電極端子と、 前記第 2の回路部と接続する第 3の電極端子と、 前記第 2の回路部に前記第 1の電位を供給するための第 4の電極端子と を有しており、 The back surface of the semiconductor chip is fixed on the main surface of the tub, the plurality of circuit units include a first circuit unit and a second circuit unit, and the plurality of electrode terminals are A first electrode terminal for inputting an external signal to one circuit portion; a second electrode terminal for supplying the first potential to the first circuit portion; and the second circuit portion. A third electrode terminal to be connected, and a fourth electrode terminal for supplying the first potential to the second circuit portion,
前記複数のリードは、 第 1のリードと、 第 2のリードと、 前記第 1のリ 一ドと第 2のリードの間に配置された第 3のリードとを含んでおり、 前記第 1の電極端子は導電性のワイヤを介して前記第 1のリー ドと接続 しており、 The plurality of leads include a first lead, a second lead, and a third lead disposed between the first lead and the second lead. The electrode terminal is connected to the first lead via a conductive wire,
前記第 2の電極端孑は導電性のワイヤを介して前記第 3のリー ドと接続 しており、 前記第 3の電極端子は導電性のワイヤを介して前記第 2のリー ドと接続 しており、 The second electrode terminal is connected to the third lead via a conductive wire; The third electrode terminal is connected to the second lead via a conductive wire,
前記第 4の電極端子は導電性のワイャを介して前記夕ブと接続しており . 前記第 3のリー ドと前記タブは分離されていることを特徴とする半導体 装置。 The fourth electrode terminal is connected to the tab via a conductive wire. The semiconductor device is characterized in that the third lead and the tab are separated.
2 . 前記第 1の回路部は前記第 1のリー ド、 および前記第 1の電極端 子を介して入力される外部信号を増幅するための増幅回路であることを 特徴とする請求の範囲第 1項記載の半導体装置。  2. The first circuit unit is an amplifier circuit for amplifying an external signal input through the first lead and the first electrode terminal. 2. The semiconductor device according to claim 1.
3 . 前記第 2の回路部は、 前記第 1 の回路部によって増幅された信号 を処理する機能の少なく とも一部を有することを特徴とする請求の範囲 第 2項記載の半導体装置。  3. The semiconductor device according to claim 2, wherein the second circuit unit has at least a part of a function of processing a signal amplified by the first circuit unit.
4 . 前記第 1の回路部は、 無線信号がアンテナを介して変換された電 気信号を増幅するための回路であるこ とを特徴とする請求の範囲第 1項 に記載の半導体装置。  4. The semiconductor device according to claim 1, wherein the first circuit unit is a circuit for amplifying an electric signal obtained by converting a radio signal via an antenna.
5 . 前記第 2の回路部は、 前記アンテナを介して無線信号として出力 するための電気信号を処理するための回路の少なく とも一部を構成する ことを特徴とする請求の範囲第 1項に記載の半導体装置。  5. The second circuit unit according to claim 1, wherein the second circuit unit constitutes at least a part of a circuit for processing an electric signal to be output as a wireless signal via the antenna. 13. The semiconductor device according to claim 1.
6 . 前記半導体チップは、 その主面上に前記第 2の接続端子と前記第 1の回路部を接続するための第 1の配線と、 前記第 4の接続端子と第 2 の回路部を接続するための第 2の配線とを有しており、 前記半導体チッ プの主面上において、 前記第 1の配線と第 2の配線は絶縁されているこ とを特徴とする請求の範囲第 4項に記載の半導体装置。  6. The semiconductor chip has, on its main surface, a first wiring for connecting the second connection terminal and the first circuit portion, and a connection between the fourth connection terminal and the second circuit portion. 5. The semiconductor device according to claim 4, further comprising: a second wiring for performing the operation, wherein the first wiring and the second wiring are insulated on a main surface of the semiconductor chip. 13. The semiconductor device according to item 9.
7 . 前記半導体チップの主面上において、 前記第 1の接続端子から前 記第 1の回路部までの配線長さは、 前記第 3の接続端子から前記第 2の 回路部までの配線長さよ り も小さいことを特徴とする請求の範囲第 4項 に記載の半導体装置。 7. On the main surface of the semiconductor chip, the wiring length from the first connection terminal to the first circuit portion is equal to the wiring length from the third connection terminal to the second circuit portion. The semiconductor device according to claim 4, wherein the semiconductor device is smaller than the semiconductor device.
8 . 前記タブの裏面は、 前記封止体の外部に露出していることを特徴 とする請求の範囲第 4項に記載の半導体装置。 8. The semiconductor device according to claim 4, wherein a back surface of the tab is exposed outside the sealing body.
9 . 前記タブは、 単数または複数の導電性のワイヤを介して、 単数ま たは複数の前記リー ドと電気的に接続しており、 前記タブと接続する リ 一ドの数は、 前記タブと接続する電極端子の数に比べて少ないことを特 徴とする請求の範囲第 4項に記載の半導体装置。  9. The tab is electrically connected to one or more leads via one or more conductive wires, and the number of leads connected to the tab is 5. The semiconductor device according to claim 4, wherein the number is smaller than the number of electrode terminals connected to the semiconductor device.
1 0 . 前記封止体は実装面を有しており、 前記複数のリードは、 前記 封止体の実装面に露出することを特徴とする請求の範囲第 4項に記載の 半導体装置。  10. The semiconductor device according to claim 4, wherein the sealing body has a mounting surface, and the plurality of leads are exposed on a mounting surface of the sealing body.
1 1 . 前記タブは、 前記封止体の実装面に露出することを特徴とする 請求の範囲第 1 0項に記載の半導体装置。  11. The semiconductor device according to claim 10, wherein the tab is exposed on a mounting surface of the sealing body.
1 2 . 前記第 1の回路部は前記第 1のリー ド、 および前記第 1の電極 端子を介して入力される外部信号の周波数を小さ くするための周波数変 換回路であることを特徴とする請求の範囲第 1項記載の半導体装置。  12. The first circuit portion is a frequency conversion circuit for reducing the frequency of an external signal input via the first lead and the first electrode terminal. The semiconductor device according to claim 1, wherein
1 3 . 前記複数の回路部は、 発振器を含んでおり、 前記発振器に前記 第 1の電位を供給するための電極端子は、 導電性のワイヤを介して前記 夕ブと接続している事を特徴とする請求の範囲第 1項記載の半導体装置, 13. The plurality of circuit units include an oscillator, and an electrode terminal for supplying the first potential to the oscillator is connected to the node via a conductive wire. The semiconductor device according to claim 1, wherein
1 4 . 前記半導体チップは、 その主面上に前記第 2の接続端子と前記 第 1の回路部を接続するための第 1の配線と、 前記第 4の接続端子と第 2の回路部を接続するための第 2の配線とを有しており、 前記半導体チ ップの主面上において、 前記第 1の配線と第 2の配線は絶縁されている ことを特徴とする請求の範囲第 1項に記載の半導体装置。 14. The semiconductor chip includes, on its main surface, a first wiring for connecting the second connection terminal and the first circuit portion, and a fourth connection terminal and a second circuit portion. And a second wiring for connection, wherein the first wiring and the second wiring are insulated on a main surface of the semiconductor chip. 2. The semiconductor device according to item 1.
1 5 . 前記半導体チップの主面上において、 前記第 1の接続端子から 前記第 1の回路部までの配線長さは、 前記第 3の接続端子から前記第 2 の回路部までの配線長さよ り も小さいことを特徴とする請求の範囲第 1 項に記載の半導体装置。 15. On the main surface of the semiconductor chip, the wiring length from the first connection terminal to the first circuit portion is equal to the wiring length from the third connection terminal to the second circuit portion. 2. The semiconductor device according to claim 1, wherein said semiconductor device is smaller than said semiconductor device.
1 6 . 前記タブの裏面は、 前記封止体の外部に露出していることを特 徴とする請求の範囲第 1項に記載の半導体装置。 16. The semiconductor device according to claim 1, wherein a back surface of the tab is exposed outside the sealing body.
1 7 . 前記タブは、 単数または複数の導電性のワイヤを介して、 単数 または複数の前記リー ドと電気的に接続してお り、 前記タブと接続する リー ドの数は、 前記タブと接続する電極端子の数に比べて少ないことを 特徴とする請求の範囲第 1項に記載の半導体装置。  17. The tab is electrically connected to one or more leads via one or more conductive wires, and the number of leads connected to the tab is 2. The semiconductor device according to claim 1, wherein the number is smaller than the number of electrode terminals to be connected.
1 8 . 前記封止体は実装面を有しており、 前記複数のリー ドは、 前記 封止体の実装面に露出することを特徴とする請求の範囲第 1項に記載の 半導体装置。  18. The semiconductor device according to claim 1, wherein the sealing body has a mounting surface, and the plurality of leads are exposed on a mounting surface of the sealing body.
1 9 . 前記タブは、 前記封止体の実装面に露出することを特徴とする 請求の範囲第 1 8項に記載の半導体装置。  19. The semiconductor device according to claim 18, wherein the tab is exposed on a mounting surface of the sealing body.
2 0 . 請求の範囲第 1項に記載の半導体装置を有する無線通信装置で あって、 無線信号を電気信号に変換するためのアンテナと、 前記アンテ ナによって変換された電気信号を前記第 1のリー ドに入力するための配 線を有する事を特徴とする無線通信装置。  20. A wireless communication device having the semiconductor device according to claim 1, wherein an antenna for converting a radio signal to an electric signal, and an electric signal converted by the antenna are transmitted to the first communication device. A wireless communication device having a wiring for inputting to a lead.
2 1 . 絶縁性樹脂からなる封止体と、  2 1. a sealing body made of an insulating resin;
前記封止体の周囲に沿って、 前記封止体の内外に亘つて設けられる複数 のリー ドと、 A plurality of leads provided along the periphery of the sealing body and inside and outside the sealing body;
主面および裏面を有するタブと、 A tab having a main surface and a back surface;
主面および裏面を有しており、 その主面上に複数の電極端子と、 それそ れが複数の半導体素子によって構成される複数の回路部とを有する半導 体チップと、 A semiconductor chip having a main surface and a back surface, having a plurality of electrode terminals on the main surface, and a plurality of circuit portions each including a plurality of semiconductor elements;
前記複数の電極端子と前記リ一ドとを接続する複数の導電性のワイヤと、 前記複数の電極端子に第 1の電位を供給するために、 前記複数の電極端 子と前記夕ブの主面とを接続する複数の導電性のヮィャとを有する半導 体装置であって、 前記半導体チップの裏面は前記タブの主面上に固定されており、 前記複数の回路部は、 無線信号がアンテナを介して変換された電気信号 を増幅するための第 1の増幅回路部、 および第 2の増幅回路部を含んで おり、 A plurality of conductive wires for connecting the plurality of electrode terminals and the lead; and a plurality of electrode terminals and a main terminal of the connector for supplying a first potential to the plurality of electrode terminals. A semiconductor device comprising: a plurality of conductive keys for connecting to a surface; A back surface of the semiconductor chip is fixed on a main surface of the tab; the plurality of circuit units are a first amplifier circuit unit for amplifying an electric signal obtained by converting a radio signal via an antenna; and Including a second amplifier circuit section,
前記複数の電極端子は、 前記第 1の増幅回路部に外部信号を入力するた めの第 1の電極端子と、 前記第 1の増幅回路部に前記第 1の電位を供給 するための第 2の電極端子と、 前記第 2の増幅回路部に外部信号を入力 するための第 3の電極端子とを有しており、 The plurality of electrode terminals include a first electrode terminal for inputting an external signal to the first amplifier circuit unit, and a second electrode terminal for supplying the first potential to the first amplifier circuit unit. And a third electrode terminal for inputting an external signal to the second amplifier circuit section,
前記複数のリー ドは、 第 1のリー ドと、 第 2のリー ドと、 前記第 1のリ —ドと第 2のリー ドの間に配置された第 3のリー ドとを含んでおり、 前記第 1の接続端子は導電性のワイャを介して前記第 1のリー ドと接続 しており、 The plurality of leads include a first lead, a second lead, and a third lead disposed between the first and second leads. The first connection terminal is connected to the first lead via a conductive wire;
前記第 2の接続端子は導電性のワイヤを介して前記第 3のリー ドと接続 しており、 The second connection terminal is connected to the third lead via a conductive wire,
前記第 3の接続端子は導電性のワイャを介して前記第 2のリー ドと接続 しており、 The third connection terminal is connected to the second lead via a conductive wire,
前記第 3のリー ドと前記タブは分離されていることを特徴とする半導体 A semiconductor, wherein the third lead and the tab are separated from each other;
2 2 . 前記第 2の増幅回路部は、 前記第 1の増幅回路部とは異なる周 波数帯の外部信号を増幅するための回路部であることを特徴とする請求 の範囲第 2 1項に記載の半導体装置。 22. The second amplifier circuit according to claim 21, wherein the second amplifier circuit is a circuit for amplifying an external signal in a frequency band different from that of the first amplifier circuit. 13. The semiconductor device according to claim 1.
2 3 . 前記複数の回路部は、 発振回路部を含んでおり、 前記発振回路 部に前記第 1 の電位を供給するための接続端子は、 導電性のワイヤを介 して前記タブと接続していることを特徴とする請求の範囲第 2 2項に記 載の半導体装置。  23. The plurality of circuit units include an oscillation circuit unit, and a connection terminal for supplying the first potential to the oscillation circuit unit is connected to the tab via a conductive wire. 23. The semiconductor device according to claim 22, wherein:
PCT/JP2002/004339 2002-04-30 2002-04-30 Semiconductor device and radio communication apparatus WO2003094236A1 (en)

Priority Applications (19)

Application Number Priority Date Filing Date Title
PCT/JP2002/004339 WO2003094236A1 (en) 2002-04-30 2002-04-30 Semiconductor device and radio communication apparatus
AU2003235967A AU2003235967A1 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
KR1020047017429A KR100993276B1 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
KR1020087009547A KR100993277B1 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
CNA2009101340438A CN101515579A (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
US10/512,459 US7425756B2 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
CNB2007101273468A CN100536123C (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
CNA2009101340423A CN101515578A (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
JP2004502352A JP4351150B2 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
KR1020087009552A KR100993579B1 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
CNB038096366A CN100380651C (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
PCT/JP2003/005475 WO2003094232A1 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
US11/455,157 US7312511B2 (en) 2002-04-30 2006-06-19 Semiconductor device with electrically isolated ground structures
US11/455,171 US20060237831A1 (en) 2002-04-30 2006-06-19 Semiconductor device and electronic device
US12/032,690 US7937105B2 (en) 2002-04-30 2008-02-17 Semiconductor device and electronic device
US12/033,061 US7777309B2 (en) 2002-04-30 2008-02-19 Amplifier chip mounted on a lead frame
JP2009142145A JP5080532B2 (en) 2002-04-30 2009-06-15 Semiconductor device
US13/094,383 US8126501B2 (en) 2002-04-30 2011-04-26 Semiconductor device and electronic device
JP2012128107A JP5473026B2 (en) 2002-04-30 2012-06-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2002/004339 WO2003094236A1 (en) 2002-04-30 2002-04-30 Semiconductor device and radio communication apparatus

Publications (1)

Publication Number Publication Date
WO2003094236A1 true WO2003094236A1 (en) 2003-11-13

Family

ID=29287943

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/004339 WO2003094236A1 (en) 2002-04-30 2002-04-30 Semiconductor device and radio communication apparatus

Country Status (2)

Country Link
CN (3) CN101515578A (en)
WO (1) WO2003094236A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1889243A2 (en) * 2005-05-24 2008-02-20 Radiall AEP, Inc. Common integrated circuit for multiple antennas and methods

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10880991B2 (en) * 2018-04-04 2020-12-29 Marvell Asia Pte, Ltd. Apparatus and methods for enhancing signaling bandwidth in an integrated circuit package
CN115940872B (en) * 2022-12-12 2024-03-08 武汉润晶汽车电子有限公司 Base for crystal oscillator and crystal oscillator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04130654A (en) * 1990-09-20 1992-05-01 Hitachi Ltd Resin sealing type semiconductor device
JP2001267484A (en) * 2000-03-14 2001-09-28 Hitachi Ltd Semiconductor device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3732987B2 (en) * 1999-12-28 2006-01-11 株式会社ルネサステクノロジ Semiconductor device
JP4319339B2 (en) * 2000-08-30 2009-08-26 株式会社ルネサステクノロジ Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04130654A (en) * 1990-09-20 1992-05-01 Hitachi Ltd Resin sealing type semiconductor device
JP2001267484A (en) * 2000-03-14 2001-09-28 Hitachi Ltd Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1889243A2 (en) * 2005-05-24 2008-02-20 Radiall AEP, Inc. Common integrated circuit for multiple antennas and methods
EP1889243A4 (en) * 2005-05-24 2010-01-27 Radiall Aep Inc Common integrated circuit for multiple antennas and methods

Also Published As

Publication number Publication date
CN101093823A (en) 2007-12-26
CN100536123C (en) 2009-09-02
CN101515578A (en) 2009-08-26
CN101515579A (en) 2009-08-26

Similar Documents

Publication Publication Date Title
KR100993277B1 (en) Semiconductor device and electronic device
US7312511B2 (en) Semiconductor device with electrically isolated ground structures
US8472911B2 (en) Wireless communication system
US8115295B2 (en) Semiconductor device
US20110183474A1 (en) Electronic device and manufacturing method of the same
JP4137059B2 (en) Electronic device and semiconductor device
US20070202832A1 (en) Wireless communication system
WO2003094236A1 (en) Semiconductor device and radio communication apparatus
TWI283471B (en) Semiconductor device and electronic apparatus
JP3576465B2 (en) High frequency semiconductor device and portable communication device using the same
JP2000232326A (en) High frequency power amplifying device and radio communication equipment

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP