CN100536123C - Semiconductor device and electronic device - Google Patents

Semiconductor device and electronic device Download PDF

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Publication number
CN100536123C
CN100536123C CNB2007101273468A CN200710127346A CN100536123C CN 100536123 C CN100536123 C CN 100536123C CN B2007101273468 A CNB2007101273468 A CN B2007101273468A CN 200710127346 A CN200710127346 A CN 200710127346A CN 100536123 C CN100536123 C CN 100536123C
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China
Prior art keywords
lead
electrode
wire
semiconductor device
mounting portion
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Expired - Lifetime
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CNB2007101273468A
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Chinese (zh)
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CN101093823A (en
Inventor
団野忠敏
土屋勉
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NEC Electronics Corp
Renesas Electronics Corp
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Renesas Technology Corp
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Publication of CN101093823A publication Critical patent/CN101093823A/en
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Publication of CN100536123C publication Critical patent/CN100536123C/en
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Abstract

This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab. In such a semiconductor device, a circuit formed in the semiconductor element in a monolithic manner is comprised of a plurality of circuit parts and, in a specified circuit part (a low noise amplifier) which forms a portion of the circuit parts, all grounding electrode terminals out of electrode terminals of the semiconductor element are not connected to the tab through wires but are connected with the leads through wires.

Description

Semiconductor device and electronic equipment
The application is to be on April 28th, 2003 applying date, and application number is 03809636.6, and title is divided an application for the patent application of " semiconductor device and electronic equipment ".
Technical field
The present invention relates to semiconductor device and electronic equipment, and can effectively be applied to hf power module (semiconductor device) for example and include the technology of the Wireless Telecom Equipment (electronic equipment) of the HFS analog signal processing IC that comprises the low noise amplifier (LNA:Low Noise Amplifier) that is used for the amplifying stage small-signal.
Background technology
Mobile communication equipment (portable terminal) such as mobile phone is set for a plurality of communication systems of processing.That is, in the transmitter/receiver unit (front end) of mobile phone, include a plurality of Circuits System, to carry out the emission/reception of a plurality of communication systems.For example, as the method that allows to call out between the different mobile phone of communication means (system) (for example, cell phone), known have a communicating in two frequency bands method.For the double frequency-band method, known have GSM (global system for mobile communications) that adopt to use 880 to 915MHz carrier frequency bands and a double frequency-band method of using 1710 to 1785MHz carrier frequency bands and being used for the DCS-1800 (Digital Cellular System 1800) of the high frequency power amplifier of double frequency-band.
In addition, in the open No.Hei 11 (1999)-186921 of Japanese unexamined patent publication No. (not examining open on July 9th, 1999) for public inspection, disclosed a kind of multiband mobile communicating equipment, it can be used for (the personal communication network (PCN): DCS-1800) such as PCN, PCS (personal communication service DCS-1900), the mobile telephone system of GSM etc.
In addition, at the front end of mobile phone, the HFS analog signal processing circuit that will be used for GSM forms module.For example, known RF (radio frequency) power model that use MOSFET (mos field effect transistor) is arranged, be used for double frequency-band or three frequency band GSM.
The double frequency-band method is handled the signal such as two communication systems of GSM method and DCS-1800 method, and three frequency band methods are handled such as the double frequency-band method, the signal of three communication systems of DCS (Digital Cellular System) 1800 and PCS 1900 methods.As GSM, include GSM 900 or GSM 850.
In addition, in hf power module, include by with LNA, blender, PLL (phase-locked loop) synthesizer adds the PGA (programmable gain amplifier) of calibration automatically, the IQ modulator/demodulator, the biasing PLL, VCC (voltage controlled oscillator) etc.s with monolithic form integrated and formation individual pieces of semiconductor elements.
In addition, in the open No.2002-76235 of Japanese unexamined patent publication No., disclosed a kind of double frequency-band emission/reception semiconductor integrated circuit.The differential low noise amplifier that is included in the double frequency-band emission/reception semiconductor integrated circuit (is made up of two Unit Amplifier, and input signal is inverting each other in these two Unit Amplifier) comprise a pair of input terminal and a pair of outlet terminal, wherein, the grounding pin of the amplifier that is formed by the pair of differential amplifier closely is provided with each other.In addition, the input pin of same amplifier and grounding pin closely are provided with each other.Therefore, this patent documentation has disclosed the technology that is used to improve the differential amplifier gain, and is wherein, inverting each other by the signal that makes adjacent leads, and, the impedance that puts on emitter is reduced by using the converter knot (transformerjunction) between the pin.
On the other hand, for easy to carry, mobile phone miniaturization and weight are reduced.Thereby, electronic unit miniaturization and weight such as hf power module etc. are reduced.
There is the multiple semiconductor device that depends on encapsulation mode, and wherein a kind of as these semiconductor device, known have a kind of do not have the lead-in wire type semiconductor device, in this device, the back of the body surface of the seal of making at insulating resin (encapsulation) exposes lead-in wire (external electrode terminal), and avoids outstanding from the side surface of seal than long lead.
As there not being lead-in wire type semiconductor device, can list along two opposite side exposed leads on seal back of the body surface SON (not having the little gabarit encapsulation of lead-in wire) and at the QFN (not having the lead-in wire quad-flat-pack) of the four limit exposed leads on seal back of the body surface.For example, in the open No.2001-313363 of Japanese unexamined patent publication No., the nothing lead-in wire type semiconductor device of having described a kind of miniaturization and having gone between crooked.
The resin-encapsulated semiconductor device of describing in the document has following structure.Promptly, semiconductor device comprises, island (island) with wafer pad that semiconductor chip is fixed to, the lead attachment that are connected to lead, wherein, semiconductor chip is fixed in wafer pad, and each electrode terminal of semiconductor chip is connected with the lead attachment on lead-in wire and island.Between wafer pad and lead attachment, be limited with the gap, peel off or block to stop the wire bonds that causes because of thermal stress.In this structure, by using lead the grounding terminals of semiconductor chip is connected with the island, can as ground lead semiconductor chip and printed circuit board (PCB) etc. be connected by the use island.
In addition, in the open No.Hei 11 (1999)-251494 of Japanese unexamined patent publication No., described a kind of high-frequency device, wherein, be used for mobile phone etc. and the pin configuration of semiconductor element mounting parts ground connection is adopted the gull wing (gull wing) type.In this technology, use lead that the electrode of semiconductor element is connected with lead-in wire, wafer pad is used as grounding electrode, thereby, with lead the electrode of semiconductor element is connected to each other with the semiconductor installing component (time engage (down-bonding)).For realizing down engaging, the semiconductor element installing component is provided with, makes that the semiconductor element mounting parts are bigger than semiconductor element, and under installment state, the periphery of semiconductor element mounting parts is projected into the outside of semiconductor element, and lead links to each other with these parts.
Applicant of the present invention studies a kind of technology that adopted, wherein hf power module being included in does not have in the lead-in wire type semiconductor device, and be the quiet earth electromotive force, comprise that the grounding terminals of each circuit block of hf power module is electrically connected with tab (tab) by lead.By adopting down joint, can reduce the quantity of external electrode terminal, and therefore can make the encapsulation miniaturization, thereby can finally make the semiconductor device miniaturization.
Yet,, found following shortcoming for the hf power module that is used for radio communications system (communication system).
In the receiving system of mobile phone, even if the signal of antenna being caught by low noise amplifier (LNA) amplifies, input signal is still very faint.Therefore, respond the operation (the particularly operation of the oscillator of periodical operation) of each circuit block as the electromotive force (ground potential just) of the tab of common terminal and fluctuation takes place or change.Because this fluctuation of ground potential produces between some circuit blocks and crosstalks, output is fluctuateed, thereby can not realize satisfied calling.
Particularly, by crosstalk between the lead-in wire or induced current that ground potential fluctuation causes and cause the signal waveform distortion, from communication system output, and output signal enters the communication system in the use, thereby produces noise.
As the circuit block that is easy to be subjected to ground potential fluctuation or cross talk effects, except that low noise amplifier, also has RFVCO (high frequency voltage controlled oscillator) etc.
In view of this, the inventor finds out, for low noise amplifier or REVCO, do not use lead that the grounding terminals in the middle of the electrode terminal of semiconductor element is connected with tab as common terminal, and be to use lead that grounding terminals is connected with independent wire lead termination (external electrode terminal), thereby can reduce the influence of ground potential fluctuation when other circuit blocks open or close.Then, obtain the present invention.
Therefore, the object of the present invention is to provide a kind of semiconductor device, wherein in the middle of the circuit in being formed at semiconductor element, the ground potential in the specified circuit parts is arranged to not be subject to the influence of remaining circuit parts ground potential with following connected structure.
Another object of the present invention is to provide a kind of hf power module, in this module, such as low noise amplifier, circuit blocks such as RFVCO are not subject to the influence of crosstalking that the fluctuation because of ground potential in other circuit blocks causes.
Another object of the present invention is to, a kind of satisfied Wireless Telecom Equipment of calling out that makes it possible to carry out less noise in radio communications system is provided.
Another object of the present invention is to, a kind of satisfied Wireless Telecom Equipment of calling out that makes it possible to carry out less noise in comprising the wireless communication system of a plurality of communication systems is provided.
On the other hand, the inventor analyzes and has studied the dual input method low noise amplifier (LNA: differential low noise amplifier) that imports signal inverting each other (complementary signal).Figure 34 A and Figure 34 B demonstrate respectively and comprise low noise amplifier (LNA) 100, the circuit block of high frequency voltage controlled oscillator (RFVCO) 101 and blender 102, and wherein, Figure 34 A represents single input method LNA, Figure 34 B represents dual input method LNA.
For in blender 102 will from the output signal of low noise amplifier 100 received signal of antenna (handle from) with from local oscillator (RFVCO: the circuit structure that mixes of 101 signal high frequency voltage controlled oscillator), in low noise amplifier with single input structure shown in Figure 34 A, the output frequency of RFVCO 101 becomes and equates with the output frequency of LNA 100, therefore, when the output signal of RFVCO 101 leaks into the LNA incoming line, output signal is directly amplified at LNA 100 places, thereby, the shortcoming that DC setovers can appear increasing.
Therefore, shown in Figure 34 B, by adopting with differential low noise amplifier (differential amplifier: LNA) be used as LNA 100, and import the dual input method of signal inverting each other (complementary signal), smaller value is arranged in the DC biasing.Just, differential amplifier (differential amplifier circuit) 100 is made up of two Unit Amplifier with same structure, and when importing two high-frequency signals (complementary signal) inverting each other, carries out differential amplification.Therefore, eliminate composition with same phase, thereby, the DC bias can be suppressed to smaller value.
Yet find, when further lifting carrier frequency band, only use the dual input system of above-mentioned input complementary signal can not eliminate shortcoming at all about above-mentioned DC biasing.Allow the input lead path of the above-mentioned complementary signal of input roughly to divide for the lead portion that constitutes by lead frame, with the conductor part that is connected lead portion and semiconductor core plate electrode.
For example, the lead portion that is formed by board member (being made by the metal such as copper) has relatively large thickness and width, therefore, because the difference in inductance that minute differences caused of several millimeters wire length is less.Yet, be approximately the conductor part of 20 to 30 μ m for diameter, because of the length difference of conductor part is easy to produce bigger difference in inductance.The input time that this difference of lead inductance can be expressed as two complementary input signals is poor, thereby, weakened the paired characteristic of input signal.Therefore, in high-speed communication system, from reducing the aspect of gain, the foregoing circuit parts are also unsatisfactory.
Therefore, another object of the present invention is to, in the circuit block of importing complementary signal to differential low noise amplifier simultaneously, strengthen the paired characteristic of input signal.
Another object of the present invention is to, strengthen the characteristic (reducing the DC biasing) of hf power module with differential low noise amplifier.
Description and accompanying drawing in conjunction with this specification will be well understood to above-mentioned and other purpose, and novel feature.
Summary of the invention
Representative invention disclosed in following concise and to the point description the application in the invention.
(1) a kind of semiconductor device of the present invention is the semiconductor device (for example, not having lead-in wire type semiconductor device) that comprises with lower member:
Seal is made by insulating resin;
A plurality of lead-in wires are along the peripheral of seal and in the inside and outside setting of seal;
Tab has first type surface and back of the body surface;
Semiconductor chip has first type surface and back of the body surface, and comprise a plurality of electrode terminals and a plurality of circuit block on first type surface, and each circuit block is made up of a plurality of semiconductor elements respectively;
Be used for a plurality of electrode terminals and a plurality of leads that go between and link to each other; With
Be used for a plurality of leads that a plurality of electrode terminals are linked to each other with the first type surface of tab, wherein
The first type surface of tab is fixed on the back of the body surface of semiconductor chip,
A plurality of circuit blocks comprise first circuit block (specified circuit parts) and second circuit parts,
A plurality of electrode terminals comprise, be used for first electrode terminal to first circuit block input external signal, be used for applying second electrode terminal of first electromotive force (ground potential) to first circuit block, the third electrode terminal that connects the second circuit parts, with the 4th electrode terminal that first electromotive force is provided to the second circuit parts
A plurality of lead-in wires comprise, first lead-in wire (lead-in wire that is used for signal), second lead-in wire (lead-in wire that is used for signal) and the 3rd lead-in wire (lead-in wire that is used for ground connection), the 3rd lead-in wire are arranged between first lead-in wire and second lead-in wire,
First electrode terminal links to each other with first lead-in wire by lead,
Second electrode terminal links to each other with the 3rd lead-in wire by lead,
The third electrode terminal links to each other with second lead-in wire by lead,
The 4th electrode terminal links to each other with tab as common ground by lead, and
The 3rd lead-in wire and the 4th lead-in wire are electrically isolated from one, thereby form high-frequency model.
First circuit block is to be used to amplify amplifying circuit through the external signal of first electrode terminal input (low noise amplifier: LNA), and be to be used for the circuit that amplifies from the wireless signal electrical signal converted by antenna.
The second circuit parts have the function that at least a portion is handled the first circuit block amplifying signal.
In addition, in hf power module, form a plurality of telecommunication circuits to tackle a plurality of communication meanss.These hf power modules are included in the Wireless Telecom Equipment.
According to above-mentioned device (1), (a) electrode terminal of semiconductor element not only is connected with lead-in wire by lead, also is connected (engaging down) with the tab that forms common ground.The grounding electrode terminal (electrode terminal of semiconductor element) of the low noise amplifier (specified circuit parts) that atomic weak signal is amplified is not connected with tab, but be connected with wire lead termination (lead-in wire that is used for ground connection) independently, therefore, it is irrelevant with other circuit blocks that ground potential becomes, even thereby at the power supply opening of other circuit blocks or when closing, be difficult for causing the fluctuation of ground potential, be difficult for producing the fluctuation of low noise amplifier output and the distortion of signal waveform because of the fluctuation of ground potential.Therefore, by semiconductor device is included in the Wireless Telecom Equipment, can provide the calling that does not have output pulsation and distortion.
(b) in having the hf power module of a plurality of telecommunication circuits, for the common ground that uses tab, fluctuation along with ground potential, in untapped telecommunication circuit, produce induced current, and the noise that this induced current caused enters the telecommunication circuit in using (operation), just, produce crosstalk noise.Yet, in hf power module of the present invention,, can suppress the output pulsation of low noise amplifier and the distortion of signal waveform because the low noise amplifier of each telecommunication circuit separates with the ground connection of another circuit block.Thereby,, also can realize no-output fluctuation and undistorted satisfied the calling even in having the Wireless Telecom Equipment of a plurality of telecommunication circuits.
(c) electrode terminal from low noise amplifier arrives the holding wire that goes between by lead, and the state that is arranged on the holding wire both sides according to earth connection carries out electromagnetic shielding, therefore, can reduce crosstalking between the holding wire.
(d) hf power module is the nothing lead-in wire type semiconductor device with following connected structure, therefore, can improve semi-conductive degree of miniaturization, reduces its thickness and weight.In addition, because tab is exposed to the back of the body surface of seal, thermal radiation property is satisfactory, thereby guarantees stable operation.Therefore, by hf power module is included in the mobile phone, can provide the mobile phone that shows satisfied call features and small portable.
Description of drawings
Fig. 1 represents the schematic plan view of the hf power module of one embodiment of the present of invention (embodiment 1) when removing a part of seal.
Fig. 2 represents the profile of the hf power module of embodiment 1.
Fig. 3 represents the schematic plan view of the hf power module of embodiment 1.
Fig. 4 represents to be included in the circuit structure schematic plan view of the block semiconductor chip in the hf power module of embodiment 1.
Fig. 5 represents to demonstrate the schematic plan view of lead connection status between external electrode terminal and each circuit block of semiconductor chip (as the low noise amplifier in the hf power module of embodiment 1, synthesizer etc.).
The flow chart of Fig. 6 shows the manufacture method of the hf power module of embodiment 1.
Fig. 7 is illustrated in the plane graph of employed lead frame in the manufacturing of hf power module of first embodiment.
The schematic plan view of Fig. 8 is presented at the unit lead frame pattern in the lead frame.
The schematic cross sectional view of Fig. 9 shows the lead frame that semiconductor chip is installed thereon.
The schematic cross sectional view of Figure 10 is presented at finishes lead joint lead frame afterwards.
The schematic cross sectional view of Figure 11 shows the lead frame that has formed seal thereon.
The block diagram of Figure 12 shows the circuit structure of the mobile phone of the hf power module that wherein includes embodiment 1.
The schematic cross sectional view of Figure 13 is presented at the installment state of the hf power module of embodiment 1 in the mobile phone.
Figure 14 represents the schematic plan view of the hf power module of another embodiment of the present invention (embodiment 2) when removing a part of seal.
Figure 15 represents the schematic plan view of the hf power module of another embodiment of the present invention (embodiment 3) when removing a part of seal.
Figure 16 represents the schematic plan view of the hf power module of another embodiment of the present invention (embodiment 4) when removing a part of seal.
Figure 17 represents the profile of the hf power module of embodiment 4.
The schematic cross sectional view of Figure 18 shows a kind of modification of the hf power module of embodiment 4.
Figure 19 represents the schematic cross sectional view of the hf power module of another embodiment of the present invention (embodiment 5).
Figure 20 represents the plane graph of the hf power module of embodiment 5.
Figure 21 represents the bottom plan view of the hf power module of embodiment 5.
Figure 22 represents the plane graph of the hf power module of embodiment 5 when removing a part of seal.
The schematic diagram of Figure 23 demonstrates, in embodiment 5, be provided with the example of lead-in wire in the differential amplifier circuit parts of hf power module of a pair of input block lead inductance and wire pattern and in embodiment 5, be not provided with lead-in wire in the differential amplifier circuit parts of hf power module of a pair of input block lead inductance and the example of wire pattern.
The schematic diagram of Figure 24 is used to illustrate the difference of the lead connection reliability that causes because of the difference of lead pattern as shown in figure 23.
Figure 25 represents to demonstrate the schematic plan view of lead connection status between external electrode terminal and each circuit block of semiconductor chip (as the low noise amplifier in the hf power module of embodiment 5, synthesizer etc.).
The plane graph of a part of lead frame of Figure 26 demonstrates, and in the manufacturing of the hf power module of embodiment 5, utilizes lead will be fixed to the electrode and the interconnective state of lead-in wire of the semiconductor chip of lead frame.
Figure 27 represents the internal structure of semiconductor chip of hf power module of embodiment 5 and the schematic amplification profile of lead connection status.
Figure 28 represents the schematic amplification profile of internal structure of semiconductor chip of the hf power module of embodiment 5.
The schematic cross sectional view of Figure 29 shows the installment state of the hf power module of embodiment 5.
The block diagram of Figure 30 shows the circuit structure of the mobile phone of the hf power module that wherein includes embodiment 5.
Figure 31 represents the schematic cross sectional view of the hf power module of another embodiment of the present invention (embodiment 6), and in the structure of this embodiment, the tab of support semiconductor chip is than semiconductor chip littler (little tab structure).
The schematic plan view of Figure 32 shows, a part of lead frame with little tab structure that uses in the manufacturing of the hf power module of embodiment 6.
Figure 33 represents the schematic cross sectional view of hf power module, demonstrates several other modifications to little tab structure.
Figure 34 is illustrated in the block diagram that comprises two input differential amplifier circuit parts (LNA) in the mobile phone and comprises the block diagram of input differential amplifier circuit parts (LNA) in mobile phone.
Embodiment
Below, in conjunction with the accompanying drawings, describe embodiments of the invention in detail.At the institute's drawings attached that is used for illustrating the embodiment of the invention,, and omit the description of its repetition herein, for the given identical symbol of the parts with identical function.
Fig. 1 to Figure 13 represents about the view of the semiconductor device (hf power module) of one embodiment of the invention (embodiment 1) and the Wireless Telecom Equipment that wherein includes this hf power module.Fig. 1 to Fig. 5 represents the view about hf power module, and Fig. 6 to Figure 11 represents the view about the hf power module manufacture method, and Figure 12 and Figure 13 represent the view about radio communication equipment.
In embodiment 1, be described with reference to the example that applies the present invention to QFN N-type semiconductor N device, in QFN N-type semiconductor N device, tab, tab suspension (suspending) lead-in wire and the lead-in wire (external electrode terminal) that abut to form with tab are exposed on the installation surface, and installation surface is formed on the back of the body surface of quad seal body (encapsulation).Semiconductor device 1 forms for example hf power module.
As depicted in figs. 1 and 2, QFN N-type semiconductor N device 1 comprises the seal (encapsulation) that is formed by the insulating resin with flat square shape.In the inside of seal 2, embed square semiconductor element (semiconductor chip: chip) 3.Semiconductor chip 3 is fixed in the tab surface (first type surface) (referring to Fig. 2) of square knuckle sheet 4 by adhesive 5.As shown in Figure 2, the back of the body surface (lower surface) of seal 2 is for installing the face side (installation surface) of semiconductor chip 3.
Semiconductor device 1 has the wherein structure on a surface (installation surface 7a) of the tab support lead-in wire 6 of exposed contacts sheet 4, supported joint sheet 4 and lead-in wire (external electrode terminal) 7 on seal 2 back of the body surfaces.In the manufacturing of semiconductor device 1, these tabs 4, tab support lead-in wire 6 and going between 7 is made by a slice lead frame, and lead frame is made of metal (for example, being made of copper), afterwards, is cut into each parts.
Therefore, in embodiment 1, tab 4, tab support lead-in wire 6 and go between and 7 have identical thickness.But, so the structure lead-in wire 7, make its inner end portion form thinlyyer by the back of the body surface of this inner end portion of etching, and therefore, the resin that forms seal 2 enters the downside of thin lead portion.Therefore, make that lead-in wire 7 is difficult to break away from from seal 2.
Tab 4 has four angles being supported by narrower tab support lead-in wire 6.These tab support lead-in wires 6 are arranged on the diagonal of quad seal body 2, and make each angle part towards quad seal body 2, its outer end.Seal 2 has the flat square shape, and is cut sth. askew to form inclined-plane 2a (referring to Fig. 1) in its angle part.The outer end of tab support lead-in wire 6 is slightly to the outstanding 0.1mm or littler of chamfered portion.Outstanding length is determined by cut the go between cutting die (cutting mold) of 6 o'clock stamping machines of tab support in the incision of lead frame state.For example, select 0.1mm or littler outstanding length.
In addition, as shown in Figure 1,, be provided with given interval along each limit of quad seal body 2 and make a plurality of lead-in wires 7 of its inner towards tab 4 in the periphery of tab 4.The outer end of tab support lead-in wire 6 and lead-in wire 7 extend to the periphery of seal 2.Just, lead-in wire 7 and tab support lead-in wire 6 spreads all over the inside and outside of seal 2.According to the above-mentioned tab support 6 identical modes that go between, the outstanding length of the 7 self sealss bodies 2 that go between during by cutting lead 7 under the lead frame state cutting die of stamping machine determine.For example, lead-in wire 7 is outstanding as 0.1mm or littler from seal 2.
In addition, the side surface with seal 2 forms inclined-plane 2b (referring to Fig. 2).The reason that forms inclined-plane 2b is to form seal 2 for seal 2 being designed so that be able on the surface that single face is molded into lead frame, and after this when removing seal 2 from the chamber of shaping dies, the side in chamber is formed the inclined-plane so that remove shaping dies.Herein, Fig. 1 represents to remove the top of seal 2 to allow to see tab 4, tab support lead-in wire 6, lead-in wire 7, the schematic diagram of semiconductor chip 3 grades.
In addition, as shown in Figure 1 and Figure 4, on the first type surface of the semiconductor chip 3 that exposes, on the first type surface of semiconductor chip 3, form electrode terminal 9.Electrode terminal 9 forms with approximate given spacing along square semiconductor chip 3 each limit.By lead 10 with these electrode terminals 9 and lead-in wire interior distolateral connection of 7.
The tab 4 that forms is compared greatly with semiconductor chip 3, and has the semiconductor element mounting district at the first type surface center, and outside the semiconductor element mounting district lead bonding pad of (periphery of tab 4 just).Then, semiconductor chip 3 is fixed in the semiconductor element fixed area, and the other end of the lead 10 that the one end links to each other with the electrode terminal 9 of semiconductor chip 3 links to each other with the lead bonding pad.Particularly, the lead 10 that is connected to tab 4 is called wire bonds 10a down.Because of using wire jointing device to carry out in wire-bonded and the wire-bonded between electrode terminal 9 and tab 4 between electrode terminal 9 and the lead-in wire 7, lead 10a and following wire bonds are made by same material.
Realize time connected structure has been adopted in the public use of the ground potential of each circuit block of semiconductor chip inside for using tab.By using tab as the common ground terminal and by using lead that tab is linked to each other with many electrode terminals as the grounding electrode terminal, can reduce as external electrode terminal and along the quantity of the lead-in wire (pin) of seal peripheral arrangement, thereby can make the seal miniaturization by the quantity that reduces lead-in wire.This causes the miniaturization of semiconductor device.
In addition, in the semiconductor device 1 of embodiment 1, as shown in Figure 3, between each lead-in wire 7 and lead-in wire 7, and go between 7 with tab support lead-in wire 6 between, have the resin burr (burr) of generation when formation seal 2.These resin burrs partly are to use single face to be molded into when forming seal 2 on the surface of lead frame in making semiconductor device 1 to produce.Although after molding, cut unnecessary lead frame part, yet in cutting lead and tab support lead-in wire, also cutting resin burr simultaneously, therefore, the whole joint in edge of the outward flange of resin burr and lead-in wire 7 edge and tab support lead-in wire 6, thus some resin burr remain in respectively go between 7 with go between between 7 and go between 7 and the tab support go between between 6.
In addition, in embodiment 1, the back of the body surface of seal 2 is arranged to back of the body surface (installation surface), the tab support lead-in wire 6 from tab 4 and goes between 7 recessed.This be because, in the single face molding when transfer modling, the sheet that resin is made is stretched between the upper and lower mould of shaping dies, and realize molding: a surface of lead frame is contacted with this sheet by following state, after this, clamp this sheet with the gap that defines in the lead frame, thereby the back of the body surface of seal 2 is recessed shape or groove shapes.
In addition, after using transfer modling to realize the single face molding, on the surface of lead frame, form week in the plated film of mounted on surface.Therefore, although tab 4, tab support lead-in wire 6 and the 7 lip-deep surfaces of the back of the body that are exposed to the seal 2 of semiconductor device 1 that go between also have been capped plated film, also not shown in the accompanying drawings.
In this way, for the bias structure of the back of the body surface indentation of and seal 2 outstanding wherein as the installation surface on the back of the body surface of lead-in wire 7 and tab support lead-in wire 6, when on printed circuit board (PCB), carrying out the mounted on surface of semiconductor device such as mounting panel etc., be welded owing to specifying the zone that is soaked with scolder, can being beneficial to.
Below, in conjunction with Fig. 6 to Figure 11, the manufacture method of the semiconductor device 1 of embodiment 1 is described.Shown in the flow chart of Fig. 6, make semiconductor device 1 by each step, described step comprises, preparation lead frame (S101), chip join (S102), lead engages (S103), sealing (molding: S104), electroplating processes (S105) and cutting and the unnecessary lead frame (S106) of removing.
Fig. 7 represents to have the schematic plan view of the lead frame 13 of employed matrix structure in the manufacturing of the QFN of first embodiment N-type semiconductor N device 1.
In lead frame 13, unit lead frame pattern 14 is arranged in 20 row along directions X, be arranged in 4 row along the Y direction, thereby can produce 80 chip semiconductor devices 1 by a lead frame 13.Be formed with the guide hole 15a to 15c that is used for transmission and location lead frame 13 in the both sides of lead frame 13.
In addition, in the left side of lead frame 13 each row, runner (runner) is the position when carrying out transfer modling.Then, for the runner cured resin being peeled off from lead frame 13, form the jemmy hole 16 that jemmy passes by outstanding jemmy (ejector pin).In addition, for peel off from runner branch by outstanding jemmy and after flowing into cavity on the doorway (gate) partly solidified doorway cured resin, form and allow jemmy to pass wherein jemmy hole 17.
The plane graph of Fig. 8 shows a part of unit lead frame pattern 14.Because unit lead frame pattern 14 be the pattern of actual manufacturing, compare some inconsistent part of existence with Fig. 2 with Fig. 1 as schematic diagram.
Unit lead frame pattern 14 has rectangle rack part 18.In pattern, tab support lead-in wire 6 extends from four angles of frame part 18, and is supported on the tab 4 that frame part 18 centers are provided with.A plurality of lead-in wires 7 extend internally from each inside, limit of frame part 18, and its inner is positioned adjacent to the periphery of tab 4.First type surface at tab 4 and lead-in wire 7 is formed for the plated film (not shown in the accompanying drawings) that chip join or lead engage.
In addition, by etching partially back of the body surface attenuation (referring to Fig. 2) with the end side of lead-in wire 7.Herein, the periphery of lead-in wire 7, tab 4 etc. comprises the inclined-plane, so that the width of first type surface becomes bigger than the width on back of the body surface, puts upside down trapezoidal cross-section with formation, thereby the feasible structure that is difficult to break away from from seal 2 lead-in wire 7 and tab 4 is provided.This structure can or be used the stamping machine manufacturing by etching.
In addition, as shown in Figure 8, on the first type surface of tab 4, the square region at heart place is semiconductor element mounting portion 4a (by a double dot dash line institute area surrounded) therein, is lead bonding pad 4b in the zone of semiconductor element mounting portion 4a outside.
After preparing such lead frame 13, as Fig. 8 and shown in Figure 9, by adhesive 5 semiconductor chip 3 is installed to each unit lead frame pattern 14 tab 4 semiconductor element mounting portion 4a (chip join) (S102).
Secondly, as shown in figure 10, carry out lead and engage,, simultaneously given electrode terminal is connected (S103) with the lead bonding pad 4b of tab 4 so that use lead 10 that the electrode terminal of semiconductor chip 3 is connected with the end of lead-in wire 7.The lead that electrode terminal is linked to each other with the lead bonding pad 4b of tab 4 specifically is called wire bonds 10a down.This lead is for example made by gold thread.
Next, use common transfer modling to realize the single face molding, on the first type surface of lead frame 13, form seal 2 (S104) to use insulating resin.Seal 2 covers semiconductor chip 3, the lead-in wire 7 that forms etc. on the first type surface of lead frame 13.In Fig. 8, be the part that forms seal 2 by the represented part of double dot dash line.
Below, carry out electroplating processes, but not shown in the accompanying drawings (S105).Thereby, on the back of the body surface of lead frame 13, form unshowned in the accompanying drawings plated film.The grafting material of plated film when semiconductor device 1 mounted on surface, and make by for example solder plating film.Can also use the product that forms by the pre-Pd of formation coating on all surfaces of lead frame 13, replace the above-mentioned plated film of formation.In addition, when use using the lead frame 13 of Pd coating, can be omitted in the plating step after the above-mentioned sealing, therefore, can simplify manufacturing step, and can reduce manufacturing cost.
Then, cut the lead frame part (S106) unnecessary, thereby make semiconductor device 1 as shown in Figure 1 with removing.The outside slightly of seal 2 in double dot dash line framework shown in Figure 8 uses cutting die (not shown in the accompanying drawings) cutting lead 7 of stamping machine and tab support to go between 6.Because the structure of cutting die away from the position cutting lead 7 and the tab support lead-in wire 6 of seal 2, will be arranged to for example 0.1mm or littler slightly away from the distance between position and the seal 2.Lead-in wire 7 and tab support lead-in wire 6 are preferably shorter from the outstanding length of seal 2, so as not to go between 7 and tab support lead-in wire 6 run into for miscellaneous part.Suppose that outstanding length is 0.1mm or bigger, then can freely select outstanding length by the cutting die that changes stamping machine.
The example of the each several part size of semiconductor device 1 is described herein, for example.
Lead frame 13 (tab 4, tab support lead-in wire 6, lead-in wire 7) thickness is 0.2mm, the thickness of chip 3 is 0.28mm, the thickness of semiconductor device 1 is 1.0mm, and the width of lead-in wire 7 is 0.2mm, and the length of lead-in wire 7 is 0.5mm, wire interconnecting piece branch of tab 4 (point) and the distance that is installed between the end of the chip 3 on the tab 4 are 0.1mm, and the distance between tab 4 and the lead-in wire 7 is 0.2mm.
On the other hand, one of the present invention is characterised in that, for a part of circuit in semiconductor chip 3 inside, the ground wire of specified circuit parts is drawn with as the grounding electrode terminal, and it is link to each other with lead-in wire, and isolated with remaining circuit ground wire partly by lead.Use lead that all the other each circuit blocks are connected with the tab that is used as common ground in case of necessity, simultaneously, can it be linked to each other with lead-in wire by lead.In addition, the ground of specified circuit parts and the ground of remaining circuit parts (but not shown in the accompanying drawings) is isolated by interlayer dielectric etc. with insulation mode, even if the wiring in semiconductor chip 3 inside also is like this.
For using hf power module of the present invention in this embodiment, when all circuit blocks that form in single semiconductor chip use ground connection jointly, as mentioned previously, can produce because of the fluctuation of ground potential and crosstalk, this can cause the output of each circuit block to produce fluctuation, and the distortion that causes signal waveform.In addition, for the hf power module that has such as a plurality of telecommunication circuits of double frequency-band or three frequency bands, in the telecommunication circuit of not operation, produce induced current, and this induced current enters the telecommunication circuit of operation as noise situation may occur.Therefore, in embodiment 1, the electrode terminal that is used for ground connection of specified circuit parts (grounding electrode terminal) does not link to each other with tab, but links to each other with independent lead-in wire (ground lead) by lead.
In addition, also, may in each circuit block, output pulsation occur, and may make the signal waveform distortion owing to crosstalking between the input signal cable.Particularly, must avoid the influence of crosstalking of adjacent legs for being used for as far as possible from the lead-in wire of antenna input external signal with less input signal.
In embodiment 1, because semiconductor device 1 is the hf power module that is used for mobile phone three frequency bands, the specified circuit parts are low noise amplifier (LNA).Because hf power module is used for three frequency bands, as the low noise amplifier that links to each other with antenna (LNA), three low noise amplifiers (LNA) is set.
From the narrow sense definition of term, single LNA represents specified circuit parts of the present invention.Just, as shown in Figure 5, there are two from the input signal cable of the antenna of each LNA.In addition, for these two holding wires are realized electromagnetic shielding, the lead-in wire that will be used for ground connection is arranged between two signal leads and another signal lead, is preferably in the both sides of two signal leads.
By adopting differential input structure when using two input signal cables, two input signal cables are subjected to because of the crosstalk influence of the basic equivalent that causes of rank on an equal basis, therefore, and (elimination) noise (crosstalking) of can setovering.As shown in Figure 5, will partly be set to the specified circuit parts 11 of generalized definition herein, around the rectangular frame of three LNA.In these specified circuit parts 11, in semiconductor chip to form each LNA in insulation mode and other circuit block area isolated.Then, each LNA uses the common ground electromotive force.This be because, in dual communication system and three communication systems, when just using a communication system, other communication systems are in idle condition, therefore, the LNA that belongs to the communication system that now is in idle condition is less to the influence of ground potential, thereby, even if public use belongs to grounding electrode or the ground wire of the LNA of different communication system, the adverse effect that each LNA produces mutually also can be very little.But, where necessary, can adopt and wherein each LNA be isolated so that the ground potential of each LNA and irrelevant each other structure.
The schematic cross sectional view of Figure 13 is presented at the installment state of the semiconductor device (hf power module) 1 of embodiment 1 in the mobile phone.
On the first type surface of the mounting panel (printed circuit board (PCB)) 80 of mobile phone, for semiconductor device 1 is installed, form bank (land) 81 and tab standing part 82, this bank 81 and tab standing part 82 usefulness abut to form corresponding to the lead-in wire 7 of semiconductor device 1 and the lead of tab 4.Herein, with semiconductor device 1 location and be arranged on the mounting panel 80 so that the lead-in wire 7 of semiconductor device 1 and tab 4 corresponding to and cover bank 81 and standing part 82.Then, in such state, make temporarily that preformed solder plating film refluxes on the back of the body surface of the lead-in wire 7 of semiconductor device 1 and tab 4,7 be connected (installation) with scolder 83 with tab 4 going between.
Herein, in conjunction with Figure 12, the concise and to the point circuit structure (functional structure) of describing mobile phone with three frequency structures.That is, mobile phone can be realized for example gsm communication method of 900MHz frequency band, the signal processing of DCS 1800 communication meanss of 1800MHz frequency band and PCS 1900 communication meanss of 1900MHz frequency band.
In block diagram as shown in figure 12, demonstrate emission system and the receiving system of using duplexer 21 to be connected with antenna 20, wherein, emission system all links to each other with baseband chip 22 with receiving system.
Receiving system comprises antenna 20, duplexer 21, parallel three band pass filters 23 that are connected to duplexer 21, the low noise amplifier (LNA) 24 that links to each other with each band pass filter 23 is with the variable amplifier 25 that links to each other and be connected in parallel with each other with three LNA 24.For these two variable amplifiers 25 each, be connected with blender 26, low pass filter 27, PGA28, low pass filter 29, PGA 30, low pass filter 31, PGA 32, low pass filter 33 and modulator 34.PGA 28, and PGA 30 and PGA 32 are controlled by the control logic circuit parts 35 that are used for ADC/DAC and DC biasing respectively.In addition, two blenders 26 are subjected to the phase control of the phase shifters (90-degree phase shifter) 40 of 90 degree.
In Figure 12, corresponding to three LNA the I/O modulators of forming by 90-degree phase shifter 40 and two blenders 26 are provided, to handle each frequency band.Yet, for the purpose of brief, in Figure 12, only demonstrate an I/Q modulator.
To semiconductor chip 3 provide by RF synthesizer 41 and IF (centre) synthesizer 42 form, as the synthesizer of signal processing IC.RF synthesizer 41 links to each other with RFVCO44 by buffer 43, and carries out control, so that RFVCO 44 output RF local signals.To link to each other with buffer 43 series connection at two frequency dividers 37,38 of local signal, switch 48,49 links to each other with the corresponding output end of frequency divider 37,38.By the conversion of switch 48, will be input to 90 degree phase converters 40 from the RF local signal of REVCO 44 emissions.90 degree phase converters 40 respond the RF local signals and blender 26 are controlled.
In the situation of Rx pattern, for GSM, the signal output mode of RFVCO 44 is 3780 to 3840MHz, is 3610 to 3760MHz for DCS, is 3860 to 3980MHz for PCS.In addition, in the Tx pattern, for GSM, the signal output mode of RFVCO 44 is 3840 to 3980MHz, is 3580 to 3730MHz for DCS, is 3860 to 3980MHz for PCS.
IF synthesizer 42 links to each other with IFVCO (intermediate wave voltage controlled oscillator) 45 by frequency divider 46, and IF synthesizer 42 is carried out control, so that IFVCO 45 output IF local signals.In all communication meanss, the output signal frequency of IFVCO 45 is 640MHz.In addition, VCXO (VCXO) 50 is subjected to the control of RF synthesizer 41 and IF synthesizer 42, and with the output reference signal, and reference signal sends to baseband chip 22.
For receiving system, the IF signal is subjected to synthesizer and is used for ADC/DAC﹠amp; The control of the control logic circuit parts 35 of DC biasing, and the IF signal converts baseband chip signal (I, Q signal) to by modulator 34, and the baseband chip signal is transferred to baseband chip 22.
Emission system comprises, use is from the i/q signal of baseband chip 22 output two blenders 61 as input signal, control the 90-degree phase shifter 62 of the phase place of these two blenders 61, adder 63 with the output addition of these two blenders 61, with the output of adder 63 blender 64 and DPD (digital phase detector) 65 as its input, the output of blender 64 and DPD 65 is imported the loop filter 66 that receives as it, the output of loop filter 66 is imported two TXVCO (transmitted wave voltage controlled oscillator) 67 that receive as it, receive the power model 68 of the output of two TXVCO 67 as its input, and duplexer 21.Loop filter 66 be one by outside mounted component.
The DC-AC modulator is by blender 61, and 90-degree phase shifter 62 and adder 63 are formed.90-degree phase shifter 62 links to each other with frequency divider 46 by frequency divider 47, and controls according to the IF local signal of IFVCO 45 outputs.
By using coupler 70 to detect electric current, the output of TXVCO 67 is detected.The signal that is detected is by amplifier 71 input mixers 72.Blender 72 is imported as it by the RF local signal that switch 49 is received from RFVCO 44 outputs.The output signal of blender 72 is input to blender 64 and DPD 65 with the output signal of adder 63.Biasing PLL (phase-locked loop) is made up of blender 64 and DPD 65.In each communication means, blender 72 output signal frequency are 80MHz.
In two TXVCO 67, TXVCO 67 adopts the gsm communication methods, and wherein output signal frequency is 880 to 915MHz.In addition, another TXVCO 67 is used for DCS and PCS communication means, and wherein output signal frequency is 1710 to 1785MHz or 1850 to 1910MHz.Comprise low frequency power module and hf power module in the power model 68, TXVCO 67 received signals of low frequency power module wherein from exporting 880 to 915MHz signals, and carry out processing and amplifying, and hf power module is from exporting 1710 to 1785MHz or TXVCO 67 received signals of 1850 to 1910MHz signals, and signal carried out processing and amplifying, signal is transferred to duplexer 21.
Mode by monolithic integrated circuit in the semiconductor device 1 of embodiment 1 also forms logical circuit 60, and logical circuit 60 is transferred to baseband chip 22 with its output signal.
In the semiconductor device (high frequency power module) 1 of embodiment 1, form among Figure 12 by solid line with the mode of monolithic integrated circuit and to be centered on each circuit block in the part.In addition, with the specified circuit parts 11 (referring to Figure 4 and 5) of three LNA, 24 corresponding parts as embodiment 1.The block diagram of the semiconductor chip 3 that demonstrates among Fig. 4 and Fig. 5 schematically shows the part of these related circuit parts.
The radio signal that antenna 20 receives (electric wave) is converted into the signal of telecommunication, and handles in succession by each element of receiving system, and is transferred to baseband chip 22.In addition, obtain the processing of each element of emission system in succession, and launch with the electric wave form from antenna 20 from the signal of telecommunication of base band 22 output.
The schematic arrangement of Fig. 4 illustrates the layout of each circuit block in the semiconductor chip 3.On the first type surface of semiconductor chip 3, electrode terminal (pad) 9 is provided with along each limit.In addition, in the inside of these electrode terminals 9, arrange each circuit block by cut zone.As shown in Figure 4, the center at semiconductor chip 3 is provided for ADC/DAC﹠amp; The control logic circuit parts 35 of DC biasing.On the other hand, left side at control logic circuit parts 35,26,64 and three LNA 24 of blender be arranged in parallel, RFVCO 44 is positioned at the upside of control logic circuit parts 35, RF synthesizer 41, VCXO 50, IF synthesizer 42 and IFVCO45 are arranged on the right side of control logic circuit parts 35 from the top down, and TXVCO 67 is arranged on the downside of control logic circuit parts 35.
Fig. 5 represents the relation between each parts (first circuit block and second circuit parts) and the electrode terminal 9, and the wiring state of electrode terminal 9 and lead-in wire 7 use leads 10.As lead 10, lead 10 connection electrode terminals 9 and lead-in wire 7, following wire bonds 10a connection electrode terminal 9 and tab 4.
Observation is as three LNA 24 of specified circuit parts 11 (first circuit block), the lead-in wire 7 that expectation is connected with band pass filter 23 as outside installing component, that is, the lead-in wire 7 in its left side with " signal " is connected with the signal electrode terminal 9 of LNA 24 by lead 10.Be provided with two holding wires that arrive lead-in wire 7 from electrode terminal 9 by lead 10.In the both sides of these holding wires, as the grounding electrode terminal 9 of the LNA 24 of specified circuit parts 11, is connected with ground lead 7 (left side is designated as the lead-in wire 7 of GND in the drawings) by lead 10, thus the formation ground wire.
Because this structure, specified circuit parts 11 are isolated by mode and other circuit blocks of insulation.That is, the ground connection of the ground connection of each VCO and LNA 24 is isolated by the mode of insulation at least, simultaneously, and space between the lead-in wire of the lead-in wire of other adjacent circuit blocks and LNA 24 and ground lead 7 electromagnetic shieldings.In addition, adjacent LNA 24 is also by ground lead 7 electromagnetic shieldings.
With the LNA 24 that amplifies from the utmost point weak signal of antenna transmission is compared, to each circuit block of the emission system handled from the signal of telecommunication of baseband chip 22 output (for example, biasing PLL, TXVCO 67 etc.), the signal of telecommunication is bigger than above-mentioned utmost point weak signal, thereby the circuit block of emission system has following character, i.e. the ability of the noise that the anti-earth potential of circuit block fluctuation and crosstalking causes is stronger.Thereby, for the circuit block to emission system provides ground potential,, can reduce the quantity of lead-in wire 7, thereby can make the semiconductor device miniaturization by using via tab 4 and the shared ground potential of corresponding VCO.
Preferably more close electrode terminal 9 ground are provided with LNA, cause signal to degrade with crosstalking between the circuit that prevents to form on the first type surface owing to semiconductor chip 3.For example, with the circuit of handling via the LNA amplifying signal, for example PGA etc., or the circuit of emission system compares, and in order to shorten the length of arrangement wire of LNA, preferably more close electrode terminal 9 ground are provided with LNA.
According to embodiment 1, can obtain following beneficial effect.
(1) be in the hf power module 1 at semiconductor device 1, the electrode terminal 9 of semiconductor element (semiconductor chip) 3 not only is connected with lead-in wire 7 by lead 10, but also is connected (engaging down) with tab 4.Herein, owing under this, engage center tap sheet 4 as public ground, grounding electrode terminal (electrode terminal of semiconductor element) as the low noise amplifier 24 of specified circuit parts 11 is not connected with tab 4, and is connected with lead end (ground lead) independently.Because low noise amplifier 24 amplifying stage weak signals, the fluctuation of ground potential become the fluctuation of low noise amplifier 24 outputs, at this moment, distortion also takes place in signal waveform.But, the earth terminal of low noise amplifier 24 separates with the ground wire of other circuit blocks, thereby, can suppress the fluctuation of the output of low noise amplifier 24, and suppress the signal waveform distortion.As a result, by in Wireless Telecom Equipment, comprising hf power module, can provide the good calling that does not have output pulsation and distortion.
(2) in comprising the hf power module of a plurality of telecommunication circuits, when hf power module adopts the public ground that uses tab 4, follow the fluctuation of ground potential, in untapped telecommunication circuit, produce induced current, thereby produce so-called crosstalking, wherein enter the telecommunication circuit that (is under the mode of operation) in the use owing to faradic noise.But, in hf power module 1 of the present invention,, can suppress the fluctuation of low noise amplifier 24 outputs, and suppress the signal waveform distortion because the low noise amplifier 24 of each telecommunication circuit separates with the ground wire of other circuit blocks.As a result, in having the Wireless Telecom Equipment of a plurality of telecommunication circuits, can provide the good calling that does not have output pulsation and do not have distortion.
(3) in hf power module 1, ground wire is arranged on the both sides of holding wire, and holding wire arrives lead-in wire 7 from the electrode terminal 9 of low noise amplifier 24 by lead 10, thereby with the holding wire magnetic screen, thereby holding wire is difficult to receive crosstalks.
(4) in hf power module 1, tab 4 is exposed on the back of the body surface of seal 2, thus can be effectively with the heat leakage that produces in the semiconductor chip 3 to mounting panel 80.Therefore, the Wireless Telecom Equipment that wherein comprises hf power module 1 can guarantee the operation that it is stable.
(5) be exposed to the lip-deep non-terminal type semiconductor device of seal 2 back ofs the body because hf power module 1 is tab 4 and lead-in wire 7, can realize miniaturization, and reduce the thickness of hf power module 1, thereby hf power module 1 can also lighten.Thereby, can also realize the miniaturization of Wireless Telecom Equipment and alleviate the weight of Wireless Telecom Equipment, wherein comprise hf power module 1 in the Wireless Telecom Equipment.
(6) in hf power module 1, the electrode terminal 9 of semiconductor chip 3 uses lead 10 to be connected to each other with lead-in wire (pin) 7, simultaneously, the tab 4 of taking ground potential uses down with the electrode terminal (grounding electrode terminal) of semiconductor chip 3 that wire bonds 10a is connected to each other, thereby forms connected structure down.Therefore, can reduce the quantity of the ground lead 7 that becomes external electrode terminal, therefore, can realize reducing the miniaturization of the seal 2 that causes, thereby can realize the miniaturization of hf power module 1 owing to pin number.
(embodiment 2)
Figure 14 represents the schematic plan view of the hf power module of another embodiment of the present invention (embodiment 2) when removing a part of seal.
In embodiment 1, circuit block comprises that three low noise amplifiers (LNA) 24 are with as specified circuit parts 11.In embodiment 2, except above-mentioned circuit block, in VCO, also use and handle high-frequency RFVCO 44 as the specified circuit parts.Therefore, all grounding electrode terminals 9 of RFVCO 44 all are connected to lead-in wire (ground lead) 7 by lead 10, and grounding electrode terminal 9 is not connected with tab 4 by lead simultaneously.
Pass through the circuit that lead 10 arrives lead-in wire 7 for the electrode terminal 9 from semiconductor chip 3, ground wire is arranged on the both sides of two signal line of RFVCO 44, thereby, for holding wire provides electromagnetic shielding.
Therefore, handle the ground potential of the specified circuit parts 11 of high-frequency signal and isolate, crosstalk thereby no longer produce by the mode of insulation and the ground potential of other circuit blocks.
(embodiment 3)
Figure 15 represents the schematic plan view of the hf power module of another embodiment of the present invention (embodiment 3) when removing a part of seal.
Embodiment 3 relates to an example, wherein provide RFVCO 44 as outside installing component, thereby semiconductor chip 3 does not form in the mode of monolithic integrated circuit.In this communicating in two frequency bands method, each circuit block such as low noise amplifier, blender, VCO, synthesizer, the IQ modulator/demodulator, frequency divider, DC-AC modulators etc. form in the mode of monolithic integrated circuit.
Two blenders in the receiving system are subjected to the control of frequency divider respectively, and frequency divider is a kind of freq converting circuit, are used for converting the high-frequency signal as RFVCO 44 outputs of outside installing component to low frequency signal.
Therefore, in embodiment 3, as shown in Figure 15, RFVCO 44 is arranged on the outside of semiconductor device 1, and two signal line of RFVCO 44 are connected with the lead-in wire 7 of semiconductor device 1.In addition, be arranged on, 7 be connected to each other with going between by lead 10 from the electrode terminal 9 of the both sides of the holding wire of the electrode terminal 9 of two lead-in wires 7 (lead-in wire 7 by lead 10 are connected) arrival semiconductor chips 3 with RFVCO 44.The electrode terminal 9 that is arranged on these two signal line both sides is the grounding electrode terminal, thereby the lead-in wire 7 that is connected with the grounding electrode terminal by lead 10 is also as ground lead.Therefore, by the mode identical with embodiment 2, the holding wire of handling high-frequency signal is also by electromagnetic shielding, and simultaneously, the ground potential of other circuit blocks has nothing to do in the ground potential of circuit block and the semiconductor chip 3.
Among this external embodiment 3,, no longer produce the problem that the ground potential fluctuation of RFVCO 44 brings by the mode identical with embodiment 2.
(embodiment 4)
Figure 16 and Figure 17 relate to the hf power module of another embodiment of the present invention (embodiment 4), and wherein Figure 16 represents the schematic plan view of hf power module when removing a part of seal, and Figure 17 represents the schematic cross sectional view of hf power module.
Embodiment 4 is characterised in that, uses lead 10b to be electrically connected to each other as the tab 4 and the lead-in wire 7 of taking ground potential of common ground end, and goes between 7 also as the grounded outer electrode terminal.In the semiconductor device 1 of embodiment 4, because expose from the back of the body surface (installation surface) of seal 2 on the back of the body surface of tab 4, can use tab 4 as the grounded outer electrode terminal, simultaneously, be connected to the lead-in wire 7 of tab 4 also as the grounded outer electrode terminal by lead 10b.
Figure 18 is a kind of modification of embodiment 4.That is, in this modified example because thinner by etching partially back of the body surface one side that makes tab 4, when carrying out the single face molding, resin be enclosed in tab 4 back of the body face side around.Therefore, as shown in Figure 18, the back of the body surface of tab 4 is not exposed to outside the seal yet, and is embedded in fully in the seal 2.By adopting this structure,, can use lead-in wire 7 as the grounded outer electrode terminal because tab 4 is connected with lead-in wire 7 by lead 10b.Herein, the another kind of structure as tab being embedded in the seal can adopt following structure, wherein makes mid portion that tab hangs lead-in wire with the mode of the similar step curved step that rises that hoists.
In the structure shown in Figure 18, compare with the quantity of the electrode terminal 9 that is used to provide ground potential, is connected with tab 4 by wire bonds 10a down, the quantity of the lead-in wire 7 that is connected with tab by lead 10b reduces, thereby has also reduced the quantity of the lead-in wire 7 that is provided with along the periphery of seal 2.Therefore, can make device miniaturization.Because the sealed body 2 in the back of the body of tab 4 surface covers, when the semiconductor device 1 of present embodiment was installed on the printed circuit board (PCB), semiconductor device 1 following zone also can be used for being provided with circuit on wire-printed circuit board.Thereby in the present embodiment, the packing density with printed circuit board (PCB) increases, simultaneously the advantage of semiconductor device 1 miniaturization.
(embodiment 5)
Figure 19 to 30 relates to the hf power module according to another embodiment of the present invention (embodiment 5).Basically the hf power module with embodiment 1 is identical according to the hf power module of embodiment 5.
As shown in Figure 30, hf power module 1 according to embodiment 5 is applied under a kind of like this state, wherein have in the Wireless Telecom Equipment (portable radio machine, as mobile phone etc.) of three band structures (gsm communication, DCS communication communicate by letter) and comprise hf power module 1 with PCS.Figure 30 is corresponding with Figure 12 basically, shows the circuit structure have from antenna 20 to base band 22 transmitting/receiving system.In embodiment 5,23 outputs of the band pass filter that links to each other with duplexer 21 have the complementary signal of a pair of phase place inverting each other, and duplexer 21 links to each other with antenna 20, and this complementary signal is input in the low noise amplifier (LNA) 24 with 2 inputs/2 export structures.Then, base band 22 or emission/reception change over switch 36 are handled and sent to the output signal of LNA 24 order process in each circuit block.
As shown in figure 30 structure and as shown in figure 12 the basic difference between the structure be, in Figure 30, come from the complementary signal processing for demonstrating signal, the quantity that connects the connecting line of each circuit block is set to 2, and the quantity of the output signal line to blender 26 also is set to 2 from 90-degree phase shifter 40.
Extremely shown in Figure 22 as Figure 19, hf power module 1 according to embodiment 5 adopts nothing lead-in wire type semiconductor device, this device is from the surface (lower surface: installation surface 7a), and have the 7 QFN structures of giving prominence to from four square limits respectively that wherein go between of the back of the body surface exposed leads 7 of seal (resin sealing body) 2.Chip mounting portion (tab) 4, tab hang lead-in wire 6 and lead-in wire 7 by using punching press or etching a slice metallic plate (for example, copper coin) of fixed thickness (for example, being approximately 0.2mm) is carried out patterning and forming.In addition, the lower surface of lead-in wire 7 or tab suspension lead-in wire 6 (back of the body surface) makes its local attenuation by etching away fixed thickness (for example, being approximately 0.1mm).In addition, wire widths for example is 0.2mm in the 7c of first, for example is 0.15mm in second portion 7d.Therefore, the upper surface of the chip mounting portion 4 of semiconductor chip 3 is installed, the upper surface of lead-in wire 7, the upper surface that hangs lead-in wire 6 with tab is positioned at same plane, simultaneously, from the lower surface of resin sealing body 2, expose the lower surface of chip mounting portion 4, and expose portion lead-in wire 7 and tab suspension lead-in wire 6.
Resin sealing body 2 has the flattened rectangular structure, and it has upper surface, and back of the body surface (with the lower surface of relative mode) in the face of upper surface, and be clipped in side surface between above-mentioned upper surface and the back of the body surface.Then, along the periphery of resin sealing body 2, the 7 inside and outside states that extend to resin sealing body 2 are provided with a plurality of lead-in wires 7 to go between.The overall dimension of hf power module 1 equals the overall dimension of the hf power module 1 described in the embodiment 1.
Chip mounting portion 4 has the following structure shown in Figure 22.That is, chip mounting portion 4 is arranged on by in 7 region surrounded of a plurality of lead-in wires, and by bonding agent 5 semiconductor chip 3 is fixed on this chip mounting portion 4.The flat shape of semiconductor chip 3 is square configuration, and forms a plurality of electrode terminals 9 and a plurality of circuit blocks that include a plurality of semiconductor elements on the first type surface of semiconductor chip 3.
Semiconductor chip 3 is installed to the square region that the slit 200 that forms along the periphery of chip mounting portion (tab) 4 is centered on.Chip mounting portion 4 is fixed to ground potential.In addition, the given electrode terminal 9 of chip mounting portion 4 and semiconductor chip 3 (ground potential electrode terminal) is connected to each other by lead 10.These leads 10 promptly descend wire bonds 10a to be connected with the chip mounting portion of slit 200 outsides.Because following wire bonds 10a is connected with the chip mounting portion of slit 200 outsides, the adhesive 5 that the chip mounting portion of slit 200 outsides can not be flowed out pollutes, thereby following wire bonds 10a realizes good connection character.In addition, owing to there is slit 200, the resin that constitutes resin sealing body 2 enters in the slit 200, thereby, increased the adhesive strength of chip mounting portion 4, and improved encapsulation property with resin sealing body 2.In addition, owing to have slit 200, the thermal resistance when having increased installation and heating, the so-called wire stripping that can be implemented in down tab bonding portion when engaging prevents effect.
A plurality of circuit blocks of semiconductor chip 3 comprise the differential amplifier (differential amplifier circuit parts) with a pair of input.In this differential amplifier circuit parts, as shown in Figure 25, form low noise amplifier (LNA) 24.As shown in Figure 25, for the specified circuit parts 11 that surround three LNA, with semiconductor chip in other circuit blocks insulation and the zone that isolates, form each LNA.Then, each LNA uses public ground level.Structure described in the structure of these parts and the embodiment 1 is basic identical.
Each LNA 24 is one and is used for the circuit block that amplifies by the antenna institute electrical signal converted of portable radio machine.Because each LNA 24 according to embodiment 5 constitutes differential amplifier, LNA comprises two electrode terminals 9 that are used for input lead.The length setting of the lead 10 that will be connected with these two electrode terminals is an equal length, with the paired characteristic of the input signal that guarantees the differential amplifier circuit parts.In addition, with these two electrode terminals 9 with the both sides of the corresponding lead-in wire of electrode terminal 97 leads that are connected 10, be provided with the lead 10 that is used for ground connection, provide electromagnetic shielding to holding wire, thereby prevent that generation from crosstalking.
Below, further explain input lead (holding wire) the differential amplifier circuit parts, that comprise lead-in wire patterns such as 7.As shown in Figure 23 A, a plurality of electrode terminals 9 of semiconductor chip 3 comprise the corresponding first electrode terminal 9a and the second electrode terminal 9b of a pair of input with the differential amplifier circuit parts.The first electrode terminal 9a and the second electrode terminal 9b are arranged close to each other along a side of semiconductor chip 3.To the first electrode terminal 9a and a pair of complementary signal of second electrode terminal 9b input with out of phase (phase place is put upside down each other).Input characteristics when obtaining input signal (complementary signal) (characteristic in pairs) is an equal length with the length setting that is connected to the lead 10 of the first electrode terminal 9a and the second electrode terminal 9b.
For the length setting with lead 10 is an equal length, change the plane pattern of lead-in wire 7, so that lead-in wire 7 is equated with distance between the given electrode terminal 9.
, explain chip mounting portion 4 herein, lead-in wire 7 and tab hang the relation between the lead-in wire 6.As shown in Figure 19, a plurality of lead-in wires 7 comprise the 7c of first that expose from the back of the body surface of resin sealing body 2 on its back of the body surface (lower surface), with the second portion 7d that extends to 4 inside, chip mounting portion, and remove the lower surface of second portion 7d by etching away fixed thickness.Therefore, lead-in wire 7 has following structure, and wherein the thickness of second portion 7d is less than the thickness of the 7c of first, and whole second portion 7d is coated in the resin sealing body 2.In addition, owing to hang the mid portion of lead-in wire 6 at tab, lower surface is etched away given thickness as above-mentioned second portion 7d is same, resin enters in the etching part during transfer modling, thereby tab suspended portion 6 is only partly exposed from the back of the body surface of resin sealing body 2.In addition, the 7c of first of lead-in wire 7 stretches out the edge of resin sealing body 2 in the following manner, makes the 7c of first expose from the side (peripheral surface) of resin sealing body 2.Its extension elongation is less than about 0.1mm.
The inside of the second portion 7d embedded resin seal 2 of lead-in wire 7, and be provided with insulating resin between the periphery of the end of second portion 7d (wiring part) and chip mounting portion 4, thereby the end of second portion 7d can be provided with near chip mounting portion 4.
That is, the second portion 7d of lead-in wire 7 has following structure, and promptly second portion 7d does not expose from the back of the body surface of resin sealing body 2, and extends to resin sealing body 2 inside.Therefore, as shown in Figure 29, when being installed to hf power module 1 on the mounting panel 80, when lead-in wire 7 and chip mounting portion 4 are installed on the bank 81 of mounting panel 80 or the standing part 82 by scolder 83, contact with each other or close problem with the scolder 83 that chip mounting portion 4 is fixed to standing part 82 owing to needn't consider to make lead-in wire 7 to be fixed to the scolder 83 of bank 81, can make the periphery of the end of second portion 7d near chip mounting portion 4 with the generation electrical short.
In this way, in 7 the second portion 7d embedded resin seal 2 of will going between, determining of the pattern of above-mentioned second portion 7d can be irrelevant with the shape as the part of outer electrode (7c of first).Thereby in order to realize the paired characteristic of input signal (complementary signal), the pattern of can determine to go between 7 (7c of first and second portion 7d) makes the equal in length of the lead 10 that is connected to the first electrode terminal 9a and the second electrode terminal 9b.In embodiment 5, compare with the second electrode terminal 9b, the first electrode terminal 9a is configured to the bight of more close semiconductor chip 3, and compare with the end of the second portion 7d of the lead-in wire 7 that is electrically connected to the second electrode terminal 9b, the end of second portion 7d that is electrically connected to the lead-in wire 7 of the first electrode terminal 9a extends to the position (referring to Figure 23 A) near semiconductor chip 3 one sides.Then, will connect the length of the first electrode terminal 9a, be set to L0 with being connected the length of the second electrode terminal 9b, promptly basic equal lengths with the lead 10 of the second portion 7d of lead-in wire 7 with the lead 10 of the second portion 7d of lead-in wire 7.
On the other hand, do not have under the situation of second portion 7d at lead-in wire 7 shown in Figure 23 B, the length that connects the lead 10 of lead-in wire 7 that is arranged close to each other and electrode terminal 9a, the 9b that is arranged close to each other is made as L1, L2 respectively, and it is longer than above-mentioned L0, thereby, inductance increases, and high frequency characteristics reduces.
In addition, because the length of L1 and L2 differs from one another, the difference between the inductance increases, and the paired characteristic of input signal reduces.
For example, be in the situation of gold (Au) lead of 25 μ m using diameter as lead, when working band is the GHZ magnitude,, also can cause the difference of 0.5nH (nanohenry) even the difference of conductor length only is 0.5mm.Therefore, might significantly destroy the paired characteristic of complementary input signal.
As the distribution standard (profile standard) of QFN, the lead-in wire 7 of back of the body surface periphery that is arranged on resin sealing body 2 is as external electrode terminal, 7 must be arranged in parallel with given spacing thereby go between.
In embodiment 5, as shown in Figure 23 A, lead-in wire 7 comprises the 7c of first that its lower surface exposes from the back of the body surface of resin sealing body 2, with the second portion 7d that extends and under the embedding state of embedded resin seal 2 inside, extend from the 7c of first, as previously described, second portion 7d can extend along free direction, the lead-in wire that is arranged close to each other can be respectively extends along desired direction, thereby the length of the lead 10 between the lead-in wire that is arranged close to each other 7 and the electrode terminal 9 that is arranged close to each other can be set at substantially and equates (L0).This result allows to connect the length of the first electrode terminal 9a and the lead 10 of lead-in wire 7, and is connected the length of the second electrode terminal 9b with the lead 10 of lead-in wire 7 and has equal length, and allow each lead 10 to have identical inductances.
In addition, as mentioned above, lead-in wire 7 second portion 7d is in seal 2 inside, do not expose from the back of the body surface of resin sealing body 2, thereby 7 the second portion 7d of going between can extend along free direction.That is, as shown in Figure 24 A, the bearing of trend of second portion 7d can be consistent with the bearing of trend of lead 10, thereby lead 10 can be arranged in the width of lead-in wire 7 end, and the length of coupling part of lead 10 is long to be " f " thereby can make.
Figure 24 B is the view that only is made of the situation of lead-in wire 7 7c of first.Because the 7c of first comprises the external electrode terminal in the back of the body surface that is in resin sealing body 2, each external electrode terminal be arranged in parallel in the mode that has therebetween to fixed gap.Therefore, as shown in Figure 24 B, because external electrode terminal more is close to the bight of rectangle resin sealing body 2 and is provided with, the angle theta of lead and external electrode terminal increases, and lead 10 is arranged to depart from the width of lead-in wire 7, intersect with the lateral edges of lead-in wire 7, thereby, lead 10 is h with the length that is connected of lead-in wire 7, and is shorter than connecting length f.
As 5 described in conjunction with the embodiments, consistent by the bearing of trend that makes second portion 7d as shown in Figure 24 A with the direction of extension of lead 10, lead-in wire 7 can be extended for " f " with the length that is connected between the lead 10.Therefore, can increase the bonding strength of lead, and strengthen the reliability that lead connects (lead joint).
In addition, in the RFVCO44 that handles high-frequency signal, the paired characteristic no less important of input signal.In embodiment 5, as shown in Figure 25, still will be designed to have same wire length as two leads 10 of two holding wires that in RFVCO44, extend.In addition,, provide electromagnetic shielding, crosstalk thereby prevent to produce to two holding wires by being arranged on the ground wire of two holding wire both sides.
Plane graph shown in Figure 26 shows the part of the manufacturing of hf power module, and show that the view of a part of lead frame, this lead frame partly are in and utilize lead 10 will be fixed to the electrode terminal 9 and lead-in wire 7 interconnective states of the semiconductor chip 3 of lead frame 13.Because the manufacture method according to the hf power module 1 of embodiment 5 is basic identical with the manufacture method of embodiment 1 medium-high frequency power model 1, omits its explanation.
In embodiment 5, as shown in the schematic amplification profile of Figure 27, semiconductor chip 3 is installed on the chip mounting portion 4 by adhesive 5.Semiconductor chip 3 comprises first semiconductor chip 85, be formed on the lip-deep insulating barrier 86 of first semiconductor chip 85, be formed on second semiconductor chip 87 on the insulating barrier 86, a plurality of electrode terminals 9 are formed on the first type surface of second semiconductor chip 87, a plurality of circuit blocks are formed on second semiconductor chip 87, and the back of the body of first semiconductor chip 85 of semiconductor chip 3 surface is electrically connected with chip mounting portion 4 by conductive adhesive 5.
First semiconductor chip 85 is P type silicon plates, and second semiconductor chip 87 is N type silicon plates.Both are stacked by insulating barrier 86 for first semiconductor chip 85 and second semiconductor chip 87, thereby form soi structure (silicon-on-insulator).The a plurality of electrode terminals 9 that are arranged on semiconductor chip 3 upper surfaces form the signal electrode terminal respectively, electrical source voltage electrode terminal and reference power source potential electrode terminal.The lead 10 that connects the electrode terminal 9 of chip mounting portion 4 and semiconductor chip 3 is following wire bonds 10a, and ground potential or negative potential are fixed in chip mounting portion 4.When negative potential was fixed in chip mounting portion 4, first semiconductor chip 85 was fixed on negative potential, thereby depletion layer extends to first semiconductor chip, 85 1 sides.
Thereby, can reduce to put on the parasitic capacitance of formed a plurality of circuit blocks on second semiconductor chip 87, thereby produce the quick operating effect of circuit.
In second semiconductor chip 87, form the isolation channel that a large amount of its lower bottom parts arrive insulating barrier 86.In these isolation channels, be filled with insulator 89, and isolation channel institute region surrounded constitutes electric independently island.Thereby, on the surface of second semiconductor chip 87 that each isolation channel centered on, whole or partly form N type with given impurity concentration and p type semiconductor layer (N P), thereby forms the semiconductor element that comprises given pn knot.In addition, this embodiment is designed to, on the surface of second semiconductor chip that comprises each electronic component, form insulating barrier INS1, INS2 (as silica membrane etc.) in succession, perhaps metal wiring layer (as aluminium, copper etc.), the conductor M1 to M4 that connects upper wiring layer and bottom wiring layer, and as shown in Figure 27, in the wiring M4 of the superiors, form a plurality of electrode terminals 9.
Schematic cross sectional view shown in Figure 28 shows the detailed structure of chip shown in Figure 27, and from left to right, semiconductor element is NPN vertical transistor (NPN Trs), PNP vertical transistor (V-PNP Trs), P channel type MOS transistor (PMOS), N channel type MOS transistor (NMOS), mos capacitance and resistance (polysilicon resistance).Thereby,, form the hf power module (semiconductor device) 1 shown in Fig. 3 by the combination of these a plurality of semiconductor elements.
, when making this hf power module 1, prepare first semiconductor chip 85 herein, afterwards, utilize insulating barrier 86 that second semiconductor chip 87 is laminated on first semiconductor chip 85.Then, after the semiconductor chip 87 that forms given thickness, remove second semiconductor chip 87 selectively by etching away given thickness.Subsequently, form required semiconductor layer selectively and repeatedly, and form each semiconductor element, simultaneously, form isolation channel and insulator 89.Then, form wire structures, last, longitudinally reach transverse cuts first semiconductor chip 85, to form semiconductor chip 3.
In hf power module 1 according to embodiment 5, low noise amplifier (LNA) 24 and RFVCO 44 that high-frequency signal is handled adopt 2 inputs/2 export structures, simultaneously, for guaranteeing the paired characteristic of two input signals, the length of two input leads 10 is arranged to identical length.In addition,, link to each other, make conductor length shorter, to reduce lead inductance by end with the electrode terminal 9 of lead 10 and semiconductor chip 3 and 7 the second portion 7d of going between for the length of the lead 10 that forms holding wire.Therefore, can strengthen high frequency characteristics (the DC biasing is less).
In other words, in embodiment 5, be used for GSM, three low noise amplifiers (LNA) 24 that DCS communicates by letter with PCS are made up of the differential low noise amplifier (differential amplifier) of 2 input types shown in Figure 33 B.Just, according to each low noise amplifier (LNA) 24 of embodiment 5 by two Unit Amplifier of its input signal (complementary signal) inverting each other are formed.Therefore,, still import complementary signal, therefore, eliminated same phase constituent, and in LNA 24, do not carried out amplification, thereby reduce the DC biasing even if leak in the LNA incoming line from the output signal of 90-degree phase shifter 40.Therefore, in the higher communication system of carrier frequency band, can obtain to suppress the advantageous effects that the DC biasing characteristic worsens.
In addition, the hf power module 1 according to embodiment 5 has the advantageous effects that reduces the DC biasing and suppress the gain reduction.
(embodiment 6)
Figure 31 represents the schematic cross sectional view according to the hf power module of another embodiment of the present invention (embodiment 6), this module has is arranged to the structure littler than semiconductor chip (little tab structure) with the tab of support semiconductor chip, and Figure 32 is illustrated in the schematic plan view of a part of lead frame with little tab structure that uses in the manufacturing of hf power module of embodiment 6.
Hf power module 1 according to embodiment 6 has such structure, wherein in according to the hf power module among the embodiment 51, adopts the chip mounting portion 4 little tab structure littler than semiconductor chip 3.In addition, mode with similar step makes tab hang crooked step of mid portion (not shown) of lead-in wire 6, make the lower surface of chip mounting portion 4 become higher than the lower surface of the 7c of first of lead-in wire 7, therefore, chip mounting portion 4 is embedded in the inside of resin sealing body 2.Just, embodiment 6 is characterised in that, forms step part between chip mounting portion 4 and 7 the 7c of first of going between, and chip mounting portion 4 is placed in the inside of resin sealing body 2.Therefore, not to the just welding of the certain applications below the lead bonding part, and when on mounting panel semiconductor chip being installed, the plate stress influence that not caused by variations in temperature can improve connection reliability.
As shown in figure 31, for the lead 10 that connects semiconductor chip 3 and lead-in wire 7, the link position of representing lead 10 and lead-in wire 7 with two point-line, by lead 10 being connected in the end of lead-in wire 7 second portion 7d, and be not attached to the end of lead-in wire 7 the 7c of first, can be with the about k of the contraction in length of lead.
Also has some beneficial effect that the hf power module 1 according to embodiment 1 is provided according to the hf power module 1 of embodiment 6.As shown in Figure 32, by adopting tab (chip mounting portion) 4, can strengthen the versatility of lead frame, and can reduce the manufacturing cost of hf power module 1 less than a kind of like this structure of semiconductor chip 3.
Figure 33 A to 33D represents the schematic cross sectional view of hf power module, demonstrates some other modified example of little tab structure.Figure 33 A has following structure, and wherein second portion 7d extends in a kind of mode of bending from 7 the 7c of first of going between, and second portion 7d is in the inside of resin sealing body 2.Because this structure, in the lead frame forming process, by crooked step part in the part therebetween, form lead-in wire 7 and tab and hang lead-in wire 6, in lead-in wire 7, in lead-in wire 7, form the second portion 7d that extends from the 7c of first with bend mode by this bending operation, and by making tab hang lead-in wire 6 bendings, chip mounting portion 4 embeds the inside of seal 2.Use this structure, it not is essential that the selective etch process of lead-in wire, chip mounting portion 4 and tab suspension lead-in wire 6 becomes, and can reduce the manufacturing cost of hf power module 1.
Figure 33 B represents that second portion 7d is with a kind of bend mode that only makes lead-in wire 7 bendings, do not make 6 bendings of tab suspension lead-in wire, from the structure of the 7c of first extension.In this example, owing to the structure that has adopted chip mounting portion 4 on the lower surface of resin sealing body 2, to expose, increased the thermal radiation effect of the lower surface of chip mounting portion 4.Therefore, improve the thermal radiation that is installed in the semiconductor element on the chip mounting portion 4, and realized stable operation.
Figure 33 C represents following structure, wherein in hf power module 1 according to embodiment 5, chip mounting portion 4 is created the tab littler than semiconductor chip 3, thereby, strengthen the versatility of lead frame, and can reduce the manufacturing cost of hf power module 1.
Figure 33 D is illustrated in the hf power module 1 according to embodiment 5, chip mounting portion 4 is created the tab littler than semiconductor chip 3, simultaneously, similar with the second portion 7d of lead-in wire 7, lower surface by etching chip mounting portion 4 forms chip mounting portion 4 thinner.
Because little tab structure, can strengthen the versatility of employed lead frame in the product, thereby, can reduce the manufacturing cost of hf power module 1.
Detailed explanation has been carried out in the invention that make inventor of the present invention on the basis of embodiment the front, but, the invention is not restricted to the foregoing description, can carry out multiple modification under the condition that does not depart from main idea of the present invention.
Though only described the shared of electrical source voltage or separation in the above-described embodiments at ground potential, application range but of the present invention is not limited to ground potential and its dependency structure, by when application is of the present invention, paying close attention to suitable electrical source voltage (first electromotive force), for example can be by making the shared electrical source voltage that reduces lead-in wire 7 quantity of electrode, the present invention can be applicable to provide the electrode terminal 9 of electrical source voltage or 7 the structure of going between.
In the above-described embodiments, be used to make the example of QFN N-type semiconductor N device although explained the present invention, for example, the present invention can similarly be applied to make SON N-type semiconductor N device, and can obtain substantially the same beneficial effect.In addition, the invention is not restricted to the non-terminal type semiconductor device, the present invention can similarly be applied to for example be called the semiconductor device of QFP (quad-flat-pack) or SOP (little gabarit encapsulation), and the lead-in wire that bends to the wing shape of gull in SOP stretches out along the edge of seal 2.But, compare, in order to realize miniaturization of devices, preferably adopt that lead-in wire has the QFP type structure of little overhang around seal 2 with above-mentioned QFP or SOP.
The following describes the beneficial effect of inventing acquisition by the typical case among the present invention who discloses among the application.
(1) provides a kind of and have following connected structure, is difficult to produce the semiconductor device of crosstalking.
(2) can provide the hf power module that comprises semiconductor element, wherein the mode by monolithic integrated circuit forms each circuit block such as low noise amplifier, blender, VCO, synthesizer, the IQ modulator/demodulator, the DC-AC modulator wherein can be subjected to the influence of the ground potential of remaining circuit parts hardly such as the ground potential of the specified circuit parts of low noise amplifier, RFVCO etc.
(3) can provide the non-terminal type hf power module that comprises semiconductor element with following connected structure, wherein the mode by monolithic integrated circuit forms each circuit block such as low noise amplifier, blender, VCO, synthesizer, the IQ modulator/demodulator, the DC-AC modulator wherein can be subjected to the influence of the ground potential of remaining circuit parts hardly such as the ground potential of the specified circuit parts of low noise amplifier, RFVCO etc.
(4) can provide miniaturization and the lightweight hf power module that comprises semiconductor element, wherein the mode by monolithic integrated circuit forms each circuit block such as low noise amplifier, blender, VCO, synthesizer, the IQ modulator/demodulator, the DC-AC modulator wherein can be subjected to the influence of the ground potential of remaining circuit parts hardly such as the ground potential of the specified circuit parts of low noise amplifier, RFVCO etc.
(5) can provide Wireless Telecom Equipment, it can provide has low noise good call.
(6) a kind of Wireless Telecom Equipment of handling a plurality of communication systems, it can provide has low noise good call.
(7) as previously mentioned, semiconductor device according to the invention is used for Wireless Telecom Equipment such as mobile phone etc.Particularly, in having the mobile phone of a plurality of communication systems, the circuit block of handling for extremely weak input signal such as the ground electrode terminal of low noise amplifier, be not connected with the tab that is used as the common ground electromotive force, and be connected with lead-in wire independent of each other, thereby, when using a certain communication system, do not produce between this communication system and other communication systems and crosstalk, a kind of hf power module that can carry out good call can be provided.
(8) by constituting lead-in wire with the second portion that extends to resin sealing body inside by the first that comprises external electrode terminal, can freely select the pattern of second portion, thereby, can select to make the as far as possible little lead pattern of length of the lead that connects semiconductor chip electrode terminal and lead-in wire.Therefore, can reduce lead inductance.
(9) in semiconductor device, can be equal length with the length setting of the lead that is connected with the electrode terminal that is used for two inputs, and obtain the paired characteristic of input signal with two input structure circuit blocks such as differential amplifier circuit parts etc.Therefore, when the low noise amplifier (LNA) of Wireless Telecom Equipment or RFVCO adopt two input structure circuit blocks, in each circuit block, can obtain the paired characteristic of input signal, can strengthen high frequency property, and suppress the reduction of gain.
Industrial applicibility
As previously described, semiconductor device according to the invention is used for radio communication equipment such as movement Phone etc. Particularly, in the mobile phone with a plurality of communication system, to extremely weak input letter The circuit block of number processing such as the ground electrode terminal of low-noise amplifier not with have public The joint sheet of ground potential connects, and lead-in wire is connected with being independently, thereby, when using certain During one communication system, this communication system communicates by letter with other with not producing between system and crosstalks, thereby, The hf power module that can carry out good call can be provided.

Claims (33)

1. semiconductor device comprises:
Seal is made by insulating resin;
A plurality of lead-in wires are along the peripheral of seal and in the inside and outside setting of seal;
Tab has first type surface and back of the body surface;
Semiconductor chip has first type surface and back of the body surface, and comprise a plurality of electrode terminals and a plurality of circuit block on its first type surface, and described circuit block is made up of a plurality of semiconductor elements respectively;
Be used for a plurality of electrode terminals and a plurality of leads that go between and link to each other; With
Be used for a plurality of electrode terminals are linked to each other with the tab first type surface, so that a plurality of leads of ground potential to be provided to these a plurality of electrode terminals,
Wherein the back of the body surface of semiconductor chip is fixed on the first type surface of tab,
Wherein said a plurality of circuit block comprises and being used to amplify by antenna by the first amplifying circuit parts of the electronic signal of wireless signal conversion be used to amplify by the second amplifying circuit parts of antenna by the electronic signal of wireless signal conversion,
Wherein said a plurality of electrode terminal comprises, be used for first electrode terminal to first amplifying circuit parts input external signal, be used for providing second electrode terminal of ground potential and to the third electrode terminal of second amplifying circuit parts inputs external signal to the first amplifying circuit parts
Wherein said a plurality of lead-in wire comprises first lead-in wire, and second goes between, and is arranged at the 3rd lead-in wire between first lead-in wire and second lead-in wire,
Wherein said first connecting terminal is connected with first lead-in wire by lead,
Wherein said second connecting terminal is connected with the 3rd lead-in wire by lead,
Wherein said the 3rd connecting terminal is connected with second lead-in wire by lead, and
Wherein said the 3rd lead-in wire is separated from one another with tab.
2. semiconductor device according to claim 1, the wherein said second amplifying circuit parts are for amplifying the circuit block of external signal that frequency range is different from the frequency range of the first amplifying circuit parts.
3. semiconductor device according to claim 2, wherein said a plurality of circuit blocks comprise oscillating circuit part, and are used for providing the connecting terminal of ground potential to be connected with tab by lead to oscillating circuit part.
4. semiconductor device that is used for Wireless Telecom Equipment comprises:
The semiconductor chip that comprises differential low noise amplifier with a pair of wireless signal input;
This is arranged on the first type surface of semiconductor chip first electrode and second electrode of wireless signal input;
The chip mounting portion is installed described semiconductor chip thereon;
Be arranged in chip mounting portion a plurality of lead-in wires on every side;
Be electrically connected first lead of first lead-in wire of first electrode and described a plurality of lead-in wires;
Be electrically connected second lead of second lead-in wire of second electrode and described a plurality of lead-in wires;
Cover the resin sealing body of the part of the each several part of described semiconductor chip, described lead-in wire and described chip mounting portion,
Wherein said semiconductor device has and does not have lead-in wire quad-flat-pack QFN structure;
Each of first and second lead-in wires has first and second portion;
Second portion extends internally towards the chip mounting portion from first;
First exposes from the back of the body surface of resin sealing body;
Second portion has the thickness less than first;
Second portion is positioned at the inside of resin sealing body;
Second portion in plan view from a part of diagonally extending; And
First and second leads join the second portion of first and second lead-in wires respectively to.
5. according to the semiconductor device of claim 4, wherein first and second leads have identical length.
6. according to the semiconductor device of claim 4, wherein differential low noise amplifier is handled the wireless signal that is received by antenna.
7. according to the semiconductor device of claim 4, wherein semiconductor device and baseband circuit electric coupling, and comprise modulator and demodulator;
Output signal from demodulator is imported into baseband circuit; And
Output signal from baseband circuit is imported into modulator.
8. according to the semiconductor device of claim 4, wherein said chip mounting portion exposes from the back of the body surface of described resin sealing body.
9. according to the semiconductor device of claim 4, the back of the body surface of the back of the body of the first of wherein said first and second lead-in wires surface and described chip mounting portion is arranged to receive welding material to be connected to mounting panel.
10. according to the semiconductor device of claim 4, wherein third electrode is disposed on the first type surface of semiconductor chip, and third electrode is connected to the chip mounting portion by following closing line.
12. according to the semiconductor device of claim 4, wherein said first the lead-in wire first and second parts upper surface at grade, and second the lead-in wire first and second parts upper surface at grade.
12. a semiconductor device that is used for Wireless Telecom Equipment comprises:
The semiconductor chip that comprises voltage controlled oscillator and low noise amplifier;
The chip mounting portion is installed described semiconductor chip thereon;
Be arranged in chip mounting portion a plurality of lead-in wires on every side; With
Cover the resin sealing body of the part of the each several part of described semiconductor chip, described lead-in wire and described chip mounting portion,
Wherein said chip mounting portion exposes from the back of the body surface of resin sealing body;
Be used to provide predetermined potential to be disposed in semiconductor chip to first electrode of low noise amplifier;
Be used to provide described predetermined potential to be disposed in semiconductor chip to second electrode of voltage controlled oscillator;
First electrode is electrically connected with one of described lead-in wire by first lead;
Second electrode is electrically connected with described chip mounting portion by second lead;
First electrode and second electrode are not electrically connected to each other in semiconductor device; And
First lead and second lead are not electrically connected to each other in semiconductor device.
13. according to the semiconductor device of claim 12, wherein said predetermined potential is a ground potential.
14. according to the semiconductor device of claim 12, wherein said semiconductor device is not have lead-in wire quad-flat-pack QFN structure.
15. according to the semiconductor device of claim 12, wherein said low noise amplifier is handled the wireless signal that is received by antenna.
16. according to the semiconductor device of claim 12, wherein semiconductor device also comprises modulator, demodulator and is used for terminal with the coupling of the baseband circuit of Wireless Telecom Equipment,
Output signal from demodulator is provided for one of described terminal to be input to baseband circuit; And
The input of modulator is coupled to another or described terminal to receive the output signal from baseband circuit.
17. a semiconductor device that is used for Wireless Telecom Equipment comprises:
Semiconductor chip, comprise the voltage controlled oscillator of the low noise amplifier that amplifies wireless signal, outputting oscillation signal, the output signal that receives low noise amplifier and voltage controlled oscillator oscillator signal blender and receive the demodulator of the output signal of blender;
The chip mounting portion is installed described semiconductor chip thereon;
Be arranged in chip mounting portion a plurality of lead-in wires on every side; With
Cover the resin sealing body of the part of the each several part of described semiconductor chip, described lead-in wire and described chip mounting portion,
Wherein said chip mounting portion exposes from the back of the body surface of resin sealing body;
Be used to provide predetermined potential to be disposed in semiconductor chip to first electrode of low noise amplifier;
Be used for providing described predetermined potential to be disposed in semiconductor chip to voltage controlled oscillator, blender and demodulator second electrode one of at least;
First electrode is electrically connected with one of described lead-in wire by first lead;
Second electrode is electrically connected with described chip mounting portion by second lead;
First electrode and second electrode are not electrically connected to each other in semiconductor device; And
First lead and second lead are not electrically connected to each other in semiconductor device.
18. a semiconductor device that is used for Wireless Telecom Equipment comprises:
The semiconductor chip that comprises wireless signal amplifier and voltage controlled oscillator;
The chip mounting portion is installed described semiconductor chip thereon;
Be arranged in chip mounting portion a plurality of lead-in wires on every side;
Cover the resin sealing body of the part of the each several part of described semiconductor chip, described lead-in wire and described chip mounting portion;
First electrode is disposed on the semiconductor chip, is used to provide predetermined potential to arrive the wireless signal amplifier;
Second electrode is disposed on the semiconductor chip, is used to provide described predetermined potential to voltage controlled oscillator,
Wherein said chip mounting portion exposes from the back of the body surface of resin sealing body;
First electrode is electrically connected with one of described lead-in wire by first lead;
Second electrode is electrically connected with described chip mounting portion by second lead;
First electrode and second electrode are not electrically connected to each other in semiconductor device; And
First lead and second lead are not electrically connected to each other in semiconductor device.
19. a semiconductor device that is used for Wireless Telecom Equipment comprises:
The semiconductor chip that comprises wireless signal amplifier and voltage controlled oscillator;
The chip mounting portion is installed described semiconductor chip thereon;
Be arranged in chip mounting portion a plurality of lead-in wires on every side;
Cover the resin sealing body of the part of the each several part of described semiconductor chip, described lead-in wire and described chip mounting portion;
First electrode is disposed on the semiconductor chip, is used to provide predetermined potential to arrive the wireless signal amplifier;
Second electrode is disposed on the semiconductor chip, is used to provide described predetermined potential to voltage controlled oscillator,
Wherein said chip mounting portion exposes from the back of the body surface of resin sealing body;
First electrode is electrically connected with one of described lead-in wire by first lead;
Second electrode is electrically connected with described chip mounting portion by second lead;
First electrode and second electrode are electrically isolated from one in semiconductor device; And
First lead and second lead are electrically isolated from one in semiconductor device.
20. a semiconductor device that is used for Wireless Telecom Equipment comprises:
The semiconductor chip that comprises modulator, demodulator, the first differential low noise amplifier and the second differential low noise amplifier;
The chip mounting portion is installed described semiconductor chip thereon;
Be arranged in chip mounting portion a plurality of lead-in wires on every side;
Cover the resin sealing body of the part of the each several part of described semiconductor chip, described lead-in wire and described chip mounting portion,
Wherein said first and second low noise amplifiers are arranged side by side;
Each of described first and second low noise amplifiers has a pair of wireless signal input;
First pair of right electrode of described wireless signal input of described first low noise amplifier is arranged side by side on the first type surface of semiconductor chip;
Second pair of right electrode of described wireless signal input of described second low noise amplifier is arranged side by side on the first type surface of semiconductor chip;
Be used to provide the 5th electrode of predetermined potential to be disposed in the first type surface of semiconductor chip;
First pair of electrode is electrically connected with the first couple lead-in wire of described a plurality of lead-in wires respectively by first pair of lead;
Second pair of electrode is electrically connected with the second couple lead-in wire of described a plurality of lead-in wires respectively by second pair of lead;
The 5th electrode is connected to the 5th lead, and the 5th electrode is between first and second pairs of electrodes; And
The 5th lead is between first and second pairs of leads.
21. according to the semiconductor device of claim 20, wherein said predetermined potential is a ground potential.
22. according to the semiconductor device of claim 20, wherein said semiconductor device is not have lead-in wire quad-flat-pack QFN structure.
23. according to the semiconductor device of claim 20, the lead-in wire of wherein said first and second pairs of lead-in wires bends in plan view.
24. according to the semiconductor device of claim 20, wherein said first and second low noise amplifiers are handled the wireless signal that is received by antenna.
25. according to the semiconductor device of claim 20, wherein semiconductor device and baseband circuit electric coupling is imported into baseband circuit from the output signal of demodulator, and is imported into modulator from the output signal of baseband circuit.
26. according to the semiconductor device of claim 20, wherein said chip mounting portion exposes from the back of the body surface of described resin sealing body.
27. a semiconductor device that is used for Wireless Telecom Equipment comprises:
The semiconductor chip that comprises modulator, demodulator, the first differential low noise amplifier and the second differential low noise amplifier;
The chip mounting portion is installed described semiconductor chip thereon;
Be arranged in chip mounting portion a plurality of lead-in wires on every side;
Cover the resin sealing body of the part of the each several part of described semiconductor chip, described lead-in wire and described chip mounting portion,
Each of wherein said first and second low noise amplifiers has a pair of wireless signal input;
First pair of right electrode of described wireless signal input of described first low noise amplifier is arranged side by side on the first type surface of semiconductor chip, and this first pair of electrode comprises first electrode and second electrode;
Second pair of right electrode of described wireless signal input of described second low noise amplifier is arranged side by side on the first type surface of semiconductor chip, and this second pair of electrode comprises third electrode and the 4th electrode;
Be used to provide the 5th electrode of predetermined potential to be disposed in the first type surface of semiconductor chip;
First to the 5th electrode is pressed following sequence arrangement along its length in a side of semiconductor chip: first electrode, second electrode, the 5th electrode, third electrode and the 4th electrode;
First pair of electrode is electrically connected with the first couple lead-in wire of described a plurality of lead-in wires respectively by first pair of lead;
Second pair of electrode is electrically connected with the second couple lead-in wire of described a plurality of lead-in wires respectively by second pair of lead;
The 5th electrode is connected to the 5th lead; And
The 5th lead is between first and second pairs of leads.
28. according to the semiconductor device of claim 27, wherein said predetermined potential is a ground potential.
29. according to the semiconductor device of claim 27, wherein said semiconductor device is not have lead-in wire quad-flat-pack QFN structure.
30. according to the semiconductor device of claim 27, the lead-in wire of wherein said first and second pairs of lead-in wires bends in plan view.
31. according to the semiconductor device of claim 27, wherein said first and second low noise amplifiers are handled the wireless signal that is received by antenna.
32. according to the semiconductor device of claim 27, wherein semiconductor device and baseband circuit electric coupling is imported into baseband circuit from the output signal of demodulator, and is imported into modulator from the output signal of baseband circuit.
33. according to the semiconductor device of claim 27, wherein said chip mounting portion exposes from the back of the body surface of described resin sealing body.
CNB2007101273468A 2002-04-30 2003-04-28 Semiconductor device and electronic device Expired - Lifetime CN100536123C (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001189402A (en) * 1999-12-28 2001-07-10 Hitachi Ltd Semiconductor device and manufacturing method therefor
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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001189402A (en) * 1999-12-28 2001-07-10 Hitachi Ltd Semiconductor device and manufacturing method therefor
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