JP4828235B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4828235B2
JP4828235B2 JP2006009373A JP2006009373A JP4828235B2 JP 4828235 B2 JP4828235 B2 JP 4828235B2 JP 2006009373 A JP2006009373 A JP 2006009373A JP 2006009373 A JP2006009373 A JP 2006009373A JP 4828235 B2 JP4828235 B2 JP 4828235B2
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Japan
Prior art keywords
electrode
protruding
amplifier circuit
electrodes
semiconductor chip
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Expired - Fee Related
Application number
JP2006009373A
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Japanese (ja)
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JP2007194305A (en
Inventor
▲静▼城 中島
浩之 長井
智 櫻井
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2006009373A priority Critical patent/JP4828235B2/en
Publication of JP2007194305A publication Critical patent/JP2007194305A/en
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Publication of JP4828235B2 publication Critical patent/JP4828235B2/en
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Description

本発明は、半導体装置技術に関し、特に、ＲＦ（Radio Frequency：高周波）パワーモジュールに適用して有効な技術に関するものである。   The present invention relates to a semiconductor device technology, and more particularly to a technology effective when applied to an RF (Radio Frequency) power module.

ＲＦパワーモジュールについては、例えば特開平９−１１６０９１号公報（特許文献１）に開示がある。この文献では、高周波電力増幅回路が形成された半導体チップが、その主面を上に向けた状態で配線基板上に実装されている。この半導体チップの主面の電極は、ボンディングワイヤを通じて配線基板に電気的に接続されている。
特開平９−１１６０９１号公報 The RF power module is disclosed in, for example, Japanese Patent Laid-Open No. 9-116091 (Patent Document 1). In this document, a semiconductor chip on which a high frequency power amplifier circuit is formed is mounted on a wiring board with its main surface facing upward. The electrodes on the main surface of the semiconductor chip are electrically connected to the wiring board through bonding wires.
JP-A-9-116091

ところで、半導体装置の小型化要求に伴い、半導体チップを配線基板に実装する方式をフェイスアップ実装方式からフェイスダウン（フリップチップ）実装方式に変更することが検討されている。   By the way, in response to a demand for miniaturization of a semiconductor device, it is considered to change a method for mounting a semiconductor chip on a wiring board from a face-up mounting method to a face-down (flip chip) mounting method.

しかし、フェイスアップ実装方式の場合は、半導体チップで生じた熱を半導体チップの裏面全面を通じて外部に放散していたのに対して、フリップチップ実装方式の場合は、半導体チップで生じた熱を、半導体チップの主面に形成された複数の微細なバンプ電極のみを通じて外部に放散するようになる。この結果、放熱領域が小さくなり、熱抵抗が増大してしまう。また、フェイスアップ実装方式でワイヤボンディング接続を行う場合、高周波信号の端子においてはボンディングワイヤ同士を直交させることで発振現象を抑制または防止しているが、フリップチップ実装方式の場合は、その手法を採用できず発振による不良発生のポテンシャルが大きい。いずれの不具合も半導体装置の動作信頼性を低下させるという問題がある。   However, in the case of the face-up mounting method, the heat generated in the semiconductor chip is dissipated to the outside through the entire back surface of the semiconductor chip, whereas in the case of the flip chip mounting method, the heat generated in the semiconductor chip is It diffuses to the outside only through a plurality of fine bump electrodes formed on the main surface of the semiconductor chip. As a result, the heat dissipation area is reduced and the thermal resistance is increased. In addition, when performing wire bonding connection with the face-up mounting method, the oscillation phenomenon is suppressed or prevented by making the bonding wires orthogonal to each other at the terminals of the high frequency signal. Cannot be used, and the potential for defects due to oscillation is great. Any of these problems has a problem of reducing the operation reliability of the semiconductor device.

そこで、本発明の目的は、半導体装置の動作信頼性を向上させることのできる技術を提供することにある。   Therefore, an object of the present invention is to provide a technique capable of improving the operation reliability of a semiconductor device.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

すなわち、本発明は、電極増幅回路を有する半導体チップの第１主面上に複数の突起電極を備え、前記複数の突起電極の各々は、金属層と、前記金属層に接した状態で形成され前記金属層よりも融点が低い半田層とを有しており、前記複数の突起電極のうちの第１突起電極と第２突起電極との間に、前記第１、第２突起電極よりも平面積の大きな発振シールド用の第３突起電極を配置したものである。   That is, the present invention includes a plurality of protruding electrodes on a first main surface of a semiconductor chip having an electrode amplifier circuit, and each of the plurality of protruding electrodes is formed in contact with the metal layer. A solder layer having a melting point lower than that of the metal layer, and is more flat than the first and second protruding electrodes between the first protruding electrode and the second protruding electrode of the plurality of protruding electrodes. A third protruding electrode for an oscillation shield having a large area is arranged.

また、本願において開示される発明のうち、他のものの概要を簡単に説明すれば、次のとおりである。   The outline of other inventions disclosed in the present application will be briefly described as follows.

すなわち、本発明は、半導体チップの第１主面に形成された複数の突起電極とを備え、前記複数の突起電極の中には、相対的に平面積が異なる突起電極があり、前記複数の突起電極のうち、相対的に面積が大きな突起電極の平面パターンは、その幅方向の寸法が、相対的に広い部分と狭い部分とを有しており、前記相対的に広い部分の隣接間に、前記相対的に狭い部分が配置される形状を有しているものである。   That is, the present invention includes a plurality of protruding electrodes formed on a first main surface of a semiconductor chip, and among the plurality of protruding electrodes, there are protruding electrodes having relatively different plane areas. Among the projecting electrodes, the planar pattern of the projecting electrode having a relatively large area has a relatively wide portion and a narrow portion in the width direction, and is adjacent to the relatively wide portion. And a shape in which the relatively narrow portion is arranged.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。   Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

すなわち、前記複数の突起電極のうちの第１突起電極と第２突起電極との間に、前記第１、第２突起電極よりも平面積の大きな発振シールド用の第３突起電極を配置したことにより、半導体装置の動作信頼性を向上させることができる。   That is, the third projection electrode for the oscillation shield having a larger area than the first and second projection electrodes is disposed between the first projection electrode and the second projection electrode of the plurality of projection electrodes. As a result, the operational reliability of the semiconductor device can be improved.

以下の実施の形態においては便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。また、本実施の形態を説明するための全図において同一機能を有するものは同一の符号を付すようにし、その繰り返しの説明は可能な限り省略するようにしている。以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、本願で「高周波」と言う場合、概ね５００ＭＨｚ程度以上の周波数帯を指している。また、ＲＦパワーモジュールを単にパワーモジュールという。   In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present application, “high frequency” refers to a frequency band of approximately 500 MHz or more. The RF power module is simply called a power module.

（実施の形態１）
図１は本実施の形態１のパワーモジュール（半導体装置）ＰＭの一例の全体平面図、図２は図１のパワーモジュールＰＭのＹ１−Ｙ１線の断面図である。なお、図１および図２では、図面を見易くするため封止部材を取り除いた状態を示している。 (Embodiment 1)
1 is an overall plan view of an example of a power module (semiconductor device) PM according to the first embodiment, and FIG. 2 is a cross-sectional view taken along line Y1-Y1 of the power module PM in FIG. 1 and 2 show a state in which the sealing member is removed for easy viewing of the drawings.

パワーモジュールＰＭを構成するモジュール基板（基板）ＰＭＢは、例えば平面四角形状の薄板からなり、その厚さ方向に沿って複数の絶縁層および配線層を交互に積み重ねて一体化した多層配線構造を有している。モジュール基板ＰＭＢの絶縁層は、例えばミリ波域まで誘電損失の少ないアルミナ（酸化アルミニウム、Ａｌ２Ｏ３、比誘電率＝９〜９．７）等のようなセラミックによって形成されている。ただし、モジュール基板ＰＭＢの絶縁層の材料は、これに限定されるものではなく種々変更可能であり、例えばガラスエポキシ樹脂により形成しても良い。 The module substrate (substrate) PMB that constitutes the power module PM is made of, for example, a planar rectangular thin plate, and has a multilayer wiring structure in which a plurality of insulating layers and wiring layers are alternately stacked and integrated along the thickness direction. is doing. The insulating layer of the module substrate PMB is formed of a ceramic such as alumina (aluminum oxide, Al 2 O 3 , relative dielectric constant = 9 to 9.7) having a low dielectric loss up to the millimeter wave region, for example. However, the material of the insulating layer of the module substrate PMB is not limited to this and can be variously changed. For example, the insulating layer may be formed of a glass epoxy resin.

また、モジュール基板ＰＭＢは、その厚さ方向に沿って互いに反対側に位置する第１主面および第２主面を有している。このモジュール基板ＰＭＢの第１主面には、電極３および配線（伝送線路）が形成されている。また、モジュール基板ＰＭＢの第１主面上には、半導体チップ１およびチップ部品２等のような電子部品が搭載されている。ここでは、モジュール基板ＰＭＢの第１主面上に、１個の半導体チップ１と複数のチップ部品２とが搭載されている場合が例示されている。   Further, the module substrate PMB has a first main surface and a second main surface which are located on opposite sides along the thickness direction. An electrode 3 and wiring (transmission line) are formed on the first main surface of the module substrate PMB. Electronic components such as the semiconductor chip 1 and the chip component 2 are mounted on the first main surface of the module substrate PMB. Here, a case where one semiconductor chip 1 and a plurality of chip components 2 are mounted on the first main surface of the module substrate PMB is illustrated.

また、モジュール基板ＰＭＢの第２主面には、パワーモジュールＰＭの信号および電源用の複数の外部端子４が配置されている。この複数の外部端子４は、パワーモジュールＰＭを搭載する配線基板の電極と電気的に接続される。   A plurality of external terminals 4 for signals and power of the power module PM are arranged on the second main surface of the module substrate PMB. The plurality of external terminals 4 are electrically connected to electrodes of a wiring board on which the power module PM is mounted.

さらに、モジュール基板ＰＭＢの第１主面と第２主面との間の上記配線層には配線５が形成されている。異なる配線層の配線５，５同士は、スルーホールによって電気的に接続されている。スルーホールは、配線層に対して交差する方向に延び、配線層間を貫通するように形成されている。   Furthermore, wiring 5 is formed in the wiring layer between the first main surface and the second main surface of the module substrate PMB. The wirings 5 and 5 in different wiring layers are electrically connected by through holes. The through hole extends in a direction intersecting the wiring layer and is formed so as to penetrate the wiring layer.

上記半導体チップ１は、例えばシリコン（Ｓｉ）等のような半導体を基材とする平面四角形状の薄板からなり、その厚さ方向に沿って互いに反対側に位置する第１主面および第２主面を有している。この半導体チップ１の第１主面には、複数のバンプ電極（突起電極）８が形成されている。また、半導体チップ１には増幅回路が形成されている。ここでは、その増幅回路が、例えば３段の高周波パワーＭＩＳ・ＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor：以下、単にパワーＭＩＳと略す）が直列接続された構成を有している。この増幅回路は、上記複数のバンプ電極８と電気的に接続されている。   The semiconductor chip 1 is composed of a flat plate-like thin plate whose base material is a semiconductor such as silicon (Si), and has a first main surface and a second main surface located on opposite sides along the thickness direction. Has a surface. A plurality of bump electrodes (projection electrodes) 8 are formed on the first main surface of the semiconductor chip 1. In addition, an amplifier circuit is formed on the semiconductor chip 1. Here, the amplifier circuit has a configuration in which, for example, three stages of high-frequency power MIS • FETs (Metal Insulator Semiconductor Field Effect Transistors: hereinafter simply referred to as power MIS) are connected in series. This amplifier circuit is electrically connected to the plurality of bump electrodes 8.

このような半導体チップ１は、上記モジュール基板ＰＭＢの第１主面上にフリップチップボンディング（またはフェースダウンボンディング）されている。すなわち、半導体チップ１は、その第１主面を、上記モジュール基板ＰＭＢの第１主面に向けた状態で、バンプ電極８を介してモジュール基板ＰＭＢの第１主面上に搭載されている。これにより、半導体チップ１に形成された増幅回路はバンプ電極８を介してモジュール基板ＰＭＢの上記配線と電気的に接続されている。   Such a semiconductor chip 1 is flip-chip bonded (or face-down bonded) on the first main surface of the module substrate PMB. That is, the semiconductor chip 1 is mounted on the first main surface of the module substrate PMB via the bump electrodes 8 with the first main surface thereof facing the first main surface of the module substrate PMB. Thereby, the amplifier circuit formed on the semiconductor chip 1 is electrically connected to the wiring of the module substrate PMB via the bump electrode 8.

ここでは、半導体チップ１が、モジュール基板ＰＭＢの第１主面の中央よりも若干入力（図１の左側）寄りに配置されており、モジュール基板ＰＭＢの第１主面の出力側の領域の方が入力側の領域よりも広くなっている。これにより、モジュール基板ＰＭＢに配置された出力用の整合回路を低損失に設計することができるので、パワーモジュールＰＭの出力損失を低減でき、高い出力を引き出すことが可能となっている。なお、半導体チップ１の第１主面とモジュール基板ＰＭＢの第１主面との対向面間には、アンダーフィルＵＦが充填されている。   Here, the semiconductor chip 1 is arranged slightly closer to the input (left side in FIG. 1) than the center of the first main surface of the module substrate PMB, and the region on the output side of the first main surface of the module substrate PMB Is wider than the area on the input side. As a result, the output matching circuit disposed on the module substrate PMB can be designed with low loss, so that the output loss of the power module PM can be reduced and high output can be extracted. An underfill UF is filled between the opposing surfaces of the first main surface of the semiconductor chip 1 and the first main surface of the module substrate PMB.

上記チップ部品は、例えばコンデンサ、インダクタおよび抵抗等のような受動部品であり、例えばパワーモジュールＰＭの電力増幅回路の整合回路等を形成するものである。   The chip component is a passive component such as a capacitor, an inductor, and a resistor, and forms a matching circuit of a power amplifier circuit of the power module PM, for example.

次に、図３は上記半導体チップ１の第１主面の全体平面図、図４は図３の半導体チップ１の第１主面上のバンプ電極８の拡大平面図、図５はバンプ電極８の変形例の拡大平面図を示している。   3 is an overall plan view of the first main surface of the semiconductor chip 1, FIG. 4 is an enlarged plan view of the bump electrode 8 on the first main surface of the semiconductor chip 1 in FIG. 3, and FIG. The enlarged plan view of the modification of is shown.

半導体チップ１の第１主面には、上記複数のバンプ電極８が配置されている。このうち、黒塗りのバンプ電極（第１突起電極）８ｇは、上記パワーＭＩＳのゲート電極に電気的に接続されている。このバンプ電極８ｇは、例えば平面略円形状に形成されている。   The plurality of bump electrodes 8 are arranged on the first main surface of the semiconductor chip 1. Among these, the black bump electrode (first protruding electrode) 8g is electrically connected to the gate electrode of the power MIS. The bump electrode 8g is formed in a substantially circular shape, for example.

また、複数のバンプ電極８のうち、斜線のハッチングが付されたバンプ電極（第２突起電極）８ｄは、上記パワーＭＩＳのドレイン電極に電気的に接続されている。このバンプ電極８ｄの中には、上記バンプ電極８ｇと同等の平面積および平面形状のものと、上記バンプ電極８ｇよりも平面積が大きく平面帯状に形成されたものとがある。   Of the plurality of bump electrodes 8, a hatched hatch electrode (second protrusion electrode) 8d is electrically connected to the drain electrode of the power MIS. Among the bump electrodes 8d, there are a plane area and a plane shape equivalent to the bump electrode 8g, and a bump area having a plane area larger than that of the bump electrode 8g and formed in a plane band shape.

また、複数のバンプ電極８のうち、梨地のハッチングが付されたバンプ電極（第３突起電極）８ｓは、上記パワーＭＩＳのソース電極に電気的に接続されており、基準電位（例えばＧＮＤ電位で０Ｖ）が印加されるようになっている。このバンプ電極８ｓは、平面帯状（Ｌ字状やＴ字状）に形成されており、その平面積（長さ）が他のバンプ電極８よりも大きい（長い）。特に、本実施の形態１では、バンプ電極８ｓに発振シールド機能を持たせている。すなわち、相対的に面積が大きい（長さが長い）ソース電極用のバンプ電極８ｓが、相対的に面積が小さい（長さが短い）ゲート電極用のバンプ電極８ｇと、ドレイン電極用のバンプ電極８ｄとの間に配置されている。好ましくはソース電極用のバンプ電極８ｓがドレイン電極用のバンプ電極８ｄを取り囲むように配置されている。これにより、発振現象を抑制または防止できる。また、バンプ電極８ｓ，８ｄの面積を大きくしたことにより、半導体チップ１の回路動作時において発生した熱の放熱性を向上させることができる。これらにより、パワーモジュールＰＭの動作信頼性を向上させることができる。また、ゲート電極用のバンプ電極とドレイン電極用のバンプ電極とを離すことで発振現象を抑制または防止することも考えられるが、半導体チップのサイズ縮小と、それらの電極をあまり離して配置すると配線長が長くなり機能や動作信頼性が阻害される観点とからゲート電極用のバンプ電極とドレイン電極用のバンプ電極とをあまり離して配置することはできない。これに対して本実施の形態１では、ゲート電極用のバンプ電極とドレイン電極用のバンプ電極とを大きく離して配置することもないので、半導体チップのサイズ縮小と、機能や動作信頼性の向上とを確保したまま発振を抑制または防止できる。   Among the plurality of bump electrodes 8, a bump electrode (third projection electrode) 8s with a satin hatching is electrically connected to the source electrode of the power MIS, and is a reference potential (for example, a GND potential). 0V) is applied. The bump electrode 8s is formed in a flat belt shape (L-shaped or T-shaped), and the plane area (length) thereof is larger (longer) than the other bump electrodes 8. In particular, in the first embodiment, the bump electrode 8s has an oscillation shield function. That is, a bump electrode 8s for a source electrode having a relatively large area (long length), a bump electrode 8g for a gate electrode having a relatively small area (short length), and a bump electrode for a drain electrode 8d. Preferably, the bump electrode 8s for the source electrode is disposed so as to surround the bump electrode 8d for the drain electrode. Thereby, an oscillation phenomenon can be suppressed or prevented. Further, by increasing the area of the bump electrodes 8s and 8d, the heat dissipation of the heat generated during the circuit operation of the semiconductor chip 1 can be improved. As a result, the operational reliability of the power module PM can be improved. In addition, it may be possible to suppress or prevent the oscillation phenomenon by separating the bump electrode for the gate electrode and the bump electrode for the drain electrode. However, if the size of the semiconductor chip is reduced and these electrodes are arranged too far apart, wiring is performed. The bump electrode for the gate electrode and the bump electrode for the drain electrode cannot be arranged so far from the viewpoint that the length becomes long and the function and operation reliability are hindered. On the other hand, in the first embodiment, the bump electrode for the gate electrode and the bump electrode for the drain electrode are not arranged greatly apart from each other, so that the size of the semiconductor chip is reduced and the function and operation reliability are improved. Oscillation can be suppressed or prevented while ensuring.

なお、バンプ電極８の平面形状は、Ｌ字状やＴ字状の他に、図５に示すようにコ字状にしても良い。また、上記以外の平面円形状の白地のバンプ電極８は、その他の信号および電源用の電極である。また、本実施の形態１では、平面積が相対的に大きいバンプ電極８の幅方向（短方向）寸法は、設計上、バンプ電極８の延在方向（長手方向）において等しくなるように設計されている。   The planar shape of the bump electrode 8 may be a U shape as shown in FIG. 5 in addition to the L shape or the T shape. Further, the planar bump electrode 8 having a flat circular shape other than the above is an electrode for other signals and power. Further, in the first embodiment, the width direction (short direction) dimension of the bump electrode 8 having a relatively large plane area is designed to be equal in the extending direction (longitudinal direction) of the bump electrode 8 by design. ing.

次に、図６は上記半導体チップ１のバンプ電極８の拡大平面図、図７は図６のＸ１−Ｘ１線の断面図である。なお、図７は、半導体チップ１の第１主面の最上の配線層（半導体チップ１の外部端子であるボンディングパッド（以下、単にパッドという）ＢＰが配置された層）とその上層とを示し、それよりも下層については図示を省略している。   6 is an enlarged plan view of the bump electrode 8 of the semiconductor chip 1, and FIG. 7 is a cross-sectional view taken along line X1-X1 of FIG. FIG. 7 shows an uppermost wiring layer (a layer in which a bonding pad (hereinafter simply referred to as a pad) BP, which is an external terminal of the semiconductor chip 1) is disposed, and an upper layer thereof. The lower layers are not shown.

半導体チップ１の第１主面の最上の配線層（最も表層の配線層）には、表面保護膜１０が堆積されている。この表面保護膜１０は、下層の保護膜１０ａと、その上層の保護膜１０ｂとの積層膜を有している。下層の保護膜１０ａは、例えば窒化シリコン（Ｓｉ３Ｎ４）の単体膜や酸化シリコン（ＳｉＯ２）膜上に窒化シリコン膜が堆積された積層膜で形成されている。その上層の保護膜１０ｂは、例えばポリイミド樹脂等のような有機膜で形成されている。 A surface protective film 10 is deposited on the uppermost wiring layer (most surface wiring layer) on the first main surface of the semiconductor chip 1. The surface protective film 10 has a laminated film of a lower protective film 10a and an upper protective film 10b. The lower protective film 10a is formed of, for example, a single film of silicon nitride (Si 3 N 4 ) or a laminated film in which a silicon nitride film is deposited on a silicon oxide (SiO 2 ) film. The upper protective film 10b is formed of an organic film such as a polyimide resin.

この表面保護膜１０の一部には開口部１１が形成されており、そこから上記パッドＢＰの一部が露出されている。パッドＢＰは、例えばアルミニウム（Ａｌ）等のような金属によって形成されている。パッドＢＰは、例えば平面八角形状に形成されている。   An opening 11 is formed in a part of the surface protective film 10, and a part of the pad BP is exposed therefrom. The pad BP is made of a metal such as aluminum (Al). The pad BP is formed in a planar octagon shape, for example.

このパッドＢＰ上には、上記バンプ電極８が電気的に接続された状態で形成されている。バンプ電極８は、相対的に大きいものも小さいものも、下地金属層ＵＢＭと、金属層Ｍと、バリア金属層ＢＭと、半田層Ｓとを有している。   On the pad BP, the bump electrode 8 is formed in an electrically connected state. The bump electrode 8 has a base metal layer UBM, a metal layer M, a barrier metal layer BM, and a solder layer S, both relatively large and small.

下地金属層ＵＢＭは、例えばＴｉＣｕ等のような上記半田層よりも融点の高い金属によって形成されている。下地金属層ＵＢＭは、その上下の金属層の原子の拡散を抑制または防止する機能を有する機能層であり、パッドＢＰおよび金属層の間にその各々に直接接した状態で形成されている。   The base metal layer UBM is formed of a metal having a melting point higher than that of the solder layer, such as TiCu. The underlying metal layer UBM is a functional layer having a function of suppressing or preventing diffusion of atoms in the upper and lower metal layers, and is formed between the pad BP and the metal layer so as to be in direct contact with each other.

上記金属層Ｍは、例えば銅（Ｃｕ）のような上記半田層よりも融点が高い金属によって形成されている。銅に代えて金（Ａｕ）を使用しても良いが、銅にすることでコストを低減できる。金属層Ｍの厚さは、下地金属層ＵＢＭよりも厚く形成されている。   The metal layer M is made of a metal having a melting point higher than that of the solder layer, such as copper (Cu). Although gold (Au) may be used instead of copper, the cost can be reduced by using copper. The metal layer M is formed thicker than the base metal layer UBM.

上記バリア金属層は、例えばニッケル（Ｎｉ）等のような上記半田層よりも融点が高い金属によって形成されている。バリア金属層は、半田層Ｓおよび金属層Ｍの原子の拡散を抑制または防止する機能と、その他に、半田層Ｓと金属層Ｍとの接着性を向上させる機能とを有する機能層であり、半田層Ｓと金属層Ｍとの間にその各々に接触した状態で形成されている。   The barrier metal layer is formed of a metal having a higher melting point than the solder layer, such as nickel (Ni). The barrier metal layer is a functional layer having a function of suppressing or preventing diffusion of atoms in the solder layer S and the metal layer M and a function of improving the adhesion between the solder layer S and the metal layer M. The solder layer S and the metal layer M are formed in contact with each other.

上記半田層Ｓは、例えば鉛（Ｐｂ）−錫（Ｓｎ）等により形成されている。半田層Ｓは、鉛―錫に代えて、例えば銅（Ｃｕ）−ニッケル（Ｎｉ）−錫（Ｓｎ）−銀（Ａｇ）合金等のような無鉛半田を用いても良い。   The solder layer S is made of, for example, lead (Pb) -tin (Sn). For the solder layer S, lead-free solder such as copper (Cu) -nickel (Ni) -tin (Sn) -silver (Ag) alloy may be used instead of lead-tin.

このようなバンプ電極８の形成方法は、例えば次のとおりである。まず、上記開口部１１を形成した後の半導体基板（半導体チップ１を構成する部材であって、この段階ではウエハと称する平面略円形状の半導体薄板）の第１主面上全面に、下地金属層ＵＢＭをスパッタリング法または蒸着法によって堆積した後、その上にバンプ電極形成領域（すなわち、パッドＢＰの上面）が露出されるようなフォトレジストパターンを形成する。続いて、フォトレジストパターンをマスクにして、そこから露出されるパッドＢＰ上に、例えば銅のような金属層Ｍをメッキ法により堆積する。その後、その金属層Ｍ上にバリア金属層をメッキ法または蒸着法によって堆積した後、さらにその上に半田層Ｓをメッキ法または蒸着法によって堆積する。その後、上記フォトレジストパターンを除去した後、残された金属層Ｍ、バリア金属層ＢＭおよび半田層Ｓのパターンをマスクにして、そこから露出される下地金属層ＵＢＭをエッチング除去する。その後、半導体基板に熱処理（リフロ処理）を施すことにより、上記半田層Ｓを溶融してバンプ電極８を形成する。   A method for forming such a bump electrode 8 is, for example, as follows. First, a base metal is formed on the entire surface of the first main surface of the semiconductor substrate (a member constituting the semiconductor chip 1, which is a planar thin semiconductor plate called a wafer at this stage) after the opening 11 is formed. After the layer UBM is deposited by sputtering or vapor deposition, a photoresist pattern is formed on which the bump electrode formation region (that is, the upper surface of the pad BP) is exposed. Subsequently, a metal layer M such as copper is deposited on the pad BP exposed from the photoresist pattern as a mask by a plating method. Thereafter, a barrier metal layer is deposited on the metal layer M by plating or vapor deposition, and a solder layer S is further deposited thereon by plating or vapor deposition. Thereafter, after removing the photoresist pattern, the underlying metal layer UBM exposed therefrom is etched away using the remaining metal layer M, barrier metal layer BM, and solder layer S patterns as a mask. Thereafter, the solder layer S is melted by performing a heat treatment (reflow treatment) on the semiconductor substrate to form the bump electrodes 8.

次に、図８は上記半導体チップ１の上記パワーＭＩＳのセル部分の要部拡大断面図である。   Next, FIG. 8 is an enlarged cross-sectional view of the main part of the cell portion of the power MIS of the semiconductor chip 1.

本実施の形態１のパワーＭＩＳは、例えば１．７ＧＨｚ以上の周波数の入出力信号で動作する携帯電話端末（移動通信機器）または携帯電話端末用の基地局の高周波電力増幅回路を構成するものである。   The power MIS of the first embodiment constitutes a high frequency power amplifier circuit of a mobile phone terminal (mobile communication device) or a base station for a mobile phone terminal that operates with, for example, an input / output signal having a frequency of 1.7 GHz or higher. is there.

このパワーＭＩＳを有する半導体チップ１は、例えばホウ素（Ｂ）を含有するｐ型（第１導電型）のシリコン（Ｓｉ）単結晶からなる半導体基板１Ｓを有している。半導体基板１Ｓは、その厚さ方向に沿って互いに反対側に位置する第１主面（主面、上面）および第２主面（裏面、下面）を持ち、その全体が、例えばチョクラルスキー法等のような単結晶引き上げ法により形成されている。すなわち、パワーＭＩＳのドレイン直下にあたる半導体基板１Ｓの全体がｐ型の高比抵抗層で形成されている。半導体基板１Ｓの比抵抗値は、例えば３ｍΩｃｍ程度またはそれ以上である。半導体基板１Ｓの厚さは、例えば２８０μｍ程度である。   The semiconductor chip 1 having the power MIS includes a semiconductor substrate 1S made of a p-type (first conductivity type) silicon (Si) single crystal containing, for example, boron (B). The semiconductor substrate 1S has a first main surface (main surface, upper surface) and a second main surface (back surface, lower surface) located on opposite sides along the thickness direction, and the whole is formed by, for example, the Czochralski method. The single crystal pulling method is used. That is, the entire semiconductor substrate 1S, which is directly under the power MIS drain, is formed of a p-type high specific resistance layer. The specific resistance value of the semiconductor substrate 1S is, for example, about 3 mΩcm or more. The thickness of the semiconductor substrate 1S is, for example, about 280 μm.

上記パワーＭＩＳＱは、複数のセルＱＣが並列接続されることで構成されている。各セルＱＣは、例えばエンハンスメント（ノーマリオフ）型のｎチャネル型のＬＤＭＩＳ・ＦＥＴ（Lateral Diffusion MIS・FET：電界効果トランジスタ）で構成されている。   The power MISQ is configured by connecting a plurality of cells QC in parallel. Each cell QC is composed of, for example, an enhancement (normally off) type n-channel LDMIS • FET (Lateral Diffusion MIS • FET: field effect transistor).

このセルＱＣは、上記半導体基板１Ｓの第１主面のフィールド絶縁膜（分離用絶縁膜）１５で規定される活性領域に配置されている。このフィールド絶縁膜１５は、例えばＬＯＣＯＳ（Local Oxidation of Silicon）法により形成された酸化シリコン（ＳｉＯ２等）により形成されている。 The cell QC is arranged in an active region defined by a field insulating film (isolation insulating film) 15 on the first main surface of the semiconductor substrate 1S. The field insulating film 15 is formed of silicon oxide (SiO 2 or the like) formed by, for example, a LOCOS (Local Oxidation of Silicon) method.

また、セルＱＣは、ゲート絶縁膜１６と、ゲート電極ＧＥと、ソース用のｎ＋型（第２導電型）の半導体領域１７Ｓと、ドレイン用のｎ＋型の半導体領域（第１ドレイン領域）１７Ｄと、ｎ−型の半導体領域（第２ドレイン領域）１８ａと、ｎ型の半導体領域（第２ドレイン領域）１８ｂと、チャネル形成用のｐ型のウエル領域（半導体領域、チャネル形成領域）１９とを有している。 The cell QC includes a gate insulating film 16, a gate electrode GE, a source n + type (second conductivity type) semiconductor region 17S, and a drain n + type semiconductor region (first drain region). 17D, an n − type semiconductor region (second drain region) 18a, an n type semiconductor region (second drain region) 18b, and a p type well region (semiconductor region, channel formation region) 19 for forming a channel. And have.

上記ゲート絶縁膜１６は、例えば熱酸化法で形成された酸化シリコンからなり、半導体基板１Ｓの第１主面上に形成されている。このゲート絶縁膜１６上には、上記ゲート電極ＧＥが形成されている。このゲート電極ＧＥは、例えば低抵抗多結晶シリコンからなる導体層の単体構成または低抵抗多結晶シリコンからなる導体層上にタングステンシリサイド等のようなシリサイド層を積み重ねた積層構成により形成されている。   The gate insulating film 16 is made of, for example, silicon oxide formed by a thermal oxidation method, and is formed on the first main surface of the semiconductor substrate 1S. On the gate insulating film 16, the gate electrode GE is formed. The gate electrode GE is formed by, for example, a single conductor layer made of low-resistance polycrystalline silicon or a laminated structure in which a silicide layer such as tungsten silicide is stacked on a conductor layer made of low-resistance polycrystalline silicon.

ゲート電極ＧＥの側面には、サイドウォールスペーサ２０が形成されている。このサイドウォールスペーサ２０は、例えば酸化シリコンのような絶縁膜を上記ゲート電極ＧＥを覆うように半導体基板１Ｓの主面上にＣＶＤ（Chemical Vapor Deposition）法により堆積した後、その絶縁膜を異方性のドライエッチング法によりエッチバックすることにより形成されている。   Sidewall spacers 20 are formed on the side surfaces of the gate electrode GE. The sidewall spacer 20 is formed by depositing an insulating film such as silicon oxide on the main surface of the semiconductor substrate 1S by the CVD (Chemical Vapor Deposition) method so as to cover the gate electrode GE, and then anisotropically forming the insulating film. It is formed by etching back by a characteristic dry etching method.

上記ソース用のｎ＋型の半導体領域１７Ｓ、ドレイン用のｎ＋型の半導体領域１７Ｄ、ｎ−型の半導体領域１８ａ、ｎ型の半導体領域１８ｂおよびチャネル形成用のｐ型のウエル領域１９は、半導体基板１Ｓに形成されている。 N + -type semiconductor region 17S for the source, n + -type semiconductor region 17D for the drain, n - -type semiconductor region 18a, n-type p-type well region 19 in the semiconductor region 18b and the channel formation, It is formed on the semiconductor substrate 1S.

このうち、ソース用のｎ＋型の半導体領域１７Ｓは、ｎ＋型の浅い半導体領域１７Ｓ１と、ｎ＋型の深い半導体領域１７Ｓ２とを有している。ソース用の浅い半導体領域１７Ｓ１は、ゲート電極ＧＥの幅方向の一方の端部からゲート電極ＧＥに対して遠ざかる方向に、かつ、半導体基板１Ｓの第１主面に沿って延びている。また、ソース用の深い半導体領域１７Ｓ２は浅い半導体領域１７Ｓ１に接続された状態で浅い半導体領域１７Ｓ１の終端からさらにゲート電極ＧＥに対して遠ざかる方向に、かつ半導体基板１Ｓの第１主面に沿って延びている。このようにソース用の浅い半導体領域１７Ｓ１を設けることにより、熱処理による不純物の広がりを抑制し、深い半導体領域１７Ｓ２のみでソース領域を形成する場合に比べて、パワーＭＩＳのしきい値電圧（Ｖｔｈ）の低下を防ぐことができる。このような半導体領域１７Ｓ１，１７Ｓ２には、例えばリンまたはヒ素が導入されている。ただし、浅い半導体領域１７Ｓ１は、上記ゲート電極ＧＥの形成後、上記サイドウォールスペーサ２０の形成前であって、上記ｎ−型の半導体領域１８ａとは別の不純物導入工程により形成されている。また、深い半導体領域１７Ｓ２は、サイドウォールスペーサ２０の形成後にサイドウォールスペーサ２０に対して自己整合的に上記浅い半導体領域１７Ｓ１よりも深い位置まで不純物を導入することで形成されている。 Among these, the source n + -type semiconductor region 17S includes an n + -type shallow semiconductor region 17S1 and an n + -type deep semiconductor region 17S2. The shallow semiconductor region 17S1 for source extends in a direction away from the gate electrode GE from one end in the width direction of the gate electrode GE and along the first main surface of the semiconductor substrate 1S. Further, the source deep semiconductor region 17S2 is connected to the shallow semiconductor region 17S1, and further away from the end of the shallow semiconductor region 17S1 with respect to the gate electrode GE and along the first main surface of the semiconductor substrate 1S. It extends. By providing the shallow semiconductor region 17S1 for the source as described above, the spread of impurities due to the heat treatment is suppressed, and the threshold voltage (Vth) of the power MIS is compared with the case where the source region is formed only by the deep semiconductor region 17S2. Can be prevented. For example, phosphorus or arsenic is introduced into the semiconductor regions 17S1 and 17S2. However, the shallow semiconductor region 17S1 is formed after the formation of the gate electrode GE and before the formation of the sidewall spacer 20, and by an impurity introduction process separate from the n − type semiconductor region 18a. The deep semiconductor region 17S2 is formed by introducing impurities to a position deeper than the shallow semiconductor region 17S1 in a self-aligned manner with respect to the sidewall spacer 20 after the sidewall spacer 20 is formed.

上記ドレイン用のｎ＋型の半導体領域１７Ｄは、上記ゲート電極ＧＥの幅方向の他方の端部から離れた位置に形成されている。ｎ−型の半導体領域１８ａおよびｎ型の半導体領域１８ｂは、上記チャネル形成用のｐ型のウエル領域１９と上記ドレイン用のｎ＋型の半導体領域１７Ｄとの間に設けられている。すなわち、ｎ−型の半導体領域１８ａは、上記ゲート電極ＧＥの幅方向の上記他方の端部から上記ドレイン用のｎ＋型の半導体領域１７Ｄまでに延び、その半導体領域１７Ｄに電気的に接続されている。ｎ型の半導体領域１８ｂは、ｎ−型の半導体領域１８ａよりも浅く形成され、ｎ−型の半導体領域１８ａに内包された状態で、サイドウォールスペーサ２０の端部から上記ドレイン用のｎ＋型の半導体領域１７Ｄまでに延び、その半導体領域１７Ｄに電気的に接続されている。このような半導体領域１７Ｄ，１８ａ，１８ｂには、例えばリン（Ｐ）またはヒ素（Ａｓ）等のようなｎ型を形成する不純物が含有されている。ただし、ｎ−型の半導体領域１８ａの不純物濃度は、ソース、ドレイン用の半導体領域１７Ｓ，１７Ｄおよびｎ型の半導体領域１８ｂの不純物濃度よりも低くなっている。また、半導体領域１８ｂの不純物濃度は、ソース、ドレイン用の半導体領域１７Ｓ，１７Ｄの不純物濃度よりも低くなっている。このような構成により、チャネル形成用のｐ型のウエル領域１９と上記ドレイン用のｎ＋型の半導体領域１７Ｄとの間の電界の強さを平均化（緩和）することができるので、ドレイン耐圧を高くすることが可能になっている。また、半導体領域１８ａ，１８ｂの不純物濃度を独立に変えることにより、パワーＭＩＳのオン抵抗を低減しつつ、ゲート−ドレイン間容量の低減も可能となる。これにより、電力増幅器の電力効率を向上させることができる。 The drain n + -type semiconductor region 17D is formed at a position away from the other end in the width direction of the gate electrode GE. The n − type semiconductor region 18a and the n type semiconductor region 18b are provided between the p type well region 19 for channel formation and the n + type semiconductor region 17D for drain. That is, the n − type semiconductor region 18a extends from the other end in the width direction of the gate electrode GE to the drain n + type semiconductor region 17D and is electrically connected to the semiconductor region 17D. ing. n-type semiconductor region 18b is, n - -type are formed shallower than the semiconductor region 18a of, n - a type state of being included in the semiconductor region 18a of the end portion of the sidewall spacers 20 for the drain n + -type The semiconductor region 17D extends to and is electrically connected to the semiconductor region 17D. Such semiconductor regions 17D, 18a, and 18b contain impurities that form an n-type such as phosphorus (P) or arsenic (As). However, the impurity concentration of the n − type semiconductor region 18a is lower than the impurity concentration of the source and drain semiconductor regions 17S and 17D and the n type semiconductor region 18b. The impurity concentration of the semiconductor region 18b is lower than the impurity concentration of the semiconductor regions 17S and 17D for the source and drain. With such a configuration, the strength of the electric field between the p-type well region 19 for forming the channel and the n + -type semiconductor region 17D for the drain can be averaged (relaxed). Can be raised. In addition, by independently changing the impurity concentrations of the semiconductor regions 18a and 18b, it is possible to reduce the gate-drain capacitance while reducing the on-resistance of the power MIS. Thereby, the power efficiency of the power amplifier can be improved.

上記チャネル形成用のｐ型のウエル領域１９は、ゲート電極ＧＥが対向する上記半導体基板１Ｓに形成されるように設けられている。上記パワーＭＩＳのセルＱＣの動作時には、上記ゲート電極ＧＥが対向する上記チャネル形成用のｐ型のウエル領域１９の表層に、ゲート電極ＧＥの対向面に沿うようにチャネル領域が形成される。すなわち、セルＱＣの動作時には、キャリアである電子が、ソース用のｎ＋型の半導体領域１７Ｓ、チャネル形成用のｐ型のウエル領域１９のチャネル領域およびｎ−型の半導体領域１８ａを半導体基板１Ｓの第１主面に対してほぼ水平に通り、ドレイン用のｎ＋型の半導体領域１７Ｄに達するようになっている。ウエル領域１９は、ｎ＋型の半導体領域１７Ｄからソース用のｎ＋型の半導体領域１７Ｓに延びる空乏層の延びを抑えるためのパンチスルーストッパとして機能する役割も有している。 The channel-forming p-type well region 19 is provided in the semiconductor substrate 1S facing the gate electrode GE. During the operation of the power MIS cell QC, a channel region is formed along the surface facing the gate electrode GE on the surface layer of the channel-forming p-type well region 19 facing the gate electrode GE. That is, during the operation of the cell QC, electrons as carriers are transferred from the n + type semiconductor region 17S for source, the channel region of the p type well region 19 for channel formation, and the n − type semiconductor region 18a to the semiconductor substrate 1S. It passes substantially horizontally with respect to the first main surface of the semiconductor layer 17 and reaches the n + type semiconductor region 17D for drain. The well region 19 also functions as a punch-through stopper for suppressing the extension of a depletion layer extending from the n + type semiconductor region 17D to the source n + type semiconductor region 17S.

次に、半導体基板１Ｓの第１主面上の配線層の構成等について説明する。なお、図６では、この配線層中にキャパシタＣＡおよびインダクタンスＬＡ等のような受動素子が形成されている場合が例示されている。   Next, the configuration of the wiring layer on the first main surface of the semiconductor substrate 1S will be described. FIG. 6 illustrates a case where passive elements such as a capacitor CA and an inductance LA are formed in the wiring layer.

上記ゲート電極ＧＥは、プラグを通じて第１層配線に電気的に接続され、さらにプラグを通じて第２層配線に電気的に接続され、そして、プラグを通じて第３層配線のパッドＢＰに電気的に接続され、これを介してバンプ電極８ｇに電気的に接続されている。   The gate electrode GE is electrically connected to the first layer wiring through the plug, further electrically connected to the second layer wiring through the plug, and electrically connected to the pad BP of the third layer wiring through the plug. Through this, it is electrically connected to the bump electrode 8g.

上記ドレイン用の半導体領域１７Ｄは、プラグ２４ａ１を通じて第１層配線２５ａ１に電気的に接続され、さらにプラグ２４ａ２を通じて第２層配線２５ａ２に電気的に接続され、そして、プラグ２４ａ３を通じて第３層配線のパッドＢＰに電気的に接続され、これを介してバンプ電極８ｄに電気的に接続されている。   The drain semiconductor region 17D is electrically connected to the first layer wiring 25a1 through the plug 24a1, further electrically connected to the second layer wiring 25a2 through the plug 24a2, and the third layer wiring through the plug 24a3. It is electrically connected to the pad BP, and is electrically connected to the bump electrode 8d through this.

上記ソース用の半導体領域１７Ｓは、プラグ２４ｂ１を通じて第１層配線２５ｂ１に電気的に接続され、さらにプラグ２４ｂ２を通じて第２層配線２５ｂ２に電気的に接続され、そして、プラグ２４ｂ３を通じて第３層配線のパッドＢＰに電気的に接続され、これを介してバンプ電極８ｄに電気的に接続されている。   The source semiconductor region 17S is electrically connected to the first layer wiring 25b1 through the plug 24b1, further electrically connected to the second layer wiring 25b2 through the plug 24b2, and then connected to the third layer wiring through the plug 24b3. It is electrically connected to the pad BP, and is electrically connected to the bump electrode 8d through this.

このように本実施の形態１では、ゲート電極ＧＥ、上記ドレイン用の半導体領域１７Ｄおよび上記ソース用の半導体領域１７Ｓが、半導体チップ１の第１主面側のバンプ電極８ｇ，８ｄ，８ｓ（８）に引き出されている。   As described above, in the first embodiment, the gate electrode GE, the drain semiconductor region 17D, and the source semiconductor region 17S are bump electrodes 8g, 8d, 8s (8 on the first main surface side of the semiconductor chip 1). ).

上記プラグ２４ａ１，２４ｂ１は、例えばタングステン（Ｗ）からなり、絶縁層２６ａに穿孔されたコンタクトホール２７内に埋め込まれている。上記第１層配線２５ａ１，２５ｂ１は、例えばタングステンからなり、絶縁層２６ｂに形成された配線溝２８ａ内に埋め込まれている。上記プラグ２４ａ２，２４ｂ２は、例えば銅（Ｃｕ）またはタングステンを主材料としてなり、絶縁層２６ｃに形成されたスルーホール２９ａ内に埋め込まれている。上記第２層配線２５ａ２，２５ｂ２は、例えば銅またはタングステンを主材料としてなり、絶縁層２６ｄに形成された配線溝２８ｂ内に埋め込まれている。上記プラグ２４ａ３，２４ｂ３は、例えば銅またはタングステンを主材料としてなり、絶縁層２６ｅに形成されたスルーホール２９ｂ内に埋め込まれている。上記パッドＢＰおよび第３層配線は、例えばアルミニウムまたはアルミニウム合金からなる。第３層配線を銅（Ｃｕ）で形成しても良い。上記絶縁層２６ａ〜２６ｅは、例えば酸化シリコンからなる。   The plugs 24a1 and 24b1 are made of tungsten (W), for example, and are buried in the contact hole 27 drilled in the insulating layer 26a. The first layer wirings 25a1 and 25b1 are made of tungsten, for example, and are embedded in a wiring groove 28a formed in the insulating layer 26b. The plugs 24a2 and 24b2 are made of, for example, copper (Cu) or tungsten as a main material, and are embedded in a through hole 29a formed in the insulating layer 26c. The second layer wirings 25a2 and 25b2 are made of, for example, copper or tungsten as a main material, and are embedded in a wiring groove 28b formed in the insulating layer 26d. The plugs 24a3 and 24b3 are made of, for example, copper or tungsten as a main material, and are embedded in a through hole 29b formed in the insulating layer 26e. The pad BP and the third layer wiring are made of, for example, aluminum or an aluminum alloy. The third layer wiring may be formed of copper (Cu). The insulating layers 26a to 26e are made of, for example, silicon oxide.

次に、上記パワーモジュールＰＭを有するシステムの一例を説明する。図９は、例えばＧＳＭ方式のネットワークを利用して情報を伝送するデジタル携帯電話システムＤＰＳを示している。このデジタル携帯電話システムＤＰＳは、マザーボードＭＢ上に搭載されたモジュール、回路および素子等によって構築されている。符号ＦＥＭはフロントエンド・モジュールである。符号ＢＢＣは音声信号をベースバンド信号に変換したり、受信信号を音声信号に変換したり、変調方式切換信号やバンド切換信号を生成したりする前記ベースバンド回路である。符号ＦＭＣは受信信号をダウンコンバートして復調しベースバンド信号を生成したり送信信号を変調したりする変復調用回路である。Ｔａ１，Ｔｂ１はパワーモジュールＰＭの入力端子、Ｔａ２，Ｔｂ２はパワーモジュールＰＭの出力端子である。フィルタＦＬＴ１はＧＳＭ用、フィルタＦＬＴ２はＤＣＳ用である。   Next, an example of a system having the power module PM will be described. FIG. 9 shows a digital cellular phone system DPS that transmits information using, for example, a GSM network. This digital cellular phone system DPS is constructed by modules, circuits, elements and the like mounted on the motherboard MB. The symbol FEM is a front end module. Reference numeral BBC denotes the baseband circuit that converts an audio signal into a baseband signal, converts a received signal into an audio signal, and generates a modulation system switching signal and a band switching signal. A code FMC is a modulation / demodulation circuit that down-converts and demodulates a received signal to generate a baseband signal and modulates a transmission signal. Ta1 and Tb1 are input terminals of the power module PM, and Ta2 and Tb2 are output terminals of the power module PM. The filter FLT1 is for GSM, and the filter FLT2 is for DCS.

ベースバンド回路ＢＢＣは、ＤＳＰやマイクロプロセッサ、半導体メモリ等の複数の半導体集積回路で構成されている。フロントエンド・モジュールＦＥＭは、ロウパスフィルタＬＰＦ１，ＬＰＦ２、スイッチ回路ＳＷ１，ＳＷ２、キャパシタＣ０，Ｃ０および分波器ＷＤＣを有している。スイッチ回路ＳＷ１，ＳＷ２は，ＧＳＭ９００帯の信号とＤＣＳ１８００帯の信号との各々で送受信信号切り換え用のスイッチ回路、分波器ＷＤＣは、ＧＳＭ９００帯の信号と、ＤＣＳ１８００帯の信号とを分波する回路である。スイッチ回路ＳＷ１，ＳＷ２の切換信号ＣＮＴ１，ＣＮＴ２は上記ベースバンド回路ＢＢＣから供給される。   The baseband circuit BBC is composed of a plurality of semiconductor integrated circuits such as a DSP, a microprocessor, and a semiconductor memory. The front end module FEM has low-pass filters LPF1 and LPF2, switch circuits SW1 and SW2, capacitors C0 and C0, and a duplexer WDC. The switch circuits SW1 and SW2 are switch circuits for switching transmission / reception signals in each of the GSM900 band signal and the DCS1800 band signal, and the duplexer WDC is a circuit that demultiplexes the GSM900 band signal and the DCS1800 band signal. It is. Switching signals CNT1 and CNT2 of the switch circuits SW1 and SW2 are supplied from the baseband circuit BBC.

なお、ＧＳＭ（Global System for Mobile Communication）は、デジタル携帯電話に使用されている無線通信方式の１つまたは規格をいう。ＧＳＭには、使用する電波の周波数帯が３つあり、９００ＭＨｚ帯をＧＳＭ９００または単にＧＳＭ、１８００ＭＨｚ帯をＧＳＭ１８００またはＤＣＳ（Digital Cellular System）１８００若しくはＰＣＮ、１９００ＭＨｚ帯をＧＳＭ１９００またはＤＣＳ１９００若しくはＰＣＳ（Personal Communication Services）という。また、ＧＳＭ１９００は主に北米で使用されている。北米ではその他に８５０ＭＨｚ帯のＧＳＭ８５０を使用する場合もある。   Note that GSM (Global System for Mobile Communication) is one of wireless communication systems or standards used for digital mobile phones. GSM has three frequency bands of radio waves to be used: 900 MHz band is GSM900 or simply GSM, 1800 MHz band is GSM1800 or DCS (Digital Cellular System) 1800 or PCN, 1900 MHz band is GSM1900 or DCS1900 or PCS (Personal Communication Services) ). GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may also be used.

次に、図１０は、上記パワーモジュールＰＭの回路ブロック図の一例を示している。パワーモジュールＰＭは、例えばＧＳＭ８５０、ＧＳＭ９００、ＤＣＳ１８００およびＤＣＳ１９００の４つの周波数帯を使用可能（フォーバンド方式）で、それぞれの周波数帯でＧＭＳＫ（Gaussian filtered Minimum Shift Keying）変調方式とＥＤＧＥ（Enhanced Data GSM Environment）変調方式との２つの通信方式を使用可能な構成とされている。ＧＭＳＫ変調方式は、音声信号の通信に用いる方式で搬送波の位相を送信データに応じて位相シフトする方式である。ＥＤＧＥ変調方式は、データ通信に用いる方式でＧＭＳＫ変調の位相シフトにさらに振幅シフトを加えた方式である。   Next, FIG. 10 shows an example of a circuit block diagram of the power module PM. The power module PM can use, for example, four frequency bands of GSM850, GSM900, DCS1800, and DCS1900 (four-band method), and GMSK (Gaussian filtered Minimum Shift Keying) modulation method and EDGE (Enhanced Data GSM Environment) in each frequency band. ) It is configured to be able to use two communication methods, ie, a modulation method. The GMSK modulation method is a method used for communication of audio signals and is a method of shifting the phase of a carrier wave according to transmission data. The EDGE modulation method is a method used for data communication and is a method in which an amplitude shift is further added to the phase shift of GMSK modulation.

このパワーモジュールＰＭは、ＧＳＭ８５０およびＧＳＭ９００用の増幅回路部３５Ｂと、ＤＣＳ１８００およびＤＣＳ１９００用の増幅回路部３５Ｃと、それら増幅回路部３５Ｂ，３５Ｃの増幅動作の制御や補正等を行う周辺回路３６Ｂと、ＧＳＭ側の電源周辺パターン３７Ｂと、ＤＣＳ側の電源周辺パターン３７Ｃとを有している。   The power module PM includes an amplifier circuit unit 35B for GSM850 and GSM900, an amplifier circuit unit 35C for DCS1800 and DCS1900, and a peripheral circuit 36B for controlling and correcting the amplification operation of these amplifier circuit units 35B and 35C, A power supply peripheral pattern 37B on the GSM side and a power supply peripheral pattern 37C on the DCS side are provided.

各増幅回路部３５Ｂ，３５Ｃは、それぞれ直列に接続された３つの増幅回路部（増幅素子、パワーＭＩＳ）３５ｂ１〜３５ｂ３，３５ｃ１〜３５ｃ３と、４つのインピーダンス整合回路３５Ｂｍ１〜３５Ｂｍ４，３５Ｃｍ１〜３５Ｃｍ４とを有している。すなわち、パワーモジュールＰＭの入力端子Ｔａ１，Ｔｂ１は、入力段のインピーダンス整合回路３５Ｂｍ１，３５Ｃｍ１を介して１段目の増幅回路部３５ｂ１，３５ｃ１の入力に電気的に接続されている。１段目の増幅回路部３５ｂ１，３５ｃ１の出力は段間用のインピーダンス整合回路３５Ｂｍ２，３５Ｃｍ２を介して２段目の増幅回路部３５ｂ２，３５ｃ２の入力に電気的に接続されている。２段目の増幅回路部３５ｂ２，３５ｃ２の出力は段間用のインピーダンス整合回路３５Ｂｍ３，３５Ｃｍ３を介して最終段の増幅回路部３５ｂ３，３５ｃ３の入力に電気的に接続されている。さらに、最終段の増幅回路部３５ｂ３，３５ｃ３の出力は出力段のインピーダンス整合回路３５Ｂｍ４，３５Ｃｍ４を介して出力端子Ｔａ２，Ｔｂ２に電気的に接続されている。なお、上記図１〜３の例では、３つの増幅回路部３５ｂ１〜３５ｂ３，３５ｃ１〜３５ｃ３が１つの半導体チップ１内に形成されている。ただし、最終段の増幅回路部３５ｂ３，３５ｃ３を別の半導体チップ内に形成して２つの半導体チップをモジュール基板ＰＭＢ上に実装するようにしても良いし、３つの増幅回路部３５ｂ１〜３５ｂ３，３５ｃ１〜３５ｃ３を段毎に別々の半導体チップに形成しても良い。   Each of the amplifier circuit units 35B and 35C includes three amplifier circuit units (amplifier elements, power MIS) 35b1 to 35b3, 35c1 to 35c3 connected in series, and four impedance matching circuits 35Bm1 to 35Bm4 and 35Cm1 to 35Cm4. Have. That is, the input terminals Ta1 and Tb1 of the power module PM are electrically connected to the inputs of the first stage amplifier circuit sections 35b1 and 35c1 via the impedance matching circuits 35Bm1 and 35Cm1 of the input stage. The outputs of the first stage amplifier circuit sections 35b1 and 35c1 are electrically connected to the inputs of the second stage amplifier circuit sections 35b2 and 35c2 via interstage impedance matching circuits 35Bm2 and 35Cm2. The outputs of the second-stage amplifier circuit sections 35b2 and 35c2 are electrically connected to the inputs of the final-stage amplifier circuit sections 35b3 and 35c3 via inter-stage impedance matching circuits 35Bm3 and 35Cm3. Further, the outputs of the final-stage amplifier circuit sections 35b3 and 35c3 are electrically connected to the output terminals Ta2 and Tb2 via the output-stage impedance matching circuits 35Bm4 and 35Cm4. In the example of FIGS. 1 to 3, three amplifier circuit portions 35 b 1 to 35 b 3 and 35 c 1 to 35 c 3 are formed in one semiconductor chip 1. However, the final stage amplifier circuit sections 35b3 and 35c3 may be formed in another semiconductor chip, and two semiconductor chips may be mounted on the module substrate PMB, or the three amplifier circuit sections 35b1 to 35b3 and 35c1 may be mounted. ˜35c3 may be formed in separate semiconductor chips for each stage.

上記周辺回路３６Ｂは、制御回路、上記増幅回路部３５ｂ１〜３５ｂ３，３５ｃ１〜３５ｃ３にバイアス電圧を印加するバイアス回路、モード／バンド切換回路、パワー検出回路等を有している。制御回路は、上記増幅回路部３５Ｂ，３５Ｃに印加する所望の電圧を発生する回路であり、電源制御回路およびバイアス電圧生成回路を有している。電源制御回路は、上記増幅回路部３５ｂ１〜３５ｂ３，３５ｃ１〜３５ｃ３の各々の出力用のパワーＭＩＳのドレイン端子に印加される第１電源電圧を生成する回路である。また、上記バイアス電圧生成回路は、上記バイアス回路を制御するための第１制御電圧を生成する回路である。本実施の形態１では、電源制御回路が、パワーモジュールＰＭの外部の上記ベースバンド回路ＢＢＣから供給される出力レベル指定信号に基づいて上記第１電源電圧を生成すると、バイアス電圧生成回路が電源制御回路で生成された上記第１電源電圧に基づいて上記第１制御電圧を生成するようになっている。上記ベースバンド回路ＢＢＣは、上記出力レベル指定信号を生成する回路である。この出力レベル指定信号は、増幅回路部３５Ｂ，３５Ｃの出力レベルを指定する信号で、携帯電話と、基地局との間の距離、すなわち、電波の強弱に応じた出力レベルに基づいて生成されているようになっている。   The peripheral circuit 36B includes a control circuit, a bias circuit that applies a bias voltage to the amplifier circuit portions 35b1 to 35b3 and 35c1 to 35c3, a mode / band switching circuit, a power detection circuit, and the like. The control circuit is a circuit that generates a desired voltage to be applied to the amplification circuit units 35B and 35C, and includes a power supply control circuit and a bias voltage generation circuit. The power supply control circuit is a circuit that generates a first power supply voltage to be applied to the drain terminal of the output power MIS of each of the amplifier circuit units 35b1 to 35b3 and 35c1 to 35c3. The bias voltage generation circuit is a circuit that generates a first control voltage for controlling the bias circuit. In the first embodiment, when the power supply control circuit generates the first power supply voltage based on the output level designation signal supplied from the baseband circuit BBC outside the power module PM, the bias voltage generation circuit controls the power supply. The first control voltage is generated based on the first power supply voltage generated by the circuit. The baseband circuit BBC is a circuit that generates the output level designation signal. This output level designation signal is a signal that designates the output level of the amplifier circuits 35B and 35C, and is generated based on the distance between the mobile phone and the base station, that is, the output level corresponding to the strength of the radio wave. It is supposed to be.

（実施の形態２）
まず、本実施の形態２の説明の前に、前記実施の形態１の場合の平面帯状のバンプ電極８について本発明者が見出した課題を説明する。 (Embodiment 2)
First, prior to the description of the second embodiment, the problems found by the present inventor regarding the planar strip-shaped bump electrode 8 in the first embodiment will be described.

図１１は、前記実施の形態１で説明したバンプ電極８の断面図である。同一の半導体チップ１の第１主面内に、相対的に面積の小さいバンプ電極８と、相対的に面積の大きなバンプ電極８とが存在すると、その面積の異なるバンプ電極８同士の高さにバラツキＤ１が生じる場合がある。また、半田だれの問題が生じる場合がある。また、図１２および図１３は、前記実施の形態１で説明したバンプ電極８の平面図である。半田層Ｓの相対的に高い部分に梨地のハッチングが付してある。図１２および図１３に示すように、相対的に面積が大きなバンプ電極８では、互いに交差する方向に延びるパターンが交わる角部に半田が集中し、同じバンプ電極８のパターン内で高さバラツキが生じる場合がある。   FIG. 11 is a cross-sectional view of the bump electrode 8 described in the first embodiment. If bump electrodes 8 having a relatively small area and bump electrodes 8 having a relatively large area exist in the first main surface of the same semiconductor chip 1, the bump electrodes 8 having different areas have different heights. Variation D1 may occur. Moreover, a problem of solder dripping may occur. 12 and 13 are plan views of the bump electrode 8 described in the first embodiment. The relatively high portion of the solder layer S is hatched with a satin finish. As shown in FIG. 12 and FIG. 13, in the bump electrode 8 having a relatively large area, the solder concentrates at the corner where the patterns extending in the intersecting directions intersect, and there is a height variation in the pattern of the same bump electrode 8. May occur.

そこで、本実施の形態２においては、複数のバンプ電極のうち、相対的に面積が大きなバンプ電極の平面形状をドックボーン形状にした。図１４は本実施の形態２のバンプ電極８の拡大平面図、図１５は図１４のＸ２−Ｘ２線の断面図を示している。   Therefore, in the second embodiment, the planar shape of the bump electrode having a relatively large area among the plurality of bump electrodes is formed into a dock bone shape. 14 is an enlarged plan view of the bump electrode 8 according to the second embodiment, and FIG. 15 is a cross-sectional view taken along line X2-X2 of FIG.

本実施の形態２では、相対的に面積が大きな（長さが長い）バンプ電極８の平面形状がドックボーン形状とされている。すなわち、相対的に面積が大きな（長さが長い）バンプ電極８は、その幅方向（短方向）の寸法が、相対的に広い部分８Ａと狭い部分８Ｂとを一体的に有しており、相対的に広い部分８Ａの隣接間に、相対的に狭い部分８Ｂが配置される形状を有している。すなわち、相対的に面積が大きいバンプ電極８は、その長手方向に沿って相対的に広い部分８Ａと狭い部分８Ｂとが連続的に交互に配置されるような構成となっている。相対的に面積が大きなバンプ電極８における相対的に広い部分８Ａ同士の平面積は設計上互いに等しく、また、相対的に狭い部分８Ｂ同士の平面積も設計上互いに等しくなっている。   In the second embodiment, the planar shape of the bump electrode 8 having a relatively large area (long length) is a dockbone shape. That is, the bump electrode 8 having a relatively large area (long length) integrally has a relatively wide portion 8A and a narrow portion 8B in the width direction (short direction). It has a shape in which a relatively narrow portion 8B is disposed between adjacent portions of a relatively wide portion 8A. That is, the bump electrode 8 having a relatively large area has a configuration in which relatively wide portions 8A and narrow portions 8B are alternately arranged along the longitudinal direction thereof. The plane areas of the relatively wide portions 8A of the bump electrode 8 having a relatively large area are equal to each other in design, and the plane areas of the relatively narrow portions 8B are also equal to each other in design.

このような構成にすることにより、相対的に面積が大きいバンプ電極８の半田の量をコントロールすることができるので、図１５に示すように、相対的に面積の小さいバンプ電極８の高さと、相対的に面積の大きいバンプ電極８の高さとが等しくなるようにすることができる。すなわち、相対的に面積の小さいバンプ電極８と、相対的に面積の大きいバンプ電極８との高さバラツキを低減または無くすことができる。また、相対的に面積が大きいバンプ電極８の面内での高さバラツキも低減または無くすことができる。さらに、半田だれの問題も低減または無くすことができる。   With such a configuration, the amount of solder of the bump electrode 8 having a relatively large area can be controlled. Therefore, as shown in FIG. 15, the height of the bump electrode 8 having a relatively small area, The height of the bump electrode 8 having a relatively large area can be made equal. That is, the height variation between the bump electrode 8 having a relatively small area and the bump electrode 8 having a relatively large area can be reduced or eliminated. Also, the height variation in the surface of the bump electrode 8 having a relatively large area can be reduced or eliminated. Furthermore, the problem of solder dripping can be reduced or eliminated.

次に、図１６は本実施の形態２の場合の半導体チップ１の第１主面の全体平面図、図１７は図１６の半導体チップ１の第１主面上のバンプ電極８の拡大平面図、図１８は本実施の形態２のバンプ電極８の変形例の拡大平面図を示している。   Next, FIG. 16 is an overall plan view of the first main surface of the semiconductor chip 1 in the second embodiment, and FIG. 17 is an enlarged plan view of the bump electrode 8 on the first main surface of the semiconductor chip 1 in FIG. FIG. 18 shows an enlarged plan view of a modification of the bump electrode 8 of the second embodiment.

複数のバンプ電極８のうち、平面略円形状の黒塗りのバンプ電極８ｇは、前記実施の形態１と同様に、上記パワーＭＩＳのゲート電極に電気的に接続されている。また、複数のバンプ電極８のうち、斜線のハッチングが付されたバンプ電極８ｄは、上記パワーＭＩＳのドレイン電極に電気的に接続されている。このバンプ電極８ｄの中には、上記バンプ電極８ｇと同等の平面積および平面形状のものと、上記バンプ電極８ｇよりも平面積（長さ）が大きく（長く）平面帯状（Ｉ字状）に形成されたものとがある。   Among the plurality of bump electrodes 8, a black bump electrode 8g having a substantially circular plane is electrically connected to the gate electrode of the power MIS, as in the first embodiment. Of the plurality of bump electrodes 8, the hatched hatched bump electrode 8d is electrically connected to the drain electrode of the power MIS. Among the bump electrodes 8d, those having a planar area and a planar shape equivalent to the bump electrode 8g and a planar area (length) larger (longer) than the bump electrode 8g in a planar belt shape (I shape). Some have been formed.

さらに、複数のバンプ電極８のうち、梨地のハッチングが付されたバンプ電極８ｓは、上記パワーＭＩＳのソース電極に電気的に接続されており、基準電位（例えばＧＮＤ電位で０ｂＶ）が印加されるようになっている。また、このバンプ電極８ｓは、平面帯状（Ｌ字状やＴ字状）に形成されており、その平面積（長さ）が他のバンプ電極８よりも大きい（長い）。   Further, among the plurality of bump electrodes 8, the bump electrode 8 s with the satin hatching is electrically connected to the source electrode of the power MIS, and a reference potential (for example, 0 bV at the GND potential) is applied. It is like that. Further, the bump electrode 8s is formed in a flat band shape (L-shaped or T-shaped), and its planar area (length) is larger (longer) than the other bump electrodes 8.

本実施の形態２でも、バンプ電極８ｓに発振シールド機能を持たせている。すなわち、相対的に面積が大きいソース電極用のバンプ電極８ｓが、相対的に面積が小さいゲート電極用のバンプ電極８ｇと、ドレイン電極用のバンプ電極８ｄとの間に配置されている。好ましくはソース電極用のバンプ電極８ｓがドレイン電極用のバンプ電極８ｄを取り囲むように配置されている。これにより、発振現象を抑制または防止できる。また、バンプ電極８ｓ，８ｄの面積を大きくしたことにより、半導体チップ１の回路動作時において発生した熱の放熱性を向上させることができる。これらにより、パワーモジュールＰＭの動作信頼性を向上させることができる。また、前記実施の形態１と同様に、ゲート電極用のバンプ電極とドレイン電極用のバンプ電極とを大きく離して配置することもないので、半導体チップのサイズ縮小と、機能や動作信頼性の向上とを確保したまま発振を抑制または防止できる。
Also in the second embodiment, the bump electrode 8s has an oscillation shield function. In other words, the bump electrode 8s for the source electrode having a relatively large area is disposed between the bump electrode 8g for the gate electrode having a relatively small area and the bump electrode 8d for the drain electrode. Preferably, the bump electrode 8s for the source electrode is disposed so as to surround the bump electrode 8d for the drain electrode. Thereby, an oscillation phenomenon can be suppressed or prevented. Further, by increasing the area of the bump electrodes 8s and 8d, the heat dissipation of the heat generated during the circuit operation of the semiconductor chip 1 can be improved. As a result, the operational reliability of the power module PM can be improved. Further, as in the first embodiment, the bump electrode for the gate electrode and the bump electrode for the drain electrode are not greatly separated from each other, so that the size of the semiconductor chip can be reduced and the function and operation reliability can be improved. Oscillation can be suppressed or prevented while ensuring.

ただし、相対的に面積が大きなバンプ電極８ｓ，８ｄは、その平面形状が上記のようにドックボーン形状とされている。相対的に面積が大きなバンプ電極８ｓでは、互いに異なる方向交差する方向に延在するパターン部分が交わる角部に、相対的に広い部分８Ａが配置されるようになっている。これにより、相対的に面積が大きなバンプ電極８のパターン内において、互いに交差する方向に延びるパターンが交わる角部に半田が集中するのを抑制または防止できるので、同じバンプ電極８のパターン内で高さバラツキが生じる問題を抑制または防止することができる。   However, the bump electrodes 8s and 8d having a relatively large area have a dockbone shape as described above. In the bump electrode 8s having a relatively large area, a relatively wide portion 8A is arranged at a corner where pattern portions extending in directions intersecting with different directions intersect. As a result, in the pattern of the bump electrodes 8 having a relatively large area, it is possible to suppress or prevent the solder from concentrating at the corners where the patterns extending in the intersecting directions intersect with each other. It is possible to suppress or prevent the problem of unevenness.

なお、本実施の形態２の場合もバンプ電極８の平面形状は、Ｌ字状やＴ字状の他に、図１８に示すようにコ字状にしても良い。   In the second embodiment, the planar shape of the bump electrode 8 may be a U shape as shown in FIG. 18 in addition to the L shape or the T shape.

以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発
明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

例えば前記実施の形態１，２では、フォーバンド方式の携帯電話に適用した場合について説明したが、これに限定されるものではなく、例えばＧＳＭ９００およびＧＳＭ１８００の２つの周波数帯の電波を取り扱うことが可能なデュアルバンド方式またはＧＳＭ９００、ＧＳＭ１８００およびＧＳＭ１９００の３つの周波数帯の電波を取り扱うことが可能なトリプルバンド方式の携帯電話に適用することもできる。   For example, in the first and second embodiments, the case where the present invention is applied to a four-band mobile phone has been described. However, the present invention is not limited to this. For example, radio waves in two frequency bands of GSM900 and GSM1800 can be handled. The present invention can also be applied to a dual-band mobile phone that can handle radio waves in three frequency bands of GSM900, GSM1800, and GSM1900.

また、上記モジュール基板ＰＭＢの第１主面に断面凹状にキャビティを設け、そのキャビティ内に、半導体チップ１を収めるように搭載しても良い。   Further, a cavity having a concave cross section may be provided in the first main surface of the module substrate PMB, and the semiconductor chip 1 may be mounted in the cavity.

また、モジュール基板に代えてリードフレームを使用するような構成でも適用できる。   Further, a configuration in which a lead frame is used instead of the module substrate can be applied.

以上の説明では主として本発明者によってなされた発明をその背景となった利用分野である携帯電話端末にかかる電子装置に適用した場合について説明したが、それに限定されるものではなく種々適用可能であり、例えば自動車用の電子装置にも適用できる。   In the above description, the case where the invention made mainly by the present inventor is applied to an electronic device related to a mobile phone terminal, which is a field of use behind the present invention, has been described. However, the present invention is not limited thereto and can be applied in various ways. For example, the present invention can be applied to an electronic device for automobiles.

本発明は、半導体装置の製造業に適用できる。   The present invention can be applied to the semiconductor device manufacturing industry.

本発明の一実施の形態である半導体装置の一例の全体平面図である。It is a whole top view of an example of the semiconductor device which is one embodiment of the present invention. 図１の半導体装置のＹ１−Ｙ１線の断面図である。FIG. 2 is a cross-sectional view taken along line Y1-Y1 of the semiconductor device of FIG. 図１の半導体装置の半導体チップの第１主面の全体平面図である。FIG. 2 is an overall plan view of a first main surface of a semiconductor chip of the semiconductor device of FIG. 1. 図３の半導体チップの第１主面上のバンプ電極の拡大平面図である。FIG. 4 is an enlarged plan view of a bump electrode on a first main surface of the semiconductor chip of FIG. 3. 図３の半導体チップの第１主面上のバンプ電極の変形例の拡大平面図である。FIG. 4 is an enlarged plan view of a modification of the bump electrode on the first main surface of the semiconductor chip of FIG. 3. 図３の半導体チップのバンプ電極の拡大平面図である。FIG. 4 is an enlarged plan view of a bump electrode of the semiconductor chip of FIG. 3. 図６のＸ１−Ｘ１線の断面図である。It is sectional drawing of the X1-X1 line | wire of FIG. 図３の半導体チップの増幅回路を構成する電界効果トランジスタ部分の要部拡大断面図である。FIG. 4 is an enlarged cross-sectional view of a main part of a field effect transistor portion constituting the amplifier circuit of the semiconductor chip of FIG. 図１の半導体装置を有するシステムの一例の説明図である。It is explanatory drawing of an example of the system which has the semiconductor device of FIG. 図１の半導体装置の回路ブロック図の一例の説明図である。FIG. 2 is an explanatory diagram of an example of a circuit block diagram of the semiconductor device of FIG. 1. 発明者が見出した課題の説明する図であって、図３の半導体チップのバンプ電極の断面図である。It is a figure explaining the subject which inventors found, Comprising: It is sectional drawing of the bump electrode of the semiconductor chip of FIG. 発明者が見出した課題の説明する図であって、図３の半導体チップのバンプ電極の平面図である。It is a figure explaining the subject which inventors found, Comprising: It is a top view of the bump electrode of the semiconductor chip of FIG. 発明者が見出した課題の説明する図であって、図３の半導体チップのバンプ電極の平面図である。It is a figure explaining the subject which inventors found, Comprising: It is a top view of the bump electrode of the semiconductor chip of FIG. 本発明の他の実施の形態である半導体装置の半導体チップのバンプ電極の拡大平面図である。It is an enlarged plan view of the bump electrode of the semiconductor chip of the semiconductor device which is other embodiment of this invention. 図１４のＸ２−Ｘ２線の断面図である。It is sectional drawing of the X2-X2 line | wire of FIG. 図１４のバンプ電極を有する半導体チップの第１主面の全体平面図である。FIG. 15 is an overall plan view of a first main surface of a semiconductor chip having the bump electrode of FIG. 14. 図１６の半導体チップの第１主面上のバンプ電極の拡大平面図である。FIG. 17 is an enlarged plan view of a bump electrode on the first main surface of the semiconductor chip of FIG. 16. 図１６の半導体チップの第１主面上のバンプ電極の変形例の拡大平面図である。FIG. 17 is an enlarged plan view of a modified example of the bump electrode on the first main surface of the semiconductor chip of FIG. 16.

符号の説明Explanation of symbols

１ 半導体チップ
２ チップ部品
３ 電極
４ 外部端子
５ 配線
８ バンプ電極（突起電極）
８ｇ バンプ電極（第１突起電極）
８ｄ バンプ電極（第２突起電極）
８ｓ バンプ電極（第３突起電極）
８Ａ 相対的に広い部分
８Ｂ 相対的に狭い部分
１０ 表面保護膜
１０ａ 保護膜
１０ｂ 保護膜
１１ 開口部
１５ フィールド絶縁膜
１６ ゲート絶縁膜
１７Ｓ 半導体領域
１７Ｄ 半導体領域
１８ａ 半導体領域
１８ｂ 半導体領域
１９ ウエル領域
２０ サイドウォールスペーサ
２４ａ１，２４ａ２，２４ａ３，２４ｂ１，２４ｂ２，２４ｂ３ プラグ
２５ａ１，２５ｂ１ 第１層配線
２５ａ２，２５ｂ２ 第２層配線
２６ａ〜２６ｅ 絶縁層
２７ コンタクトホール
２８ａ，２８ｂ 配線溝
２９ａ，２９ｂ スルーホール
３５Ｂ，３５Ｃ 増幅回路部
３５ｂ１〜３５ｂ３ 増幅回路部
３５ｃ１〜３５ｃ３ 増幅回路部
３５Ｂｍ１〜３５Ｂｍ４ インピーダンス整合回路
３５Ｃｍ１〜３５Ｃｍ４ インピーダンス整合回路
３６Ｂ 周辺回路
３７Ｂ，３７Ｃ 電源周辺パターン
ＰＭ ＲＦパワーモジュール（半導体装置）
ＰＭＢ モジュール基板（基板）
ＵＦ アンダーフィル
ＢＰ ボンディングパッド
ＵＢＭ 下地金属層
Ｍ 金属層
ＢＭ バリア金属層
Ｓ 半田層
ＱＣ セル
ＣＡ キャパシタ
ＬＡ インダクタンス
ＤＰＳ デジタル携帯電話システム
ＭＢ マザーボード
ＦＥＭ フロントエンド・モジュール
ＢＢＣ ベースバンド回路
ＦＭＣ 変復調用回路
Ｔａ１，Ｔｂ１ 入力端子
Ｔａ２，Ｔｂ２ 出力端子
ＦＬＴ１，ＦＬＴ２ フィルタ
ＬＰＦ１，ＬＰＦ２ ロウパスフィルタ
ＳＷ１，ＳＷ２ スイッチ回路
Ｃ０ キャパシタ
ＷＤＣ 分波器 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Chip components 3 Electrode 4 External terminal 5 Wiring 8 Bump electrode (projection electrode)
8g Bump electrode (first protruding electrode)
8d Bump electrode (second protruding electrode)
8s Bump electrode (third protruding electrode)
8A Relatively wide portion 8B Relatively narrow portion 10 Surface protective film 10a Protective film 10b Protective film 11 Opening 15 Field insulating film 16 Gate insulating film 17S Semiconductor region 17D Semiconductor region 18a Semiconductor region 18b Semiconductor region 19 Well region 20 Side Wall spacer 24a1, 24a2, 24a3, 24b1, 24b2, 24b3 Plug 25a1, 25b1 First layer wiring 25a2, 25b2 Second layer wiring 26a-26e Insulating layer 27 Contact hole 28a, 28b Wiring groove 29a, 29b Through hole 35B, 35C Amplification Circuit parts 35b1 to 35b3 Amplifier circuit parts 35c1 to 35c3 Amplifier circuit parts 35Bm1 to 35Bm4 Impedance matching circuits 35Cm1 to 35Cm4 Impedance matching circuit 36B Peripheral circuits 37B and 37C Power supply peripheral pattern P M RF power module (semiconductor device)
PMB module substrate (substrate)
UF Underfill BP Bonding pad UBM Underlying metal layer M Metal layer BM Barrier metal layer S Solder layer QC Cell CA Capacitor LA Inductance DPS Digital mobile phone system MB Motherboard FEM Front end module BBC Baseband circuit FMC Modulation / demodulation circuit Ta1, Tb1 Input Terminal Ta2, Tb2 Output terminal FLT1, FLT2 Filter LPF1, LPF2 Low pass filter SW1, SW2 Switch circuit C0 Capacitor WDC Demultiplexer

Claims (10)

厚さ方向に沿って互いに反対側に位置する第１主面および第２主面を有する半導体チップと、
前記半導体チップの第１主面に対向するように配置された基板と、
前記半導体チップの第１主面と前記基板との間に介在され、双方を電気的に接続する複数の突起電極とを備え、
前記半導体チップは、増幅回路を構成する電界効果トランジスタを備え、
前記複数の突起電極の各々は、前記基板の電極に接する半田層と、前記半田層に接するように設けられ、前記半田層よりも融点の高い金属で形成された金属層とを有しており、
前記複数の突起電極の中には、前記増幅回路の第１突起電極と、前記増幅回路の第２突起電極と、前記第１、第２突起電極よりも大きな平面積を持つ第３突起電極とがあり、
前記第３突起電極の平面パターンは、その幅方向の寸法が、相対的に広い部分と狭い部分とを有しており、前記相対的に広い部分の隣接間に、前記相対的に狭い部分が配置される形状を有し、
前記第３突起電極は前記増幅回路のソース電極に電気的に接続される半導体装置。 A semiconductor chip having a first main surface and a second main surface located on opposite sides along the thickness direction;
A substrate disposed to face the first main surface of the semiconductor chip;
A plurality of projecting electrodes interposed between the first main surface of the semiconductor chip and the substrate and electrically connecting both;
The semiconductor chip includes a field effect transistor constituting an amplifier circuit,
Each of the plurality of protruding electrodes includes a solder layer in contact with the electrode of the substrate, and a metal layer provided in contact with the solder layer and formed of a metal having a melting point higher than that of the solder layer. ,
Among the plurality of projecting electrodes, a first projecting electrode of the amplifier circuit, a second projecting electrode of the amplifier circuit, a third projecting electrode having a larger planar area than the first and second projecting electrodes, There is
The planar pattern of the third protruding electrode has a relatively wide portion and a narrow portion in the width direction, and the relatively narrow portion is adjacent to the relatively wide portion. Having a shape to be arranged ,
The third protruding electrode is a semiconductor device electrically connected to a source electrode of the amplifier circuit . 請求項１記載の半導体装置において、The semiconductor device according to claim 1,
前記第１突起電極は前記増幅回路のゲート電極に電気的に接続され、前記第２突起電極は前記増幅回路のドレイン電極に電気的に接続され、The first protruding electrode is electrically connected to a gate electrode of the amplifier circuit; the second protruding electrode is electrically connected to a drain electrode of the amplifier circuit;
前記複数の第２突起電極の全ては、前記半導体チップの一組の対向する辺に沿って配置される半導体装置。All of the plurality of second protruding electrodes are semiconductor devices disposed along a pair of opposing sides of the semiconductor chip. 請求項２記載の半導体装置において、前記相対的に広い部分および狭い部分は、１つの前記第３突起電極の平面パターン内に複数箇所存在し、
前記相対的に広い部分同士は、その各々の面積が互いに等しくなるように形成され、
前記相対的に狭い部分同士は、その各々の面積が互いに等しくなるように形成されている半導体装置。 The semiconductor device according to claim 2, wherein the relatively wide portions and narrow portions, a plurality of locations exist in one of the third plane pattern of the bump electrode,
The relatively wide portions are formed so that their areas are equal to each other,
The relatively narrow portion between the semi-conductor device area of each of that has been formed to be equal to each other. 請求項３記載の半導体装置において、The semiconductor device according to claim 3.
前記複数の第３突起電極の一部は、前記一組の対向する辺に並行に配置され、Some of the plurality of third protruding electrodes are arranged in parallel on the set of opposing sides,
前記第２突起電極は、前記辺に並行に配置された前記第３突起電極と、前記辺との間に配置される半導体装置。The second projecting electrode is a semiconductor device disposed between the third projecting electrode disposed in parallel with the side and the side. 請求項４記載の半導体装置において、前記第３突起電極を、前記第１、第２突起電極の間に配置することで、前記第３突起電極に発振シールド機能を持たせる半導体装置。 The semiconductor device according to claim 4, wherein the third protruding electrode, the first, by placing between the second protruding electrode, the semi-conductor device that imparted an oscillation shielding function to the third protruding electrode. 請求項３、４または５記載の半導体装置において、前記第１突起電極は前記増幅回路の電界効果トランジスタのゲート端子であり、前記第２突起電極は前記増幅回路の電界効果トランジスタのドレイン端子であり、前記第３突起電極には、接地電位が印加される半導体装置。 The semiconductor device according to claim 3, 4 or 5, wherein the first protruding electrode is a gate terminal of the field effect transistor of the amplifier circuit, the second protruding electrode is the drain terminal of the field effect transistor of the amplifier circuit A semiconductor device in which a ground potential is applied to the third protruding electrode . 厚さ方向に沿って互いに反対側に位置する第１主面および第２主面を有する半導体チップと、
前記半導体チップの第１主面に形成された複数の突起電極と、を備え、
前記半導体チップは、増幅回路を構成するトランジスタを有し、
前記複数の突起電極は、前記増幅回路のゲート電極に電気的に接続される第１突起電極と、前記増幅回路のドレイン電極に電気的に接続される第２突起電極と、前記第１、第２突起電極よりも大きな平面積を持ち、前記増幅回路のソース電極に電気的に接続される第３突起電極と、があり、
前記複数の突起電極の中には、相対的に平面積が異なる突起電極があり、
相対的に面積が大きな突起電極である前記第３突起電極の平面パターンは、その幅方向の寸法が、相対的に広い部分と狭い部分とを有しており、前記相対的に広い部分の隣接間に、前記相対的に狭い部分が配置される形状を有している半導体装置。 A semiconductor chip having a first main surface and a second main surface located on opposite sides along the thickness direction;
And a plurality of protruding electrodes formed on the first main surface of the semiconductor chip,
The semiconductor chip has a transistor constituting an amplifier circuit,
The plurality of protruding electrodes include a first protruding electrode electrically connected to the gate electrode of the amplifier circuit, a second protruding electrode electrically connected to the drain electrode of the amplifier circuit, and the first and first A third protruding electrode having a larger planar area than the two protruding electrodes and electrically connected to the source electrode of the amplifier circuit;
Among the plurality of protruding electrodes, there are protruding electrodes having relatively different plane areas,
Plane pattern of the third protruding electrode relative to the area is a major protruding electrodes, the dimensions in the width direction, has a relatively wide portion and a narrow portion, of the relatively wide portion semi conductor arrangement between adjacent, that has a shape that the relatively narrow portions are arranged. 請求項７記載の半導体装置において、前記複数の突起電極の各々は、前記半導体チップの端子と接した状態で形成された金属層と、前記金属層に接した状態で形成され、前記金属層よりも融点の低い半田層とを有する半導体装置。 8. The semiconductor device according to claim 7 , wherein each of the plurality of protruding electrodes is formed in a state in contact with a terminal of the semiconductor chip, in a state in contact with the metal layer, and from the metal layer. semi conductor arrangement also that having a low melting point solder layer. 請求項８記載の半導体装置において、The semiconductor device according to claim 8.
前記複数の第３突起電極の一部は、一組の対向する辺に並行に配置され、Some of the plurality of third protruding electrodes are arranged in parallel on a pair of opposing sides,
前記第２突起電極は、前記辺に並行に配置された前記第３突起電極と、前記辺との間に配置される半導体装置。The second projecting electrode is a semiconductor device disposed between the third projecting electrode disposed in parallel with the side and the side. 請求項８または９記載の半導体装置において、前記第３突起電極を、前記第１、第２突起電極の間に配置することで、前記第３突起電極に発振シールド機能を持たせる半導体装置。10. The semiconductor device according to claim 8, wherein the third protruding electrode is provided between the first and second protruding electrodes so that the third protruding electrode has an oscillation shield function.
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