JP2006237286A - Semiconductor device and its manufacturing method, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide such a technology that can suppress the drain voltage dependency of feedback capacity affecting high-frequency characteristic, and can prevent the degradation of distortion characteristic in a liner type power amplifier. <P>SOLUTION: A gate electrode 45 is formed on a semiconductor substrate 40 with a gate insulating film 44. A field plate electrode 59a is formed in a manner to cover the side wall of the drain area side of the gate electrode 45. Then, the potential of the field plate electrode 59a is put into floating state. The field plate electrode 59a is formed of a polysilicon film for example. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to an RF (Radio Frequency) module used in a mobile phone.

  Japanese Laid-Open Patent Publication No. 2001-094094 (Patent Document 1) discloses a technique capable of miniaturizing and reducing on-resistance in a high-frequency amplification MISFET having a drain offset region. Specifically, a conductor plug for extracting an electrode is provided on the source region, the drain region, and the reach through layer. The first-layer wirings are connected to the conductor plugs, respectively, and the second-layer wiring for backing is connected to the first-layer wirings via the conductor plugs.

Japanese Unexamined Patent Application Publication No. 2004-221344 (Patent Document 2) discloses a technique capable of improving the high-frequency characteristics and reliability of a MISFET used in an RF module for a mobile phone. That is, in the MISFET used for the mobile phone RF module, the field plate electrode connected to the source potential is formed on the drain side surface of the gate electrode, thereby suppressing the generation of hot carriers and the gate electrode The capacitance between the drains (feedback capacitance) is reduced. Further, a side wall spacer is formed on the side wall of the gate electrode, and the distance between the gate electrode and the field plate electrode is increased, thereby providing a gap between the gate electrode and the source resulting from the provision of the field plate electrode in the vicinity of the gate electrode. The increase in capacity is suppressed.
JP 2001-094094 A JP 2004-221344 A

  A mobile phone is equipped with a power amplifier (RF module) for amplifying a transmission signal. This power amplifier includes, for example, a plurality of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and an impedance matching circuit provided between the input side and output side of the power amplifier and the MISFET. The performance of the power amplifier depends on the performance of the MISFET at the final stage among the plurality of MISFETs.

  Since mobile phones using third-generation mobile communication systems (WCDMA: Wide-band Code Division Multiple Access, cdma2000, which is an extension of cdmaOne), which are expected to become mainstream in the future, are systems that perform digital modulation, the above-mentioned As a power amplifier, a linear power amplifier that performs linear amplification is required. The most important thing for this linear power amplifier is the distortion characteristics during amplification. In other words, it is necessary that the linear power amplifier does not cause amplification distortion.

  Here, during the low power operation of the power amplifier, the drain voltage of the MISFET provided in the final stage does not change much from the bias voltage (Vdd). On the other hand, at the time of high power operation, the drain voltage of the MISFET provided in the final stage changes greatly centering on the bias voltage. This causes distortion in the output of the power amplifier during high power operation. Thus, the distortion of the output of the power amplifier is caused by a large change in the drain voltage of the MISFET, so that the feedback capacitance (capacitance between the gate electrode and the drain region) changes greatly and the matching is shifted. There is.

  In the MISFET used for the power amplifier, a high drain withstand voltage is required to cope with the change of the drain voltage as described above. For example, a drain offset region having a low impurity concentration is provided between the gate electrode and the drain region to ensure the drain breakdown voltage as in the MISFET structure described in Patent Document 1 (Japanese Patent Laid-Open No. 2001-094094).

  In the MISFET in which the drain offset region is formed, the fringe component is dominant in the feedback capacitance that affects the high frequency performance. That is, the capacitance between the gate electrode and the drain offset region is mainly used.

  As the output power of the power amplifier provided with the drain offset region increases in this way, the voltage applied to the drain region greatly changes accordingly. When the voltage applied to the drain region changes, the degree of depletion of the drain offset region adjacent to the gate electrode changes. Therefore, the feedback capacitance determined by the distance between the gate electrode and the non-depleted region of the drain offset region (neutral region) also changes greatly in terms of high frequency, and the output of the power amplifier is distorted. is there. In particular, a linear power amplifier causes a problem when distortion occurs in the output.

  Further, in the linear power amplifier, not only distortion due to change in the feedback capacitance itself but also distortion depending on the size of the feedback capacitance itself becomes a problem.

  Here, as described in Patent Document 2 (Japanese Patent Laid-Open No. 2004-221344), a field plate electrode connected to the source potential is formed on the side surface of the gate electrode on the drain region side, thereby providing a feedback capacitor. Is disclosed to improve high-frequency performance. In other words, the technique described in Patent Document 2 reduces the feedback capacitance and improves the efficiency as a saturation amplifier (for example, a power amplifier that does not require linearity used in the Global System for Mobile Communication (GSM) system). Is disclosed.

  An object of the present invention is to provide a technique capable of preventing the deterioration of distortion characteristics by suppressing the drain voltage dependency of a feedback capacitor that affects high frequency characteristics in a linear power amplifier.

  Another object of the present invention is to provide a technique capable of reducing feedback capacitance and preventing deterioration of distortion characteristics in a linear power amplifier.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device according to the present invention is a semiconductor device including a MISFET, wherein the MISFET includes (a) a semiconductor substrate, (b) a gate insulating film formed on the semiconductor substrate, and (c) the gate insulating film. A gate electrode formed thereon, (d) a source region having a first conductivity type, (e) a first drain region formed away from the gate electrode and having the first conductivity type, and (f A second drain region formed between the gate electrode and the first drain region, having the first conductivity type and having an impurity concentration lower than that of the first drain region; and (g) the gate insulating film. And a semiconductor region formed under the source region and having a second conductivity type opposite to the first conductivity type, and (h) an insulating film covering the top surface, side surfaces and the second drain region of the gate electrode , (I) A conductive film formed on the insulating film formed on a side wall of the gate electrode located on the second drain region side and on the insulating film on the second drain region; It is characterized in that it is not connected.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a MISFET, and (a) forming a semiconductor region having a second conductivity type opposite to the first conductivity type on a semiconductor substrate; (B) forming a gate insulating film on the semiconductor region; (c) forming a gate electrode on the gate insulating film; and (d) having the first conductivity type in the semiconductor region. Forming a source region; (e) forming a first drain region formed away from the gate electrode and having the first conductivity type; and (f) the gate electrode and the first drain region. Forming a second drain region having the first conductivity type and having an impurity concentration lower than that of the first drain region, and (g) an upper surface, a side surface and the second drain of the gate electrode. Over the area Forming an insulating film; and (h) forming a conductive film on the insulating film formed on a side wall of the gate electrode located on the second drain region side and on the insulating film on the second drain region. And the conductive film is not electrically connected to a power source.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the field plate electrode in which the potential is in a floating state is formed on the side surface of the gate electrode on the drain region side, the dependency of the feedback capacitance on the drain voltage that affects the high frequency characteristics can be suppressed. Therefore, it is possible to prevent deterioration of distortion characteristics of the power amplifier.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted.

(Embodiment 1)
The spread spectrum system is a communication system that spreads information over a wide frequency band by digitally modulating a carrier wave or shifting a carrier frequency by a discontinuous amount based on a spread code sequence. The CDMA system is a generic name for a representative group of systems, and the WCDMA system is a generic name for a typical group of systems within the CDMA system. In these systems, information is transmitted using a single broadband channel. Note that the frequency band of the WCDMA system is 1.92 GHz to 1.98 GHz.

  The multicarrier scheme is a general term for communication schemes that transmit information in parallel over a plurality of channels in a wide band, and the OFDM (Orthogonal Frequency Division Multiplexing) scheme is a representative scheme. These spread spectrum systems and multicarrier systems are collectively referred to as broadband digital modulation systems. A linear power amplifier (a power amplifier having a linear amplification function) is used as a power amplifier used in a spread spectrum system or a multicarrier system. When there is amplification distortion in the linear power amplifier, the spectrum waveform of the channel is deformed. In these methods, since transmission information is woven into the spectrum waveform, an error is likely to occur in the demodulated data when it is deformed. Therefore, in the linear power amplifier, the standard for amplification distortion is strict.

  FIG. 1 is a block diagram showing a configuration of a digital mobile phone (mobile communication device) using, for example, the WCDMA system. In FIG. 1, the digital cellular phone has a control display unit 1, a baseband unit 2, an RF (Radio Frequency) block unit 3, and an antenna 4.

  The control display unit 1 includes, for example, a microcomputer and a memory constituting the control unit, and also includes, for example, a liquid crystal display unit as the display unit.

  The baseband unit 2 is configured to modulate or demodulate an audio signal and includes, for example, a D / A converter 5.

  The RF block unit 3 includes a transmission unit and a reception unit, and the transmission unit includes a quadrature modulator 6, a transmission mixer 7, a power amplifier (power amplifier) 8, and an antenna switch 9. A synthesizer composed of an oscillator 13 and a PLL (Phase-locked Loop) circuit is connected to the quadrature modulator 6 and the transmission mixer 7. On the other hand, the reception unit includes an antenna switch 9, a low noise amplifier 10, a reception mixer 11, and an IF (Intermediate Frequency) unit 12. A synthesizer composed of an oscillator 13 and a PLL circuit 14 is connected to the reception mixer 11.

  Next, the operation of the digital mobile phone will be briefly described. First, a case where a signal is transmitted will be described. A signal obtained by digitizing the audio signal is D / A converted by a D / A converter 5 in the baseband unit 2 and input to the RF block unit 3 as an I / Q signal. In the RF block unit 3, the quadrature modulator 6 modulates the I / Q signal into an IF frequency signal. Subsequently, the IF frequency signal is converted into a transmission signal by the transmission mixer 7, and then the transmission signal is amplified by the power amplifier 8. The amplified transmission signal is transmitted from the antenna 4 via the antenna switch 9.

  Next, a case where a signal is received will be described. First, the received signal received by the antenna 4 is amplified by the low noise amplifier 10 via the antenna switch 9. The amplified reception signal is converted into a signal having an IF frequency of about 150 to 250 MHz by the reception mixer 11. Subsequently, this signal is further frequency-converted into a signal of about 455 kHz by the IF circuit unit 12, and then guided to the baseband unit 2 and demodulated.

  As described above, when a signal is transmitted from the digital mobile phone, the transmission signal is amplified by the power amplifier. An example of the circuit configuration of this power amplifier is shown in FIG. In FIG. 2, the power amplifier includes a first amplification stage by a first LDMISFET (Lateral Diffused Metal Insulator Semiconductor Field Effect Transistor) 22 and a second amplification stage by a second LDMISFET 23. The first LDMISFET is also called, for example, a driver FET, and the second LDMISFET is also called, for example, a power FET.

  The input terminal 20 of the power amplifier is connected to the gate electrode of the first LDMISFET 22 through a capacitor and matching circuit 24a. A bias circuit for applying a predetermined voltage is further connected to the gate electrode of the first LDMISFET 22. A bias circuit for applying a predetermined voltage is connected to the drain electrode of the first LDMISFET 22. On the other hand, the source electrode of the first LDMISFET 22 is grounded (GND).

  Next, the drain electrode of the first LDMISFET 22 is connected to the gate electrode of the second LDMISFET 23 via a capacitor and matching circuit 24b. Further, a bias circuit for applying a predetermined voltage is connected to the gate electrode of the second LDMISFET 23. A bias circuit for applying a predetermined voltage is connected to the drain electrode of the second LDMISFET 23, and is connected to the output terminal 21 through a matching circuit 24c and a capacitor. The source electrode of the second LDMISFET 23 is grounded.

  In the power amplifier configured as described above, when a signal is first input to the input terminal 20, the input signal is amplified by the first LDMISFET 22. The amplified input signal is further amplified by the second LDMISFET 23 and output from the output terminal 21. The performance of the power amplifier is determined by the performance of the second LDMISFET 23 closest to the antenna (the output side of the power amplifier). Therefore, suppressing the amplification distortion of the second LDMISFET 23 is essential for improving the performance of the power amplifier.

Next, FIG. 3 shows an RF power module PM (power amplifier) in which an IC chip (semiconductor chip) 25 on which LDMISFETs (first LDMISFET 22 and second LDMISFET 23 in FIG. 2) are formed is mounted on a module substrate (substrate) 26. It is sectional drawing which showed an example of (electronic device). As shown in FIG. 3, the IC chip 25 is bonded to a chip mounting electrode 27 formed on the main surface of the module substrate 26. The electrode 27 is electrically and thermally bonded to the electrode 29G on the back surface of the module substrate 26 through conductors in the plurality of thermal vias 28. A reference potential (for example, about 0 V at the ground potential) is supplied to the electrode 29G. That is, the reference potential supplied to the electrode 29G on the back surface of the module substrate 26 is supplied to the IC chip 25 through the thermal via 28 and the electrode 27. Conversely, heat generated during the operation of the IC chip 25 is transferred from the back surface of the IC chip 25 to the electrode 29G on the back surface of the module substrate 26 through the electrode 27 and the thermal via 28, and is dissipated. An electrode 29 </ b> S is formed on the outer periphery of the back surface of the module substrate 26. The electrode 29S indicates a signal electrode. In addition to the IC chip 25, a passive element 30 such as a capacitor, a resistor, and an inductor is mounted on the main surface of the module substrate 26. This passive element is electrically connected to the IC chip 25. The module substrate 26 has a multilayer wiring structure in which a plurality of insulating plates are stacked and integrated. The insulator plate is made of a ceramic such as alumina (aluminum oxide, Al ₂ O ₃ , relative dielectric constant 9 to 9.7) having a low dielectric loss up to the millimeter wave region, but is not limited thereto. For example, a glass epoxy resin may be used. Note that a lead frame or the like may be used as the module substrate 26.

  Next, the operation of the second LDMISFET 23 shown in FIG. 2 will be described. That is, the operation of the second LDMISFET 23 formed on the output terminal side (closest to the antenna) among the LDMISFETs mounted on the power amplifier will be described. FIG. 4 is a graph showing the relationship between the drain voltage and the drain current in the second LDMISFET 23. The horizontal axis shows the drain voltage, and the vertical axis shows the drain current. FIG. 4 shows the relationship between the drain voltage and the drain current when the gate voltage applied to the gate electrode is fixed to a predetermined value. FIG. 4 shows a load line. When the second LDMISFET 23 operates, it moves on this load line. Further, there is a bias point near the center of the load line. That is, FIG. 4 shows the bias voltage (Vdd) applied to the drain electrode of the second LDMISFET 23.

  At the time of low power output, the second LDMISFET 23 only moves on the load line near the bias point. Therefore, the drain voltage of the second LDMISFET 23 does not change much from the bias voltage (Vdd). However, at the time of high power output, the drain voltage of the second LDMISFET 23 moves greatly on the load line around the bias point. For this reason, the drain voltage changes greatly with the bias voltage (Vdd) as the center.

  If the drain voltage changes greatly in this way, the amplification distortion of the linear power amplifier increases. This is because, when the drain voltage changes greatly, for example, device parameters such as a feedback capacitance formed between the gate electrode and the drain region change greatly, and impedance matching shifts.

  Hereinafter, it will be described with reference to FIG. 5 that the feedback capacitance greatly changes when the drain voltage changes greatly in the LDMISFET. That is, the drain voltage dependency of the feedback capacitance will be described.

  FIG. 5 is a cross-sectional view showing an LDMISFET studied by the present inventors. In FIG. 5, a p-type epitaxial layer 41 into which a p-type impurity is introduced is formed on a semiconductor substrate 40 made of silicon. A p-type semiconductor layer 42 and a p-type semiconductor layer 43 reaching the semiconductor substrate 40 are formed in the p-type epitaxial layer 41. A gate electrode 45 is formed on the end portion of the p-type semiconductor layer 43 via a gate insulating film 44, and a cap insulating film 46 is formed on the gate electrode 45.

An n ⁺ type semiconductor region 47 serving as a source region, an n ⁻ type semiconductor region 48 serving as a drain offset region, and an n ⁺ type semiconductor region 49 serving as a drain region are formed in alignment with the gate electrode 45. The n ⁻ type semiconductor region 48 that is a drain offset region is doped with an n-type impurity having a lower concentration than the n + type semiconductor region 49. The reason for forming such a low concentration region is to improve the drain breakdown voltage.

Further, an insulating film 50 is formed so as to cover the gate electrode 45 and the cap insulating film 46, and the conductive film 51 reaching the n ⁺ type semiconductor region 47 and the n ⁺ type semiconductor region 49 are formed on the insulating film 50. A conductive plug 53 is formed.

  An insulating film 55 is formed on the insulating film 50, while a source electrode 52 and a wiring 56 are formed on the plug 51. A drain electrode 54 and a wiring 57 are formed on the plug 53.

Here, although a depletion layer is formed in the vicinity of the pn junction between the n ⁻ type semiconductor region 48 that is the drain offset region and the p type epitaxial layer 41, when the voltage applied to the drain region is small, for example, the pn junction boundary It is assumed that a depletion layer is formed in the region from to the broken line A. At this time, the distance between the gate electrode 45 and the neutral region of the n ⁻ type semiconductor region 48 is d1, and a feedback capacitance inversely proportional to the distance d1 is generated.

Next, when the voltage applied to the drain region increases, the region that becomes the depletion layer increases, and for example, the region from the pn junction boundary to the broken line B becomes the depletion layer. That is, the depletion layer increases from the broken line A to the broken line B. At this time, the distance between the gate electrode 45 and the neutral region of the n ⁻ type semiconductor region 48 is d2, and a feedback capacitance inversely proportional to the distance d2 is generated.

  Since the distance d2 is longer than the distance d1, the feedback capacity is reduced. Thus, when the voltage applied to the drain region changes, the depletion layer formed in the drain offset region changes. As a result, the distance between the gate electrode 45 and the neutral region of the drain offset region changes, and the feedback capacitance changes. That is, it can be seen that the feedback capacitance changes greatly when the drain voltage changes greatly.

  As described above, in the LDMISFET structure studied by the present inventors, when the drain voltage changes greatly, the feedback capacitance (device parameter) changes greatly, so that the amplification distortion of the linear power amplifier increases. Therefore, the present inventors propose an LDMISFET having the structure shown below.

  FIG. 6 is a layout diagram showing a formation region of an LDMISFET (for example, used for a power amplifier of a mobile phone) in the first embodiment. In FIG. 6, there are a drain pad (pad electrode, bonding pad) 61 electrically connected to the drain electrode of the LDMISFET and a gate pad (pad) electrically connected to the gate electrode of the LDMISFET around the LDMISFET formation region 60. Electrodes, bonding pads) 62 are arranged.

  By supplying the drain voltage to the drain pad 61, the drain voltage is applied to the drain region of the LDMISFET formed in the LDMISFET formation region 60, and by supplying the gate voltage to the gate pad 62, the drain voltage is applied to the LDMISFET formation region 60. A gate voltage is applied to the gate electrode of the formed LDMISFET. Further, by supplying a source voltage (for example, a ground potential or a fixed potential) to a source electrode (not shown) on the back surface of the LDMISFET formation region, the source voltage is applied to the source region of the LDMISFET formed in the LDMISFET formation region 60. Is applied. The fixed potential is referred to as a fixed potential even when the potential fluctuates due to an influence of noise or the like or a large current flows. The ground potential is the lowest potential among a plurality of power supply potentials.

  In the LDMISFET formation region 60, a plurality of unit cell regions 60a shown in FIG. 6 are provided two-dimensionally. FIG. 7 shows a layout of one unit cell region 60a. In FIG. 7, an element isolation region 70 and an active region 71 are formed in the unit cell region 60a. Two gate electrodes 45 are formed in the unit cell region 60 a, a drain region is formed in the active region 71 between the two gate electrodes 45, and a source is provided outside each of the two gate electrodes 45. A region is formed. That is, two LDMISFETs are formed in the unit cell region 60a. In these two LDMISFETs, the drain region is common.

  The gate electrode 45 extends from the active region 71 to the element isolation region 70 and is connected to the upper layer wiring via a plug on the element isolation region 70. The gate electrode 45 is finally electrically connected to the gate pad. A field plate electrode 59a is formed on the side wall of the gate electrode 45 on the drain region side through an insulating film (not shown).

In the drain region, an n ⁻ type semiconductor region 48 and an n ⁺ type semiconductor region 49 serving as a drain offset region are formed, and the n ⁺ type semiconductor region 49 is connected to the drain electrode 54 through a plug 53. On the other hand, the source region, p-type semiconductor region 42 and the n ⁺ semiconductor region 47 has been formed, the p-type semiconductor region 42 and the n ⁺ semiconductor region 47 is connected to the source electrode 52 through the plug 51 . In FIG. 7, the illustration of the configuration above the source electrode 52 and the drain electrode 54 is omitted.

  In the LDMISFET formation region 60 shown in FIG. 6, a plurality of unit cell regions having the configuration shown in FIG. 7 are two-dimensionally formed, so that a plurality of LDMISFETs are formed, and the plurality of LDMISFETs are electrically connected. By being connected in parallel, each amplification stage of the power amplifier is formed.

Next, FIG. 8 is a cross-sectional view taken along line AA in FIG. In FIG. 8, in the LDMISFET according to the first embodiment, a p-type epitaxial layer 41 is formed on a semiconductor substrate 40. The p-type epitaxial layer 41 includes a p ⁺ -type semiconductor region 42 and a p-type ( A second conductivity type) semiconductor region 43 is formed. The p ⁺ type semiconductor region (source punching layer) 42 reaches the semiconductor substrate 40 and has a function of connecting the source region to the source electrode made of the semiconductor substrate 40. That is, a source region described later is electrically connected to a source electrode formed on the back surface of the semiconductor substrate. The p-type semiconductor region 43 has a role as a punch-through stopper layer that prevents punch-through in the LDMISFET. The p-type semiconductor region 43 constitutes a p-type well and is formed below the gate insulating film 44 and the n ⁺ semiconductor region 47 (source region).

A gate electrode 45 is formed on the end portion of the p-type semiconductor region 43 via a gate insulating film 44, and a cap insulating film 46 is formed on the gate electrode 45. An insulating film 58 is formed so as to cover the gate electrode 45, and a field plate electrode 59 a is formed on the insulating film 58. Insulating film 58 is formed to cover the upper surface and side surfaces of gate electrode 45 and n ⁻ type semiconductor region 48. Field plate electrode (conductive film) 59 a is formed on insulating film 58 formed on the side wall of gate electrode 45 located on the n ⁻ type semiconductor region 48 side and on insulating film 58 on n ⁻ type semiconductor region 48. Yes. The provision of the field plate electrode 59a is one of the features of the LDMISFET according to the first embodiment. That is, the field plate electrode 59a is formed so as to cover the side wall of the gate electrode 45 on the drain region side, and is in a floating state. That is, the field plate electrode 59a is not electrically connected to the power source. The field plate electrode 59a is formed of a conductor film such as a polysilicon film into which impurities are introduced.

Thus, by providing the field plate electrode 59a in a floating state, the drain voltage dependency of the feedback capacitance can be suppressed. More specifically, first, in the LDMISFET having the configuration shown in FIG. 5, the feedback capacitance is a capacitance between the gate electrode 45 and the neutral region of the n ⁻ semiconductor region 48 which is the drain offset region, which is not depleted. . On the other hand, in the first embodiment, as shown in FIG. 8, a field plate electrode 59a in a floating state is provided. Therefore, the feedback capacitance is generated between the first capacitance generated between the gate electrode 45 and the field plate electrode 59a, the field plate electrode 59a, and the n ⁻ type (first conductivity type) semiconductor region 48. The second capacitor is connected in series. That is, the first capacitance corresponding to the distance a2 between the gate electrode 45 and the field plate electrode 59a and the second capacitance corresponding to the distance a1 between the field plate electrode 59a and the n ⁻ -type semiconductor region 48 are connected in series. It becomes capacity.

Here, when the drain voltage applied to the drain region is changed, the depletion layer formed in the n ⁻ type semiconductor region 48 changes. However, the depletion layer only spreads from the left side to the right side on the surface of the n ⁻ type semiconductor region 48. That is, even if the region of the depletion layer changes, the distance a1 between the field plate electrode 59a and the neutral region of the n ⁻ type semiconductor region 48 that is not depleted does not change. Therefore, the change of the feedback capacity can be suppressed. That is, according to the structure of the LDMISFET in the first embodiment, the distance a1 and the distance a2 related to the feedback capacitance can be set to an amount independent of the drain voltage, so that the drain dependency of the feedback capacitance can be suppressed. It can be done.

An insulating film 50 is formed on the insulating film 58 and the field plate electrode 59a. The insulating film 50 includes conductive plugs (source plugs) 51 and n that reach the n ⁺ -type semiconductor region 47. ^A conductive plug (drain plug) 53 reaching the ⁺ -type semiconductor region 49 is formed. The plug 51 and the plug 53 are formed by embedding a conductive material in the source contact hole and the drain contact hole, respectively. Further, an insulating film 55 is formed on the insulating film 50, while a source electrode (source wiring) 52 and a wiring 56 are formed on the plug 51. A drain electrode (drain wiring) 54 and a wiring 57 are formed on the plug 53. In FIG. 8, the structure on the source electrode 52 and the drain electrode 54 not shown in FIG. 7 is also illustrated. The n ⁻ type semiconductor region (second drain region) 48 is a drain offset region, and is provided between the gate electrode 45 and the n ⁺ type semiconductor region (first drain region) 49. In other words, the n ⁻ type semiconductor region (second drain region) 48 is provided between the gate electrode 45 and the n ⁺ type semiconductor region (first drain region) 49 provided apart from the gate electrode 45. . The impurity concentration of the n ⁻ type semiconductor region 48 is lower than the impurity concentration of the n ⁺ type semiconductor region 49.

Next, FIG. 9, the drain of the first embodiment LDMISFET feedback capacitance _{(C rss)} in the drain voltage dependency and examination examples of LDMISFET feedback capacitor in (see FIG. 8) _{(C rss)} (see FIG. 5) It is a figure which shows the result of having compared with voltage dependence. FIG. 9 shows an actual measurement of the drain voltage dependence of the feedback capacitance by making an LDMISFET having the structure shown in FIG.

  9, in the structure of the study example, the feedback capacitance is 1.38 (pF) when the drain voltage is 3.5 (V), and the feedback capacitance is 2.20 (pF) when the drain voltage is 0 (V). ). Therefore, the change rate of the feedback capacitance when the drain voltage is changed from 3.5 (V) to 0 (V) is about + 60%.

  On the other hand, in the structure of the first embodiment, when the drain voltage is 3.5 (V), the feedback capacitance is 1.70 (pF), and when the drain voltage is 0 (V), the feedback capacitance is 2. 13 (pF). Therefore, the change rate of the feedback capacitance when the drain voltage is changed from 3.5 (V) to 0 (V) is about + 25%.

  From the above, it can be seen that the drain voltage dependency of the feedback capacitance can be suppressed lower in the first embodiment than in the study example. For this reason, when the LDMISFET in the first embodiment is used in a linear power amplifier, amplification distortion can be reduced.

  10 and 11 show that the performance (efficiency) of the linear power amplifier can be improved when the LDMISFET of the first embodiment is used for the linear power amplifier. FIG. 10 is a graph showing the results of tuning so that the distortion characteristics are substantially the same when comparing the study example and the first embodiment. The horizontal axis represents the output power (dBm) of the power amplifier, and the vertical axis represents the distortion characteristic (dBc).

  FIG. 11 is a graph showing the relationship between the output power (dBm) of the power amplifier and the power added efficiency (%). For example, in FIG. 10, when the point where the distortion is the same −40 (dBc) in the study example and the first embodiment, the output power at that time is 27.5 (dBm). Then, in FIG. 11, looking at the power added efficiency when the output power is 27.5 (dBm), the power added efficiency is 46% in the case of the study example, whereas in the case of the first embodiment, The power added efficiency is 48%. For this reason, in the first embodiment, amplification distortion can be suppressed, and as a result, power added efficiency can be improved by 2% compared to the study example.

  Next, a method for manufacturing the LDMISFET according to the first embodiment will be described with reference to the drawings.

First, as shown in FIG. 12, a p-type epitaxial layer 41 into which a p-type impurity such as boron (B) is introduced is formed on a semiconductor substrate 40. Then, a p ⁺ type semiconductor region 42 is formed in the p type epitaxial layer 41 by using a photolithography technique and an ion implantation method. The p ⁺ type semiconductor region 42 is formed so that the bottom reaches the semiconductor substrate 40 by introducing, for example, boron into the p type epitaxial layer 41. Subsequently, a p-type semiconductor region 43 is formed in the p-type epitaxial layer 41 using a photolithography technique and an ion implantation method. Thereafter, a gate insulating film 44 is formed on the surface of the p-type epitaxial layer 41 using, for example, a thermal oxidation method. The gate insulating film 44 is formed of, for example, a silicon oxide film, but may be formed of a so-called high-k film having a dielectric constant higher than that of the silicon oxide film.

  Next, after a polysilicon film is formed on the gate insulating film 44 by using, for example, a CVD (Chemical Vapor Deposition) method, an insulating film is formed on this polysilicon film by using, for example, the CVD method. The insulating film is formed from, for example, a silicon oxide film. Subsequently, as shown in FIG. 13, the gate electrode 45 and the cap insulating film 46 are formed by sequentially patterning the insulating film and the polysilicon film using a photolithography technique and an etching technique.

Next, as illustrated in FIG. 14, an n ⁺ type semiconductor region 47, an n ⁻ type semiconductor region 48, and an n ⁺ type semiconductor region 49 are formed using a photolithography technique and an ion implantation method. These regions are formed by introducing n-type impurities such as phosphorus (P) and arsenic (As). The n ⁺ type semiconductor region 47 functions as a source region, and the n ⁺ type semiconductor region 49 functions as a drain region. The n ⁻ type semiconductor region 48 functions as a drain offset region, and an n type impurity is introduced at a lower concentration than the n ⁺ type semiconductor region 49.

  Subsequently, as shown in FIG. 15, after an insulating film 58 is formed on the element formation surface of the semiconductor substrate 40, a polysilicon film 59 is formed on the insulating film 58. The insulating film 58 is made of, for example, a silicon oxide film formed by a CVD method and has a film thickness of, for example, about 100 nm. Similarly, the polysilicon film 59 is also formed by using, for example, a CVD method, and the film thickness thereof is, for example, about 100 nm.

Next, as shown in FIG. 16, the polysilicon film 59 is patterned using a photolithography technique and an etching technique to form a field plate electrode 59a. The field plate electrode 59a is formed so as to cover the side wall on the drain region side of the gate electrode 45, and is formed so that the potential of the field plate electrode 59a is in a floating state.

  Subsequently, as shown in FIG. 17, an insulating film 50 is formed on the insulating film 58 and the field plate electrode 59a. The insulating film 50 is made of, for example, a silicon oxide film, and can be formed using, for example, a CVD method. The film thickness of the insulating film 50 is, for example, about 300 nm to 500 nm. Thereafter, the contact hole 51a and the contact hole 53a are formed by using a photolithography technique and an etching technique.

  Thereafter, a conductor film is formed on the element formation surface of the semiconductor substrate 40, thereby forming plugs 51 and 53 for embedding the contact holes 51a and 53a. Subsequently, after forming an aluminum alloy film on the element formation surface of the semiconductor substrate 40, the source electrode 52 and the drain electrode 54 are formed by patterning using a photolithography technique and an etching technique. The aluminum alloy film can be formed using, for example, a sputtering method.

  Similarly, wiring 56 and wiring 57 made of an aluminum alloy film are formed in the insulating film 55. In this manner, the LDMISFET (semiconductor device) in the first embodiment can be formed.

(Embodiment 2)
In the first embodiment, the example in which the field plate electrode is formed so as to cover the side wall on the drain region side of the gate electrode has been described. In the second embodiment, an example in which the field plate electrode is formed so as not to cover the side wall of the gate electrode on the drain region side is described. A description of the same components as those in the first embodiment will be omitted.

  In the LDMISFET according to the second embodiment, side walls 72 made of an insulating film (for example, a silicon oxide film) are formed on both sides of the side wall of the gate electrode 45. A field plate electrode 59b is formed outside the side wall 72 formed on the side wall on the drain region side. Unlike the first embodiment, the field plate electrode 59b is not formed so as to cover the side wall of the gate electrode 45 on the drain region side.

  By forming the field plate electrode 59b in this way, the feedback capacitance determined by the facing area between the gate electrode 45 and the field plate electrode 59b can be reduced. This is because the area of the field plate electrode 59b facing the gate electrode 45 can be reduced. That is, since the value of the feedback capacitance is proportional to the area of the gate electrode 45 and the field plate electrode 59b facing the gate electrode 45, the value of the feedback capacitance is reduced by forming the field plate electrode 59b so as not to cover the gate electrode 45. can do. In the second embodiment, since the value of the feedback capacitance can be reduced, the amplification distortion of the linear power amplifier can be suppressed, and the performance (efficiency) of the linear power amplifier can be improved.

Further, since the potential of the field plate electrode 59b is in a floating state, the feedback capacitance is a capacitance in which a first capacitance corresponding to the distance a2 and a second capacitance corresponding to the distance a1 are connected in series. Here, when the drain voltage changes, the depletion layer formed in the drain offset region (n ⁻ type semiconductor region 48) changes. However, as in the first embodiment, even if the depletion layer changes, the distance a1 between the field plate electrode 59b and the drain offset region does not change, so that the dependency of the feedback capacitance on the drain voltage can be suppressed. Therefore, the amplification distortion of the linear power amplifier can be reduced, and the performance (efficiency) of the linear power amplifier can be improved.

  Further, in the second embodiment, a sidewall 72 is formed between the gate electrode 45 and the field plate electrode 59b. Therefore, the distance a2 between the gate electrode 45 and the field plate electrode 59b can be changed by changing the width of the side wall 72 to be formed. That is, the capacitance formed between the gate electrode 45 and the field plate electrode 59b can be adjusted by changing the width of the side wall 72 to be formed, so that an effect of increasing the design freedom of the LDMISFET can be obtained.

  Next, a method for manufacturing the LDMISFET according to the second embodiment will be described with reference to the drawings.

Through the same process as in the first embodiment, a p-type epitaxial layer 41 is formed on the semiconductor substrate 40, and a p ⁺ semiconductor region 42 and a p-type semiconductor region 43 are formed in the p-type epitaxial layer 41. Subsequently, a gate insulating film 44 is formed, and a gate electrode 45 and a cap insulating film 46 are formed on the gate insulating film 44. Then, an n ⁺ type semiconductor region 47, an n ⁻ type semiconductor region 48 and an n ⁺ type semiconductor region 49 are formed in alignment with the gate electrode 45.

  Next, an insulating film is formed on the element formation surface of the semiconductor substrate 40. This insulating film is made of, for example, a silicon oxide film, and can be formed by using, for example, a CVD method. Thereafter, as shown in FIG. 19, sidewalls 72 are formed on the sidewalls on both sides of the gate electrode 45 by anisotropically etching the insulating film. At this time, the width of the sidewall 72 can be adjusted to a predetermined value by changing the etching conditions.

  Subsequently, as shown in FIG. 20, after an insulating film 58 is formed on the element formation surface of the semiconductor substrate 40, a polysilicon film 59 is formed on the insulating film 58. The polysilicon film 59 can be formed using, for example, a CVD method. In place of the polysilicon film 59, another conductor film may be formed.

Next, as shown in FIG. 21, field plate electrodes 59 b are formed on the sidewalls on both sides of the gate electrode 45 by anisotropically etching the polysilicon film 59. At this time, the field plate electrode 59b is formed so that the potential is in a floating state. And after apply | coating the resist film 73 to the element formation surface of the semiconductor substrate 40 as shown in FIG.
The resist film 73 is patterned by performing exposure / development processing. The patterning is performed so that the drain region side is covered with the resist film 73 from the central portion of the gate electrode 45 while the source region side is exposed from the central portion of the gate electrode 45. That is, the field plate electrode 59b formed on the side wall on the drain region side of the gate electrode 45 is covered with the resist film 73, while the field plate electrode 59b formed on the side wall on the source region side of the gate electrode 45 is exposed. Patterned.

  Subsequently, as shown in FIG. 23, the field plate electrode 59b formed on the source region side is removed by etching using the patterned resist film 73 as a mask. Thereafter, the patterned resist film 73 is removed.

  Next, as shown in FIG. 24, after the insulating film 50 is formed on the element formation surface of the semiconductor substrate 40, contact holes 51a and 53a are formed in the insulating film 50 by using a photolithography technique and an etching technique. . The insulating film 50 is formed of, for example, a silicon oxide film, and can be formed using, for example, a CVD method.

  Thereafter, the wiring 56 and the wiring 57 are formed in the same manner as in the first embodiment. In this way, the LDMISFET in the second embodiment can be formed.

(Embodiment 3)
In the first embodiment and the second embodiment, the example in which the potential of the field plate electrode is set to the floating state has been described. In the third embodiment, an example in which the field plate electrode is electrically connected to the drain region will be described.

  FIG. 25 is a plan view showing a layout configuration of the LDMISFET according to the third embodiment. FIG. 25 is basically the same as FIG. 7 showing the LDMISFET in the first embodiment. The difference from the first embodiment is that the field plate electrode 59c is connected to the wiring 57 connected to the drain region via the plug 74, as shown in FIG. That is, in the third embodiment, a voltage having the same potential as the voltage applied to the drain region is applied to the field plate electrode 59c. As shown in FIG. 25, the field plate electrode 59c and the drain region are connected in a region (element isolation region) other than the active region.

  26 is a cross-sectional view taken along line AA in FIG. Since the drain voltage is applied to the field plate electrode 59c, the feedback capacitance is not between the gate electrode 45 and the offset drain region, but is between the gate electrode 45 and the field plate electrode 59c.

  Here, the field plate electrode 59c is made of, for example, a polysilicon film into which p-type impurities or n-type impurities are introduced. However, the field plate electrode 59c is surrounded by an insulating film and is not in contact with silicon layers having different conductivity types. For this reason, a pn junction that causes a depletion layer is not formed. Further, since impurities are introduced at a high concentration, a depletion layer is not formed. Therefore, the distance of the insulating layer between the field plate electrode 59c and the gate electrode 45 does not depend on the drain voltage. For this reason, since the drain voltage dependency of the feedback capacitance can be suppressed, the amplification distortion of the linear power amplifier can be suppressed, and the performance (efficiency) of the linear power amplifier can be improved.

  The manufacturing method of the LDMISFET in the third embodiment is almost the same as that in the first embodiment. The difference is that the field plate electrode 59c is formed to be electrically connected to the drain region.

(Embodiment 4)
In the third embodiment, the example in which the field plate electrode is electrically connected to the drain region has been described. In the fourth embodiment, an example will be described in which a field plate electrode is provided in a MISFET included in a linear power amplifier used in the WCDMA system and the field plate electrode is electrically connected to a source region.

  FIG. 27 is a plan view showing a layout configuration of the LDMISFET according to the fourth embodiment. FIG. 27 is basically the same as FIG. 7 showing the LDMISFET in the first embodiment. The difference from the first embodiment is that the field plate electrode 59c is connected to the wiring 56 connected to the source region via the plug 75 as shown in FIG. That is, in the fourth embodiment, a voltage having the same potential as that applied to the source region is applied to the field plate electrode 59d. As shown in FIG. 27, the field plate electrode 59d and the source region are connected in a region (element isolation region) other than the active region.

  A sectional view taken along line AA in FIG. 27 is basically the same as FIG. A different point is that the field plate electrode 59d is connected to a source potential, that is, a ground potential. The field plate electrode 59 is formed so as to cover the side wall of the gate electrode 45 on the drain region side, and is further connected to the ground potential. The feedback capacitor is formed between the gate electrode 45 and the drain offset region (n− type semiconductor region 48) (fringe component), but is a field plate connected to the ground potential between the gate electrode 45 and the drain offset region. An electrode 59d is formed. Since the field plate electrode 59d connected to the ground potential functions as a shield, the feedback capacitance is greatly reduced. Therefore, since the amplification distortion of the linear power amplifier can be suppressed, the performance (efficiency) of the linear power amplifier can be improved.

  28 and 29 show that when the LDMISFET of the fourth embodiment is used for a linear power amplifier, the performance (efficiency) of the linear power amplifier can be improved. FIG. 28 is a graph showing the results of tuning so that the distortion characteristics are substantially the same when comparing the study example and the fourth embodiment. The horizontal axis represents the output power (dBm) of the power amplifier, and the vertical axis represents the distortion characteristic (dBc).

  FIG. 29 is a graph showing the relationship between the output power (dBm) of the power amplifier and the power added efficiency (%). For example, in FIG. 28, when the point where the distortion becomes the same −40 (dBm) in the study example and the fourth embodiment, the output power at that time is 27.5 (dBm). In FIG. 29, when the power added efficiency when the output power is 27.5 (dBm) is seen, the power added efficiency is 46% in the case of the study example, whereas in the case of the fourth embodiment, The power added efficiency is 48%. Therefore, in the fourth embodiment, amplification distortion can be suppressed, and as a result, the power added efficiency can be improved by 2% compared to the study example.

  The manufacturing method of the LDMISFET in the fourth embodiment is almost the same as that in the first embodiment. The difference is that the field plate electrode 59d is formed so as to be electrically connected to the source region.

(Embodiment 5)
In the first to third embodiments, the power amplifier mounted on the WCDMA mobile phone has been described. However, in the fifth embodiment, both the WCDMA method and the GSM (Global System for Mobile Communication) method are supported. An example used for the power amplifier of the mobile phone will be described.

  GSM refers to one or standard of wireless communication methods used in digital mobile phones. GSM has three frequency bands of radio waves to be used: GSM900 for the 900 MHz band or simply GSM, 1800 MHz band for GSM1800 or DCS (Digital Cellular System) or PCN, 1900 MHz band for GSM1900 or DCS1900 or PCS (Personal Communication Services) That's it. GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may also be used.

  FIG. 30 is a diagram illustrating a circuit configuration of a power amplifier that supports both the WCDMA system and the GSM system. In FIG. 30, a circuit formed between an input terminal 80a and an output terminal 81a is a WCDMA power amplifier. In this power amplifier, a matching circuit 82 is formed on the input terminal 80a side, and the first stage LDMISFET 83 is connected to the matching circuit 82. In the LDMISFET 83, a second-stage LDMISFET 85 is formed via a matching circuit 84.

  On the other hand, a circuit formed between the input terminal 80b and the output terminal 81b is a GSM power amplifier. In this power amplifier, a matching circuit 86 is formed on the input terminal 80 b side, and the first-stage LDMISFET 87 is connected to the matching circuit 82. The second stage LDMISFET 89 is connected to the LDMISFET 87 via a matching circuit 88. Reference numerals 90 and 91 denote transmission lines.

  In the circuit thus configured, WCDMA LDMISFETs 83 and 85 and GSM LDMISFETs 87 and 89 are mounted on, for example, one chip. It may be configured not to be mounted on one chip.

  In the LDMISFET 85 for the WCDMA system, the field plate electrode is formed on the drain region side of the gate electrode as described in the above embodiment, and this field plate electrode is not connected to the power source and is in a floating state. Yes. By providing the floating field plate electrode in this way, the same effect as in the first embodiment or the second embodiment can be obtained. Similarly, a field plate electrode in a floating state is also formed in the LDMISFET 89 for the GSM system.

  Note that the field plate electrode may be connected to the drain region as in the third embodiment (the drain potential may be set).

  In FIG. 30, the two amplification stages are used. However, the present invention is not limited to this. For example, three amplification stages may be used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing wireless communication devices such as mobile phones.

It is the block diagram which showed the structure of the digital mobile phone. It is a figure which shows an example of the circuit structure of a power amplifier. It is sectional drawing which showed an example of RF power module (power amplifier). In LDMISFET, it is the graph which described the relationship between a drain voltage and drain current, and a load line. It is sectional drawing which showed LDMISFET which the present inventors examined. It is the layout figure which showed the formation area of LDMISFET in Embodiment 1 of this invention. It is the top view which showed the unit cell area | region of the LDMISFET formation area. It is sectional drawing cut | disconnected by the AA line of FIG. It is a figure which shows the result of having compared the drain voltage dependence of the feedback capacity | capacitance in LDMISFET of Embodiment 1, and the drain voltage dependence of the feedback capacity | capacitance in LDMISFET of the examination example. 5 is a graph showing the relationship between the output power of the power amplifier and the amplification distortion in each of the first embodiment and the study example. 5 is a graph showing a relationship between output power of a power amplifier and power added efficiency in each of the first embodiment and a study example. 6 is a cross-sectional view showing a manufacturing process of the LDMISFET in the first embodiment. FIG. FIG. 13 is a cross-sectional view showing a manufacturing step of the LDMISFET subsequent to FIG. 12. FIG. 14 is a cross-sectional view showing a manufacturing step of the LDMISFET subsequent to FIG. 13. FIG. 15 is a cross-sectional view showing a manufacturing step of the LDMISFET subsequent to FIG. 14. FIG. 16 is a cross-sectional view showing a manufacturing step of the LDMISFET subsequent to FIG. 15. FIG. 17 is a cross-sectional view showing a manufacturing step of the LDMISFET subsequent to FIG. 16. FIG. 6 is a cross-sectional view showing an LDMISFET in a second embodiment. FIG. 10 is a cross-sectional view showing a manufacturing process of the LDMISFET in the second embodiment. FIG. 20 is a cross-sectional view showing a manufacturing step of the LDMISFET subsequent to FIG. 19. FIG. 21 is a cross-sectional view showing a manufacturing step of the LDMISFET subsequent to FIG. 20. FIG. 22 is a cross-sectional view showing a manufacturing step of the LDMISFET subsequent to FIG. 21. FIG. 23 is a cross-sectional view showing a manufacturing step of the LDMISFET following FIG. FIG. 24 is a cross-sectional view showing a manufacturing step of the LDMISFET subsequent to FIG. 23. FIG. 6 is a plan view showing an LDMISFET according to a third embodiment. It is sectional drawing cut | disconnected by the AA line of FIG. FIG. 10 is a plan view showing an LDMISFET according to a fourth embodiment. 6 is a graph showing the relationship between the output power of the power amplifier and the amplification distortion in each of the fourth embodiment and the study example. 6 is a graph showing a relationship between output power of a power amplifier and power added efficiency in each of Embodiment 4 and a study example. It is a figure which shows the circuit structure of the power amplifier corresponding to both a WCDMA system and a GSM system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control display part 2 Baseband part 3 RF block part 4 Antenna 5 D / A converter 6 Quadrature modulator 7 Transmission mixer 8 Power amplifier 9 Antenna switch 10 Low noise amplifier 11 Reception mixer 12 IF circuit 13 Oscillator 14 PLL circuit 20 Input Terminal 21 Output terminal 22 First LDMISFET
23 Second LDMISFET
24a matching circuit 24b matching circuit 24c matching circuit 25 IC chip 26 module substrate 27 electrode 28 thermal via 29G electrode 29S electrode 30 passive element 40 semiconductor substrate 41 p-type epitaxial layer 42 p ⁺ type semiconductor region 43 p-type semiconductor region 44 gate insulating film 45 gate electrode 46 cap insulating film 47 n ⁺ type semiconductor region 48 n ⁻ type semiconductor region 49 n ⁺ type semiconductor region 50 insulating film 51 plug 51a contact hole 52 source electrode 53 plug 53a contact hole 54 drain electrode 55 insulating film 56 wiring 57 Wiring 58 Insulating film 59 Polysilicon film 59a Field plate electrode 59b Field plate electrode 59c Field plate electrode 59d Field plate electrode 60 LDMISFET formation region 6 a unit cell region 61 drain pad 62 gate pad 70 isolation region 71 the active region 72 side wall 73 resist film 74 plugs 75 Plug 80a input terminal
80b input terminal 81a output terminal 81b output terminal 82 matching circuit 83 LDMISFET
84 Matching circuit 85 LDMISFET
86 Matching circuit 87 LDMISFET
88 matching circuit 89 LDMISFET
90 Transmission line 91 Transmission line PM RF power module

Claims (17)

A semiconductor device including a MISFET,
The MISFET is
(A) a semiconductor substrate;
(B) a gate insulating film formed on the semiconductor substrate;
(C) a gate electrode formed on the gate insulating film;
(D) a source region having a first conductivity type;
(E) a first drain region formed apart from the gate electrode and having the first conductivity type;
(F) a second drain region formed between the gate electrode and the first drain region, having the first conductivity type and having an impurity concentration lower than that of the first drain region;
(G) a semiconductor region formed below the gate insulating film and the source region and having a second conductivity type opposite to the first conductivity type;
(H) an insulating film covering the top and side surfaces of the gate electrode and the second drain region;
(I) comprising a conductive film formed on the insulating film formed on a side wall of the gate electrode located on the second drain region side and on the insulating film on the second drain region;
The semiconductor device is characterized in that the conductive film is not electrically connected to a power source.   The semiconductor device according to claim 1, wherein the conductive film is formed of a polysilicon film.   2. The semiconductor device according to claim 1, wherein the MISFET is an LDMISFET, and the conductive film is a field plate electrode. The semiconductor device further includes:
(J) an interlayer insulating film formed on the conductive film;
(K) a source contact hole and a drain contact hole formed in the interlayer insulation;
(L) a source plug and a drain plug respectively formed in the source and drain contact holes;
(M) a source wiring and a drain wiring formed on the source and drain plugs and electrically connected to the source and drain plugs, respectively;
The semiconductor device according to claim 1, wherein the source wiring and the drain wiring are electrically connected to the source region and the first drain region, respectively.   The semiconductor device according to claim 1, wherein the semiconductor device has a source electrode on a back surface of the semiconductor substrate, and the source region and the source electrode are electrically connected.   The semiconductor device according to claim 1, wherein the insulating film is a sidewall.   2. The semiconductor device according to claim 1, wherein the semiconductor device is a power amplifier mounted on a WCDMA mobile phone.   The semiconductor device according to claim 1, wherein the semiconductor device is a power amplifier mounted on a mobile communication device.   9. The semiconductor device according to claim 8, wherein the power amplifier has a linear amplification function. A semiconductor device including a MISFET,
The MISFET is
(A) a semiconductor substrate;
(B) a gate insulating film formed on the semiconductor substrate;
(C) a gate electrode formed on the gate insulating film;
(D) a source region having a first conductivity type;
(E) a first drain region formed apart from the gate electrode and having the first conductivity type;
(F) a second drain region formed between the gate electrode and the first drain region, having the first conductivity type and having an impurity concentration lower than that of the first drain region;
(G) a semiconductor region formed below the gate insulating film and the source region and having a second conductivity type opposite to the first conductivity type;
(H) an insulating film covering the top and side surfaces of the gate electrode and the second drain region;
(I) comprising a conductive film formed on the insulating film formed on a side wall of the gate electrode located on the second drain region side and on the insulating film on the second drain region;
The semiconductor device, wherein the conductive film is electrically connected to the first drain region.   11. The semiconductor device according to claim 10, wherein a voltage having the same potential as a voltage applied to the first drain region is applied to the conductive film.   11. The semiconductor device according to claim 10, wherein the conductive film is electrically connected to a drain wiring connected to the first drain region outside the active region. A method for manufacturing a semiconductor device including a MISFET,
(A) forming a semiconductor region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate;
(B) forming a gate insulating film on the semiconductor region;
(C) forming a gate electrode on the gate insulating film;
(D) forming a source region having the first conductivity type in the semiconductor region;
(E) forming a first drain region formed away from the gate electrode and having the first conductivity type;
(F) forming a second drain region having the first conductivity type and having an impurity concentration lower than that of the first drain region between the gate electrode and the first drain region;
(G) forming an insulating film covering an upper surface, a side surface and the second drain region of the gate electrode;
(H) forming a conductive film on the insulating film formed on a side wall of the gate electrode located on the second drain region side and on the insulating film on the second drain region;
The method for manufacturing a semiconductor device, wherein the conductive film is not electrically connected to a power source.   14. The method of manufacturing a semiconductor device according to claim 13, wherein the conductive film is a polysilicon film. A method for manufacturing a semiconductor device including a MISFET,
(A) forming a semiconductor region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate;
(B) forming a gate insulating film on the semiconductor region;
(C) forming a gate electrode on the gate insulating film;
(D) forming a source region having the first conductivity type in the semiconductor region;
(E) forming a first drain region formed away from the gate electrode and having the first conductivity type;
(F) forming a second drain region having the first conductivity type and having an impurity concentration lower than that of the first drain region between the gate electrode and the first drain region;
(G) forming an insulating film covering an upper surface, a side surface and the second drain region of the gate electrode;
(H) forming a conductive film on the insulating film formed on a side wall of the gate electrode located on the second drain region side and on the insulating film on the second drain region;
The method for manufacturing a semiconductor device, wherein the conductive film is electrically connected to the first drain region. A semiconductor chip including a MISFET constituting a power amplifier;
An electronic device comprising a substrate on which the semiconductor chip is mounted,
The MISFET is
(A) a semiconductor substrate;
(B) a gate insulating film formed on the semiconductor substrate;
(C) a gate electrode formed on the gate insulating film;
(D) a source region having a first conductivity type;
(E) a first drain region formed apart from the gate electrode and having the first conductivity type;
(F) a second drain region formed between the gate electrode and the first drain region, having the first conductivity type and having an impurity concentration lower than that of the first drain region;
(G) a semiconductor region formed below the gate insulating film and the source region and having a second conductivity type opposite to the first conductivity type;
(H) an insulating film covering the top and side surfaces of the gate electrode and the second drain region;
(I) comprising a conductive film formed on the insulating film formed on a side wall of the gate electrode located on the second drain region side and on the insulating film on the second drain region;
The electronic device is characterized in that the conductive film is not electrically connected to a power source. The substrate further includes a passive element,
The electronic device according to claim 16, wherein the passive element is electrically connected to the semiconductor chip.

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