WO2019116482A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2019116482A1
WO2019116482A1 PCT/JP2017/044823 JP2017044823W WO2019116482A1 WO 2019116482 A1 WO2019116482 A1 WO 2019116482A1 JP 2017044823 W JP2017044823 W JP 2017044823W WO 2019116482 A1 WO2019116482 A1 WO 2019116482A1
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WO
WIPO (PCT)
Prior art keywords
electrode
insulating film
interlayer insulating
mounting substrate
source
Prior art date
Application number
PCT/JP2017/044823
Other languages
French (fr)
Japanese (ja)
Inventor
安藤　直人
Original Assignee
三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2017/044823 priority Critical patent/WO2019116482A1/en
Publication of WO2019116482A1 publication Critical patent/WO2019116482A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a semiconductor element, a mounting substrate, and a bump electrode.
  • a semiconductor device having a chip size package structure includes a semiconductor chip having a source electrode, a drain electrode, and a gate electrode.
  • the semiconductor chip is connected to the mounting substrate by a bump electrode.
  • a first interlayer insulating film and a second interlayer insulating film are formed on the gate electrode of the semiconductor chip.
  • An interlayer insulating film wiring electrode is disposed in the first interlayer insulating film.
  • An interlayer insulating film surface electrode connected to the interlayer insulating film wiring electrode is disposed in the uppermost second interlayer insulating film.
  • a bump electrode for surface mounting is disposed on the interlayer insulating film surface layer electrode.
  • a connection electrode or an interlayer insulating film surface electrode is disposed on the outermost surface (or the uppermost layer) of the semiconductor chip.
  • connection electrodes solder bumps (bump electrodes) used for connection with the wiring substrate (or mounting substrate) are formed.
  • the semiconductor chip and the mounting substrate are connected using the solder bumps.
  • the source electrode of the transistor is connected to the connection electrode of the semiconductor device without electrically separating a connection point with another electrode connected to the ground electrode (see, for example, Patent Document 1).
  • the ground electrode is disposed on the outermost surface.
  • the source electrodes of the transistors are connected to the common ground electrode. For this reason, the respective source electrodes are susceptible to each other, and the circuit element tends to oscillate.
  • the semiconductor device having the chip size package structure is electrically connected to the other circuit element whose source electrode is connected to the ground electrode and the connection electrode (or the interlayer insulating film surface electrode) on the outermost surface of the semiconductor device. It is done. For this reason, the interruption
  • the connection between the source electrode and the connection electrode on the outermost surface of the semiconductor device is not made immediately above the source electrode which is the shortest distance, the transistor characteristics may be degraded.
  • the present invention has been made to solve the above-mentioned problems in a semiconductor device having a chip size package structure. That is, it is an object of the present invention to obtain a semiconductor device capable of enhancing the barrier property between circuit elements by electrically making the bump electrode connected to the source electrode independent from other bump electrodes.
  • a semiconductor device includes a semiconductor element in which a source electrode, a drain electrode, and a gate electrode are formed, an interlayer insulating film source wiring electrode, an interlayer insulating film drain wiring electrode, and A first interlayer insulating film in which an interlayer insulating film gate wiring electrode is formed, and an interlayer insulating film source surface electrode and an interlayer insulating film ground surface electrode are disposed on the first interlayer insulating film.
  • a second interlayer insulating film, a first bump electrode disposed on an interlayer insulating film source surface layer electrode formed on the second interlayer insulating film, and the second interlayer insulating film A second bump electrode disposed on an interlayer insulating film ground surface layer electrode, and a mounting substrate connected to the first bump electrode and the second bump electrode;
  • the film source wiring electrode is connected to the source electrode and the interlayer insulating film source surface electrode, and the interlayer insulating film source surface electrode is surrounded by the interlayer insulating film ground surface electrode, and the interlayer insulating film A separation groove is formed between the source surface electrode and the interlayer insulating film ground surface electrode.
  • a semiconductor device includes a semiconductor element in which a source electrode, a drain electrode, and a gate electrode are formed, an interlayer insulating film source wiring electrode, an interlayer insulating film drain wiring electrode, and A first interlayer insulating film in which an interlayer insulating film gate wiring electrode is formed, and an interlayer insulating film source surface electrode and an interlayer insulating film ground surface electrode are disposed on the first interlayer insulating film.
  • a second interlayer insulating film, a first bump electrode disposed on an interlayer insulating film source surface layer electrode formed on the second interlayer insulating film, and the second interlayer insulating film A second bump electrode disposed on an interlayer insulating film ground surface layer electrode, and a mounting substrate connected to the first bump electrode and the second bump electrode;
  • the film source wiring electrode is connected to the source electrode and the interlayer insulating film source surface electrode, and the interlayer insulating film source surface electrode is surrounded by the interlayer insulating film ground surface electrode, and the interlayer insulating film
  • a separation groove is formed between the source surface layer electrode and the interlayer insulating film ground surface layer electrode, so that the blocking property between the circuit elements can be enhanced.
  • FIG. 1 is a schematic cross sectional view showing an entire configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a top view showing arrangement of circuit elements (a source electrode, a drain electrode, and a gate electrode) in connection with an embodiment of the present invention. It is a top view which shows the structure of the interlayer insulation film surface layer electrode in connection with Embodiment 1 of this invention. It is a top view which shows the 1st structure of the mounting substrate electrode in connection with Embodiment 1 of this invention. It is a top view which shows the 2nd structure of the mounting substrate electrode in connection with Embodiment 1 of this invention.
  • FIG. 21 is a plan view showing a configuration of an interlayer insulating film surface layer electrode according to a third embodiment of the present invention.
  • FIG. 21 is a plan view showing a configuration of an interlayer insulating film surface layer electrode according to a fourth embodiment of the present invention. It is a top view which shows the 1st structure of the mounting substrate electrode in connection with Embodiment 4 of this invention. It is a top view which shows the 2nd structure of the mounted substrate electrode in connection with Embodiment 4 of this invention.
  • a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.
  • the same or similar components are denoted by the same reference numerals, and the sizes and scales of the corresponding components are independent of one another.
  • the semiconductor device actually includes a plurality of members, in order to simplify the description, only portions necessary for the description are described, and the other portions are omitted.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor device 100 having a chip size package structure.
  • the semiconductor device 100 includes a semiconductor chip 10, bump electrodes 9, a mounting substrate 20, and the like.
  • the semiconductor chip 10 includes a semiconductor element 30, a first interlayer insulating film 5, an interlayer insulating film wiring electrode 6, a second interlayer insulating film 7, an interlayer insulating film surface electrode 8, and the like.
  • a source electrode, a drain electrode, a gate electrode, a ground electrode and the like are formed in the semiconductor element 30 of the semiconductor chip 10 (see FIG. 2).
  • the mounting substrate 20 includes a mounting substrate body 21, a mounting substrate electrode 22, and the like.
  • An interlayer insulating film wiring electrode 6 is formed in the first interlayer insulating film 5.
  • the interlayer insulating film wiring electrode 6 is composed of an interlayer insulating film source wiring electrode, an interlayer insulating film drain wiring electrode, an interlayer insulating film gate wiring electrode, and an interlayer insulating film ground wiring electrode (see FIGS. 2 and 3). ).
  • An interlayer insulating film surface electrode 8 is formed on the second interlayer insulating film 7.
  • the interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and an interlayer insulating film ground surface electrode (see FIGS. 2 and 4). ).
  • the semiconductor device 100 is operated with the source of the semiconductor element 30 at the ground potential.
  • the mounting substrate electrode 22 is formed on the mounting substrate 20.
  • the bump electrode 9 is connected to the mounting substrate 20 (mounting substrate electrode 22).
  • the mounting substrate electrode 22 of the mounting substrate 20 is electrically connected to the circuit elements (the source electrode, the drain electrode, and the gate electrode) of the semiconductor chip 10 (semiconductor element 30) via the bump electrodes 9.
  • the mounting substrate electrode 22 is composed of a mounting substrate drain electrode, a mounting substrate gate electrode, and a mounting substrate ground electrode (see FIG. 5).
  • the mounting substrate ground electrode, the interlayer insulating film ground surface layer electrode, and the interlayer insulating film ground wiring electrode are grounded.
  • FIG. 2 is a cross sectional view schematically showing a configuration of a semiconductor device 100 having a chip size package structure according to the first embodiment.
  • a semiconductor element 30 such as an FET (Field Effect Transistor) is formed on the semiconductor substrate 1.
  • the semiconductor element 30 is configured of a semiconductor substrate 1, source electrode 2, drain electrode 3 (3a, 3b), gate electrode 4 (4a, 4b), and the like.
  • a first interlayer insulating film 5 is disposed on the semiconductor element 30 (semiconductor substrate 1).
  • a second interlayer insulating film 7 is disposed on the first interlayer insulating film 5.
  • the interlayer insulating film wiring electrode 6 and the interlayer insulating film surface electrode 8 have a pattern electrode portion and a via electrode portion.
  • the pattern electrode portion is formed on the surface of the interlayer insulating film (the first interlayer insulating film and the second interlayer insulating film).
  • the via electrode portion runs through the interlayer insulating film (first interlayer insulating film and second interlayer insulating film) in the vertical direction.
  • the interlayer insulating film drain wiring electrode 6a is composed of a pattern electrode portion 6ax and a via electrode portion 6ay corresponding to the drain electrode.
  • the interlayer insulating film source wiring electrode 6b is composed of a pattern electrode portion 6bx corresponding to the source electrode and a via electrode portion 6by.
  • the interlayer insulating film drain wiring electrode 6c is composed of a pattern electrode portion 6cx corresponding to the drain electrode and a via electrode portion 6cy.
  • the interlayer insulating film gate wiring electrode and the interlayer insulating film ground wiring electrode are respectively formed of a pattern electrode portion and a via electrode portion.
  • the interlayer insulating film ground surface layer electrode 8a is composed of a pattern electrode portion 8ax corresponding to the ground electrode and a via electrode portion 8ay.
  • the interlayer insulating film source surface layer electrode 8b is composed of a pattern electrode portion 8bx corresponding to the source electrode and a via portion electrode portion 8by.
  • the interlayer insulating film ground surface layer electrode 8c is composed of a pattern electrode portion 8cx corresponding to the ground electrode and a via electrode portion 8cy.
  • the interlayer insulating film drain surface layer electrode and the interlayer insulating film gate surface layer electrode are respectively formed of a pattern electrode portion and a via electrode portion.
  • a separation groove 8d is formed between the interlayer insulating film ground surface electrode 8a and the interlayer insulating film source surface electrode 8b, and between the interlayer insulating film ground surface electrode 8c and the interlayer insulating film source surface electrode 8b.
  • the drain electrode 3a of the semiconductor element 30 is electrically connected to the interlayer insulating film drain wiring electrode 6a.
  • the drain electrode 3b of the semiconductor element 30 is electrically connected to the interlayer insulating film drain wiring electrode 6c.
  • the source electrode 2 of the semiconductor element 30 is electrically connected to the interlayer insulating film source wiring electrode 6 b.
  • the gate electrodes 4a and 4b of the semiconductor element 30 are an interlayer insulating film gate wiring electrode (not shown) of the interlayer insulating film wiring electrode 6 and an interlayer insulating film gate surface electrode (not shown) of the interlayer insulating film surface electrode 8 It is electrically connected.
  • the interlayer insulating film gate surface layer electrode is connected to the mounting substrate gate electrode via the bump electrode (see FIG. 5).
  • the interlayer insulating film source wiring electrode 6b is electrically connected to the interlayer insulating film source surface layer electrode 8b.
  • the interlayer insulating film drain wiring electrodes 6 a and 6 c are connected to the interlayer insulating film drain surface electrode (not shown) of the interlayer insulating film surface electrode 8.
  • the interlayer insulating film drain surface layer electrode is connected to the mounting substrate drain electrode via the bump electrode (see FIG. 5).
  • Bump electrode 9a is connected to interlayer insulating film ground surface layer electrode 8a.
  • Bump electrode 9 b is connected to interlayer insulating film source surface layer electrode 8 b.
  • Bump electrode 9c is connected to interlayer insulating film ground surface electrode 8c.
  • the mounting substrate electrode 22 is electrically connected to the bump electrode 9.
  • the mounting substrate electrode 22 has a pattern electrode portion and a via electrode portion.
  • a mounting substrate ground electrode 22W is displayed as the mounting substrate electrode 22 formed on the mounting substrate 20 (mounting substrate main body 21).
  • a mounting substrate drain electrode and a mounting substrate gate electrode are formed on the mounting substrate 20 (mounting substrate main body 21) (see FIG. 5).
  • the bump electrode 9a, the bump electrode 9b, and the bump electrode 9c are connected to the mounting substrate ground electrode 22W.
  • FIG. 3 is a plan view schematically showing the configuration of the semiconductor device 30.
  • the source electrode 2, the drain electrode 3 (3a and 3b), the gate electrode 4 (4a and 4b), the ground electrode 11, and the like are formed in the semiconductor element 30 (semiconductor substrate 1).
  • the gate electrode 4a and the gate electrode 4b are directly connected on the surface of the semiconductor element 30 (semiconductor substrate 1).
  • the source electrode 2 is connected to the via electrode portion of the interlayer insulating film source wiring electrode 6 b.
  • the drain electrode 3a is connected to the via electrode portion of the interlayer insulating film drain wiring electrode 6a.
  • the drain electrode 3b is connected to the via electrode portion of the interlayer insulating film drain wiring electrode 6c.
  • Gate electrode 4a and gate electrode 4b are connected to a via electrode portion of interlayer insulating film gate wiring electrode 6d.
  • the source electrode 2 formed in the semiconductor element 30 has a length L1.
  • FIG. 4 is a plan view schematically showing the configuration of the interlayer insulating film surface electrode 8.
  • an interlayer insulating film surface electrode 8 (interlayer insulating film source surface electrode, interlayer insulating film drain surface electrode, interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrode) is provided on the second interlayer insulating film 7. It is formed. Interlayer insulating film ground surface layer electrode 8a and interlayer insulating film ground surface layer electrode 8c are integrated as shown in this plan view, and are set to the ground potential.
  • the interlayer insulating film source surface layer electrode 8b is completely surrounded by the interlayer insulating film ground surface layer electrodes (8a, 8c).
  • the separation groove 8d is formed between the interlayer insulating film source surface layer electrode 8b and the interlayer insulating film ground surface electrode (8a, 8c) in order to separate the source and the ground.
  • the interlayer insulating film source surface layer electrode 8 b is electrically connected to the source electrode 2 (and the source) of the semiconductor element 30.
  • the interlayer insulating film drain surface layer electrode is electrically connected to the drain electrode 3 (and the drain) of the semiconductor element 30.
  • the interlayer insulating film gate surface layer electrode is electrically connected to the gate electrode 4 (and the gate) of the semiconductor element 30.
  • Bump electrodes 9 a are formed on the interlayer insulating film ground surface electrode 8 a by, for example, a method of transferring solder.
  • Bump electrodes 9 b are formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder.
  • Bump electrodes 9 c are formed on the interlayer insulating film ground surface electrode 8 c by, for example, a method of transferring solder.
  • bump electrodes are formed on the interlayer insulating film drain surface electrode and the interlayer insulating film gate surface electrode, for example, by a method of transferring solder.
  • FIG. 5 is a plan view schematically showing a first configuration of the mounting substrate 20 according to the present embodiment.
  • a mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21).
  • the mounting substrate electrode 22 is configured of a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30.
  • the mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
  • the mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
  • FIG. 6 is a plan view schematically showing a second configuration of the mounting substrate 20 according to the present embodiment.
  • a mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21).
  • the mounting substrate electrode 22 is configured of a mounting substrate source electrode 22X, a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W.
  • the mounting substrate source electrode 22 ⁇ / b> X is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
  • the mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
  • the mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
  • the mounting substrate ground electrode 22 W is connected to the bump electrodes 9 a and 9 c and electrically connected to the ground electrode of the semiconductor element 30.
  • the mounting substrate ground electrode 22W completely surrounds the mounting substrate source electrode 22X. Although the mounting substrate source electrode 22X is set to the ground potential, it is disposed independently of the mounting substrate ground electrode 22W. In the semiconductor device 100 according to the present embodiment, the separation groove 22d is formed between the mounting substrate ground electrode 22W and the mounting substrate source electrode 22X in order to separate the source and the ground.
  • a transistor structure having a source electrode 2 (and a source), a drain electrode 3 (and a drain), and a gate electrode 4 (gate) is formed on a semiconductor substrate 1 using, for example, a deposition lift-off method.
  • the first interlayer insulating film 5 is formed using, for example, a polyimide coating / photolithography process.
  • the interlayer insulating film wiring electrode 6 is formed by using, for example, a vapor deposition lift-off method.
  • the second interlayer insulating film 7 is formed by using, for example, polyimide coating / photolithography.
  • the interlayer insulating film surface electrode 8 is formed using, for example, an electrolytic plating method.
  • the interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode 8b, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrodes 8a and 8c.
  • a portion (separation groove 8d) in which the electrode is not formed is formed using, for example, a photoengraving process so as to surround the installation location of the bump electrode 9b.
  • a bump electrode 9 b is formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder.
  • interlayer insulating film source surface layer electrode 8b is connected to source electrode 2, and a bump electrode is formed thereon.
  • a separation groove 8d in which no electrode is formed is formed so as to surround the installation location of the bump electrode.
  • the mounting substrate 20 is connected to the semiconductor chip 10 via the bump electrode 9. As a result, other circuit elements electrically connected to the source electrode 2 and the ground electrode of the semiconductor element 30 are connected by the mounting substrate 20. Therefore, as the connection distance between the source electrode 2 and the other circuit element electrically connected to the ground electrode of the semiconductor element 30 is extended, it is possible to improve the blocking property between the circuit elements, It is possible to prevent unnecessary loop oscillation between the two.
  • a source electrode, a drain electrode, and a gate electrode of a transistor are provided on a semiconductor substrate, and an interlayer insulating film wiring electrode is disposed on top of that via an interlayer insulating film, and then an electrode of the uppermost layer
  • the semiconductor device includes a semiconductor element in which a source electrode, a drain electrode, and a gate electrode are formed, and an interlayer insulating film source wiring electrode and an interlayer insulating film disposed on the semiconductor element.
  • the interlayer insulating film source wiring electrode is connected to the source electrode and the interlayer insulating film source surface electrode, and the interlayer insulating film source surface electrode is surrounded
  • a semiconductor device 100 includes a semiconductor chip 10, bump electrodes 9, a mounting substrate 20 and the like (see FIG. 1).
  • the semiconductor chip 10 includes a semiconductor element 30, a first interlayer insulating film 5, an interlayer insulating film wiring electrode 6, a second interlayer insulating film 7, an interlayer insulating film surface electrode 8, and the like.
  • the mounting substrate 20 includes a mounting substrate body 21, a mounting substrate electrode 22, and the like.
  • the semiconductor device 100 operates with the source of the semiconductor element 30 at the ground potential.
  • the mounting substrate electrode 22 includes the mounting substrate drain electrode, the mounting substrate gate electrode, and the mounting substrate ground electrode.
  • FIG. 7 is a cross sectional view schematically showing a configuration of a semiconductor device 100 having a chip size package structure according to the present embodiment.
  • a semiconductor element 30 such as an FET (Field Effect Transistor) is formed on the semiconductor substrate 1.
  • the semiconductor element 30 is configured of a semiconductor substrate 1, source electrode 2, drain electrode 3 (3a, 3b), gate electrode 4 (4a, 4b), and the like.
  • a first interlayer insulating film 5 is disposed on the semiconductor element 30 (semiconductor substrate 1).
  • a second interlayer insulating film 7 is disposed on the first interlayer insulating film 5.
  • the interlayer insulating film source surface layer electrode 8 b is disposed directly on the interlayer insulating film source wiring electrode 6 b and the source electrode 2.
  • a separation groove 8d is formed between the interlayer insulating film ground surface electrode 8a and the interlayer insulating film source surface electrode 8b, and between the interlayer insulating film ground surface electrode 8c and the interlayer insulating film source surface electrode 8b.
  • the mounting substrate electrode 22 has a pattern electrode portion and a via electrode portion.
  • a mounting substrate source electrode 22X and a mounting substrate ground electrode 22W are displayed as the mounting substrate electrode 22 formed on the mounting substrate 20 (mounting substrate main body 21).
  • a mounting substrate drain electrode and a mounting substrate gate electrode are formed on the mounting substrate 20 (mounting substrate main body 21) (see FIG. 8).
  • the bump electrode 9a and the bump electrode 9c are connected to the mounting substrate ground electrode 22W.
  • the bump electrode 9b is connected to the mounting substrate source electrode 22X.
  • a separation groove 22 d is formed between the mounting substrate source electrode 22 X and the mounting substrate ground electrode 22.
  • FIG. 8 is a plan view schematically showing the configuration of interlayer insulating film surface electrode 8 according to the present embodiment.
  • an interlayer insulating film surface electrode 8 (interlayer insulating film source surface electrode, interlayer insulating film drain surface electrode, interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrode) is provided on the second interlayer insulating film 7. It is formed. Interlayer insulating film ground surface layer electrode 8a and interlayer insulating film ground surface layer electrode 8c are integrated as shown in this plan view, and are set to the ground potential.
  • the interlayer insulating film source surface layer electrode 8b is completely surrounded by the interlayer insulating film ground surface layer electrodes 8a and 8c.
  • the separation groove 8d is formed between the interlayer insulating film source surface layer electrode 8b and the interlayer insulating film ground surface electrode (8a, 8c) in order to separate the source and the ground.
  • the interlayer insulating film source surface layer electrode 8 b is electrically connected to the source electrode 2 (and the source) of the semiconductor element 30.
  • the interlayer insulating film drain surface layer electrode is electrically connected to the drain electrode 3 (and the drain) of the semiconductor element 30.
  • the interlayer insulating film gate surface layer electrode is electrically connected to the gate electrode 4 (and the gate) of the semiconductor element 30.
  • Bump electrodes 9 a are formed on the interlayer insulating film ground surface electrode 8 a by, for example, a method of transferring solder.
  • Bump electrodes 9 b are formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder.
  • Bump electrodes 9 c are formed on the interlayer insulating film ground surface electrode 8 c by, for example, a method of transferring solder.
  • bump electrodes are formed on the interlayer insulating film drain surface electrode and the interlayer insulating film gate surface electrode, for example, by a method of transferring solder.
  • the bump electrode 9 b is disposed in the middle of the interlayer insulating film source surface electrode 8 b.
  • FIG. 9 is a plan view schematically showing a first configuration of the mounting substrate 20 according to the present embodiment.
  • a mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21).
  • the mounting substrate electrode 22 is configured of a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30.
  • the mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
  • the mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
  • the bump electrode 9b is disposed in the center of the mounting substrate ground electrode 22W.
  • FIG. 10 is a plan view schematically showing a second configuration of the mounting substrate 20 according to the present embodiment.
  • a mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21).
  • the mounting substrate electrode 22 is configured of a mounting substrate source electrode 22X, a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W.
  • the mounting substrate source electrode 22 ⁇ / b> X is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
  • the mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
  • the mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
  • the mounting substrate ground electrode 22 W is connected to the bump electrodes 9 a and 9 c and electrically connected to the ground electrode of the semiconductor element 30.
  • the mounting substrate ground electrode 22W completely surrounds the mounting substrate source electrode 22X. Although the mounting substrate source electrode 22X is set to the ground potential, it is disposed independently of the mounting substrate ground electrode 22W.
  • the separation groove 22d is formed between the mounting substrate ground electrode 22W and the mounting substrate source electrode 22X in order to separate the source and the ground.
  • the bump electrode 9b is disposed in the center of the mounting substrate source electrode 22X.
  • a method of manufacturing the semiconductor device 100 compatible with the chip size package according to the present embodiment will be described.
  • a transistor structure having a source electrode 2 (and a source), a drain electrode 3 (and a drain), and a gate electrode 4 (gate) is formed on a semiconductor substrate 1 using, for example, a deposition lift-off method.
  • the first interlayer insulating film 5 is formed using, for example, a polyimide coating / photolithography process.
  • the interlayer insulating film wiring electrode 6 is formed by using, for example, a vapor deposition lift-off method.
  • an interlayer insulating film source wiring electrode 6 b connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8 b is formed directly on the source electrode 2.
  • the second interlayer insulating film 7 is formed by using, for example, polyimide coating / photolithography.
  • the interlayer insulating film surface electrode 8 is formed using, for example, an electrolytic plating method.
  • the interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode 8b, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrodes 8a and 8c.
  • a portion (separation groove 8d) in which the electrode is not formed is formed using, for example, a photoengraving process so as to surround the installation location of the bump electrode 9b.
  • a bump electrode 9 b is formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder.
  • interlayer insulating film source surface layer electrode 8b is connected to source electrode 2, and a bump electrode is formed thereon.
  • a separation groove in which no electrode material exists is formed so as to surround the installation location of the bump electrode.
  • the source electrode 2 can be electrically separated from other circuit elements on the semiconductor device.
  • the interlayer insulating film source wiring electrode 6b connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8b is disposed immediately above the source electrode 2, whereby the shortest distance between the source electrode 2 and the interlayer insulating film source surface layer electrode 8b You can connect with.
  • the mounting substrate 20 is connected to the semiconductor chip 10 via the bump electrode 9.
  • other circuit elements electrically connected to the source electrode 2 and the ground electrode of the semiconductor element 30 are connected by the mounting substrate. Therefore, as the connection distance between the source electrode 2 and the other circuit element electrically connected to the ground electrode of the semiconductor element 30 is extended, it is possible to improve the blocking property between the circuit elements, It is possible to prevent unnecessary loop oscillation between the two. Furthermore, by connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8b at the shortest distance, the parasitic resistance component and the parasitic inductance component can be reduced, and the deterioration of the transistor characteristics can be suppressed.
  • the semiconductor device according to the present embodiment is the semiconductor device described in the first embodiment, and is characterized in that the source electrode and the interlayer insulating film source surface layer electrode are connected directly above the source electrode. It is. That is, the semiconductor device is characterized in that the interlayer insulating film source surface layer electrode is disposed immediately above the source electrode.
  • a semiconductor device 100 according to the present embodiment includes a semiconductor chip 10, bump electrodes 9, a mounting substrate 20 and the like (see FIG. 1).
  • the semiconductor chip 10 includes a semiconductor element 30, a first interlayer insulating film 5, an interlayer insulating film wiring electrode 6, a second interlayer insulating film 7, an interlayer insulating film surface electrode 8, and the like.
  • a source electrode, a drain electrode, a gate electrode, a ground electrode, and the like are formed.
  • the mounting substrate 20 includes a mounting substrate body 21, a mounting substrate electrode 22, and the like.
  • FIG. 11 is a cross sectional view schematically showing a configuration of a semiconductor device 100 having a chip size package structure according to the present embodiment.
  • a semiconductor element 30 such as an FET (Field Effect Transistor) is formed on the semiconductor substrate 1.
  • the semiconductor element 30 is configured of a semiconductor substrate 1, source electrode 2, drain electrode 3 (3a, 3b), gate electrode 4 (4a, 4b), and the like.
  • a first interlayer insulating film 5 is disposed on the semiconductor element 30 (semiconductor substrate 1).
  • a second interlayer insulating film 7 is disposed on the first interlayer insulating film 5.
  • a separation groove 8d is formed between the interlayer insulating film ground surface electrode 8a and the interlayer insulating film source surface electrode 8b, and between the interlayer insulating film ground surface electrode 8c and the interlayer insulating film source surface electrode 8b.
  • FIG. 12 is a plan view schematically showing the configuration of interlayer insulating film surface electrode 8.
  • an interlayer insulating film surface electrode 8 (interlayer insulating film source surface electrode, interlayer insulating film drain surface electrode, interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrode) is provided. It is formed.
  • Interlayer insulating film ground surface layer electrode 8a and interlayer insulating film ground surface layer electrode 8c are integrated as shown in this plan view, and are set to the ground potential.
  • the interlayer insulating film source surface layer electrode 8b is completely surrounded by the interlayer insulating film ground surface layer electrodes (8a, 8c).
  • the separation groove 8d is formed between the interlayer insulating film source surface layer electrode 8b and the interlayer insulating film ground surface electrode (8a, 8c) in order to separate the source and the ground.
  • Two separation grooves 8d related to the present embodiment, which have a linear shape, are arranged.
  • the length L 2 of the separation groove 8 d having a linear shape is larger than the length L 1 of the source electrode formed in the semiconductor element 30.
  • the interlayer insulating film source surface layer electrode 8 b is electrically connected to the source electrode 2 (and the source) of the semiconductor element 30.
  • the interlayer insulating film drain surface layer electrode is electrically connected to the drain electrode 3 (and the drain) of the semiconductor element 30.
  • the interlayer insulating film gate surface layer electrode is electrically connected to the gate electrode 4 (and the gate) of the semiconductor element 30.
  • Bump electrodes 9 a are formed on the interlayer insulating film ground surface electrode 8 a by, for example, a method of transferring solder.
  • Bump electrodes 9 b are formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder.
  • Bump electrodes 9 c are formed on the interlayer insulating film ground surface electrode 8 c by, for example, a method of transferring solder.
  • bump electrodes are formed on the interlayer insulating film drain surface electrode and the interlayer insulating film gate surface electrode, for example, by a method of transferring solder.
  • FIG. 13 is a plan view schematically showing a first configuration of the mounting substrate 20 according to the present embodiment.
  • a mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21).
  • the mounting substrate electrode 22 is configured of a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30.
  • the mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
  • the mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
  • FIG. 14 is a plan view schematically showing a second configuration of the mounting substrate 20 according to the present embodiment.
  • a mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21).
  • the mounting substrate electrode 22 is configured of a mounting substrate source electrode 22X, a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W.
  • the mounting substrate source electrode 22 ⁇ / b> X is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
  • the mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
  • the mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30.
  • the mounting substrate ground electrode 22W completely surrounds the mounting substrate source electrode 22X. Although the mounting substrate source electrode 22X is set to the ground potential, it is disposed independently of the mounting substrate ground electrode 22W. In the present embodiment, in order to separate the source and the ground, a separation groove 22d having a linear shape is formed between the mounting substrate ground electrode 22W and the mounting substrate source electrode 22X. The length L 3 of the separation groove 22 d having a linear shape is larger than the length L 1 of the source electrode formed in the semiconductor element 30.
  • a transistor structure having a source electrode 2 (and a source), a drain electrode 3 (and a drain), and a gate electrode 4 (gate) is formed on a semiconductor substrate 1 using, for example, a deposition lift-off method.
  • the first interlayer insulating film 5 is formed using, for example, a polyimide coating / photolithography process.
  • the interlayer insulating film wiring electrode 6 is formed by using, for example, a vapor deposition lift-off method.
  • the second interlayer insulating film 7 is formed by using, for example, polyimide coating / photolithography.
  • the interlayer insulating film surface electrode 8 is formed using, for example, an electrolytic plating method.
  • the interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode 8b, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrodes 8a and 8c.
  • the separation groove 8d is formed in the interlayer insulating film source surface layer electrode 8b, for example, using a photolithography process, with the installation location of the bump electrode 9b interposed therebetween.
  • the interlayer insulating film ground surface layer electrode 8a is connected to the circuit element of the ground potential other than the interlayer insulating film source surface layer electrode 8b.
  • Bump electrode 9b is formed on interlayer insulating film source surface layer electrode 8b.
  • Bump electrode 9a and bump electrode 9c are formed on interlayer insulating film ground surface electrode 8a.
  • a first separation groove 8d in which the interlayer insulating film surface layer electrode does not exist is formed between the installation site of the bump electrode 9b and the installation site of the bump electrode 9a.
  • a second separation groove 8d in which the interlayer insulating film surface layer electrode 8 does not exist is formed between the installation site of the bump electrode 9b and the installation site of the bump electrode 9c.
  • the separation groove 8d has a length L2 greater than at least the length L1 of the source electrode 2.
  • a bump electrode 9 is formed on the upper surface of the interlayer insulating film surface electrode 8 by, for example, a method of transferring solder.
  • the interlayer insulating film source surface layer electrode is connected to the source electrode 2, and the bump electrode is formed thereon.
  • the separation groove 8d in the interlayer insulating film surface electrode 8 the connection distance between the interlayer insulating film source surface electrode and other circuit elements of the ground potential can be increased.
  • the connection distance between the source electrode 2 and the other circuit element electrically connected to the ground electrode of the semiconductor element 30 is extended, it is possible to improve the blocking property between the circuit elements, and between the circuit elements Unnecessary loop oscillation can be prevented.
  • the semiconductor device includes a source electrode, a drain electrode, and a gate electrode of a transistor on a semiconductor substrate, and an interlayer insulating film wiring electrode is disposed thereon via an interlayer insulating film, and then the uppermost layer is formed.
  • the semiconductor device is characterized by having a structure in which the interlayer insulating film surface layer electrode is removed in a linear manner.
  • a semiconductor device 100 according to the present embodiment includes a semiconductor chip 10, bump electrodes 9, a mounting substrate 20 and the like (see FIG. 1).
  • the semiconductor chip 10 includes a semiconductor element 30, a first interlayer insulating film 5, an interlayer insulating film wiring electrode 6, a second interlayer insulating film 7, an interlayer insulating film surface electrode 8, and the like.
  • the mounting substrate 20 includes a mounting substrate body 21, a mounting substrate electrode 22, and the like.
  • the mounting substrate electrode 22 includes the mounting substrate drain electrode, the mounting substrate gate electrode, and the mounting substrate ground electrode.
  • FIG. 15 is a cross sectional view schematically showing a configuration of a semiconductor device 100 compatible with a chip size package according to the present embodiment.
  • a semiconductor element 30 such as an FET (Field Effect Transistor) is formed on the semiconductor substrate 1.
  • the semiconductor element 30 is configured of a semiconductor substrate 1, source electrode 2, drain electrode 3 (3a, 3b), gate electrode 4 (4a, 4b), and the like.
  • a first interlayer insulating film 5 is disposed on the semiconductor element 30 (semiconductor substrate 1).
  • a second interlayer insulating film 7 is disposed on the first interlayer insulating film 5.
  • the interlayer insulating film source surface layer electrode 8 b is disposed directly on the interlayer insulating film source wiring electrode 6 b and the source electrode 2.
  • a separation groove 8d is formed between the interlayer insulating film ground surface electrode 8a and the interlayer insulating film source surface electrode 8b, and between the interlayer insulating film ground surface electrode 8c and the interlayer insulating film source surface electrode 8b.
  • a separation groove 22d is formed between the mounting substrate source electrode 22X and the mounting substrate ground electrode 22W.
  • FIG. 16 is a plan view schematically showing the configuration of the interlayer insulating film surface electrode 8 according to the present embodiment.
  • an interlayer insulating film surface electrode 8 (interlayer insulating film source surface electrode, interlayer insulating film drain surface electrode, interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrode) is provided on the second interlayer insulating film 7. It is formed. Interlayer insulating film ground surface layer electrode 8a and interlayer insulating film ground surface layer electrode 8c are integrated as shown in this plan view, and are set to the ground potential.
  • the interlayer insulating film source surface layer electrode 8b is completely surrounded by the interlayer insulating film ground surface layer electrodes (8a, 8c).
  • the separation groove 8d is formed between the interlayer insulating film source surface layer electrode 8b and the interlayer insulating film ground surface electrode (8a, 8c) in order to separate the source and the ground.
  • Two separation grooves 8d related to the present embodiment, which have a linear shape, are arranged.
  • the length L 2 of the separation groove 8 d having a linear shape is larger than the length L 1 of the source electrode formed in the semiconductor element 30.
  • the interlayer insulating film source surface layer electrode 8 b is electrically connected to the source electrode 2 (and the source) of the semiconductor element 30.
  • the interlayer insulating film drain surface layer electrode is electrically connected to the drain electrode 3 (and the drain) of the semiconductor element 30.
  • the interlayer insulating film gate surface layer electrode is electrically connected to the gate electrode 4 (and the gate) of the semiconductor element 30.
  • Bump electrodes 9 a are formed on the interlayer insulating film ground surface electrode 8 a by, for example, a method of transferring solder.
  • Bump electrodes 9 b are formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder.
  • Bump electrodes 9 c are formed on the interlayer insulating film ground surface electrode 8 c by, for example, a method of transferring solder.
  • bump electrodes are formed on the interlayer insulating film drain surface electrode and the interlayer insulating film gate surface electrode, for example, by a method of transferring solder.
  • FIG. 17 is a plan view schematically showing a first configuration of the mounting substrate 20 according to the present embodiment.
  • a mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21).
  • the mounting substrate electrode 22 is configured of a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30.
  • the mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
  • the mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
  • the bump electrode 9b is disposed in the center of the mounting substrate ground electrode 22W.
  • FIG. 18 is a plan view schematically showing a second configuration of the mounting substrate 20 according to the present embodiment.
  • a mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21).
  • the mounting substrate electrode 22 is configured of a mounting substrate source electrode 22X, a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W.
  • the mounting substrate source electrode 22 ⁇ / b> X is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
  • the mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
  • the mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
  • the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30.
  • the mounting substrate ground electrode 22W completely surrounds the mounting substrate source electrode 22X. Although the mounting substrate source electrode 22X is set to the ground potential, it is disposed independently of the mounting substrate ground electrode 22W.
  • a separation groove 22d having a linear shape is formed between the mounting substrate ground electrode 22W and the mounting substrate source electrode 22X.
  • the length L 3 of the separation groove 22 d having a linear shape is larger than the length L 1 of the source electrode formed in the semiconductor element 30.
  • the bump electrode 9b is disposed in the center of the mounting substrate source electrode 22X.
  • a method of manufacturing the semiconductor device 100 compatible with the chip size package according to the present embodiment will be described.
  • a transistor structure having a source electrode 2 (and a source), a drain electrode 3 (and a drain), and a gate electrode 4 (gate) is formed on a semiconductor substrate 1 using, for example, a deposition lift-off method.
  • the first interlayer insulating film 5 is formed using, for example, a polyimide coating / photolithography process.
  • the interlayer insulating film wiring electrode 6 is formed by using, for example, a vapor deposition lift-off method.
  • an interlayer insulating film source wiring electrode 6 b connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8 b is formed directly on the source electrode 2.
  • the second interlayer insulating film 7 is formed by using, for example, polyimide coating / photolithography.
  • the interlayer insulating film surface electrode 8 is formed using, for example, an electrolytic plating method.
  • the interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode 8b, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrodes 8a and 8c.
  • the separation groove 8d is formed in the interlayer insulating film source surface layer electrode 8b, for example, using a photolithography process, with the installation location of the bump electrode 9b interposed therebetween.
  • the interlayer insulating film ground surface layer electrode 8a is connected to the circuit element of the ground potential other than the interlayer insulating film source surface layer electrode 8b.
  • Bump electrode 9b is formed on interlayer insulating film source surface layer electrode 8b.
  • Bump electrode 9a and bump electrode 9c are formed on interlayer insulating film ground surface electrode 8a.
  • a first separation groove 8d in which the interlayer insulating film surface layer electrode does not exist is formed between the installation site of the bump electrode 9b and the installation site of the bump electrode 9a.
  • a second separation groove 8d in which the interlayer insulating film surface layer electrode 8 does not exist is formed between the installation site of the bump electrode 9b and the installation site of the bump electrode 9c.
  • the separation groove 8d has a length L2 greater than at least the length L1 of the source electrode 2.
  • a bump electrode 9 is formed on the upper surface of the interlayer insulating film surface electrode 8 by, for example, a method of transferring solder.
  • interlayer insulating film source surface layer electrode 8b is connected to source electrode 2, and bump electrode 9b is formed thereon.
  • a separation groove 8d in which no electrode material exists is formed in the interlayer insulating film surface layer electrode 8.
  • the source electrode 2 can be electrically separated from other circuit elements on the semiconductor device.
  • the interlayer insulating film source wiring electrode 6b connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8b is disposed immediately above the source electrode 2, whereby the shortest distance between the source electrode 2 and the interlayer insulating film source surface layer electrode 8b You can connect with.
  • connection distance between the interlayer insulating film source surface layer electrode 8 b and the circuit element of the other ground potential can be increased.
  • the connection distance between the source electrode 2 and the other circuit element electrically connected to the ground electrode of the semiconductor element 30 is extended, it is possible to improve the blocking property between the circuit elements, and between the circuit elements Unnecessary loop oscillation can be prevented.
  • the parasitic resistance component and the parasitic inductance component can be reduced, and the deterioration of the transistor characteristics can be suppressed.
  • the semiconductor device according to the present embodiment is the semiconductor device described in the third embodiment, and is characterized in that the source electrode and the interlayer insulating film source surface layer electrode are connected immediately above the source electrode. It is. That is, the semiconductor device is characterized in that the interlayer insulating film source surface layer electrode is disposed immediately above the source electrode.
  • the method used for forming the source electrode 2, drain electrode 3, gate electrode 4, interlayer insulating film wiring electrode 6, and interlayer insulating film surface electrode 8 has a similar shape. If it is possible, other methods may be used. In addition, if materials and manufacturing methods used for first interlayer insulating film 5 and second interlayer insulating film 7 can form the same structure, other materials (combined use is also possible) and manufacturing methods are used. I don't care. Further, a combination of a plurality of interlayer insulating film wiring electrodes and an interlayer insulating film may be inserted between the second interlayer insulating film 7 and the interlayer insulating film surface electrode 8.
  • the feature of the present invention is that the ground electrode connected to the source electrode of the semiconductor element such as FET is made independent from the surrounding ground electrode, thereby reducing the effect of the source electrodes connected to the ground electrode being influenced each other. It is possible to obtain an FET structure compatible with a chip size package which is hard to oscillate.
  • the semiconductor device includes an FET structure in which a source, a drain, and a gate electrode are provided on a semiconductor substrate, a ground electrode provided with the FET structure and an insulating layer interposed therebetween, and a mounting substrate on the ground electrode. And a ball grid array electrode for connection to the semiconductor device, and the source electrode of the FET structure is connected to a ground electrode independent of the surroundings.
  • the semiconductor device according to the present embodiment is the semiconductor device described in the third embodiment, and is characterized in that the source electrode and the interlayer insulating film source surface layer electrode are connected directly above the source electrode. It is.
  • the embodiments can be freely combined, and the embodiments can be appropriately modified or omitted.

Abstract

A semiconductor device (100) comprising a semiconductor element (30), a first inter-layer insulation film (5) disposed above the semiconductor element, a second inter-layer insulation film (7) disposed above the first inter-layer insulation film, a first bump electrode (9b) disposed above an inter-layer insulation film source surface layer electrode formed in the second inter-layer insulation film, a second bump electrode (9a) disposed above an inter-layer insulation film ground surface layer electrode formed in the second inter-layer insulation film, and a mounting substrate (20) connected to the first bump electrode and the second bump electrode, wherein the inter-layer insulation film source wiring electrode is linked to the source electrode and to the inter-layer insulation film source surface layer electrode, the inter-layer insulation film source surface layer electrode is surrounded by the inter-layer insulation film ground surface layer electrode, and a separation groove is formed between the inter-layer insulation film source surface layer electrode and the inter-layer insulation film ground surface layer electrode.

Description

半導体装置Semiconductor device
　この発明は、半導体装置に関わり、特に、半導体素子と実装基板とバンプ電極を備えている半導体装置に関するものである。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a semiconductor element, a mounting substrate, and a bump electrode.
　携帯電話、モバイルコンピュータ、パーソナル携帯情報機器、デジタルスチルカメラなどに代表されるエレクトニクス製品は、小型化、軽量化、および、高機能化、が飛躍的に進んでいる。これらの市場動向に伴い、エレクトロニクス製品に搭載される半導体パッケージについても、小型化、薄肉化、軽量化、及び、実装基板への高密度実装化、が強く要求されてきている。 Electronic products typified by mobile phones, mobile computers, personal digital assistants, digital still cameras, etc. are rapidly advancing in size reduction, weight reduction, and functional enhancement. With these market trends, there is also a strong demand for smaller size, thinner thickness, lighter weight, and high density mounting on a mounting substrate also for semiconductor packages mounted in electronic products.
　集積回路のパッケージのうち、チップ単体と同程度のサイズで実現された超小型のパッケージは、チップサイズパッケージと呼ばれている。チップサイズパッケージ構造を有する半導体装置は、ソース電極、ドレイン電極、および、ゲート電極を有する半導体チップを備えている。半導体チップは、実装基板とバンプ電極で接続されている。半導体チップのゲート電極の上には、第１の層間絶縁膜および第２の層間絶縁膜を形成している。 Among the packages of integrated circuits, ultra-small packages realized in the same size as a single chip are called chip-size packages. A semiconductor device having a chip size package structure includes a semiconductor chip having a source electrode, a drain electrode, and a gate electrode. The semiconductor chip is connected to the mounting substrate by a bump electrode. A first interlayer insulating film and a second interlayer insulating film are formed on the gate electrode of the semiconductor chip.
　第１の層間絶縁膜には、層間絶縁膜配線電極を配置している。最上層の第２の層間絶縁膜には、層間絶縁膜配線電極と接続されている層間絶縁膜表層電極を配置している。その層間絶縁膜表層電極の上に、表面実装用のバンプ電極を配置している。チップサイズパッケージ構造を有する半導体装置は、半導体チップの最表面（または最上層）に、接続電極（または層間絶縁膜表層電極）が、配置されている。 An interlayer insulating film wiring electrode is disposed in the first interlayer insulating film. An interlayer insulating film surface electrode connected to the interlayer insulating film wiring electrode is disposed in the uppermost second interlayer insulating film. A bump electrode for surface mounting is disposed on the interlayer insulating film surface layer electrode. In a semiconductor device having a chip size package structure, a connection electrode (or an interlayer insulating film surface electrode) is disposed on the outermost surface (or the uppermost layer) of the semiconductor chip.
　接続電極には、配線基板（または実装基板）との接続に用いる半田バンプ（バンプ電極）が形成されている。この半田バンプを用いて、半導体チップと実装基板が接続される。トランジスタのソース電極は、半導体装置の接続電極へ、グランド電極に接続する他の電極との接続点を電気的に分離することなく接続する構成にしている（例えば、特許文献１を参照）。 On the connection electrodes, solder bumps (bump electrodes) used for connection with the wiring substrate (or mounting substrate) are formed. The semiconductor chip and the mounting substrate are connected using the solder bumps. The source electrode of the transistor is connected to the connection electrode of the semiconductor device without electrically separating a connection point with another electrode connected to the ground electrode (see, for example, Patent Document 1).
　チップサイズパッケージ構造に対応したFET（ Field Effect Transistor ）では、最表面にグランド電極を配置している。このチップサイズパッケージ対応のFETでは、トランジスタのソース電極を、共通のグランド電極に接続している。このため、各ソース電極の間で、相互に影響を受け易く、回路素子は発振が生じやすい。 In the FET (field effect transistor) corresponding to the chip size package structure, the ground electrode is disposed on the outermost surface. In the FET for the chip size package, the source electrodes of the transistors are connected to the common ground electrode. For this reason, the respective source electrodes are susceptible to each other, and the circuit element tends to oscillate.
特開２００２－１１０９８８号公報Japanese Patent Application Laid-Open No. 2002-110988
　上述したように、チップサイズパッケージ構造を有する半導体装置は、ソース電極がグランド電極に接続する他の回路素子と半導体装置の最表面の接続電極（または層間絶縁膜表層電極）にて電気的に接続されている。このため、回路素子の間の遮断性が不十分となって、不要なループ発振を生じることがあった。また、ソース電極と半導体装置の最表面の接続電極との間の接続が、最短距離であるソース電極の直上で為されない場合には、トランジスタ特性の低下を招くことがあった。 As described above, the semiconductor device having the chip size package structure is electrically connected to the other circuit element whose source electrode is connected to the ground electrode and the connection electrode (or the interlayer insulating film surface electrode) on the outermost surface of the semiconductor device. It is done. For this reason, the interruption | blocking property between circuit elements became inadequate and the unnecessary loop oscillation might be produced. In addition, when the connection between the source electrode and the connection electrode on the outermost surface of the semiconductor device is not made immediately above the source electrode which is the shortest distance, the transistor characteristics may be degraded.
　この発明は、チップサイズパッケージ構造を有する半導体装置における上記のような課題を解消するためになされたものである。すなわち、ソース電極に接続されたバンプ電極を他のバンプ電極と電気的に独立させることにより、回路素子の間の遮断性を高める事が出来る半導体装置を得る事を目的とする。 The present invention has been made to solve the above-mentioned problems in a semiconductor device having a chip size package structure. That is, it is an object of the present invention to obtain a semiconductor device capable of enhancing the barrier property between circuit elements by electrically making the bump electrode connected to the source electrode independent from other bump electrodes.
　本発明に関わる半導体装置は、ソース電極、ドレイン電極、および、ゲート電極が形成されている半導体素子と、前記半導体素子の上に配置され、層間絶縁膜ソース配線電極、層間絶縁膜ドレイン配線電極および層間絶縁膜ゲート配線電極が形成されている第１の層間絶縁膜と、前記第１の層間絶縁膜の上に配置され、層間絶縁膜ソース表層電極および層間絶縁膜グランド表層電極が形成されている第２の層間絶縁膜と、前記第２の層間絶縁膜に形成されている層間絶縁膜ソース表層電極の上に配置された第１のバンプ電極と、前記第２の層間絶縁膜に形成されている層間絶縁膜グランド表層電極の上に配置された第２のバンプ電極と、前記第１のバンプ電極および前記第２のバンプ電極と接続されている実装基板と、を備え、前記層間絶縁膜ソース配線電極は、前記ソース電極および前記層間絶縁膜ソース表層電極と繋がっており、しかも、前記層間絶縁膜ソース表層電極は、前記層間絶縁膜グランド表層電極によって囲まれていて、前記層間絶縁膜ソース表層電極と前記層間絶縁膜グランド表層電極の間には、分離溝が形成されていることを特徴とするものである。 A semiconductor device according to the present invention includes a semiconductor element in which a source electrode, a drain electrode, and a gate electrode are formed, an interlayer insulating film source wiring electrode, an interlayer insulating film drain wiring electrode, and A first interlayer insulating film in which an interlayer insulating film gate wiring electrode is formed, and an interlayer insulating film source surface electrode and an interlayer insulating film ground surface electrode are disposed on the first interlayer insulating film. A second interlayer insulating film, a first bump electrode disposed on an interlayer insulating film source surface layer electrode formed on the second interlayer insulating film, and the second interlayer insulating film A second bump electrode disposed on an interlayer insulating film ground surface layer electrode, and a mounting substrate connected to the first bump electrode and the second bump electrode; The film source wiring electrode is connected to the source electrode and the interlayer insulating film source surface electrode, and the interlayer insulating film source surface electrode is surrounded by the interlayer insulating film ground surface electrode, and the interlayer insulating film A separation groove is formed between the source surface electrode and the interlayer insulating film ground surface electrode.
　本発明に関わる半導体装置は、ソース電極、ドレイン電極、および、ゲート電極が形成されている半導体素子と、前記半導体素子の上に配置され、層間絶縁膜ソース配線電極、層間絶縁膜ドレイン配線電極および層間絶縁膜ゲート配線電極が形成されている第１の層間絶縁膜と、前記第１の層間絶縁膜の上に配置され、層間絶縁膜ソース表層電極および層間絶縁膜グランド表層電極が形成されている第２の層間絶縁膜と、前記第２の層間絶縁膜に形成されている層間絶縁膜ソース表層電極の上に配置された第１のバンプ電極と、前記第２の層間絶縁膜に形成されている層間絶縁膜グランド表層電極の上に配置された第２のバンプ電極と、前記第１のバンプ電極および前記第２のバンプ電極と接続されている実装基板と、を備え、前記層間絶縁膜ソース配線電極は、前記ソース電極および前記層間絶縁膜ソース表層電極と繋がっており、しかも、前記層間絶縁膜ソース表層電極は、前記層間絶縁膜グランド表層電極によって囲まれていて、前記層間絶縁膜ソース表層電極と前記層間絶縁膜グランド表層電極の間には、分離溝が形成されていることを特徴とすることにより、回路素子の間の遮断性を高める事が出来る。 A semiconductor device according to the present invention includes a semiconductor element in which a source electrode, a drain electrode, and a gate electrode are formed, an interlayer insulating film source wiring electrode, an interlayer insulating film drain wiring electrode, and A first interlayer insulating film in which an interlayer insulating film gate wiring electrode is formed, and an interlayer insulating film source surface electrode and an interlayer insulating film ground surface electrode are disposed on the first interlayer insulating film. A second interlayer insulating film, a first bump electrode disposed on an interlayer insulating film source surface layer electrode formed on the second interlayer insulating film, and the second interlayer insulating film A second bump electrode disposed on an interlayer insulating film ground surface layer electrode, and a mounting substrate connected to the first bump electrode and the second bump electrode; The film source wiring electrode is connected to the source electrode and the interlayer insulating film source surface electrode, and the interlayer insulating film source surface electrode is surrounded by the interlayer insulating film ground surface electrode, and the interlayer insulating film A separation groove is formed between the source surface layer electrode and the interlayer insulating film ground surface layer electrode, so that the blocking property between the circuit elements can be enhanced.
本発明の実施の形態に関わる、半導体装置の全体構成を示している断面模式図である。FIG. 1 is a schematic cross sectional view showing an entire configuration of a semiconductor device according to an embodiment of the present invention. 本発明の実施の形態１に関わる、半導体装置の構成を示している断面図である。FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態に関わる、回路素子（ソース電極、ドレイン電極、および、ゲート電極）の配置を示している平面図である。It is a top view showing arrangement of circuit elements (a source electrode, a drain electrode, and a gate electrode) in connection with an embodiment of the present invention. 本発明の実施の形態１に関わる、層間絶縁膜表層電極の構成を示している平面図である。It is a top view which shows the structure of the interlayer insulation film surface layer electrode in connection with Embodiment 1 of this invention. 本発明の実施の形態１に関わる、実装基板電極の第１の構成を示している平面図である。It is a top view which shows the 1st structure of the mounting substrate electrode in connection with Embodiment 1 of this invention. 本発明の実施の形態１に関わる、実装基板電極の第２の構成を示している平面図である。It is a top view which shows the 2nd structure of the mounting substrate electrode in connection with Embodiment 1 of this invention. 本発明の実施の形態２に関わる、半導体装置の構成を示している断面模式図である。It is a cross-sectional schematic diagram which shows the structure of the semiconductor device in connection with Embodiment 2 of this invention. 本発明の実施の形態２に関わる、層間絶縁膜表層電極の構成を示している平面図である。It is a top view which shows the structure of the interlayer insulation film surface layer electrode in connection with Embodiment 2 of this invention. 本発明の実施の形態２に関わる、実装基板電極の第１の構成を示している平面図である。It is a top view which shows the 1st structure of the mounting substrate electrode in connection with Embodiment 2 of this invention. 本発明の実施の形態２に関わる、実装基板電極の第２の構成を示している平面図である。It is a top view which shows the 2nd structure of the mounted substrate electrode in connection with Embodiment 2 of this invention. 本発明の実施の形態３に関わる、半導体装置の構成を示している断面模式図である。It is a cross-sectional schematic diagram which shows the structure of the semiconductor device in connection with Embodiment 3 of this invention. 本発明の実施の形態３に関わる、層間絶縁膜表層電極の構成を示している平面図である。FIG. 21 is a plan view showing a configuration of an interlayer insulating film surface layer electrode according to a third embodiment of the present invention. 本発明の実施の形態３に関わる、実装基板電極の第１の構成を示している平面図である。It is a top view which shows the 1st structure of the mounting substrate electrode in connection with Embodiment 3 of this invention. 本発明の実施の形態３に関わる、実装基板電極の第２の構成を示している平面図である。It is a top view which shows the 2nd structure of the mounting substrate electrode in connection with Embodiment 3 of this invention. 本発明の実施の形態４に関わる、半導体装置の構成を示している断面模式図である。It is a cross-sectional schematic diagram which shows the structure of the semiconductor device in connection with Embodiment 4 of this invention. 本発明の実施の形態４に関わる、層間絶縁膜表層電極の構成を示している平面図である。FIG. 21 is a plan view showing a configuration of an interlayer insulating film surface layer electrode according to a fourth embodiment of the present invention. 本発明の実施の形態４に関わる、実装基板電極の第１の構成を示している平面図である。It is a top view which shows the 1st structure of the mounting substrate electrode in connection with Embodiment 4 of this invention. 本発明の実施の形態４に関わる、実装基板電極の第２の構成を示している平面図である。It is a top view which shows the 2nd structure of the mounted substrate electrode in connection with Embodiment 4 of this invention.
　本発明の実施の形態に関わる半導体装置について、図を参照しながら以下に説明する。なお、各図において、同一または同様の構成部分については同じ符号を付しており、対応する各構成部のサイズや縮尺はそれぞれ独立している。例えば、構成の一部を変更した断面図の間で、変更されていない同一構成部分を図示する際に、同一構成部分のサイズや縮尺が異なっている場合もある。また、半導体装置は、実際にはさらに複数の部材を備えているが、説明を簡単にするため、説明に必要な部分のみを記載し、他の部分については省略している。 A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In the drawings, the same or similar components are denoted by the same reference numerals, and the sizes and scales of the corresponding components are independent of one another. For example, when cross-sectional views in which a part of the configuration is changed, the size and scale of the same component may be different when illustrating the same component which is not changed. In addition, although the semiconductor device actually includes a plurality of members, in order to simplify the description, only portions necessary for the description are described, and the other portions are omitted.
実施の形態１．
　以下、この発明の実施の形態１に関わる半導体装置の形態を、図に基づいて説明する。図１は、チップサイズパッケージ構造を有する半導体装置１００を概略的に表している、断面構成図である。半導体装置１００は、半導体チップ１０、バンプ電極９、実装基板２０などを備えている。半導体チップ１０は、半導体素子３０、第１の層間絶縁膜５、層間絶縁膜配線電極６、第２の層間絶縁膜７、層間絶縁膜表層電極８などから構成されている。半導体チップ１０の半導体素子３０には、ソース電極、ドレイン電極、ゲート電極、グランド電極などが形成されている（図２を参照）。実装基板２０は、実装基板本体２１、実装基板電極２２などから構成されている。 Embodiment 1
Hereinafter, the form of a semiconductor device according to the first embodiment of the present invention will be described based on the drawings. FIG. 1 is a cross-sectional view schematically showing a semiconductor device 100 having a chip size package structure. The semiconductor device 100 includes a semiconductor chip 10, bump electrodes 9, a mounting substrate 20, and the like. The semiconductor chip 10 includes a semiconductor element 30, a first interlayer insulating film 5, an interlayer insulating film wiring electrode 6, a second interlayer insulating film 7, an interlayer insulating film surface electrode 8, and the like. A source electrode, a drain electrode, a gate electrode, a ground electrode and the like are formed in the semiconductor element 30 of the semiconductor chip 10 (see FIG. 2). The mounting substrate 20 includes a mounting substrate body 21, a mounting substrate electrode 22, and the like.
　第１の層間絶縁膜５には、層間絶縁膜配線電極６が形成されている。層間絶縁膜配線電極６は、層間絶縁膜ソース配線電極、層間絶縁膜ドレイン配線電極、層間絶縁膜ゲート配線電極、および、層間絶縁膜グランド配線電極から構成されている（図２および図３を参照）。第２の層間絶縁膜７には、層間絶縁膜表層電極８が形成されている。層間絶縁膜表層電極８は、層間絶縁膜ソース表層電極、層間絶縁膜ドレイン表層電極、層間絶縁膜ゲート表層電極、および、層間絶縁膜グランド表層電極から構成されている（図２および図４を参照）。半導体装置１００は、半導体素子３０のソースをグランド電位にして、稼働される。 An interlayer insulating film wiring electrode 6 is formed in the first interlayer insulating film 5. The interlayer insulating film wiring electrode 6 is composed of an interlayer insulating film source wiring electrode, an interlayer insulating film drain wiring electrode, an interlayer insulating film gate wiring electrode, and an interlayer insulating film ground wiring electrode (see FIGS. 2 and 3). ). An interlayer insulating film surface electrode 8 is formed on the second interlayer insulating film 7. The interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and an interlayer insulating film ground surface electrode (see FIGS. 2 and 4). ). The semiconductor device 100 is operated with the source of the semiconductor element 30 at the ground potential.
　実装基板２０には、実装基板電極２２が形成されている。バンプ電極９は、実装基板２０（実装基板電極２２）と接続されている。実装基板２０の実装基板電極２２は、バンプ電極９を経由して、半導体チップ１０（半導体素子３０）の回路素子（ソース電極、ドレイン電極、および、ゲート電極）と電気的に繋がっている。実装基板電極２２は、実装基板ドレイン電極、実装基板ゲート電極、および、実装基板グランド電極から構成されている（図５を参照）。実装基板グランド電極、層間絶縁膜グランド表層電極、および、層間絶縁膜グランド配線電極は、接地されている。 The mounting substrate electrode 22 is formed on the mounting substrate 20. The bump electrode 9 is connected to the mounting substrate 20 (mounting substrate electrode 22). The mounting substrate electrode 22 of the mounting substrate 20 is electrically connected to the circuit elements (the source electrode, the drain electrode, and the gate electrode) of the semiconductor chip 10 (semiconductor element 30) via the bump electrodes 9. The mounting substrate electrode 22 is composed of a mounting substrate drain electrode, a mounting substrate gate electrode, and a mounting substrate ground electrode (see FIG. 5). The mounting substrate ground electrode, the interlayer insulating film ground surface layer electrode, and the interlayer insulating film ground wiring electrode are grounded.
　図２は、実施の形態１に関わるチップサイズパッケージ構造を有する半導体装置１００の構成を概略的に示している断面図である。半導体基板１には、FET（ Field Effect Transistor ）などの半導体素子３０が形成されている。半導体素子３０は、半導体基板１、ソース電極２、ドレイン電極３（３ａ，３ｂ）、ゲート電極４（４ａ，４ｂ）、などから構成されている。半導体素子３０（半導体基板１）の上には、第１の層間絶縁膜５が配置されている。第１の層間絶縁膜５の上には、第２の層間絶縁膜７が配置されている。層間絶縁膜配線電極６および層間絶縁膜表層電極８は、パターン電極部とビア電極部を有している。 FIG. 2 is a cross sectional view schematically showing a configuration of a semiconductor device 100 having a chip size package structure according to the first embodiment. On the semiconductor substrate 1, a semiconductor element 30 such as an FET (Field Effect Transistor) is formed. The semiconductor element 30 is configured of a semiconductor substrate 1, source electrode 2, drain electrode 3 (3a, 3b), gate electrode 4 (4a, 4b), and the like. A first interlayer insulating film 5 is disposed on the semiconductor element 30 (semiconductor substrate 1). A second interlayer insulating film 7 is disposed on the first interlayer insulating film 5. The interlayer insulating film wiring electrode 6 and the interlayer insulating film surface electrode 8 have a pattern electrode portion and a via electrode portion.
　パターン電極部は、層間絶縁膜（第１の層間絶縁膜および第２の層間絶縁膜）の表面に形成されている。ビア電極部は、層間絶縁膜（第１の層間絶縁膜および第２の層間絶縁膜）を縦方向に走っている。層間絶縁膜ドレイン配線電極６ａは、ドレイン電極に対応したパターン電極部６ａｘおよびビア電極部６ａｙから構成されている。層間絶縁膜ソース配線電極６ｂは、ソース電極に対応したパターン電極部６ｂｘおよびビア電極部６ｂｙから構成されている。層間絶縁膜ドレイン配線電極６ｃは、ドレイン電極に対応したパターン電極部６ｃｘおよびビア電極部６ｃｙから構成されている。同様に、層間絶縁膜ゲート配線電極および層間絶縁膜グランド配線電極は、それぞれ、パターン電極部およびビア電極部から構成されている。 The pattern electrode portion is formed on the surface of the interlayer insulating film (the first interlayer insulating film and the second interlayer insulating film). The via electrode portion runs through the interlayer insulating film (first interlayer insulating film and second interlayer insulating film) in the vertical direction. The interlayer insulating film drain wiring electrode 6a is composed of a pattern electrode portion 6ax and a via electrode portion 6ay corresponding to the drain electrode. The interlayer insulating film source wiring electrode 6b is composed of a pattern electrode portion 6bx corresponding to the source electrode and a via electrode portion 6by. The interlayer insulating film drain wiring electrode 6c is composed of a pattern electrode portion 6cx corresponding to the drain electrode and a via electrode portion 6cy. Similarly, the interlayer insulating film gate wiring electrode and the interlayer insulating film ground wiring electrode are respectively formed of a pattern electrode portion and a via electrode portion.
　層間絶縁膜グランド表層電極８ａは、グランド電極に対応したパターン電極部８ａｘおよびビア電極部８ａｙから構成されている。層間絶縁膜ソース表層電極８ｂは、ソース電極に対応したパターン電極部８ｂｘおよびビア部電極部８ｂｙから構成されている。層間絶縁膜グランド表層電極８ｃは、グランド電極に対応したパターン電極部８ｃｘおよびビア電極部８ｃｙから構成されている。同様に、層間絶縁膜ドレイン表層電極、および、層間絶縁膜ゲート表層電極は、それぞれ、パターン電極部およびビア電極部から構成されている。層間絶縁膜グランド表層電極８ａと層間絶縁膜ソース表層電極８ｂの間、および、層間絶縁膜グランド表層電極８ｃと層間絶縁膜ソース表層電極８ｂの間には、分離溝８ｄが形成されている。 The interlayer insulating film ground surface layer electrode 8a is composed of a pattern electrode portion 8ax corresponding to the ground electrode and a via electrode portion 8ay. The interlayer insulating film source surface layer electrode 8b is composed of a pattern electrode portion 8bx corresponding to the source electrode and a via portion electrode portion 8by. The interlayer insulating film ground surface layer electrode 8c is composed of a pattern electrode portion 8cx corresponding to the ground electrode and a via electrode portion 8cy. Similarly, the interlayer insulating film drain surface layer electrode and the interlayer insulating film gate surface layer electrode are respectively formed of a pattern electrode portion and a via electrode portion. A separation groove 8d is formed between the interlayer insulating film ground surface electrode 8a and the interlayer insulating film source surface electrode 8b, and between the interlayer insulating film ground surface electrode 8c and the interlayer insulating film source surface electrode 8b.
　半導体素子３０のドレイン電極３ａは、層間絶縁膜ドレイン配線電極６ａと電気的に繋がっている。半導体素子３０のドレイン電極３ｂは、層間絶縁膜ドレイン配線電極６ｃと電気的に繋がっている。半導体素子３０のソース電極２は、層間絶縁膜ソース配線電極６ｂと電気的に繋がっている。半導体素子３０のゲート電極４ａ、４ｂは、層間絶縁膜配線電極６の層間絶縁膜ゲート配線電極（図示せず）と、層間絶縁膜表層電極８の層間絶縁膜ゲート表層電極（図示せず）と電気的に繋がっている。層間絶縁膜ゲート表層電極は、バンプ電極を経由して、実装基板ゲート電極と接続されている（図５を参照）。 The drain electrode 3a of the semiconductor element 30 is electrically connected to the interlayer insulating film drain wiring electrode 6a. The drain electrode 3b of the semiconductor element 30 is electrically connected to the interlayer insulating film drain wiring electrode 6c. The source electrode 2 of the semiconductor element 30 is electrically connected to the interlayer insulating film source wiring electrode 6 b. The gate electrodes 4a and 4b of the semiconductor element 30 are an interlayer insulating film gate wiring electrode (not shown) of the interlayer insulating film wiring electrode 6 and an interlayer insulating film gate surface electrode (not shown) of the interlayer insulating film surface electrode 8 It is electrically connected. The interlayer insulating film gate surface layer electrode is connected to the mounting substrate gate electrode via the bump electrode (see FIG. 5).
　層間絶縁膜ソース配線電極６ｂは、層間絶縁膜ソース表層電極８ｂと電気的に繋がっている。層間絶縁膜ドレイン配線電極６ａ、６ｃは、層間絶縁膜表層電極８の層間絶縁膜ドレイン表層電極（図示せず）に接続されている。層間絶縁膜ドレイン表層電極は、バンプ電極を経由して、実装基板ドレイン電極と接続されている（図５を参照）。バンプ電極９ａは、層間絶縁膜グランド表層電極８ａに接続されている。バンプ電極９ｂは、層間絶縁膜ソース表層電極８ｂに接続されている。バンプ電極９ｃは、層間絶縁膜グランド表層電極８ｃに接続されている。実装基板電極２２は、バンプ電極９と、電気的に繋がっている。 The interlayer insulating film source wiring electrode 6b is electrically connected to the interlayer insulating film source surface layer electrode 8b. The interlayer insulating film drain wiring electrodes 6 a and 6 c are connected to the interlayer insulating film drain surface electrode (not shown) of the interlayer insulating film surface electrode 8. The interlayer insulating film drain surface layer electrode is connected to the mounting substrate drain electrode via the bump electrode (see FIG. 5). Bump electrode 9a is connected to interlayer insulating film ground surface layer electrode 8a. Bump electrode 9 b is connected to interlayer insulating film source surface layer electrode 8 b. Bump electrode 9c is connected to interlayer insulating film ground surface electrode 8c. The mounting substrate electrode 22 is electrically connected to the bump electrode 9.
　実装基板電極２２は、パターン電極部とビア電極部を有している。図には、実装基板２０（実装基板本体２１）に形成される実装基板電極２２として、実装基板グランド電極２２Ｗが表示されている。実装基板２０（実装基板本体２１）には、他に、実装基板ドレイン電極および実装基板ゲート電極が、形成されている（図５を参照）。バンプ電極９ａ、バンプ電極９ｂ、およびバンプ電極９ｃは、実装基板グランド電極２２Ｗと接続されている。 The mounting substrate electrode 22 has a pattern electrode portion and a via electrode portion. In the drawing, a mounting substrate ground electrode 22W is displayed as the mounting substrate electrode 22 formed on the mounting substrate 20 (mounting substrate main body 21). In addition, a mounting substrate drain electrode and a mounting substrate gate electrode are formed on the mounting substrate 20 (mounting substrate main body 21) (see FIG. 5). The bump electrode 9a, the bump electrode 9b, and the bump electrode 9c are connected to the mounting substrate ground electrode 22W.
　図３は、半導体素子３０の構成を概略的に示している平面図である。半導体素子３０（半導体基板１）には、ソース電極２、ドレイン電極３（３ａおよび３ｂ）、ゲート電極４（４ａおよび４ｂ）、グランド電極１１などが形成されている。ゲート電極４ａとゲート電極４ｂは、半導体素子３０（半導体基板１）の表面上で、直接、繋がっている。ソース電極２は、層間絶縁膜ソース配線電極６ｂのビア電極部と繋がっている。 FIG. 3 is a plan view schematically showing the configuration of the semiconductor device 30. As shown in FIG. In the semiconductor element 30 (semiconductor substrate 1), the source electrode 2, the drain electrode 3 (3a and 3b), the gate electrode 4 (4a and 4b), the ground electrode 11, and the like are formed. The gate electrode 4a and the gate electrode 4b are directly connected on the surface of the semiconductor element 30 (semiconductor substrate 1). The source electrode 2 is connected to the via electrode portion of the interlayer insulating film source wiring electrode 6 b.
　ドレイン電極３ａは、層間絶縁膜ドレイン配線電極６ａのビア電極部と繋がっている。ドレイン電極３ｂは、層間絶縁膜ドレイン配線電極６ｃのビア電極部と繋がっている。ゲート電極４ａおよびゲート電極４ｂは、層間絶縁膜ゲート配線電極６ｄのビア電極部と繋がっている。半導体素子３０に形成されているソース電極２は、長さＬ１を有する。 The drain electrode 3a is connected to the via electrode portion of the interlayer insulating film drain wiring electrode 6a. The drain electrode 3b is connected to the via electrode portion of the interlayer insulating film drain wiring electrode 6c. Gate electrode 4a and gate electrode 4b are connected to a via electrode portion of interlayer insulating film gate wiring electrode 6d. The source electrode 2 formed in the semiconductor element 30 has a length L1.
　図４は、層間絶縁膜表層電極８の構成を概略的に示している平面図である。第２の層間絶縁膜７の上には、層間絶縁膜表層電極８（層間絶縁膜ソース表層電極、層間絶縁膜ドレイン表層電極、層間絶縁膜ゲート表層電極、および、層間絶縁膜グランド表層電極）が形成されている。層間絶縁膜グランド表層電極８ａおよび層間絶縁膜グランド表層電極８ｃは、この平面図からわかるように、一体化されていて、グランド電位に設定されている。層間絶縁膜ソース表層電極８ｂは、層間絶縁膜グランド表層電極（８ａ，８ｃ）によって周囲を完全に囲まれている。 FIG. 4 is a plan view schematically showing the configuration of the interlayer insulating film surface electrode 8. On the second interlayer insulating film 7, an interlayer insulating film surface electrode 8 (interlayer insulating film source surface electrode, interlayer insulating film drain surface electrode, interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrode) is provided. It is formed. Interlayer insulating film ground surface layer electrode 8a and interlayer insulating film ground surface layer electrode 8c are integrated as shown in this plan view, and are set to the ground potential. The interlayer insulating film source surface layer electrode 8b is completely surrounded by the interlayer insulating film ground surface layer electrodes (8a, 8c).
　分離溝８ｄは、ソースとグランドを分離するために、層間絶縁膜ソース表層電極８ｂと層間絶縁膜グランド表層電極（８ａ，８ｃ）の間に形成されている。層間絶縁膜ソース表層電極８ｂは、半導体素子３０のソース電極２（およびソース）と電気的に接続されている。層間絶縁膜ドレイン表層電極は、半導体素子３０のドレイン電極３（およびドレイン）と電気的に接続されている。層間絶縁膜ゲート表層電極は、半導体素子３０のゲート電極４（およびゲート）と電気的に接続されている。 The separation groove 8d is formed between the interlayer insulating film source surface layer electrode 8b and the interlayer insulating film ground surface electrode (8a, 8c) in order to separate the source and the ground. The interlayer insulating film source surface layer electrode 8 b is electrically connected to the source electrode 2 (and the source) of the semiconductor element 30. The interlayer insulating film drain surface layer electrode is electrically connected to the drain electrode 3 (and the drain) of the semiconductor element 30. The interlayer insulating film gate surface layer electrode is electrically connected to the gate electrode 4 (and the gate) of the semiconductor element 30.
　層間絶縁膜グランド表層電極８ａには、バンプ電極９ａが、例えば、半田を転写する方法等により形成されている。層間絶縁膜ソース表層電極８ｂには、バンプ電極９ｂが、例えば、半田を転写する方法等により形成されている。層間絶縁膜グランド表層電極８ｃには、バンプ電極９ｃが、例えば、半田を転写する方法等により形成されている。同様に、層間絶縁膜ドレイン表層電極および層間絶縁膜ゲート表層電極には、バンプ電極が、例えば、半田を転写する方法等により形成されている。 Bump electrodes 9 a are formed on the interlayer insulating film ground surface electrode 8 a by, for example, a method of transferring solder. Bump electrodes 9 b are formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder. Bump electrodes 9 c are formed on the interlayer insulating film ground surface electrode 8 c by, for example, a method of transferring solder. Similarly, bump electrodes are formed on the interlayer insulating film drain surface electrode and the interlayer insulating film gate surface electrode, for example, by a method of transferring solder.
　図５は、本実施の形態に関わる実装基板２０の第１の構成を概略的に示している平面図である。実装基板２０（実装基板本体２１）には、実装基板電極２２が形成されている。実装基板電極２２は、実装基板ドレイン電極２２Ｙ、実装基板ゲート電極２２Ｚ、および、実装基板グランド電極２２Ｗから構成されている。実装基板グランド電極２２Ｗは、バンプ電極９ｂと接続されていて、半導体素子３０のソース電極２と電気的に繋がっている。 FIG. 5 is a plan view schematically showing a first configuration of the mounting substrate 20 according to the present embodiment. A mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21). The mounting substrate electrode 22 is configured of a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W. The mounting substrate ground electrode 22 W is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
　さらに、実装基板グランド電極２２Ｗは、バンプ電極９ａおよびバンプ電極９ｃと接続されていて、半導体素子３０のグランド電極と電気的に繋がっている。実装基板ドレイン電極２２Ｙは、バンプ電極９ｄと接続されていて、半導体素子３０のドレイン電極３（３ａ，３ｂ）と電気的に繋がっている。実装基板ゲート電極２２Ｚは、バンプ電極９ｅと接続されていて、半導体素子３０のゲート電極４（４ａ，４ｂ）と電気的に繋がっている。 Furthermore, the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30. The mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30. The mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
　図６は、本実施の形態に関わる実装基板２０の第２の構成を概略的に示している平面図である。実装基板２０（実装基板本体２１）には、実装基板電極２２が形成されている。実装基板電極２２は、実装基板ソース電極２２Ｘ、実装基板ドレイン電極２２Ｙ、実装基板ゲート電極２２Ｚ、および、実装基板グランド電極２２Ｗから構成されている。実装基板ソース電極２２Ｘは、バンプ電極９ｂと接続されていて、半導体素子３０のソース電極２と電気的に繋がっている。 FIG. 6 is a plan view schematically showing a second configuration of the mounting substrate 20 according to the present embodiment. A mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21). The mounting substrate electrode 22 is configured of a mounting substrate source electrode 22X, a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W. The mounting substrate source electrode 22 </ b> X is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
　実装基板ドレイン電極２２Ｙは、バンプ電極９ｄと接続されていて、半導体素子３０のドレイン電極３（３ａ，３ｂ）と電気的に繋がっている。実装基板ゲート電極２２Ｚは、バンプ電極９ｅと接続されていて、半導体素子３０のゲート電極４（４ａ，４ｂ）と電気的に繋がっている。実装基板グランド電極２２Ｗは、バンプ電極９ａ，９ｃと接続されていて、半導体素子３０のグランド電極と電気的に繋がっている。 The mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30. The mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30. The mounting substrate ground electrode 22 W is connected to the bump electrodes 9 a and 9 c and electrically connected to the ground electrode of the semiconductor element 30.
　実装基板グランド電極２２Ｗは、実装基板ソース電極２２Ｘの周囲を完全に囲んでいる。実装基板ソース電極２２Ｘは、グランド電位に設定されているが、実装基板グランド電極２２Ｗとは独立して配設されている。本実施の形態に関わる半導体装置１００では、ソースとグランドを分離するために、実装基板グランド電極２２Ｗと実装基板ソース電極２２Ｘの間に、分離溝２２ｄが形成されている。 The mounting substrate ground electrode 22W completely surrounds the mounting substrate source electrode 22X. Although the mounting substrate source electrode 22X is set to the ground potential, it is disposed independently of the mounting substrate ground electrode 22W. In the semiconductor device 100 according to the present embodiment, the separation groove 22d is formed between the mounting substrate ground electrode 22W and the mounting substrate source electrode 22X in order to separate the source and the ground.
　つぎに、本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００の製造方法について説明する。まず、半導体基板１の上へ、ソース電極２（およびソース）、ドレイン電極３（およびドレイン）、および、ゲート電極４（ゲート）を有するトランジスタ構造を、例えば、蒸着リフトオフ法を用いて形成する。つぎに、第１の層間絶縁膜５を、例えば、ポリイミド塗布/写真製版を用いて形成する。つぎに、層間絶縁膜配線電極６を、例えば、蒸着リフトオフ法を用いて形成する。つぎに、第２の層間絶縁膜７を、例えば、ポリイミド塗布/写真製版を用いて形成する。 Next, a method of manufacturing the semiconductor device 100 compatible with the chip size package according to the present embodiment will be described. First, a transistor structure having a source electrode 2 (and a source), a drain electrode 3 (and a drain), and a gate electrode 4 (gate) is formed on a semiconductor substrate 1 using, for example, a deposition lift-off method. Next, the first interlayer insulating film 5 is formed using, for example, a polyimide coating / photolithography process. Next, the interlayer insulating film wiring electrode 6 is formed by using, for example, a vapor deposition lift-off method. Next, the second interlayer insulating film 7 is formed by using, for example, polyimide coating / photolithography.
　つぎに、層間絶縁膜表層電極８を、例えば、電解メッキ法を用いて形成する。層間絶縁膜表層電極８は、層間絶縁膜ソース表層電極８ｂ、層間絶縁膜ドレイン表層電極、層間絶縁膜ゲート表層電極、および、層間絶縁膜グランド表層電極８ａ，８ｃから構成されている。その際、層間絶縁膜ソース表層電極８ｂに、バンプ電極９ｂの設置箇所を取り囲む様に、電極を形成しない部分（分離溝８ｄ）を、例えば、写真製版工程を用いて形成する。つぎに、層間絶縁膜ソース表層電極８ｂの上部へ、バンプ電極９ｂを、例えば、半田を転写する方法等により形成する。 Next, the interlayer insulating film surface electrode 8 is formed using, for example, an electrolytic plating method. The interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode 8b, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrodes 8a and 8c. At that time, in the interlayer insulating film source surface layer electrode 8b, a portion (separation groove 8d) in which the electrode is not formed is formed using, for example, a photoengraving process so as to surround the installation location of the bump electrode 9b. Next, a bump electrode 9 b is formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder.
　本実施の形態に関わる半導体装置では、層間絶縁膜ソース表層電極８ｂは、ソース電極２に接続し、その上にバンプ電極が形成されている。この層間絶縁膜ソース表層電極８ｂに、バンプ電極の設置箇所を取り囲む様に、電極を形成しない分離溝８ｄを形成する。このことにより、ソース電極２を、半導体装置の上にて、他の回路素子から電気的に分離する事が出来るようになる。 In the semiconductor device according to the present embodiment, interlayer insulating film source surface layer electrode 8b is connected to source electrode 2, and a bump electrode is formed thereon. In this interlayer insulating film source surface layer electrode 8b, a separation groove 8d in which no electrode is formed is formed so as to surround the installation location of the bump electrode. As a result, the source electrode 2 can be electrically separated from other circuit elements on the semiconductor device.
　実装基板２０は、バンプ電極９を介して、半導体チップ１０と接続している。その結果、ソース電極２と半導体素子３０のグランド電極と電気的に繋がっている他の回路素子は、実装基板２０にて接続される事になる。この為、ソース電極２と半導体素子３０のグランド電極と電気的に繋がっているその他の回路素子との接続距離が伸びる事で、回路素子の間の遮断性を高める事が可能となり、回路素子の間での不要なループ発振を防止する事が出来る。 The mounting substrate 20 is connected to the semiconductor chip 10 via the bump electrode 9. As a result, other circuit elements electrically connected to the source electrode 2 and the ground electrode of the semiconductor element 30 are connected by the mounting substrate 20. Therefore, as the connection distance between the source electrode 2 and the other circuit element electrically connected to the ground electrode of the semiconductor element 30 is extended, it is possible to improve the blocking property between the circuit elements, It is possible to prevent unnecessary loop oscillation between the two.
　本実施の形態には、半導体基板の上に、トランジスタのソース電極、ドレイン電極、ゲート電極を備え、その上に層間絶縁膜を介して層間絶縁膜配線電極を配置し、つぎに最上層の電極を層間絶縁膜を介して層間絶縁膜表層電極として配置し、その層間絶縁膜表層電極の上に表面実装用のバンプ電極を配置したチップサイズパッケージ構造を有する半導体装置であり、かつソース電極に接続された層間絶縁膜表層電極とバンプ電極が、他のバンプ電極と電気的に分離される様、バンプ電極を取り囲む様に層間絶縁膜表層電極を取り去った構造を有する事を特徴とする半導体装置が記載されている。 In this embodiment, a source electrode, a drain electrode, and a gate electrode of a transistor are provided on a semiconductor substrate, and an interlayer insulating film wiring electrode is disposed on top of that via an interlayer insulating film, and then an electrode of the uppermost layer A semiconductor device having a chip size package structure in which a bump electrode for surface mounting is disposed on an interlayer insulating film surface electrode via an interlayer insulating film and connected to a source electrode A semiconductor device having a structure in which the interlayer insulating film surface electrode is removed so as to surround the bump electrode so that the interlayer insulating film surface electrode and the bump electrode electrically separated from the other bump electrodes; Have been described.
　すなわち、本実施の形態に関わる半導体装置は、ソース電極、ドレイン電極、および、ゲート電極が形成されている半導体素子と、前記半導体素子の上に配置され、層間絶縁膜ソース配線電極、層間絶縁膜ドレイン配線電極および層間絶縁膜ゲート配線電極が形成されている第１の層間絶縁膜と、前記第１の層間絶縁膜の上に配置され、層間絶縁膜ソース表層電極および層間絶縁膜グランド表層電極が形成されている第２の層間絶縁膜と、前記第２の層間絶縁膜に形成されている層間絶縁膜ソース表層電極の上に配置された第１のバンプ電極と、前記第２の層間絶縁膜に形成されている層間絶縁膜グランド表層電極の上に配置された第２のバンプ電極と、前記第１のバンプ電極および前記第２のバンプ電極と接続されている実装基板と、を備え、前記層間絶縁膜ソース配線電極は、前記ソース電極および前記層間絶縁膜ソース表層電極と繋がっており、しかも、前記層間絶縁膜ソース表層電極は、前記層間絶縁膜グランド表層電極によって囲まれていて、前記層間絶縁膜ソース表層電極と前記層間絶縁膜グランド表層電極の間には、分離溝が形成されていることを特徴とするものである。 That is, the semiconductor device according to the present embodiment includes a semiconductor element in which a source electrode, a drain electrode, and a gate electrode are formed, and an interlayer insulating film source wiring electrode and an interlayer insulating film disposed on the semiconductor element. A first interlayer insulating film on which a drain wiring electrode and an interlayer insulating film gate wiring electrode are formed; an interlayer insulating film source surface electrode and an interlayer insulating film ground surface electrode disposed on the first interlayer insulating film; A second interlayer insulating film formed, a first bump electrode disposed on an interlayer insulating film source surface layer electrode formed in the second interlayer insulating film, and the second interlayer insulating film A second bump electrode disposed on an interlayer insulating film ground surface layer electrode formed on the substrate, and a mounting substrate connected to the first bump electrode and the second bump electrode; The interlayer insulating film source wiring electrode is connected to the source electrode and the interlayer insulating film source surface electrode, and the interlayer insulating film source surface electrode is surrounded by the interlayer insulating film ground surface electrode. A separation groove is formed between the interlayer insulating film source surface layer electrode and the interlayer insulating film ground surface layer electrode.
実施の形態２．
　以下、この発明の実施の形態２に関わる半導体装置の形態を、図に基づいて説明する。図において、同じ記号は、同じ、もしくは、同等部分を示す。本実施の形態に関わる半導体装置１００は、半導体チップ１０、バンプ電極９、実装基板２０などを備えている（図１を参照）。半導体チップ１０は、半導体素子３０、第１の層間絶縁膜５、層間絶縁膜配線電極６、第２の層間絶縁膜７、層間絶縁膜表層電極８などから構成されている。 Second Embodiment
Hereinafter, the form of the semiconductor device in connection with Embodiment 2 of this invention is demonstrated based on a figure. In the figures, the same symbols indicate the same or equivalent parts. A semiconductor device 100 according to the present embodiment includes a semiconductor chip 10, bump electrodes 9, a mounting substrate 20 and the like (see FIG. 1). The semiconductor chip 10 includes a semiconductor element 30, a first interlayer insulating film 5, an interlayer insulating film wiring electrode 6, a second interlayer insulating film 7, an interlayer insulating film surface electrode 8, and the like.
　半導体チップ１０の半導体素子３０には、ソース電極、ドレイン電極、ゲート電極、グランド電極などが形成されている。実装基板２０は、実装基板本体２１、実装基板電極２２などから構成されている。半導体装置１００は、半導体素子３０のソースをグランド電位にして、動作する。本実施の形態に関わる半導体装置では、実装基板電極２２は、実装基板ドレイン電極、実装基板ゲート電極、および、実装基板グランド電極から構成されている。 In the semiconductor element 30 of the semiconductor chip 10, a source electrode, a drain electrode, a gate electrode, a ground electrode, and the like are formed. The mounting substrate 20 includes a mounting substrate body 21, a mounting substrate electrode 22, and the like. The semiconductor device 100 operates with the source of the semiconductor element 30 at the ground potential. In the semiconductor device according to the present embodiment, the mounting substrate electrode 22 includes the mounting substrate drain electrode, the mounting substrate gate electrode, and the mounting substrate ground electrode.
　図７は、本実施の形態に関わるチップサイズパッケージ構造を有する半導体装置１００の構成を概略的に示している断面図である。半導体基板１には、FET（ Field Effect Transistor ）などの半導体素子３０が形成されている。半導体素子３０は、半導体基板１、ソース電極２、ドレイン電極３（３ａ，３ｂ）、ゲート電極４（４ａ，４ｂ）、などから構成されている。半導体素子３０（半導体基板１）の上には、第１の層間絶縁膜５が配置されている。第１の層間絶縁膜５の上には、第２の層間絶縁膜７が配置されている。 FIG. 7 is a cross sectional view schematically showing a configuration of a semiconductor device 100 having a chip size package structure according to the present embodiment. On the semiconductor substrate 1, a semiconductor element 30 such as an FET (Field Effect Transistor) is formed. The semiconductor element 30 is configured of a semiconductor substrate 1, source electrode 2, drain electrode 3 (3a, 3b), gate electrode 4 (4a, 4b), and the like. A first interlayer insulating film 5 is disposed on the semiconductor element 30 (semiconductor substrate 1). A second interlayer insulating film 7 is disposed on the first interlayer insulating film 5.
　本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００では、層間絶縁膜ソース表層電極８ｂは、層間絶縁膜ソース配線電極６ｂおよびソース電極２の直上に配置されている。層間絶縁膜グランド表層電極８ａと層間絶縁膜ソース表層電極８ｂの間、および、層間絶縁膜グランド表層電極８ｃと層間絶縁膜ソース表層電極８ｂの間には、分離溝８ｄが形成されている。 In the semiconductor device 100 compatible with the chip size package according to the present embodiment, the interlayer insulating film source surface layer electrode 8 b is disposed directly on the interlayer insulating film source wiring electrode 6 b and the source electrode 2. A separation groove 8d is formed between the interlayer insulating film ground surface electrode 8a and the interlayer insulating film source surface electrode 8b, and between the interlayer insulating film ground surface electrode 8c and the interlayer insulating film source surface electrode 8b.
　実装基板電極２２は、パターン電極部とビア電極部を有している。図には、実装基板２０（実装基板本体２１）に形成される実装基板電極２２として、実装基板ソース電極２２Ｘおよび実装基板グランド電極２２Ｗが表示されている。実装基板２０（実装基板本体２１）には、他に、実装基板ドレイン電極および実装基板ゲート電極が、形成されている（図８を参照）。バンプ電極９ａおよびバンプ電極９ｃは、実装基板グランド電極２２Ｗと接続されている。バンプ電極９ｂは、実装基板ソース電極２２Ｘと接続されている。実装基板ソース電極２２Ｘと実装基板グランド電極２２の間には、分離溝２２ｄが形成されている。 The mounting substrate electrode 22 has a pattern electrode portion and a via electrode portion. In the drawing, a mounting substrate source electrode 22X and a mounting substrate ground electrode 22W are displayed as the mounting substrate electrode 22 formed on the mounting substrate 20 (mounting substrate main body 21). In addition, a mounting substrate drain electrode and a mounting substrate gate electrode are formed on the mounting substrate 20 (mounting substrate main body 21) (see FIG. 8). The bump electrode 9a and the bump electrode 9c are connected to the mounting substrate ground electrode 22W. The bump electrode 9b is connected to the mounting substrate source electrode 22X. A separation groove 22 d is formed between the mounting substrate source electrode 22 X and the mounting substrate ground electrode 22.
　図８は、本実施の形態に関わる層間絶縁膜表層電極８の構成を概略的に示している平面図である。第２の層間絶縁膜７の上には、層間絶縁膜表層電極８（層間絶縁膜ソース表層電極、層間絶縁膜ドレイン表層電極、層間絶縁膜ゲート表層電極、および、層間絶縁膜グランド表層電極）が形成されている。層間絶縁膜グランド表層電極８ａおよび層間絶縁膜グランド表層電極８ｃは、この平面図からわかるように、一体化されていて、グランド電位に設定されている。層間絶縁膜ソース表層電極８ｂは、層間絶縁膜グランド表層電極８ａ，８ｃによって周囲を完全に囲まれている。 FIG. 8 is a plan view schematically showing the configuration of interlayer insulating film surface electrode 8 according to the present embodiment. On the second interlayer insulating film 7, an interlayer insulating film surface electrode 8 (interlayer insulating film source surface electrode, interlayer insulating film drain surface electrode, interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrode) is provided. It is formed. Interlayer insulating film ground surface layer electrode 8a and interlayer insulating film ground surface layer electrode 8c are integrated as shown in this plan view, and are set to the ground potential. The interlayer insulating film source surface layer electrode 8b is completely surrounded by the interlayer insulating film ground surface layer electrodes 8a and 8c.
　分離溝８ｄは、ソースとグランドを分離するために、層間絶縁膜ソース表層電極８ｂと層間絶縁膜グランド表層電極（８ａ，８ｃ）の間に形成されている。層間絶縁膜ソース表層電極８ｂは、半導体素子３０のソース電極２（およびソース）と電気的に接続されている。層間絶縁膜ドレイン表層電極は、半導体素子３０のドレイン電極３（およびドレイン）と電気的に接続されている。層間絶縁膜ゲート表層電極は、半導体素子３０のゲート電極４（およびゲート）と電気的に接続されている。 The separation groove 8d is formed between the interlayer insulating film source surface layer electrode 8b and the interlayer insulating film ground surface electrode (8a, 8c) in order to separate the source and the ground. The interlayer insulating film source surface layer electrode 8 b is electrically connected to the source electrode 2 (and the source) of the semiconductor element 30. The interlayer insulating film drain surface layer electrode is electrically connected to the drain electrode 3 (and the drain) of the semiconductor element 30. The interlayer insulating film gate surface layer electrode is electrically connected to the gate electrode 4 (and the gate) of the semiconductor element 30.
　層間絶縁膜グランド表層電極８ａには、バンプ電極９ａが、例えば、半田を転写する方法等により形成されている。層間絶縁膜ソース表層電極８ｂには、バンプ電極９ｂが、例えば、半田を転写する方法等により形成されている。層間絶縁膜グランド表層電極８ｃには、バンプ電極９ｃが、例えば、半田を転写する方法等により形成されている。同様に、層間絶縁膜ドレイン表層電極および層間絶縁膜ゲート表層電極には、バンプ電極が、例えば、半田を転写する方法等により形成されている。本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００では、バンプ電極９ｂは、層間絶縁膜ソース表層電極８ｂの真中に配置されている。 Bump electrodes 9 a are formed on the interlayer insulating film ground surface electrode 8 a by, for example, a method of transferring solder. Bump electrodes 9 b are formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder. Bump electrodes 9 c are formed on the interlayer insulating film ground surface electrode 8 c by, for example, a method of transferring solder. Similarly, bump electrodes are formed on the interlayer insulating film drain surface electrode and the interlayer insulating film gate surface electrode, for example, by a method of transferring solder. In the semiconductor device 100 compatible with the chip size package according to the present embodiment, the bump electrode 9 b is disposed in the middle of the interlayer insulating film source surface electrode 8 b.
　図９は、本実施の形態に関わる実装基板２０の第１の構成を概略的に示している平面図である。実装基板２０（実装基板本体２１）には、実装基板電極２２が形成されている。実装基板電極２２は、実装基板ドレイン電極２２Ｙ、実装基板ゲート電極２２Ｚ、および、実装基板グランド電極２２Ｗから構成されている。実装基板グランド電極２２Ｗは、バンプ電極９ｂと接続されていて、半導体素子３０のソース電極２と電気的に繋がっている。 FIG. 9 is a plan view schematically showing a first configuration of the mounting substrate 20 according to the present embodiment. A mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21). The mounting substrate electrode 22 is configured of a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W. The mounting substrate ground electrode 22 W is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
　さらに、実装基板グランド電極２２Ｗは、バンプ電極９ａおよびバンプ電極９ｃと接続されていて、半導体素子３０のグランド電極と電気的に繋がっている。実装基板ドレイン電極２２Ｙは、バンプ電極９ｄと接続されていて、半導体素子３０のドレイン電極３（３ａ，３ｂ）と電気的に繋がっている。実装基板ゲート電極２２Ｚは、バンプ電極９ｅと接続されていて、半導体素子３０のゲート電極４（４ａ，４ｂ）と電気的に繋がっている。本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００では、バンプ電極９ｂは、実装基板グランド電極２２Ｗの真中に配置されている。 Furthermore, the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30. The mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30. The mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30. In the semiconductor device 100 compatible with the chip size package according to the present embodiment, the bump electrode 9b is disposed in the center of the mounting substrate ground electrode 22W.
　図１０は、本実施の形態に関わる実装基板２０の第２の構成を概略的に示している平面図である。実装基板２０（実装基板本体２１）には、実装基板電極２２が形成されている。実装基板電極２２は、実装基板ソース電極２２Ｘ、実装基板ドレイン電極２２Ｙ、実装基板ゲート電極２２Ｚ、および、実装基板グランド電極２２Ｗから構成されている。実装基板ソース電極２２Ｘは、バンプ電極９ｂと接続されていて、半導体素子３０のソース電極２と電気的に繋がっている。実装基板ドレイン電極２２Ｙは、バンプ電極９ｄと接続されていて、半導体素子３０のドレイン電極３（３ａ，３ｂ）と電気的に繋がっている。 FIG. 10 is a plan view schematically showing a second configuration of the mounting substrate 20 according to the present embodiment. A mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21). The mounting substrate electrode 22 is configured of a mounting substrate source electrode 22X, a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W. The mounting substrate source electrode 22 </ b> X is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30. The mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
　実装基板ゲート電極２２Ｚは、バンプ電極９ｅと接続されていて、半導体素子３０のゲート電極４（４ａ，４ｂ）と電気的に繋がっている。実装基板グランド電極２２Ｗは、バンプ電極９ａ，９ｃと接続されていて、半導体素子３０のグランド電極と電気的に繋がっている。実装基板グランド電極２２Ｗは、実装基板ソース電極２２Ｘの周囲を完全に囲んでいる。実装基板ソース電極２２Ｘは、グランド電位に設定されているが、実装基板グランド電極２２Ｗとは独立して配設されている。 The mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30. The mounting substrate ground electrode 22 W is connected to the bump electrodes 9 a and 9 c and electrically connected to the ground electrode of the semiconductor element 30. The mounting substrate ground electrode 22W completely surrounds the mounting substrate source electrode 22X. Although the mounting substrate source electrode 22X is set to the ground potential, it is disposed independently of the mounting substrate ground electrode 22W.
　本実施の形態に関わる半導体装置１００では、ソースとグランドを分離するために、実装基板グランド電極２２Ｗと実装基板ソース電極２２Ｘの間に、分離溝２２ｄが形成されている。本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００では、バンプ電極９ｂは、実装基板ソース電極２２Ｘの真中に配置されている。 In the semiconductor device 100 according to the present embodiment, the separation groove 22d is formed between the mounting substrate ground electrode 22W and the mounting substrate source electrode 22X in order to separate the source and the ground. In the semiconductor device 100 compatible with the chip size package according to the present embodiment, the bump electrode 9b is disposed in the center of the mounting substrate source electrode 22X.
　つぎに、本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００の製造方法について説明する。まず、半導体基板１の上へ、ソース電極２（およびソース）、ドレイン電極３（およびドレイン）、および、ゲート電極４（ゲート）を有するトランジスタ構造を、例えば、蒸着リフトオフ法を用いて形成する。つぎに、第１の層間絶縁膜５を、例えば、ポリイミド塗布/写真製版を用いて形成する。つぎに、層間絶縁膜配線電極６を、例えば、蒸着リフトオフ法を用いて形成する。その際、ソース電極２と層間絶縁膜ソース表層電極８ｂを接続する層間絶縁膜ソース配線電極６ｂは、ソース電極２の直上に形成する。つぎに、第２の層間絶縁膜７を、例えば、ポリイミド塗布/写真製版を用いて形成する。 Next, a method of manufacturing the semiconductor device 100 compatible with the chip size package according to the present embodiment will be described. First, a transistor structure having a source electrode 2 (and a source), a drain electrode 3 (and a drain), and a gate electrode 4 (gate) is formed on a semiconductor substrate 1 using, for example, a deposition lift-off method. Next, the first interlayer insulating film 5 is formed using, for example, a polyimide coating / photolithography process. Next, the interlayer insulating film wiring electrode 6 is formed by using, for example, a vapor deposition lift-off method. At that time, an interlayer insulating film source wiring electrode 6 b connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8 b is formed directly on the source electrode 2. Next, the second interlayer insulating film 7 is formed by using, for example, polyimide coating / photolithography.
　つぎに、層間絶縁膜表層電極８を、例えば、電解メッキ法を用いて形成する。層間絶縁膜表層電極８は、層間絶縁膜ソース表層電極８ｂ、層間絶縁膜ドレイン表層電極、層間絶縁膜ゲート表層電極、および、層間絶縁膜グランド表層電極８ａ，８ｃから構成されている。その際、層間絶縁膜ソース表層電極８ｂに、バンプ電極９ｂの設置箇所を取り囲む様に、電極を形成しない部分（分離溝８ｄ）を、例えば、写真製版工程を用いて形成する。つぎに、層間絶縁膜ソース表層電極８ｂの上部へ、バンプ電極９ｂを、例えば、半田を転写する方法等により形成する。 Next, the interlayer insulating film surface electrode 8 is formed using, for example, an electrolytic plating method. The interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode 8b, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrodes 8a and 8c. At that time, in the interlayer insulating film source surface layer electrode 8b, a portion (separation groove 8d) in which the electrode is not formed is formed using, for example, a photoengraving process so as to surround the installation location of the bump electrode 9b. Next, a bump electrode 9 b is formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder.
　本実施の形態に関わる半導体装置では、層間絶縁膜ソース表層電極８ｂは、ソース電極２に接続し、その上にバンプ電極が形成されている。この層間絶縁膜ソース表層電極８ｂに、バンプ電極の設置箇所を取り囲む様に、電極材が存在しない分離溝を形成する。このことにより、ソース電極２を、半導体装置の上にて、他の回路素子から電気的に分離する事が出来る。また、ソース電極２と層間絶縁膜ソース表層電極８ｂを接続する層間絶縁膜ソース配線電極６ｂを、ソース電極２の直上へ設置する事で、ソース電極２と層間絶縁膜ソース表層電極８ｂを最短距離で接続する事が出来る。 In the semiconductor device according to the present embodiment, interlayer insulating film source surface layer electrode 8b is connected to source electrode 2, and a bump electrode is formed thereon. In the interlayer insulating film source surface layer electrode 8b, a separation groove in which no electrode material exists is formed so as to surround the installation location of the bump electrode. By this, the source electrode 2 can be electrically separated from other circuit elements on the semiconductor device. Further, the interlayer insulating film source wiring electrode 6b connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8b is disposed immediately above the source electrode 2, whereby the shortest distance between the source electrode 2 and the interlayer insulating film source surface layer electrode 8b You can connect with.
　実装基板２０は、バンプ電極９を介して、半導体チップ１０と接続している。その結果、ソース電極２と半導体素子３０のグランド電極と電気的に繋がっている他の回路素子は、実装基板にて接続される事になる。この為、ソース電極２と半導体素子３０のグランド電極と電気的に繋がっているその他の回路素子との接続距離が伸びる事で、回路素子の間の遮断性を高める事が可能となり、回路素子の間での不要なループ発振を防止する事が出来る。さらに、ソース電極２と層間絶縁膜ソース表層電極８ｂを最短距離で接続する事で、寄生抵抗成分と寄生インダクタンス成分が低減し、トランジスタ特性の低下を抑制する事も出来る。 The mounting substrate 20 is connected to the semiconductor chip 10 via the bump electrode 9. As a result, other circuit elements electrically connected to the source electrode 2 and the ground electrode of the semiconductor element 30 are connected by the mounting substrate. Therefore, as the connection distance between the source electrode 2 and the other circuit element electrically connected to the ground electrode of the semiconductor element 30 is extended, it is possible to improve the blocking property between the circuit elements, It is possible to prevent unnecessary loop oscillation between the two. Furthermore, by connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8b at the shortest distance, the parasitic resistance component and the parasitic inductance component can be reduced, and the deterioration of the transistor characteristics can be suppressed.
　本実施の形態に関わる半導体装置は、実施の形態１に記載した半導体装置であり、かつソース電極と層間絶縁膜ソース表層電極の間をソース電極の直上にて接続した事を特徴とする半導体装置である。すなわち、前記層間絶縁膜ソース表層電極は、前記ソース電極の直上に配置されていることを特徴とする半導体装置である。 The semiconductor device according to the present embodiment is the semiconductor device described in the first embodiment, and is characterized in that the source electrode and the interlayer insulating film source surface layer electrode are connected directly above the source electrode. It is. That is, the semiconductor device is characterized in that the interlayer insulating film source surface layer electrode is disposed immediately above the source electrode.
実施の形態３．
　以下、この発明の実施の形態３に関わる半導体装置の形態を、図に基づいて説明する。図において、同じ記号は、同じ、もしくは、同等部分を示す。本実施の形態に関わる半導体装置１００は、半導体チップ１０、バンプ電極９、実装基板２０などを備えている（図１を参照）。半導体チップ１０は、半導体素子３０、第１の層間絶縁膜５、層間絶縁膜配線電極６、第２の層間絶縁膜７、層間絶縁膜表層電極８などから構成されている。半導体チップ１０の半導体素子３０には、ソース電極、ドレイン電極、ゲート電極、グランド電極などが形成されている。実装基板２０は、実装基板本体２１、実装基板電極２２などから構成されている。 Third Embodiment
Hereinafter, the form of a semiconductor device according to the third embodiment of the present invention will be described based on the drawings. In the figures, the same symbols indicate the same or equivalent parts. A semiconductor device 100 according to the present embodiment includes a semiconductor chip 10, bump electrodes 9, a mounting substrate 20 and the like (see FIG. 1). The semiconductor chip 10 includes a semiconductor element 30, a first interlayer insulating film 5, an interlayer insulating film wiring electrode 6, a second interlayer insulating film 7, an interlayer insulating film surface electrode 8, and the like. In the semiconductor element 30 of the semiconductor chip 10, a source electrode, a drain electrode, a gate electrode, a ground electrode, and the like are formed. The mounting substrate 20 includes a mounting substrate body 21, a mounting substrate electrode 22, and the like.
　図１１は、本実施の形態に関わるチップサイズパッケージ構造を有する半導体装置１００の構成を概略的に示している断面図である。半導体基板１には、FET（ Field Effect Transistor ）などの半導体素子３０が形成されている。半導体素子３０は、半導体基板１、ソース電極２、ドレイン電極３（３ａ，３ｂ）、ゲート電極４（４ａ，４ｂ）、などから構成されている。半導体素子３０（半導体基板１）の上には、第１の層間絶縁膜５が配置されている。第１の層間絶縁膜５の上には、第２の層間絶縁膜７が配置されている。層間絶縁膜グランド表層電極８ａと層間絶縁膜ソース表層電極８ｂの間、および、層間絶縁膜グランド表層電極８ｃと層間絶縁膜ソース表層電極８ｂの間には、分離溝８ｄが形成されている。 FIG. 11 is a cross sectional view schematically showing a configuration of a semiconductor device 100 having a chip size package structure according to the present embodiment. On the semiconductor substrate 1, a semiconductor element 30 such as an FET (Field Effect Transistor) is formed. The semiconductor element 30 is configured of a semiconductor substrate 1, source electrode 2, drain electrode 3 (3a, 3b), gate electrode 4 (4a, 4b), and the like. A first interlayer insulating film 5 is disposed on the semiconductor element 30 (semiconductor substrate 1). A second interlayer insulating film 7 is disposed on the first interlayer insulating film 5. A separation groove 8d is formed between the interlayer insulating film ground surface electrode 8a and the interlayer insulating film source surface electrode 8b, and between the interlayer insulating film ground surface electrode 8c and the interlayer insulating film source surface electrode 8b.
　図１２は、層間絶縁膜表層電極８の構成を概略的に示している平面図である。第２の層間絶縁膜７の上には、層間絶縁膜表層電極８（層間絶縁膜ソース表層電極、層間絶縁膜ドレイン表層電極、層間絶縁膜ゲート表層電極、および、層間絶縁膜グランド表層電極）が形成されている。層間絶縁膜グランド表層電極８ａおよび層間絶縁膜グランド表層電極８ｃは、この平面図からわかるように、一体化されていて、グランド電位に設定されている。層間絶縁膜ソース表層電極８ｂは、層間絶縁膜グランド表層電極（８ａ，８ｃ）によって周囲を完全に囲まれている。 FIG. 12 is a plan view schematically showing the configuration of interlayer insulating film surface electrode 8. On the second interlayer insulating film 7, an interlayer insulating film surface electrode 8 (interlayer insulating film source surface electrode, interlayer insulating film drain surface electrode, interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrode) is provided. It is formed. Interlayer insulating film ground surface layer electrode 8a and interlayer insulating film ground surface layer electrode 8c are integrated as shown in this plan view, and are set to the ground potential. The interlayer insulating film source surface layer electrode 8b is completely surrounded by the interlayer insulating film ground surface layer electrodes (8a, 8c).
　分離溝８ｄは、ソースとグランドを分離するために、層間絶縁膜ソース表層電極８ｂと層間絶縁膜グランド表層電極（８ａ，８ｃ）の間に形成されている。本実施の形態に関わる分離溝８ｄは、線状の形状を有しているものが、２個配置されている。線状の形状を有している分離溝８ｄの長さＬ２は、半導体素子３０に形成されているソース電極の長さＬ１よりも大きい。層間絶縁膜ソース表層電極８ｂは、半導体素子３０のソース電極２（およびソース）と電気的に接続されている。層間絶縁膜ドレイン表層電極は、半導体素子３０のドレイン電極３（およびドレイン）と電気的に接続されている。層間絶縁膜ゲート表層電極は、半導体素子３０のゲート電極４（およびゲート）と電気的に接続されている。 The separation groove 8d is formed between the interlayer insulating film source surface layer electrode 8b and the interlayer insulating film ground surface electrode (8a, 8c) in order to separate the source and the ground. Two separation grooves 8d related to the present embodiment, which have a linear shape, are arranged. The length L 2 of the separation groove 8 d having a linear shape is larger than the length L 1 of the source electrode formed in the semiconductor element 30. The interlayer insulating film source surface layer electrode 8 b is electrically connected to the source electrode 2 (and the source) of the semiconductor element 30. The interlayer insulating film drain surface layer electrode is electrically connected to the drain electrode 3 (and the drain) of the semiconductor element 30. The interlayer insulating film gate surface layer electrode is electrically connected to the gate electrode 4 (and the gate) of the semiconductor element 30.
　層間絶縁膜グランド表層電極８ａには、バンプ電極９ａが、例えば、半田を転写する方法等により形成されている。層間絶縁膜ソース表層電極８ｂには、バンプ電極９ｂが、例えば、半田を転写する方法等により形成されている。層間絶縁膜グランド表層電極８ｃには、バンプ電極９ｃが、例えば、半田を転写する方法等により形成されている。同様に、層間絶縁膜ドレイン表層電極および層間絶縁膜ゲート表層電極には、バンプ電極が、例えば、半田を転写する方法等により形成されている。 Bump electrodes 9 a are formed on the interlayer insulating film ground surface electrode 8 a by, for example, a method of transferring solder. Bump electrodes 9 b are formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder. Bump electrodes 9 c are formed on the interlayer insulating film ground surface electrode 8 c by, for example, a method of transferring solder. Similarly, bump electrodes are formed on the interlayer insulating film drain surface electrode and the interlayer insulating film gate surface electrode, for example, by a method of transferring solder.
　図１３は、本実施の形態に関わる実装基板２０の第１の構成を概略的に示している平面図である。実装基板２０（実装基板本体２１）には、実装基板電極２２が形成されている。実装基板電極２２は、実装基板ドレイン電極２２Ｙ、実装基板ゲート電極２２Ｚ、および、実装基板グランド電極２２Ｗから構成されている。実装基板グランド電極２２Ｗは、バンプ電極９ｂと接続されていて、半導体素子３０のソース電極２と電気的に繋がっている。 FIG. 13 is a plan view schematically showing a first configuration of the mounting substrate 20 according to the present embodiment. A mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21). The mounting substrate electrode 22 is configured of a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W. The mounting substrate ground electrode 22 W is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
　さらに、実装基板グランド電極２２Ｗは、バンプ電極９ａおよびバンプ電極９ｃと接続されていて、半導体素子３０のグランド電極と電気的に繋がっている。実装基板ドレイン電極２２Ｙは、バンプ電極９ｄと接続されていて、半導体素子３０のドレイン電極３（３ａ，３ｂ）と電気的に繋がっている。実装基板ゲート電極２２Ｚは、バンプ電極９ｅと接続されていて、半導体素子３０のゲート電極４（４ａ，４ｂ）と電気的に繋がっている。 Furthermore, the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30. The mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30. The mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30.
　図１４は、本実施の形態に関わる実装基板２０の第２の構成を概略的に示している平面図である。実装基板２０（実装基板本体２１）には、実装基板電極２２が形成されている。実装基板電極２２は、実装基板ソース電極２２Ｘ、実装基板ドレイン電極２２Ｙ、実装基板ゲート電極２２Ｚ、および、実装基板グランド電極２２Ｗから構成されている。実装基板ソース電極２２Ｘは、バンプ電極９ｂと接続されていて、半導体素子３０のソース電極２と電気的に繋がっている。 FIG. 14 is a plan view schematically showing a second configuration of the mounting substrate 20 according to the present embodiment. A mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21). The mounting substrate electrode 22 is configured of a mounting substrate source electrode 22X, a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W. The mounting substrate source electrode 22 </ b> X is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
　実装基板ドレイン電極２２Ｙは、バンプ電極９ｄと接続されていて、半導体素子３０のドレイン電極３（３ａ，３ｂ）と電気的に繋がっている。実装基板ゲート電極２２Ｚは、バンプ電極９ｅと接続されていて、半導体素子３０のゲート電極４（４ａ，４ｂ）と電気的に繋がっている。実装基板グランド電極２２Ｗは、バンプ電極９ａおよびバンプ電極９ｃと接続されていて、半導体素子３０のグランド電極と電気的に繋がっている。 The mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30. The mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30. The mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30.
　実装基板グランド電極２２Ｗは、実装基板ソース電極２２Ｘの周囲を完全に囲んでいる。実装基板ソース電極２２Ｘは、グランド電位に設定されているが、実装基板グランド電極２２Ｗとは独立して配設されている。本実施の形態では、ソースとグランドを分離するために、実装基板グランド電極２２Ｗと実装基板ソース電極２２Ｘの間には、線状の形状を有している分離溝２２ｄが形成されている。線状の形状を有している分離溝２２ｄの長さＬ３は、半導体素子３０に形成されているソース電極の長さＬ１よりも大きい。 The mounting substrate ground electrode 22W completely surrounds the mounting substrate source electrode 22X. Although the mounting substrate source electrode 22X is set to the ground potential, it is disposed independently of the mounting substrate ground electrode 22W. In the present embodiment, in order to separate the source and the ground, a separation groove 22d having a linear shape is formed between the mounting substrate ground electrode 22W and the mounting substrate source electrode 22X. The length L 3 of the separation groove 22 d having a linear shape is larger than the length L 1 of the source electrode formed in the semiconductor element 30.
　つぎに、本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００の製造方法について説明する。まず、半導体基板１の上へ、ソース電極２（およびソース）、ドレイン電極３（およびドレイン）、および、ゲート電極４（ゲート）を有するトランジスタ構造を、例えば、蒸着リフトオフ法を用いて形成する。つぎに、第１の層間絶縁膜５を、例えば、ポリイミド塗布/写真製版を用いて形成する。つぎに、層間絶縁膜配線電極６を、例えば、蒸着リフトオフ法を用いて形成する。つぎに、第２の層間絶縁膜７を、例えば、ポリイミド塗布/写真製版を用いて形成する。 Next, a method of manufacturing the semiconductor device 100 compatible with the chip size package according to the present embodiment will be described. First, a transistor structure having a source electrode 2 (and a source), a drain electrode 3 (and a drain), and a gate electrode 4 (gate) is formed on a semiconductor substrate 1 using, for example, a deposition lift-off method. Next, the first interlayer insulating film 5 is formed using, for example, a polyimide coating / photolithography process. Next, the interlayer insulating film wiring electrode 6 is formed by using, for example, a vapor deposition lift-off method. Next, the second interlayer insulating film 7 is formed by using, for example, polyimide coating / photolithography.
　つぎに、層間絶縁膜表層電極８を、例えば、電解メッキ法を用いて形成する。層間絶縁膜表層電極８は、層間絶縁膜ソース表層電極８ｂ、層間絶縁膜ドレイン表層電極、層間絶縁膜ゲート表層電極、および、層間絶縁膜グランド表層電極８ａ，８ｃから構成されている。その際、層間絶縁膜ソース表層電極８ｂに、バンプ電極９ｂの設置箇所を挟んで、分離溝８ｄを、例えば、写真製版工程を用いて形成する。層間絶縁膜グランド表層電極８ａは、層間絶縁膜ソース表層電極８ｂ以外のグランド電位の回路素子と接続される。バンプ電極９ｂは、層間絶縁膜ソース表層電極８ｂに形成される。 Next, the interlayer insulating film surface electrode 8 is formed using, for example, an electrolytic plating method. The interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode 8b, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrodes 8a and 8c. At this time, the separation groove 8d is formed in the interlayer insulating film source surface layer electrode 8b, for example, using a photolithography process, with the installation location of the bump electrode 9b interposed therebetween. The interlayer insulating film ground surface layer electrode 8a is connected to the circuit element of the ground potential other than the interlayer insulating film source surface layer electrode 8b. Bump electrode 9b is formed on interlayer insulating film source surface layer electrode 8b.
　バンプ電極９ａおよびバンプ電極９ｃは、層間絶縁膜グランド表層電極８ａに形成される。バンプ電極９ｂの設置箇所とバンプ電極９ａの設置箇所との間に、層間絶縁膜表層電極が存在しない第１の分離溝８ｄを、形成している。また、バンプ電極９ｂの設置箇所とバンプ電極９ｃの設置箇所との間に、層間絶縁膜表層電極８が存在しない第２の分離溝８ｄを、形成している。分離溝８ｄは、少なくともソース電極２の長さＬ１よりも大きい長さＬ２を有する。つぎに、層間絶縁膜表層電極８の上部へ、バンプ電極９を、例えば、半田を転写する方法等により形成する。 Bump electrode 9a and bump electrode 9c are formed on interlayer insulating film ground surface electrode 8a. A first separation groove 8d in which the interlayer insulating film surface layer electrode does not exist is formed between the installation site of the bump electrode 9b and the installation site of the bump electrode 9a. Further, a second separation groove 8d in which the interlayer insulating film surface layer electrode 8 does not exist is formed between the installation site of the bump electrode 9b and the installation site of the bump electrode 9c. The separation groove 8d has a length L2 greater than at least the length L1 of the source electrode 2. Next, a bump electrode 9 is formed on the upper surface of the interlayer insulating film surface electrode 8 by, for example, a method of transferring solder.
　本実施の形態に関わる半導体装置では、層間絶縁膜ソース表層電極は、ソース電極２に接続し、その上にバンプ電極が形成されている。層間絶縁膜表層電極８に分離溝８ｄを形成する事により、層間絶縁膜ソース表層電極とその他のグランド電位の回路素子との接続距離を長くする事が出来る。その結果、ソース電極２と半導体素子３０のグランド電極と電気的に繋がっている他の回路素子との接続距離が伸びるので、回路素子の間の遮断性を高める事が可能となり、回路素子の間での不要なループ発振を防止する事が出来る。 In the semiconductor device according to the present embodiment, the interlayer insulating film source surface layer electrode is connected to the source electrode 2, and the bump electrode is formed thereon. By forming the separation groove 8d in the interlayer insulating film surface electrode 8, the connection distance between the interlayer insulating film source surface electrode and other circuit elements of the ground potential can be increased. As a result, since the connection distance between the source electrode 2 and the other circuit element electrically connected to the ground electrode of the semiconductor element 30 is extended, it is possible to improve the blocking property between the circuit elements, and between the circuit elements Unnecessary loop oscillation can be prevented.
　本実施の形態に関わる半導体装置は、半導体基板の上にトランジスタのソース電極、ドレイン電極、ゲート電極を備え、その上に層間絶縁膜を介して層間絶縁膜配線電極を配置し、つぎに最上層の電極を層間絶縁膜を介して層間絶縁膜表層電極として配置し、その層間絶縁膜表層電極の上に表面実装用のバンプ電極を配置したチップサイズパッケージ構造を有する半導体装置であり、かつソース電極に接続された層間絶縁膜表層電極とバンプ電極が、他のバンプ電極と最短距離で接続されない様、ソース電極に接続されたバンプ電極と他のバンプ電極の間に、少なくともソース電極の長さ以上の線状に、層間絶縁膜表層電極を取り去った構造を有する事を特徴とする半導体装置である。 The semiconductor device according to the present embodiment includes a source electrode, a drain electrode, and a gate electrode of a transistor on a semiconductor substrate, and an interlayer insulating film wiring electrode is disposed thereon via an interlayer insulating film, and then the uppermost layer is formed. A semiconductor device having a chip size package structure in which the electrode of the present invention is disposed as an interlayer insulating film surface electrode via an interlayer insulating film, and a bump electrode for surface mounting is disposed on the interlayer insulating film surface electrode; Between the bump electrode connected to the source electrode and the other bump electrode so that the interlayer insulating film surface electrode connected to the surface and the bump electrode are not connected at the shortest distance to the other bump electrode, at least the length of the source electrode The semiconductor device is characterized by having a structure in which the interlayer insulating film surface layer electrode is removed in a linear manner.
実施の形態４．
　以下、この発明の実施の形態４に関わる半導体装置の形態を、図に基づいて説明する。図において、同じ記号は、同じ、もしくは、同等部分を示す。本実施の形態に関わる半導体装置１００は、半導体チップ１０、バンプ電極９、実装基板２０などを備えている（図１を参照）。半導体チップ１０は、半導体素子３０、第１の層間絶縁膜５、層間絶縁膜配線電極６、第２の層間絶縁膜７、層間絶縁膜表層電極８などから構成されている。 Fourth Embodiment
Hereinafter, a form of a semiconductor device according to the fourth embodiment of the present invention will be described based on the drawings. In the figures, the same symbols indicate the same or equivalent parts. A semiconductor device 100 according to the present embodiment includes a semiconductor chip 10, bump electrodes 9, a mounting substrate 20 and the like (see FIG. 1). The semiconductor chip 10 includes a semiconductor element 30, a first interlayer insulating film 5, an interlayer insulating film wiring electrode 6, a second interlayer insulating film 7, an interlayer insulating film surface electrode 8, and the like.
　半導体チップ１０の半導体素子３０には、ソース電極、ドレイン電極、ゲート電極、グランド電極などが形成されている。実装基板２０は、実装基板本体２１、実装基板電極２２などから構成されている。本実施の形態に関わる半導体装置では、実装基板電極２２は、実装基板ドレイン電極、実装基板ゲート電極、および、実装基板グランド電極から構成されている。 In the semiconductor element 30 of the semiconductor chip 10, a source electrode, a drain electrode, a gate electrode, a ground electrode, and the like are formed. The mounting substrate 20 includes a mounting substrate body 21, a mounting substrate electrode 22, and the like. In the semiconductor device according to the present embodiment, the mounting substrate electrode 22 includes the mounting substrate drain electrode, the mounting substrate gate electrode, and the mounting substrate ground electrode.
　図１５は、本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００の構成を概略的に示している断面図である。半導体基板１には、FET（ Field Effect Transistor ）などの半導体素子３０が形成されている。半導体素子３０は、半導体基板１、ソース電極２、ドレイン電極３（３ａ，３ｂ）、ゲート電極４（４ａ，４ｂ）、などから構成されている。半導体素子３０（半導体基板１）の上には、第１の層間絶縁膜５が配置されている。第１の層間絶縁膜５の上には、第２の層間絶縁膜７が配置されている。 FIG. 15 is a cross sectional view schematically showing a configuration of a semiconductor device 100 compatible with a chip size package according to the present embodiment. On the semiconductor substrate 1, a semiconductor element 30 such as an FET (Field Effect Transistor) is formed. The semiconductor element 30 is configured of a semiconductor substrate 1, source electrode 2, drain electrode 3 (3a, 3b), gate electrode 4 (4a, 4b), and the like. A first interlayer insulating film 5 is disposed on the semiconductor element 30 (semiconductor substrate 1). A second interlayer insulating film 7 is disposed on the first interlayer insulating film 5.
　本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００では、層間絶縁膜ソース表層電極８ｂは、層間絶縁膜ソース配線電極６ｂおよびソース電極２の直上に配置されている。層間絶縁膜グランド表層電極８ａと層間絶縁膜ソース表層電極８ｂの間、および、層間絶縁膜グランド表層電極８ｃと層間絶縁膜ソース表層電極８ｂの間には、分離溝８ｄが形成されている。実装基板ソース電極２２Ｘと実装基板グランド電極２２Ｗの間には、分離溝２２ｄが形成されている。 In the semiconductor device 100 compatible with the chip size package according to the present embodiment, the interlayer insulating film source surface layer electrode 8 b is disposed directly on the interlayer insulating film source wiring electrode 6 b and the source electrode 2. A separation groove 8d is formed between the interlayer insulating film ground surface electrode 8a and the interlayer insulating film source surface electrode 8b, and between the interlayer insulating film ground surface electrode 8c and the interlayer insulating film source surface electrode 8b. A separation groove 22d is formed between the mounting substrate source electrode 22X and the mounting substrate ground electrode 22W.
　図１６は、本実施の形態に関わる層間絶縁膜表層電極８の構成を概略的に示している平面図である。第２の層間絶縁膜７の上には、層間絶縁膜表層電極８（層間絶縁膜ソース表層電極、層間絶縁膜ドレイン表層電極、層間絶縁膜ゲート表層電極、および、層間絶縁膜グランド表層電極）が形成されている。層間絶縁膜グランド表層電極８ａおよび層間絶縁膜グランド表層電極８ｃは、この平面図からわかるように、一体化されていて、グランド電位に設定されている。層間絶縁膜ソース表層電極８ｂは、層間絶縁膜グランド表層電極（８ａ，８ｃ）によって周囲を完全に囲まれている。 FIG. 16 is a plan view schematically showing the configuration of the interlayer insulating film surface electrode 8 according to the present embodiment. On the second interlayer insulating film 7, an interlayer insulating film surface electrode 8 (interlayer insulating film source surface electrode, interlayer insulating film drain surface electrode, interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrode) is provided. It is formed. Interlayer insulating film ground surface layer electrode 8a and interlayer insulating film ground surface layer electrode 8c are integrated as shown in this plan view, and are set to the ground potential. The interlayer insulating film source surface layer electrode 8b is completely surrounded by the interlayer insulating film ground surface layer electrodes (8a, 8c).
　分離溝８ｄは、ソースとグランドを分離するために、層間絶縁膜ソース表層電極８ｂと層間絶縁膜グランド表層電極（８ａ，８ｃ）の間に形成されている。本実施の形態に関わる分離溝８ｄは、線状の形状を有しているものが、２個配置されている。線状の形状を有している分離溝８ｄの長さＬ２は、半導体素子３０に形成されているソース電極の長さＬ１よりも大きい。層間絶縁膜ソース表層電極８ｂは、半導体素子３０のソース電極２（およびソース）と電気的に接続されている。層間絶縁膜ドレイン表層電極は、半導体素子３０のドレイン電極３（およびドレイン）と電気的に接続されている。層間絶縁膜ゲート表層電極は、半導体素子３０のゲート電極４（およびゲート）と電気的に接続されている。 The separation groove 8d is formed between the interlayer insulating film source surface layer electrode 8b and the interlayer insulating film ground surface electrode (8a, 8c) in order to separate the source and the ground. Two separation grooves 8d related to the present embodiment, which have a linear shape, are arranged. The length L 2 of the separation groove 8 d having a linear shape is larger than the length L 1 of the source electrode formed in the semiconductor element 30. The interlayer insulating film source surface layer electrode 8 b is electrically connected to the source electrode 2 (and the source) of the semiconductor element 30. The interlayer insulating film drain surface layer electrode is electrically connected to the drain electrode 3 (and the drain) of the semiconductor element 30. The interlayer insulating film gate surface layer electrode is electrically connected to the gate electrode 4 (and the gate) of the semiconductor element 30.
　層間絶縁膜グランド表層電極８ａには、バンプ電極９ａが、例えば、半田を転写する方法等により形成されている。層間絶縁膜ソース表層電極８ｂには、バンプ電極９ｂが、例えば、半田を転写する方法等により形成されている。層間絶縁膜グランド表層電極８ｃには、バンプ電極９ｃが、例えば、半田を転写する方法等により形成されている。同様に、層間絶縁膜ドレイン表層電極および層間絶縁膜ゲート表層電極には、バンプ電極が、例えば、半田を転写する方法等により形成されている。 Bump electrodes 9 a are formed on the interlayer insulating film ground surface electrode 8 a by, for example, a method of transferring solder. Bump electrodes 9 b are formed on the interlayer insulating film source surface layer electrode 8 b by, for example, a method of transferring solder. Bump electrodes 9 c are formed on the interlayer insulating film ground surface electrode 8 c by, for example, a method of transferring solder. Similarly, bump electrodes are formed on the interlayer insulating film drain surface electrode and the interlayer insulating film gate surface electrode, for example, by a method of transferring solder.
　図１７は、本実施の形態に関わる実装基板２０の第１の構成を概略的に示している平面図である。実装基板２０（実装基板本体２１）には、実装基板電極２２が形成されている。実装基板電極２２は、実装基板ドレイン電極２２Ｙ、実装基板ゲート電極２２Ｚ、および、実装基板グランド電極２２Ｗから構成されている。実装基板グランド電極２２Ｗは、バンプ電極９ｂと接続されていて、半導体素子３０のソース電極２と電気的に繋がっている。 FIG. 17 is a plan view schematically showing a first configuration of the mounting substrate 20 according to the present embodiment. A mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21). The mounting substrate electrode 22 is configured of a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W. The mounting substrate ground electrode 22 W is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30.
　さらに、実装基板グランド電極２２Ｗは、バンプ電極９ａおよびバンプ電極９ｃと接続されていて、半導体素子３０のグランド電極と電気的に繋がっている。実装基板ドレイン電極２２Ｙは、バンプ電極９ｄと接続されていて、半導体素子３０のドレイン電極３（３ａ，３ｂ）と電気的に繋がっている。実装基板ゲート電極２２Ｚは、バンプ電極９ｅと接続されていて、半導体素子３０のゲート電極４（４ａ，４ｂ）と電気的に繋がっている。本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００では、バンプ電極９ｂは、実装基板グランド電極２２Ｗの真中に配置されている。 Furthermore, the mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30. The mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30. The mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30. In the semiconductor device 100 compatible with the chip size package according to the present embodiment, the bump electrode 9b is disposed in the center of the mounting substrate ground electrode 22W.
　図１８は、本実施の形態に関わる実装基板２０の第２の構成を概略的に示している平面図である。実装基板２０（実装基板本体２１）には、実装基板電極２２が形成されている。実装基板電極２２は、実装基板ソース電極２２Ｘ、実装基板ドレイン電極２２Ｙ、実装基板ゲート電極２２Ｚ、および、実装基板グランド電極２２Ｗから構成されている。実装基板ソース電極２２Ｘは、バンプ電極９ｂと接続されていて、半導体素子３０のソース電極２と電気的に繋がっている。実装基板ドレイン電極２２Ｙは、バンプ電極９ｄと接続されていて、半導体素子３０のドレイン電極３（３ａ，３ｂ）と電気的に繋がっている。 FIG. 18 is a plan view schematically showing a second configuration of the mounting substrate 20 according to the present embodiment. A mounting substrate electrode 22 is formed on the mounting substrate 20 (mounting substrate main body 21). The mounting substrate electrode 22 is configured of a mounting substrate source electrode 22X, a mounting substrate drain electrode 22Y, a mounting substrate gate electrode 22Z, and a mounting substrate ground electrode 22W. The mounting substrate source electrode 22 </ b> X is connected to the bump electrode 9 b and electrically connected to the source electrode 2 of the semiconductor element 30. The mounting substrate drain electrode 22Y is connected to the bump electrode 9d, and is electrically connected to the drain electrode 3 (3a, 3b) of the semiconductor element 30.
　実装基板ゲート電極２２Ｚは、バンプ電極９ｅと接続されていて、半導体素子３０のゲート電極４（４ａ，４ｂ）と電気的に繋がっている。実装基板グランド電極２２Ｗは、バンプ電極９ａおよびバンプ電極９ｃと接続されていて、半導体素子３０のグランド電極と電気的に繋がっている。実装基板グランド電極２２Ｗは、実装基板ソース電極２２Ｘの周囲を完全に囲んでいる。実装基板ソース電極２２Ｘは、グランド電位に設定されているが、実装基板グランド電極２２Ｗとは独立して配設されている。 The mounting substrate gate electrode 22Z is connected to the bump electrode 9e and is electrically connected to the gate electrode 4 (4a, 4b) of the semiconductor element 30. The mounting substrate ground electrode 22 W is connected to the bump electrode 9 a and the bump electrode 9 c, and is electrically connected to the ground electrode of the semiconductor element 30. The mounting substrate ground electrode 22W completely surrounds the mounting substrate source electrode 22X. Although the mounting substrate source electrode 22X is set to the ground potential, it is disposed independently of the mounting substrate ground electrode 22W.
　本実施の形態では、ソースとグランドを分離するために、実装基板グランド電極２２Ｗと実装基板ソース電極２２Ｘの間には、線状の形状を有している分離溝２２ｄが形成されている。線状の形状を有している分離溝２２ｄの長さＬ３は、半導体素子３０に形成されているソース電極の長さＬ１よりも大きい。本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００では、バンプ電極９ｂは、実装基板ソース電極２２Ｘの真中に配置されている。 In the present embodiment, in order to separate the source and the ground, a separation groove 22d having a linear shape is formed between the mounting substrate ground electrode 22W and the mounting substrate source electrode 22X. The length L 3 of the separation groove 22 d having a linear shape is larger than the length L 1 of the source electrode formed in the semiconductor element 30. In the semiconductor device 100 compatible with the chip size package according to the present embodiment, the bump electrode 9b is disposed in the center of the mounting substrate source electrode 22X.
　つぎに、本実施の形態に関わるチップサイズパッケージ対応の半導体装置１００の製造方法について説明する。まず、半導体基板１の上へ、ソース電極２（およびソース）、ドレイン電極３（およびドレイン）、および、ゲート電極４（ゲート）を有するトランジスタ構造を、例えば、蒸着リフトオフ法を用いて形成する。つぎに、第１の層間絶縁膜５を、例えば、ポリイミド塗布/写真製版を用いて形成する。つぎに、層間絶縁膜配線電極６を、例えば、蒸着リフトオフ法を用いて形成する。その際、ソース電極２と層間絶縁膜ソース表層電極８ｂを接続する層間絶縁膜ソース配線電極６ｂは、ソース電極２の直上に形成する。つぎに、第２の層間絶縁膜７を、例えば、ポリイミド塗布/写真製版を用いて形成する。 Next, a method of manufacturing the semiconductor device 100 compatible with the chip size package according to the present embodiment will be described. First, a transistor structure having a source electrode 2 (and a source), a drain electrode 3 (and a drain), and a gate electrode 4 (gate) is formed on a semiconductor substrate 1 using, for example, a deposition lift-off method. Next, the first interlayer insulating film 5 is formed using, for example, a polyimide coating / photolithography process. Next, the interlayer insulating film wiring electrode 6 is formed by using, for example, a vapor deposition lift-off method. At that time, an interlayer insulating film source wiring electrode 6 b connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8 b is formed directly on the source electrode 2. Next, the second interlayer insulating film 7 is formed by using, for example, polyimide coating / photolithography.
　つぎに、層間絶縁膜表層電極８を、例えば、電解メッキ法を用いて形成する。層間絶縁膜表層電極８は、層間絶縁膜ソース表層電極８ｂ、層間絶縁膜ドレイン表層電極、層間絶縁膜ゲート表層電極、および、層間絶縁膜グランド表層電極８ａ，８ｃから構成されている。その際、層間絶縁膜ソース表層電極８ｂに、バンプ電極９ｂの設置箇所を挟んで、分離溝８ｄを、例えば、写真製版工程を用いて形成する。層間絶縁膜グランド表層電極８ａは、層間絶縁膜ソース表層電極８ｂ以外のグランド電位の回路素子と接続される。バンプ電極９ｂは、層間絶縁膜ソース表層電極８ｂに形成される。 Next, the interlayer insulating film surface electrode 8 is formed using, for example, an electrolytic plating method. The interlayer insulating film surface electrode 8 is composed of an interlayer insulating film source surface electrode 8b, an interlayer insulating film drain surface electrode, an interlayer insulating film gate surface electrode, and interlayer insulating film ground surface electrodes 8a and 8c. At this time, the separation groove 8d is formed in the interlayer insulating film source surface layer electrode 8b, for example, using a photolithography process, with the installation location of the bump electrode 9b interposed therebetween. The interlayer insulating film ground surface layer electrode 8a is connected to the circuit element of the ground potential other than the interlayer insulating film source surface layer electrode 8b. Bump electrode 9b is formed on interlayer insulating film source surface layer electrode 8b.
　バンプ電極９ａおよびバンプ電極９ｃは、層間絶縁膜グランド表層電極８ａに形成される。バンプ電極９ｂの設置箇所とバンプ電極９ａの設置箇所との間に、層間絶縁膜表層電極が存在しない第１の分離溝８ｄを、形成している。また、バンプ電極９ｂの設置箇所とバンプ電極９ｃの設置箇所との間に、層間絶縁膜表層電極８が存在しない第２の分離溝８ｄを、形成している。分離溝８ｄは、少なくともソース電極２の長さＬ１よりも大きい長さＬ２を有する。つぎに、層間絶縁膜表層電極８の上部へ、バンプ電極９を、例えば、半田を転写する方法等により形成する。 Bump electrode 9a and bump electrode 9c are formed on interlayer insulating film ground surface electrode 8a. A first separation groove 8d in which the interlayer insulating film surface layer electrode does not exist is formed between the installation site of the bump electrode 9b and the installation site of the bump electrode 9a. Further, a second separation groove 8d in which the interlayer insulating film surface layer electrode 8 does not exist is formed between the installation site of the bump electrode 9b and the installation site of the bump electrode 9c. The separation groove 8d has a length L2 greater than at least the length L1 of the source electrode 2. Next, a bump electrode 9 is formed on the upper surface of the interlayer insulating film surface electrode 8 by, for example, a method of transferring solder.
　本実施の形態に関わる半導体装置では、層間絶縁膜ソース表層電極８ｂは、ソース電極２に接続し、その上にバンプ電極９ｂが形成されている。層間絶縁膜表層電極８には、電極材が存在しない分離溝８ｄを形成している。このことにより、ソース電極２を、半導体装置の上にて、他の回路素子から電気的に遠ざける事が出来る。また、ソース電極２と層間絶縁膜ソース表層電極８ｂを接続する層間絶縁膜ソース配線電極６ｂを、ソース電極２の直上へ設置する事で、ソース電極２と層間絶縁膜ソース表層電極８ｂを最短距離で接続する事が出来る。 In the semiconductor device according to the present embodiment, interlayer insulating film source surface layer electrode 8b is connected to source electrode 2, and bump electrode 9b is formed thereon. In the interlayer insulating film surface layer electrode 8, a separation groove 8d in which no electrode material exists is formed. As a result, the source electrode 2 can be electrically separated from other circuit elements on the semiconductor device. Further, the interlayer insulating film source wiring electrode 6b connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8b is disposed immediately above the source electrode 2, whereby the shortest distance between the source electrode 2 and the interlayer insulating film source surface layer electrode 8b You can connect with.
　また、層間絶縁膜ソース表層電極８ｂとその他のグランド電位の回路素子との接続距離を長くする事が出来る。その結果、ソース電極２と半導体素子３０のグランド電極と電気的に繋がっている他の回路素子との接続距離が伸びるので、回路素子の間の遮断性を高める事が可能となり、回路素子の間での不要なループ発振を防止する事が出来る。さらに、ソース電極２と層間絶縁膜ソース表層電極８ｂを最短距離で接続する事で、寄生抵抗成分と寄生インダクタンス成分が低減し、トランジスタ特性の低下を抑制する事も出来る。 Further, the connection distance between the interlayer insulating film source surface layer electrode 8 b and the circuit element of the other ground potential can be increased. As a result, since the connection distance between the source electrode 2 and the other circuit element electrically connected to the ground electrode of the semiconductor element 30 is extended, it is possible to improve the blocking property between the circuit elements, and between the circuit elements Unnecessary loop oscillation can be prevented. Furthermore, by connecting the source electrode 2 and the interlayer insulating film source surface layer electrode 8b at the shortest distance, the parasitic resistance component and the parasitic inductance component can be reduced, and the deterioration of the transistor characteristics can be suppressed.
　本実施の形態に関わる半導体装置は、実施の形態３に記載した半導体装置であり、かつソース電極と層間絶縁膜ソース表層電極の間をソース電極の直上にて接続した事を特徴とする半導体装置である。すなわち、前記層間絶縁膜ソース表層電極は、前記ソース電極の直上に配置されていることを特徴とする半導体装置である。 The semiconductor device according to the present embodiment is the semiconductor device described in the third embodiment, and is characterized in that the source electrode and the interlayer insulating film source surface layer electrode are connected immediately above the source electrode. It is. That is, the semiconductor device is characterized in that the interlayer insulating film source surface layer electrode is disposed immediately above the source electrode.
　なお、実施の形態１～４で、ソース電極２、ドレイン電極３、ゲート電極４、層間絶縁膜配線電極６、層間絶縁膜表層電極８の形成に用いた方法は、同様の形状を形成することが出来るならば他の方法を用いても構わない。また、第１の層間絶縁膜５および第２の層間絶縁膜７に用いる材料と製造方法は、同様の構造を形成できるのであれば、他の材料（複合使用も可）や製造方法を用いても構わない。また、第２の層間絶縁膜７と層間絶縁膜表層電極８の間に、複数の層間絶縁膜配線電極と層間絶縁膜の組み合わせを挿入しても構わない。 In the first to fourth embodiments, the method used for forming the source electrode 2, drain electrode 3, gate electrode 4, interlayer insulating film wiring electrode 6, and interlayer insulating film surface electrode 8 has a similar shape. If it is possible, other methods may be used. In addition, if materials and manufacturing methods used for first interlayer insulating film 5 and second interlayer insulating film 7 can form the same structure, other materials (combined use is also possible) and manufacturing methods are used. I don't care. Further, a combination of a plurality of interlayer insulating film wiring electrodes and an interlayer insulating film may be inserted between the second interlayer insulating film 7 and the interlayer insulating film surface electrode 8.
　本発明の特徴は、FETなどの半導体素子のソース電極に接続するグランド電極を、周囲のグランド電極から独立させる事で、グランド電極に接続されたソース電極同士がお互いに影響を受ける効果を削減し、発振しにくいチップサイズパッケージ対応のFET構造を得る事が出来ることにある。 The feature of the present invention is that the ground electrode connected to the source electrode of the semiconductor element such as FET is made independent from the surrounding ground electrode, thereby reducing the effect of the source electrodes connected to the ground electrode being influenced each other. It is possible to obtain an FET structure compatible with a chip size package which is hard to oscillate.
　本実施の形態に関わる半導体装置は、半導体基板の上にソース、ドレイン、ゲート電極を敷設したFET構造と、そのFET構造と絶縁層を挟んで設置されたグランド電極、及びグランド電極上に実装基板と接続させる為のボールグリッドアレイ電極を備えており、かつFET構造のソース電極が周囲から独立したグランド電極と接続されている事を特徴とした半導体装置である。本実施の形態に関わる半導体装置は、実施の形態３に記した半導体装置であり、かつソース電極と層間絶縁膜ソース表層電極の間をソース電極の直上にて接続した事を特徴とする半導体装置である。 The semiconductor device according to the present embodiment includes an FET structure in which a source, a drain, and a gate electrode are provided on a semiconductor substrate, a ground electrode provided with the FET structure and an insulating layer interposed therebetween, and a mounting substrate on the ground electrode. And a ball grid array electrode for connection to the semiconductor device, and the source electrode of the FET structure is connected to a ground electrode independent of the surroundings. The semiconductor device according to the present embodiment is the semiconductor device described in the third embodiment, and is characterized in that the source electrode and the interlayer insulating film source surface layer electrode are connected directly above the source electrode. It is.
　なお、本発明は、その発明の範囲内において、実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。 In the present invention, within the scope of the invention, the embodiments can be freely combined, and the embodiments can be appropriately modified or omitted.
１　半導体装置、２　ソース電極、３　ドレイン電極、４　ゲート電極、５　第１の層間絶縁膜、６　層間絶縁膜配線電極、６ａ　層間絶縁膜ドレイン配線電極、６ｂ　層間絶縁膜ソース配線電極、６ｃ　層間絶縁膜ドレイン配線電極、６ｄ　層間絶縁膜ゲート配線電極、７　第２の層間絶縁膜、８　層間絶縁膜表層電極、８ａ　層間絶縁膜グランド表層電極、８ｂ　層間絶縁膜ソース表層電極、８ｃ　層間絶縁膜グランド表層電極、８ｄ　分離溝、９　バンプ電極、１０　半導体チップ、１１　グランド電極、２０　実装基板、２１　実装基板本体、２２　実装基板電極、２２ｄ　分離溝、２２Ｘ　実装基板ソース電極、２２Ｙ　実装基板ドレイン電極、２２Ｚ　実装基板ゲート電極、２２Ｗ　実装基板グランド電極、３０　半導体素子、１００　半導体装置 REFERENCE SIGNS LIST 1 semiconductor device, 2 source electrode, 3 drain electrode, 4 gate electrode, 5 first interlayer insulating film, 6 interlayer insulating film wiring electrode, 6 a interlayer insulating film drain wiring electrode, 6 b interlayer insulating film source wiring electrode, 6 c interlayer insulating Film drain wiring electrode, 6d interlayer insulating film gate wiring electrode, 7 second interlayer insulating film, 8 interlayer insulating film surface electrode, 8a interlayer insulating film ground surface electrode, 8b interlayer insulating film source surface electrode, 8c interlayer insulating film ground surface layer Electrode 8d separation groove 9 bump electrode 10 semiconductor chip 11 ground electrode 20 mounting substrate 21 mounting substrate main body 22 mounting substrate electrode 22d separation groove 22X mounting substrate source electrode 22Y mounting substrate drain electrode 22Z mounting Substrate gate electrode, 22 W mounting substrate ground electrode, 30 semiconductor elements, 00 semiconductor device

Claims (7)

  1. 　ソース電極、ドレイン電極、および、ゲート電極が形成されている半導体素子と、
    前記半導体素子の上に配置され、層間絶縁膜ソース配線電極、層間絶縁膜ドレイン配線電極および層間絶縁膜ゲート配線電極が形成されている第１の層間絶縁膜と、
    前記第１の層間絶縁膜の上に配置され、層間絶縁膜ソース表層電極および層間絶縁膜グランド表層電極が形成されている第２の層間絶縁膜と、
    前記第２の層間絶縁膜に形成されている層間絶縁膜ソース表層電極の上に配置された第１のバンプ電極と、
    前記第２の層間絶縁膜に形成されている層間絶縁膜グランド表層電極の上に配置された第２のバンプ電極と、
    前記第１のバンプ電極および前記第２のバンプ電極と接続されている実装基板と、を備え、
    前記層間絶縁膜ソース配線電極は、前記ソース電極および前記層間絶縁膜ソース表層電極と繋がっており、
    しかも、前記層間絶縁膜ソース表層電極は、前記層間絶縁膜グランド表層電極によって囲まれていて、前記層間絶縁膜ソース表層電極と前記層間絶縁膜グランド表層電極の間には、分離溝が形成されていることを特徴とする半導体装置。     A semiconductor element in which a source electrode, a drain electrode, and a gate electrode are formed;
    A first interlayer insulating film disposed on the semiconductor element, in which an interlayer insulating film source wiring electrode, an interlayer insulating film drain wiring electrode, and an interlayer insulating film gate wiring electrode are formed;
    A second interlayer insulating film disposed on the first interlayer insulating film, wherein an interlayer insulating film source surface electrode and an interlayer insulating film ground surface electrode are formed;
    A first bump electrode disposed on an interlayer insulating film source surface layer electrode formed on the second interlayer insulating film;
    A second bump electrode disposed on an interlayer insulating film ground surface layer electrode formed on the second interlayer insulating film;
    And a mounting substrate connected to the first bump electrode and the second bump electrode.
    The interlayer insulating film source wiring electrode is connected to the source electrode and the interlayer insulating film source surface layer electrode,
    Moreover, the interlayer insulating film source surface layer electrode is surrounded by the interlayer insulating film ground surface layer electrode, and a separation groove is formed between the interlayer insulating film source surface electrode and the interlayer insulating film ground surface electrode. A semiconductor device characterized by
  2. 　前記分離溝は、前記層間絶縁膜ソース表層電極の周囲を囲んでいることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the separation groove surrounds the periphery of the interlayer insulating film source surface layer electrode.
  3. 　前記分離溝は、線状の形状を有していることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the separation groove has a linear shape.
  4. 　前記線状の形状を有している分離溝は、前記半導体素子に形成されているソース電極よりも長さが長いことを特徴とする請求項３に記載の半導体装置。 The semiconductor device according to claim 3, wherein the separation groove having the linear shape is longer in length than a source electrode formed in the semiconductor element.
  5. 　前記層間絶縁膜ソース表層電極は、前記ソース電極の直上に配置されていることを特徴とする請求項１から４のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4, wherein the interlayer insulating film source surface layer electrode is disposed directly on the source electrode.
  6. 　前記実装基板には、実装基板ゲート電極、実装基板ドレイン電極、および実装基板グランド電極が形成されていることを特徴とする請求項１から５のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 5, wherein a mounting substrate gate electrode, a mounting substrate drain electrode, and a mounting substrate ground electrode are formed on the mounting substrate.
  7. 　前記実装基板には、実装基板ソース電極、実装基板ゲート電極、実装基板ドレイン電極、および実装基板グランド電極が形成されており、前記実装基板ソース電極は、前記実装基板グランド電極によって、周囲が囲まれていて、前記実装基板ソース電極と前記実装基板グランド電極の間には、分離溝が形成されていることを特徴とする請求項１から５のいずれか１項に記載の半導体装置。 A mounting substrate source electrode, a mounting substrate gate electrode, a mounting substrate drain electrode, and a mounting substrate ground electrode are formed on the mounting substrate, and the mounting substrate source electrode is surrounded by the mounting substrate ground electrode. The semiconductor device according to any one of claims 1 to 5, wherein a separation groove is formed between the mounting substrate source electrode and the mounting substrate ground electrode.
PCT/JP2017/044823 2017-12-14 2017-12-14 Semiconductor device WO2019116482A1 (en)

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Citations (5)

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JP2007194305A (en) * 2006-01-18 2007-08-02 Renesas Technology Corp Semiconductor device
JP2007243222A (en) * 2007-05-22 2007-09-20 Ricoh Co Ltd Semiconductor device
JP2011505705A (en) * 2007-12-04 2011-02-24 エーティーアイ・テクノロジーズ・ユーエルシー Method and apparatus for under bump wiring layer
JP2012009602A (en) * 2010-06-24 2012-01-12 Nec Corp Substrate incorporating integrated circuit element and integrated circuit element to be incorporated therein
JP2014175566A (en) * 2013-03-12 2014-09-22 Mitsubishi Electric Corp Semiconductor device and switch

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194305A (en) * 2006-01-18 2007-08-02 Renesas Technology Corp Semiconductor device
JP2007243222A (en) * 2007-05-22 2007-09-20 Ricoh Co Ltd Semiconductor device
JP2011505705A (en) * 2007-12-04 2011-02-24 エーティーアイ・テクノロジーズ・ユーエルシー Method and apparatus for under bump wiring layer
JP2012009602A (en) * 2010-06-24 2012-01-12 Nec Corp Substrate incorporating integrated circuit element and integrated circuit element to be incorporated therein
JP2014175566A (en) * 2013-03-12 2014-09-22 Mitsubishi Electric Corp Semiconductor device and switch

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