JP2007243222A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a driver transistor is arranged under electrode pads so as to prevent shortage between the source and the drain of the driver transistor and relax current crowding in a metal wiring layer. <P>SOLUTION: In the semiconductor device, an electrode pad for source potential 23s and an electrode pad for drain potential 23d are provided on a driver transistor forming region 5, and as for one-layer-under metal wiring layers 17s-3 and 17d-3, only the one-layer-under metal wiring layer for source potential 17s-3 is provided directly under the electrode pad 23s, and only the one-layer-under metal wiring layer for drain potential 17d-3 is provided directly under the electrode pad 23d. A metal wiring layer for source potential 17s-2 and a metal wiring layer for drain potential 17d-2 are provided directly under the electrode pads 23s and 23d, respectively. The potential of the metal wiring layer for source potential 17s-2 is drawn to a plurality of one-layer-under metal wiring layers for source potential 17s-3, and the potential of the metal wiring layer for drain potential 17d-2 is drawn to a plurality of one-layer-under metal wiring layers for drain potential 17d-3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device provided with an electrode pad. The electrode pads are contacted with terminals such as bonding wires and solder bumps for electrically connecting the semiconductor device to the outside, and test terminals for testing the semiconductor device.

In a semiconductor device having an electrode pad, no device is generally disposed under the electrode pad.
FIG. 10 shows a schematic configuration diagram in the vicinity of a conventional electrode pad. FIG. 10A is a plan view, and FIG. 10B is a cross-sectional view taken along the line AA in FIG.
An interlayer insulating film 13 is formed on the semiconductor substrate 1. A metal wiring layer 17 made of a metal material is formed on the interlayer insulating film 13. A final protective film 19 is formed on the interlayer insulating film 13 including the formation region of the metal wiring layer 17. The final protective film 19 has a pad opening 21 on the metal wiring layer 17 in a region to be the electrode pad 23. Terminals such as bonding wires and solder bumps are connected to the electrode pads 23 through pad openings 21.

In FIG. 10, a semiconductor device having a single-layer metal wiring layer structure is taken as an example, but electrode pads are also arranged in a semiconductor device having a multilayer metal wiring layer structure of two or more layers.
FIG. 11 shows a case of a four-layer metal wiring layer structure, for example. 11A, 11B, and 11C are cross-sectional views showing different prior arts.

In FIG. 11A, reference numerals 17-1, 17-2, 17-3, and 17-4 denote a first metal wiring layer, a second metal wiring layer, a third metal wiring layer, and a fourth metal, respectively. It is a wiring layer, and the fourth metal wiring layer 17-4 constitutes the electrode pad 23. Reference numerals 13-1, 13-2, 13-3, and 13-4 denote a BPSG (boro-phosphosilicate glass) film, a first interlayer insulating film, a second interlayer insulating film, and a third interlayer insulating film, respectively. . A final protective film 19 is formed on the third interlayer insulating film 13-4. The final protective film 19 has a pad opening 21 on the electrode pad 23. The interlayer insulating films 13-2, 13-3, and 13-4 are provided with through holes 15-2, 15-3, and 15-4 that connect the upper and lower metal wiring layers.
Further, since the uppermost metal wiring layer 17-4 is generally used as the electrode pad 23, the first metal wiring layer, the second metal wiring layer, and the third metal wiring layer are formed under the electrode pad 23 as shown in FIG. There is no problem in operation even if the first metal wiring layer is not formed.
Further, as shown in (C), there is no problem even if the through holes 15-2, 15-3, 15-4 are not provided as compared with (A).

By the way, although it is common not to arrange a device under an electrode pad, there is a conventional technique in which a device is arranged under an electrode pad (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).
In patent document 1, the diode which is an input protection element is arrange | positioned under the electrode pad. Furthermore, it is proposed that the diodes are arranged at the four corners of the electrode pad so that the impact applied to the electrode pad is not applied to the diode.
Patent Document 2 proposes that the stress applied to the electrode pad is dispersed by providing irregularities on the surface of the electrode pad, and the stress applied to the device immediately below the electrode pad is relaxed.
In Patent Document 3, an input protection element is disposed under an electrode pad.

  In addition, in the semiconductor device manufacturing process, after electrode pads are formed, a test selection using a probe card, that is, a wafer test process is performed. 12A and 12B are diagrams for explaining the wafer test. FIG. 12A is a plan view of the entire semiconductor device, FIGS. 12B and 12C are cross-sectional views showing the vicinity of one electrode pad, and FIG. The state before contacting the probe, (C) shows the state after contacting the metal probe.

  As shown in FIG. 12A, in the wafer test process, a wafer test is performed by bringing a metal probe 27 into contact with the electrode pad 23 formed on the semiconductor device 25. After the metal probe 27 is disposed on the electrode pad 23 as shown in (B), the metal probe 27 is brought into contact with the electrode pad 23 as shown in (C). At this time, in order to make the electrical connection between the electrode pad 23 and the metal probe 27 more reliable, the metal probe 27 is deeper than the surface height of the electrode pad 23 by, for example, about 50 μm (micrometer) to about 100 μm. It is pushed (in the direction of piercing the electrode pad 23). Further, in order to increase the number of tests per hour as much as possible, the metal probe 27 is moved at a high speed. Therefore, the metal probe 27 collides with the electrode pad 23 at a high speed.

It has been found by the inventors' investigation that “cracking” occurs in the interlayer insulating film 13 under the electrode pad 23 due to an impact when the metal probe 27 comes into contact with the electrode pad 23.
FIG. 13 is a photomicrograph showing a cross section of the state after the metal probe is brought into contact.
This evaluation sample is formed with a four-layer metal wiring layer structure, and reference numerals 17-1, 17-2, 17-3, and 17-4 denote a first metal wiring layer, a second metal wiring layer, and a third layer, respectively. This is the fourth metal wiring layer. The fourth metal wiring layer 17-4 constitutes an electrode pad 23.

In FIG. 13, a crack 29 can be confirmed under the electrode pad 23 of the third interlayer insulating film 13-4 between the electrode pad 23 and the third metal wiring layer 17-3. The crack 29 penetrates from the top surface to the bottom surface of the third interlayer insulating film 13-4, and the electrode pad 23 and the third metal wiring layer 17-3 are electrically short-circuited by the crack 29. I was able to confirm.
This means that when a device is arranged under the electrode pad 23, the electrode pad 23 and the metal wiring layer (the third metal wiring layer 17-3) below it are electrically connected by an impact applied to the electrode pad 23 during the wafer test. This means that the circuit is short-circuited and does not operate normally. That is, in order to dispose the element under the electrode pad, it is necessary to avoid a short circuit failure between the metal wiring layers due to the “cracking” by some method.

  Incidentally, a driver transistor is a device mounted on a semiconductor device. Here, the term “driver transistor” is used to mean “a transistor having a relatively large channel width for driving the next-stage element”. As an example of the driver transistor, a description will be given using a charging circuit frequently used in a mobile phone.

  FIG. 14 is a schematic circuit diagram of the charging device. A rechargeable battery 31 is connected to a power source 35 (corresponding to a household AC outlet) via a charge switch 33. (A) shows the state before charging, and the transistor 37 is in an OFF state. In order to perform charging, the transistor 37 is turned on. Then, the charge switch 33 connected via the electrode pad 23 is turned on, and the current A flows from the power source 35 into the rechargeable battery to perform charging (see (B)).

  In this circuit, the transistor 37 constitutes a driver transistor. That is, the transistor 37 drives the charge switch 33 which is the next stage element. Further, since charging is completed in a shorter time as the current A is larger, the current B of the transistor 37 for driving the current A is also required to be larger. Since the current flowing through the transistor is proportional to the channel width, the channel width of the transistor 37 as the driver transistor is designed to be a large value.

  Next, the layout of the driver transistor will be described. 15A and 15B are diagrams showing a general driver transistor formation region including an electrode pad formation region. FIG. 15A is a plan view, FIG. 15B is a plan view schematically showing, and FIG. It is sectional drawing in -B position.

  A LOCOS oxide film 3 for defining a driver transistor formation region 5 is formed on the silicon substrate 1. A source 7 s and a drain 7 d made of an N-type impurity diffusion layer are formed on the silicon substrate 1 in the driver transistor formation region 5. The source 7s and the drain 7d are alternately arranged in the short direction at intervals.

  A gate electrode 11 made of polysilicon is formed on the silicon substrate 1 between the source 7 s and the drain 7 d via a gate oxide film 9. The gate electrode 11 is formed in a region between the plurality of sources 7s and drains 7d. (B) and (C) show the case where the number of the gate electrodes 11 is four, but in general, several tens or more of the gate electrodes 11 are used for the convenience of designing a large channel width.

  An interlayer insulating film 13 (not shown in (A) and (B)) is formed on the entire surface of the silicon substrate 1 including the regions where the source 7s, the drain 7d and the gate electrode 11 are formed. A contact hole 15s is formed in the interlayer insulating film 13 on the source 7s. A contact hole 15d is formed in the interlayer insulating film 13 on the drain 7d. A contact hole is formed in the interlayer insulating film 13 on the gate electrode 11 in a region not shown.

A comb-like metal wiring layer 17 s is formed on the interlayer insulating film 13 including the formation region of the contact hole 15 s on the source 7 s. The plurality of sources 7s are electrically connected through the contact hole 15s and the metal wiring layer 17s. The metal wiring layer 17s is connected to an electrode pad 23s formed on the interlayer insulating film 13 in the electrode pad formation region provided in the vicinity of the driver transistor formation region.
A comb-like metal wiring layer 17d is formed on the interlayer insulating film 13 including the formation region of the contact hole 15d on the drain 7d. The plurality of drains 7d are electrically connected through the contact hole 15d and the metal wiring layer 17d. The metal wiring layer 17d is connected to an electrode pad 23d formed on the interlayer insulating film 13 in the electrode pad formation region.

A metal wiring layer is formed including a contact hole formation region on the gate electrode 11 in a region not shown. The plurality of gate electrodes 11 are electrically connected via a contact hole and a metal wiring layer (not shown).
A final protective film 19 is formed on the interlayer insulating film 13. The final protective film 19 includes pad openings 21s and 21d on the electrode pads 23s and 23d.
FIG. 15 shows an example of a one-layer metal wiring layer structure, but at present, the use of multilayer wiring of two or more layers is the mainstream.

  As shown in FIG. 15, the feature of the driver transistor is that the source 7 s and the drain 7 d are alternately arranged on both sides of the gate electrode 11. When the driver transistor is turned on, a current flows in the direction of the arrow as shown in FIG. That is, one source 7s and one drain 7d function with respect to the gate electrodes 11 on both sides, and a layout that allows a large current to flow in a small area becomes possible.

  16, FIG. 17 and FIG. 18 are diagrams showing a driver transistor formation region of a semiconductor device having a four-layer metal wiring layer structure including an electrode pad formation region. 16A is a plan view, FIG. 16B is a cross-sectional view taken along the line AA in FIG. 16A, and FIG. 16C is a cross-sectional view taken along the line BB in FIG. 17A is a plan view of the first metal wiring layer, and FIG. 17B is a plan view of the second metal wiring layer. 18A is a plan view of the third metal wiring layer, and FIG. 18B is a plan view of the fourth metal wiring layer.

A LOCOS oxide film 3 is formed on the silicon substrate 1. Sources 7 s and drains 7 d are alternately arranged on the silicon substrate 1 in the driver transistor formation region 5 at intervals.
A gate electrode 11 made of polysilicon is formed on the silicon substrate 1 between the source 7 s and the drain 7 d via a gate oxide film 9.

  A BPSG film 13-1 is formed on the entire surface of the silicon substrate 1 including the regions where the source 7s, the drain 7d and the gate electrode 11 are formed. A contact hole 15s-1 is formed in the BPSG film 13-1 on the source 7s. A contact hole 15d-1 is formed in the BPSG film 13-1 on the drain 7d. A contact hole is formed in the interlayer insulating film 13 on the gate electrode 11 in a region not shown.

  A first metal wiring layer 17s-1 is formed on the BPSG film 13-1 including the contact hole 15s-1 formation region on the source 7s. A first metal wiring layer 17d-1 is formed on the BPSG film 13-1 including the contact hole 15d-1 formation region on the drain 7d. A metal wiring layer is formed on the BPSG film 13-1 including a contact hole formation region on the gate electrode 11 in a region not shown.

  A first interlayer insulating film 13-2 is formed on the BPSG film 13-1 including the formation region of the first metal wiring layers 17s-1 and 17d-1. A through hole 15s-2 is formed in the first interlayer insulating film 13-2 on the first metal wiring layer 17s-1. A through hole 15d-2 is formed in the first interlayer insulating film 13-2 on the first metal wiring layer 17d-1.

  A second metal wiring layer 17s-2 is formed on the first interlayer insulating film 13-2 including the formation region of the through hole 15s-2 on the first metal wiring layer 17s-1. A second metal wiring layer 17d-2 is formed on the first interlayer insulating film 13-2 including the formation region of the through hole 15d-2 on the first metal wiring layer 17d-1.

  A second interlayer insulating film 13-3 is formed on the first interlayer insulating film 13-2 including the formation region of the second metal wiring layers 17s-2 and 17d-2. A through hole 15s-3 is formed in the second interlayer insulating film 13-3 on the second metal wiring layer 17s-2. A through hole 15d-3 is formed in the second interlayer insulating film 13-3 on the second metal wiring layer 17d-2.

  A third metal wiring layer 17s-3 is formed on the second interlayer insulating film 13-3 including the formation region of the through hole 15s-3 on the second metal wiring layer 17s-2. A third metal wiring layer 17d-3 is formed on the second interlayer insulating film 13-3 including the formation region of the through hole 15d-3 on the second metal wiring layer 17d-2.

  A third interlayer insulating film 13-4 is formed on the second interlayer insulating film 13-3 including the formation region of the third metal wiring layers 17s-3 and 17d-3. A through hole 15s-4 is formed in the third interlayer insulating film 13-4 on the third metal wiring layer 17s-3. A through hole 15d-4 is formed in the third interlayer insulating film 13-4 on the third metal wiring layer 17d-3.

  A fourth metal wiring layer 17s-4 is formed on the third interlayer insulating film 13-4 including the formation region of the through hole 15s-4 on the third metal wiring layer 17s-3. The fourth metal wiring layer 17s-4 is formed from the driver transistor formation region to the electrode pad formation region. The fourth metal wiring layer 17s-4 is formed over the formation region of the plurality of third metal wiring layers 17s-3, and the plurality of third metal wiring layers 17s-3 are formed through the through holes 15s-4. Electrically connected.

  A fourth metal wiring layer 17d-4 is formed on the third interlayer insulating film 13-4 including the formation region of the through hole 15d-4 on the third metal wiring layer 17d-3. The fourth metal wiring layer 17d-4 is a region different from the fourth metal wiring layer 17s-4, and is formed from the driver transistor formation region to the electrode pad formation region. The fourth metal wiring layer 17d-4 is formed over the formation region of the plurality of third metal wiring layers 17d-3, and the plurality of third metal wiring layers 17d-3 are connected to each other through the through holes 15d-4. Electrically connected.

  A final protective film 19 is formed on the third interlayer insulating film 13-4 including the formation region of the fourth metal wiring layers 17s-4 and 17d-4. A pad opening 21s is formed in the final protective film 19 on the fourth metal wiring layer 17s-4 in the electrode pad formation region. A pad opening 21d is formed in the final protective film 19 on the fourth metal wiring layer 17d-4 in the electrode pad formation region. The fourth metal wiring layers 17s-4 and 17d-4 in the formation regions of the pad openings 21s and 21d constitute electrode pads 23s and 23d.

The electrode pad 23s includes a fourth metal wiring layer 17s-4, a through hole 15s-4, a third metal wiring layer 17s-3, a through hole 15s-3, a second metal wiring layer 17s-2, and a through hole 15s. -2 is electrically connected to the source 7s via the first metal wiring layer 17s-1 and the contact hole 15s-1.
The electrode pad 23d includes a fourth metal wiring layer 17d-4, a through hole 15d-4, a third metal wiring layer 17d-3, a through hole 15d-3, a second metal wiring layer 17d-2, and a through hole 15d. -2 is electrically connected to the drain 7d through the first metal wiring layer 17d-1 and the contact hole 15d-1.

  The purpose of stacking a plurality of metal wiring layers in multiple stages and connecting them with a plurality of through holes and contact holes is designed to allow the driver transistor to flow a large current, and the current on the source 7s side and the drain 7d side This is because it is advantageous to reduce the resistance component of the path as much as possible.

  The first metal wiring layers 17s-1, 17d-1, the second metal wiring layers 17s-2, 17d-2, and the third metal wiring layers 17s-3, 17d-3 have a linear repeating pattern. On the other hand, the fourth metal wiring layers 17s-4 and 17d-4 are rectangular patterns with a large area. This is because the current flowing through the first layer, the second layer, the third layer metal wiring layers 17s-1, 17d-1, 17s-2, 17d-2, 17s-3, 17d-3 is all the fourth layer metal wiring. This is due to the fact that the wiring widths of the fourth metal wiring layers 17 s-4 and 17 d-4 are designed to be large so that a large current can flow because they concentrate on the layers 17 s-4 and 17 d-4.

  The fourth metal wiring layers 17s-4 and 17d-4 include a plurality of metal wiring layers 17s-1, 17s-2 and 17s-3 on the source side and a plurality of metal wiring layers 17d-1 and 17d on the drain side. It is formed across -2, 17d-3. Therefore, no through hole is formed below the third metal wiring layer 17d-3 on the drain side below the fourth metal wiring layer 17s-4 on the source side. Similarly, no through hole is formed on the source-side third metal wiring layer 17s-3 below the drain-side fourth metal wiring layer 17d-4.

A problem when such a driver transistor is arranged in a region immediately below the electrode pad will be described.
In FIG. 19, the electrode pads 23s and 23d are arranged on the driver transistor. As described above, the crack 29 is generated in the third interlayer insulating film 13-4 under the electrode pads 23s and 23d by the impact during the wafer test. The crack 29 electrically short-circuits the fourth metal wiring layers 17s-4 and 17d-4 and the third metal wiring layers 17s-3 and 17d-3.

Due to the influence of the crack 29, the drain-side fourth-layer metal wiring layer 17d-4 and the source-side third-layer metal wiring layer 17s-3 are electrically short-circuited, and the source-side fourth-layer metal wiring layer The layer 17s-4 and the third metal wiring layer 17d-3 on the drain side are electrically short-circuited, and the driver transistor does not operate normally. As described above, there is a fatal problem in disposing the driver transistor directly under the electrode pad.
Such a problem occurs not only when the element disposed under the electrode pad is a driver transistor, but also in an electrode electrically connected to one electrode of the element in a structure in which the two electrodes of the element are drawn to the electrode pad. A similar problem can occur when a metal wiring layer electrically connected to the other electrode of the element is disposed under the pad.

Japanese Patent Publication No. 05-053304 JP 2002-319587 A JP 2003-289104 A

As described above, although some ideas for disposing a device under an electrode pad have already been disclosed, nothing is said about disposing a driver transistor. That is, there is actually no technology for disposing the driver transistor under the electrode pad. In addition, nothing is said about the short circuit between the two electrodes of the element disposed under the electrode pad due to the crack of the interlayer insulating film under the electrode pad.
The present invention provides a semiconductor device in which an element is arranged under an electrode pad, two electrodes of the element are drawn out to at least two electrode pads, and a short circuit between the two electrodes of the element can be prevented. It is for the purpose.

A semiconductor device according to the present invention includes a driver transistor having a source and a drain and a metal wiring layer structure of three or more layers formed on the driver transistor, and is formed on an insulating film on the uppermost metal wiring layer. The metal wiring layer portion exposed in the pad opening is a semiconductor device that constitutes an electrode pad, the source potential electrode pad electrically connected to the source as the electrode pad, the drain and the electric The drain potential electrode pads are connected to each other, and the source potential electrode pads and the drain potential electrode pads are arranged on one of the driver transistors.
A metal wiring layer that is one layer lower than the uppermost metal wiring layer, a source potential lower metal wiring layer connected to the source potential electrode pad, and a drain connected to the drain potential electrode pad Regarding the metal wiring layer under one potential, only the metal wiring layer under one source potential is formed immediately below the source potential electrode pad, and the metal wiring layer under one drain potential is formed immediately under the drain potential electrode pad. Only formed.
Further, immediately below the source potential electrode pad and the drain potential electrode pad and below the one-level lower metal wiring layer, the source potential electrode pad, the source potential one-layer lower metal wiring layer, and the source A source potential metal wiring layer, a drain potential electrode pad, a drain potential lower metal wiring layer, and a drain potential metal wiring layer electrically connected to the drain are disposed together. The source potential metal wiring layer and the drain potential metal wiring layer extend in the channel width direction of the driver transistor so as to extend directly below the source potential lower metal wiring layer and directly below the drain potential lower metal wiring layer. Is formed.
And a plurality of the source potential lower metal wiring layer and the drain potential lower metal wiring layer, the source potential lower layer metal wiring layer and the drain potential lower layer metal wiring layer being the driver. Alternatingly arranged in the channel width direction of the transistor, the potential of the source potential metal wiring layer is drawn out to the plurality of one source potential lower metal wiring layers, and the potential of the drain potential metal wiring layer is extracted to the plurality of drain potentials. One layer is drawn out to the lower metal wiring layer.
Here, the source potential electrode pad and the drain potential electrode pad are arranged on the driver transistor means that at least a part of the source potential electrode pad and at least a part of the drain potential electrode pad are arranged on the element. This means that the entire source potential electrode pad and drain potential electrode pad are not necessarily arranged on the element.
Further, with respect to the metal wiring layer that is one layer below, a wiring or a dummy pattern that is not connected to either the source or the drain may be disposed under the source potential electrode pad and the drain potential electrode pad.
In the claims and the specification of the present application, an electrode pad is a region exposed in a pad opening formed in an insulating film formed on a metal wiring layer of the metal wiring layer for the electrode pad. Say.

  The metal wiring layer under the one layer is a portion where the metal probe is in contact with the source potential electrode pad and the drain potential electrode pad under the source potential electrode pad and the drain potential electrode pad during the wafer test. It may be arranged at least underneath.

  Further, an example in which no connection hole for connecting to the metal wiring layer that is one layer below is formed under the source potential electrode pad and the drain potential electrode pad.

  The uppermost metal wiring layer including the source potential electrode pad or the drain potential electrode pad and the one lower metal wiring layer under the uppermost metal wiring layer are formed in a larger area than the pad opening. An example in which the uppermost metal wiring layer and the metal wiring layer one layer below are connected by connection holes arranged around the pad opening as viewed from above can be given.

A plurality of the source potential electrode pads may be provided on one driver transistor.
A plurality of the drain potential electrode pads may be provided on one driver transistor.

  The source potential lower metal wiring layer is connected to the connection hole formed on the source and the source potential metal wiring layer two layers below the uppermost metal wiring layer through the lowermost source potential metal wiring layer. An example in which the source is connected can be given.

  Further, the drain potential metal wiring layer below the drain potential one layer is formed by connecting the lowermost drain potential metal wiring layer from the connection hole formed on the drain and the drain potential metal wiring layer two layers below the uppermost metal wiring layer. The example connected to the said drain via can be given.

  The semiconductor device of the present invention includes a driver transistor having a source and a drain, and a metal wiring layer structure of three or more layers formed on the driver transistor, and a pad formed on an insulating film on the uppermost metal wiring layer In a semiconductor device in which the metal wiring layer portion exposed in the opening constitutes an electrode pad, the source potential electrode pad that is electrically connected to the source as the electrode pad and the drain is electrically connected A drain potential electrode pad is provided, and the source potential electrode pad and the drain potential electrode pad are arranged on one driver transistor and are a metal wiring layer one layer lower than the uppermost metal wiring layer, and the source potential electrode pad The source potential is connected to the lower metal wiring layer and the drain potential electrode pad connected to the drain potential electrode pad. Regarding the in-potential one-layer metal wiring layer, only the source-potential one-layer metal wiring layer is formed immediately below the source-potential electrode pad, and only the drain-potential one-layer metal wiring layer is formed immediately below the drain-potential electrode pad. The source potential electrode pad, the source potential one lower metal wiring layer, and the source are electrically connected to the lower layer side of the metal wiring layer one layer immediately below the source potential electrode pad and the drain potential electrode pad. Since the source potential metal wiring layer, the drain potential electrode pad, the drain potential one layer lower metal wiring layer, and the drain potential metal wiring layer electrically connected to the drain are arranged together, Even if a crack occurs in the insulating film, a short circuit between the metal wiring layer connected to the drain and the source potential electrode pad, and connection to the source And are able to prevent a short circuit between the metal wiring layers and the drain potential electrode pad. As a result, the driver transistor can be disposed under the electrode pad, the source and drain of the driver transistor can be drawn out to the electrode pad, respectively, and a short circuit between the source and drain of the driver transistor can be prevented.

Furthermore, by disposing a driver transistor that occupies a large area under the electrode pad, it is possible to reduce the chip size and the chip cost.
Further, the source potential metal wiring layer and the drain potential metal wiring layer are formed by extending in the channel width direction of the driver transistor so as to extend directly below the source potential one lower metal wiring layer and immediately below the drain potential one lower metal wiring layer. A plurality of source potential one-layer metal wiring layers and drain potential one-layer lower metal wiring layers, and the source potential one-layer lower metal wiring layer and the drain potential one-layer lower metal wiring layer are provided in the channel of the driver transistor. Alternatingly arranged in the width direction, the potential of the source potential metal wiring layer is drawn out to the plurality of one source potential lower metal wiring layers, and the potential of the drain potential metal wiring layer is drawn to the plurality of drain potential one lower metal wiring layers. Reduced current concentration in the source potential metal wiring layer and drain potential metal wiring layer Kill.

  The one lower metal wiring layer is disposed at least under the source potential electrode pad and the drain potential electrode pad, below the portion where the metal probe is in contact with the source potential electrode pad and the drain potential electrode pad during the wafer test. As a result, even if a crack is generated under the electrode pad, the crack can be stopped by the metal wiring layer one layer below, and the generation of a crack below the metal wiring layer one layer below is prevented. be able to.

  Further, a structure in which no connection hole for connecting to the metal wiring layer one layer below is formed under the source potential electrode pad and the drain potential electrode pad, for example, a source potential electrode pad or a drain potential electrode pad is provided. The uppermost metal wiring layer including the metal wiring layer below the uppermost metal wiring layer is formed with a larger area than the pad opening, and is disposed around the pad opening as viewed from above. If the uppermost metal wiring layer and the lower metal wiring layer are connected by the formed connection hole, the impact applied to the electrode pad is propagated downward by the metal material embedded in the connection hole. Thus, it is possible to prevent characteristic fluctuations caused by impact.

  If a plurality of source potential electrode pads are provided on one driver transistor and a plurality of drain potential electrode pads are provided on one driver transistor, for example, a driver transistor or the like The area above the area element can be used effectively, and the layout area can be reduced and the chip manufacturing cost can be reduced.

Further, the source potential lower metal wiring layer is connected to the connection hole formed on the source and the source potential metal wiring layer two layers below the uppermost metal wiring layer through the lowermost source potential metal wiring layer. By connecting the source potential electrode pad to the source, the source potential electrode pad can be guided from the driver transistor formation region to the electrode pad formation region as compared with the case where the source potential electrode pad is arranged in a region different from that on the driver transistor. The resistance can be reduced by the amount of the metal wiring layer in the horizontal direction.
Similarly, the drain potential first metal wiring layer is connected to the connection hole formed on the drain and the drain potential metal wiring layer two layers below the uppermost metal wiring layer through the lowermost drain potential metal wiring layer. If the drain potential electrode pad is connected to the drain, the drain potential is transferred from the driver transistor formation region to the electrode pad formation region as compared with the case where the drain potential electrode pad is disposed in a region different from the driver transistor formation region. The resistance can be reduced by the amount of the horizontal metal wiring layer for guiding.
According to these aspects, it is possible to flow current at the shortest distance from the electrode pad almost directly below. As a result, the resistance component between the electrode pad and the source and drain can be reduced as compared with the case where the electrode pad is disposed in a region different from the region where the driver transistor is formed. It is possible to prevent the performance of the driver transistor from being lowered due to the voltage drop.

  1, 2 and 3 are diagrams showing a reference example of a four-layer metal wiring layer structure. 1A is a plan view, FIG. 1B is a cross-sectional view taken along the line AA in FIG. 1A, and FIG. 1C is a cross-sectional view taken along the line BB in FIG. 2A is a plan view of the first metal wiring layer, and FIG. 2B is a plan view of the second metal wiring layer. 3A is a plan view of the third metal wiring layer, and FIG. 3B is a plan view of the fourth metal wiring layer.

For example, a LOCOS oxide film 3 is formed on a P-type silicon substrate 1. A driver transistor formation region 5 is defined by the LOCOS oxide film 3. A plurality of sources 7 s and a plurality of drains 7 d made of, for example, N-type impurities are alternately arranged on the silicon substrate 1 in the driver transistor formation region 5 with a space therebetween.
A gate electrode 11 made of polysilicon is formed on the silicon substrate 1 between the source 7 s and the drain 7 d via a gate oxide film 9.

  A BPSG film 13-1 is formed on the entire surface of the silicon substrate 1 including the regions where the source 7s, the drain 7d and the gate electrode 11 are formed. A contact hole 15s-1 is formed in the BPSG film 13-1 on the source 7s. A contact hole 15d-1 is formed in the BPSG film 13-1 on the drain 7d. A contact hole is formed in the interlayer insulating film 13 on the gate electrode 11 in a region not shown.

A first metal wiring layer 17s-1 (source potential metal wiring layer) is formed on the BPSG film 13-1 including the formation region of the contact hole 15s-1 on the source 7s. First metal wiring layer 17s-1 is electrically connected to source 7s through contact hole 15s-1.
A first metal wiring layer 17d-1 (drain potential metal wiring layer) is formed on the BPSG film 13-1 including the formation region of the contact hole 15d-1 on the drain 7d. First metal wiring layer 17d-1 is electrically connected to drain 7d through contact hole 15d-1.
A metal wiring layer is formed on the BPSG film 13-1 including a contact hole formation region on the gate electrode 11 in a region not shown. The plurality of gate electrodes 11 are electrically connected via a contact hole and a metal wiring layer (not shown).

  A first interlayer insulating film 13-2 is formed on the BPSG film 13-1 including the formation region of the first metal wiring layers 17s-1 and 17d-1. A through hole (connection hole) 15s-2 is formed in the first interlayer insulating film 13-2 on the first metal wiring layer 17s-1. A through hole 15d-2 is formed in the first interlayer insulating film 13-2 on the first metal wiring layer 17d-1.

A second metal wiring layer 17s-2 (source potential metal wiring layer) is formed on the first interlayer insulating film 13-2 including the formation region of the through hole 15s-2 on the first metal wiring layer 17s-1. Is formed. Second metal wiring layer 17s-2 is electrically connected to first metal wiring layer 17s-1 through through hole 15s-2.
A second metal wiring layer 17d-2 (drain potential metal wiring layer) is formed on the first interlayer insulating film 13-2 including the formation region of the through hole 15d-2 on the first metal wiring layer 17d-1. Is formed. Second metal wiring layer 17d-2 is electrically connected to first metal wiring layer 17d-1 through through hole 15d-2.

  A second interlayer insulating film 13-3 is formed on the first interlayer insulating film 13-2 including the formation region of the second metal wiring layers 17s-2 and 17d-2. A through hole 15s-3 is formed in the second interlayer insulating film 13-3 on the second metal wiring layer 17s-2. A through hole 15d-3 is formed in the second interlayer insulating film 13-3 on the second metal wiring layer 17d-2.

The third metal wiring layer 17s-3 (source potential lower layer metal wiring) is formed on the second interlayer insulating film 13-3 including the formation region of the through hole 15s-3 on the second metal wiring layer 17s-2. Layer) is formed. The third metal wiring layer 17s-3 is electrically connected to the second metal wiring layer 17s-2 through the through hole 15s-3.
The third metal wiring layer 17d-3 (the drain potential one layer lower metal wiring is formed on the second interlayer insulating film 13-3 including the formation region of the through hole 15d-3 on the second metal wiring layer 17d-2. Layer) is formed. The third metal wiring layer 17d-3 is electrically connected to the second metal wiring layer 17d-2 through the through hole 15d-3.
The third metal wiring layers 17s-3 and 17d-3 are formed over the regions where the plurality of second metal wiring layers 17s-2 and 17d-2 are formed, that is, over the plurality of sources 7s and drains 7d.

  A third interlayer insulating film 13-4 is formed on the second interlayer insulating film 13-3 including the formation region of the third metal wiring layers 17s-3 and 17d-3. A through hole 15s-4 is formed in the third interlayer insulating film 13-4 on the third metal wiring layer 17s-3. A through hole 15d-4 is formed in the third interlayer insulating film 13-4 on the third metal wiring layer 17d-3.

A fourth metal wiring layer 17s-4 is formed on the third interlayer insulating film 13-4 including the formation region of the through hole 15s-4 on the third metal wiring layer 17s-3. The fourth metal wiring layer 17s-4 is electrically connected to the plurality of third metal wiring layers 17s-3 through through holes 15s-4.
A fourth metal wiring layer 17d-4 is formed on the third interlayer insulating film 13-4 including the formation region of the through hole 15d-4 on the third metal wiring layer 17d-3. The fourth metal wiring layer 17d-4 is electrically connected to the plurality of third metal wiring layers 17d-3 through the through holes 15d-4.
The fourth metal wiring layers 17s-4 and 17d-4 constitute the uppermost metal wiring layer.

  A final protective film 19 is formed on the third interlayer insulating film 13-4 including the formation region of the fourth metal wiring layers 17s-4 and 17d-4. A pad opening 21s is formed in the final protective film 19 on the fourth metal wiring layer 17s-4. A pad opening 21d is formed in the final protective film 19 on the fourth metal wiring layer 17d-4. The fourth metal wiring layer 17s-4 in the formation region of the pad opening 21s constitutes a source potential electrode pad 23s. The fourth metal wiring layer 17d-4 in the formation region of the pad opening 21d constitutes the drain potential electrode pad 23d.

The source potential electrode pad 23s includes a fourth metal wiring layer 17s-4, a through hole 15s-4, a third metal wiring layer 17s-3, a through hole 15s-3, a second metal wiring layer 17s-2, and a through hole. It is electrically connected to the source 7s through the hole 15s-2, the first metal wiring layer 17s-1 and the contact hole 15s-1.
The drain potential electrode pad 23d includes a fourth metal wiring layer 17d-4, a through hole 15d-4, a third metal wiring layer 17d-3, a through hole 15d-3, a second metal wiring layer 17d-2, and a through hole. It is electrically connected to the drain 7d through the hole 15d-2, the first metal wiring layer 17d-1, and the contact hole 15d-1.

  In this reference example, the source potential electrode pad 23 s connected to the source 7 s of the driver transistor and the drain potential electrode pad 23 d connected to the drain 7 d are disposed on the driver transistor formation region 5. By disposing the driver transistor occupying the area under the electrode pads 23s and 23d, it is possible to reduce the chip size and the chip cost.

Further, the third metal wiring layers 17s-3 and 17d-3, which are one layer lower than the uppermost fourth metal wiring layers 17s-4 and 17d-4, have a source potential below the source potential electrode pad 23s. Since the third metal wiring layer 17s-3 connected to the electrode pad 23s is formed and the third metal wiring layer 17d-3 connected to the drain potential electrode pad 23d is not formed, the source potential electrode Even if the third interlayer insulating film 13-4 under the pad 23s is cracked, the source potential electrode pad 23s and the third metal wiring layer 17d-3 are not short-circuited.
Furthermore, the third metal wiring layers 17s-3 and 17d-3, which are one layer lower than the uppermost fourth metal wiring layers 17s-4 and 17d-4, have a drain potential below the drain potential electrode pad 23d. Since the third metal wiring layer 17d-3 connected to the electrode pad 23d is formed and the third metal wiring layer 17s-3 connected to the source potential electrode pad 23s is not formed, the drain potential electrode Even if the third interlayer insulating film 13-4 under the pad 23d is cracked, the drain potential electrode pad 23d and the third metal wiring layer 17s-3 are not short-circuited.
As a result, the driver transistor is arranged under the electrode pads 23s and 23d, the source 7s and the drain 7d of the driver transistor are led out to the electrode pads 23s and 23d, respectively, and a short circuit between the source 7s and the drain 7d of the driver transistor is prevented. can do.

  Further, since the third metal wiring layers 17s-3 and 17d-3 are formed on the entire surface under the electrode pads 23s and 23d, even if cracks are generated under the electrode pads 23s and 23d, the cracks are removed in the third layer. It can be stopped by the metal wiring layers 17s-3 and 17d-3, and cracks can be prevented from being generated in the lower layer than the third metal wiring layers 17s-3 and 17d-3.

In this reference example, the third metal wiring layers 17s-3 and 17d-3 are formed on the entire surface under the electrode pads 23s and 23d, but the present invention is not limited to this.
For example, if the metal probe is disposed at least under the source potential electrode pad 23s and the drain potential electrode pad 23d under the portion where the metal probe contacts the electrode pads 23s and 23d during the wafer test, the third layer metal It is possible to prevent cracks from occurring below the wiring layers 17s-3 and 17d-3.

The third metal wiring layers 17s-3 and 17d-3 are under the portions where the metal probes are in contact with the electrode pads 23s and 23d during the wafer test under the source potential electrode pad 23s and the drain potential electrode pad 23d. The structure which is not arrange | positioned may be sufficient.
FIG. 4 is a plan view showing the arrangement of the third metal wiring layer of another reference example. In this reference example, the configuration other than the third metal wiring layer is the same as the reference example described with reference to FIG. 1, FIG. 2, and FIG.

For example, the third metal wiring layers 17s-3 and 17d-3 may have a strip shape as shown in (A) or an island shape as shown in (B).
Also in these reference examples, the third metal wiring layer 17s-3 is formed under the source potential electrode pad 23s (see FIGS. 1 and 3), and the third metal wiring layer 17d-3 is formed. The third metal wiring layer 17d-3 is formed under the drain potential electrode pad 23d (see FIGS. 1 and 3), and the third metal wiring layer 17s-3 is not formed. Therefore, even if a crack occurs in the third interlayer insulating film 13-4 below the electrode pads 23s, 23d, the source potential electrode pad 23s and the third metal wiring layer 17d-3 are short-circuited, and the drain potential electrode pad 23d A short circuit of the third metal wiring layer 17s-3 can be prevented.
That is, in the present invention, the third metal wiring layer 17d-3 is not disposed under the source potential electrode pad 23s, and the third metal wiring layer 17s-3 is disposed under the drain potential electrode pad 23d. That's fine.

  5A and 5B are diagrams showing still another reference example, in which FIG. 5A is a plan view of a fourth metal wiring layer and a through hole, FIG. 5B is a cross-sectional view taken along the line A-A in FIG. ) Is a cross-sectional view taken along the line BB in FIG. In this reference example, the configuration other than the through hole formed in the fourth interlayer insulating film is the same as the reference example described with reference to FIGS.

In the vicinity of the electrode pads 23s and 23d, the fourth metal wiring layers 17s-4 and 17d-4 and the third metal wiring layers 17s-3 and 17d-3 are plate-shaped with a larger area than the pad openings 21d and 23d. Is formed.
A through hole 15s-4 is formed on the outer periphery of the source potential electrode pad 23s. The fourth metal wiring layer 17s-4 and the third metal wiring layer 17s-3 are connected by the through hole 15s-4.
A through hole 15d-4 is formed on the outer periphery of the drain potential electrode pad 23d. The fourth metal wiring layer 17d-4 and the third metal wiring layer 17d-3 are connected by the through hole 15d-4.

  In this reference example, the through holes 15s-4 and 15d-4 are not formed under the electrode pads 23s and 23d. As a result, the impact applied to the electrode pads 23s and 23d is not propagated downward by the metal material embedded in the through hole, and characteristic fluctuations caused by the impact can be prevented.

  In this reference example, the third metal wiring layers 17s-3 and 17d-3 are formed in a plate shape. However, the present invention is not limited to this, and for example, as shown in FIG. It may be. In that case, the through holes 15s-4 and 15d-4 are arranged on the outer periphery of the electrode pads 23s and 23d. That is, if the through holes 15s-4 and 15d-4 are not arranged under the electrode pads 23s and 23d, the impact applied to the electrode pads 23s and 23d is propagated downward by the metal material embedded in the through holes. Can be prevented.

  6 and 7 are diagrams showing still another reference example. 6A is a plan view, FIG. 6B is a cross-sectional view taken along the line AA in FIG. 6A, and FIG. 6C is a cross-sectional view taken along the line BB in FIG. 7A is a plan view of the third metal wiring layer, and FIG. 7B is a plan view of the fourth metal wiring layer. The structures of the first metal wiring layer and the second metal wiring layer are the same as those in FIG. The structures of the third metal wiring layer and the fourth metal wiring layer shown in FIG. 7 are the same as those shown in FIG.

Two pad openings 21s are formed on the fourth metal wiring layer 17s-4, and two source potential electrode pads 23s are formed. Further, two pad openings 21d are formed on the fourth metal wiring layer 17d-4, and two drain potential electrode pads 23d are formed.
As described above, two or more source potential electrode pads 23 s or two or more drain potential electrode pads 23 d or both may be arranged in the driver transistor formation region 5.

  By the way, in the driver transistor, the larger the channel width, the larger the flowing current. On the other hand, the maximum value (upper limit value) of the current that can flow through the metal wiring layer is determined depending on the material, structure, and dimensions. If this value is exceeded, the metal wiring layer is melted or disconnected, resulting in a failure. That is, in a driver transistor having a large channel width, the allowable current value may be exceeded in the metal wiring layer portion.

For example, in FIG. 7A, focusing on the second metal wiring layer 17d-2, the current flowing from the through hole 15d-3 into the second metal wiring layer 17d-2 is the third metal wiring without the through hole. Run down to layer 17s-3. In the second metal wiring layer 17d-2, all of the current flowing in the region below the third metal wiring layer 17s-3 passes through the portion of the one-dot chain line circle, and current concentration occurs in this portion. . The current concentration also occurs in the second metal wiring layer 17s-2.
This phenomenon becomes more prominent as the channel width becomes larger. Therefore, it is necessary to intentionally increase the line width of the second metal wiring layers 17d-2 and 17s-2 in the driver transistor having a larger channel width. This originally means that the occupied area of the driver transistor that requires a large area is further increased due to the large channel width, which is a big problem that causes an increase in chip size.

  8 and 9 show an embodiment. 8A is a plan view, FIG. 8B is a cross-sectional view taken along the line AA in FIG. 8A, and FIG. 8C is a cross-sectional view taken along the line BB in FIG. 9A is a plan view of the third metal wiring layer, and FIG. 9B is a plan view of the fourth metal wiring layer. Also in this embodiment, the structures of the first metal wiring layer and the second metal wiring layer are the same as those in FIG.

  In this embodiment, two source potential electrode pads 23s and two drain potential electrode pads 23d are provided, and the third metal wiring layers 17s-3 and 17d-3 are alternately arranged, and the electrode pads 23s and 23d are also arranged. Alternatingly arranged.

  When attention is paid to the second metal wiring layer 17d-2 in the same manner as attention is paid to the second metal wiring layer 17d-2 in FIG. 7, it can be seen that the number of places where current concentrates is increased from one to three. (See the dot-dash line circle). In other words, this example shows that the current concentrated in one place is distributed in three places. In this embodiment, since the current value per location where the current concentrates in the second metal wiring layers 17d-2 and 17s-2 can be reduced to about one third, the metal wiring layer as described above is made thicker. Therefore, it is not necessary to take such a measure, and an increase in the area occupied by the driver transistor can be suppressed.

  As mentioned above, although the Example and reference example of this invention were described, this invention is not limited to these, A shape, material, arrangement | positioning, a number, etc. are examples, and this invention described in the claim Various changes can be made within the range.

For example, the first metal wiring layers 17s-1 and 17d-1 may have an island shape.
In the above embodiment, the present invention is applied to a four-layer metal wiring structure. However, the present invention is not limited to this, and the present invention is also applied to a metal wiring structure of three layers or five layers or more. Needless to say, you can.

It is a figure which shows the reference example of 4 layer metal wiring layer structure, (A) is a top view, (B) is sectional drawing in the AA position of (A), (C) is BB of (A). It is sectional drawing in a position. It is a figure which shows the same reference example, (A) is a top view of the 1st metal wiring layer, (B) is a top view of the 2nd metal wiring layer. It is a figure which shows the same reference example, (A) is a top view of the 3rd-layer metal wiring layer, (B) is a top view of the 4th-layer metal wiring layer. It is a top view which shows arrangement | positioning of the 3rd-layer metal wiring layer of another reference example. It is a figure which shows another reference example, (A) is a top view of a 4th metal wiring layer and a through hole, (B) is sectional drawing in the AA position of (A), (C) is ( It is sectional drawing in the BB position of A). It is a figure which shows another reference example, (A) is a top view, (B) is sectional drawing in the AA position of (A), (C) is a cross section in the BB position of (A). FIG. It is a figure which shows the same reference example, (A) is a top view of the 3rd-layer metal wiring layer, (B) is a top view of the 4th-layer metal wiring layer. It is a figure which shows one Example, (A) is a top view, (B) is sectional drawing in the AA position of (A), (C) is sectional drawing in the BB position of (A). is there. It is a figure which shows the Example, (A) is a top view of the 3rd-layer metal wiring layer, (B) is a top view of the 4th-layer metal wiring layer. It is a figure which shows the schematic block diagram of the conventional electrode pad vicinity, (A) is a top view, (B) is sectional drawing in the AA position of (A). It is sectional drawing which shows the prior art of 4 layer metal wiring layer structure. It is a figure for demonstrating a wafer test, (A) is a top view of the whole semiconductor device, (B) and (C) are sectional drawings which show one electrode pad vicinity, (B) is a metal probe. The state before contact, (C) shows the state after contacting the metal probe. It is a microscope picture which shows the cross section of the electrode pad vicinity after a metal probe was contacted. It is a schematic circuit diagram of a charging device. It is a figure which shows a general driver transistor formation area also including an electrode pad formation area, (A) is a top view, (B) is a top view which shows schematically, (C) is a BB position of (B). FIG. It is a figure which shows the prior art of 4 layer metal wiring layer structure, (A) is a top view, (B) is sectional drawing in the AA position of (A), (C) is BB of (A). It is sectional drawing in a position. It is a figure which shows the prior art, (A) is a top view of the 1st metal wiring layer, (B) is a top view of the 2nd metal wiring layer. It is a figure which shows the prior art, (A) is a top view of the 3rd-layer metal wiring layer, (B) is a top view of the 4th-layer metal wiring layer. 4A and 4B are diagrams showing a structure in which electrode pads are arranged in a driver transistor formation region in the conventional technology of a four-layer metal wiring layer structure, where FIG. 5A is a plan view and FIG. (C) is sectional drawing in the BB position of (A).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 LOCOS oxide film 5 Driver transistor formation area 7d Drain 7s Source 9 Gate oxide film 11 Gate electrode 13-1 BPSG film 13-2 First layer interlayer insulating film 13-3 Second layer interlayer insulating film 13-4 3 Layer interlayer insulating films 15s-1, 15d-1 Contact holes 15s-2, 15d-2 Through holes 15s-3, 15d-3 Through holes 15s-4, 15d-4 Through holes 17s-1, 17d-1 One layer Second metal wiring layers 17s-2, 17d-2 Second metal wiring layers 17s-3, 17d-3 Third metal wiring layers 17s-4, 17d-4 Fourth metal wiring layer 19 Final protective films 21d, 21s Pad opening 23d, 23s Electrode pad

Claims (1)

A driver transistor having a source and a drain, and a metal wiring layer structure of three or more layers formed on the driver transistor, and exposed to a pad opening formed in an insulating film on the uppermost metal wiring layer In a semiconductor device in which the metal wiring layer portion constitutes an electrode pad,
A source potential electrode pad electrically connected to the source as the electrode pad; and a drain potential electrode pad electrically connected to the drain;
The source potential electrode pad and the drain potential electrode pad are disposed on one of the driver transistors,
A metal wiring layer one layer lower than the uppermost metal wiring layer, a source potential 1 layer connected to the source potential electrode pad, and a drain potential 1 connected to the drain potential electrode pad Regarding the lower metal wiring layer, only the first source potential lower metal wiring layer is formed immediately below the source potential electrode pad, and only the lower first drain metal wiring layer is formed immediately below the drain potential electrode pad. Formed,
The source potential electrode pad, the source potential lower layer metal wiring layer, and the source electrically below the source potential electrode pad and the drain potential electrode pad and below the metal wiring layer lower than the first layer. The connected source potential metal wiring layer, the drain potential electrode pad, the drain potential one-layer lower metal wiring layer, and the drain potential metal wiring layer electrically connected to the drain are both disposed.
The source potential metal wiring layer and the drain potential metal wiring layer extend in the channel width direction of the driver transistor across the source potential one lower metal wiring layer and the drain potential one lower metal wiring layer. Is formed,
A plurality of the source potential lower metal wiring layer and the drain potential lower metal wiring layer, the source potential lower metal wiring layer and the drain potential lower metal wiring layer of the driver transistor; Alternatingly arranged in the channel width direction, the potential of the source potential metal wiring layer is drawn out to the plurality of one source potential lower metal wiring layers, and the potential of the drain potential metal wiring layer is extracted to the plurality of drain potential one layers. A semiconductor device characterized by being drawn out to a lower metal wiring layer.

Images