JP2012124506A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce area of a chip having an LDMOSFET, without deteriorating the high-frequency characteristics.SOLUTION: A p-type punching layer 4, electrically connecting a source region of an LDMOSFET and a source rear face electrode 36 formed on a rear face of a substrate 1, is formed of a low-resistance p-type polycrystalline silicon film which is doped with an impurity at high concentration, or a low-resistance metal film. And source wiring for electrically interconnecting sources of basic cells in the LDMOSFET is only wiring 24A. The number of wiring layers forming the source wiring is set smaller than the number of the wiring layers that form drain wiring (wiring 24B, 29B, 33).

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device mounted on an RF (Radio Frequency) power module.

  In Japanese Patent Laid-Open No. 10-27846 (Patent Document 1), by forming adjacent wirings with different wiring layers, the actual distance between wirings is made larger than when both wirings are formed with the same wiring layer. A technique for preventing the increase of the capacitance between wirings while improving the integration degree is disclosed.

  Japanese Patent Laid-Open No. 2000-323719 (Patent Document 2) discloses a low-resistance short-circuit layer under a gate electrode that short-circuits a semiconductor support substrate and a well region formed on the semiconductor support substrate via an insulating layer. A semiconductor device is disclosed which can be improved in breakdown resistance without increasing on-resistance by penetrating through the insulating layer and electrically connecting a semiconductor support substrate to a source electrode and grounding.

  In JP 2002-94054 A (Patent Document 3), a shield conductive layer having the same potential as the source and a thickness smaller than that of the gate electrode is provided above the n-type semiconductor region (drain / offset layer). Disclosed is a power MOSFET for an amplifying element in which a shield conductive layer and other electrode wiring are arranged in the order of a drain electrode, a shield conductive film, a gate electrode, a source electrode, and a gate short-circuit wiring, and output power characteristics and high frequency characteristics are good. Has been.

  Japanese Patent Laid-Open No. 2001-94094 (Patent Document 4) provides a conductor plug for extracting an electrode on a source region, a drain region, and a reach-through region, and connects the first wiring layer to the conductor plug; A technique for miniaturizing and reducing on-resistance in a high-frequency amplification MOSFET having a drain offset region in which a second wiring layer for lining is connected on a conductor plug to the first wiring layer is disclosed.

Japanese Patent Laid-Open No. 10-27846 JP 2000-323719 A JP 2002-94054 A JP 2001-94094 A

  In recent years, mobile communication devices such as GSM (Global System for Mobile Communications), PCS (Personal Communication Systems), PDC (Personal Digital Cellular), and CDMA (Code Division Multiple Access) are widely used. Is popular. In general, this type of mobile communication device includes an antenna that radiates and receives radio waves, a high-frequency power amplifier (RF power module) that amplifies and supplies a power-modulated high-frequency signal to the antenna, A receiving unit that performs signal processing, a control unit that performs these controls, and a battery (battery) that supplies a power supply voltage thereto are configured.

  Amplifying elements used in power amplifier circuits of RF power modules of mobile communication devices include compound semiconductor devices such as HBT and HEMT, silicon bipolar transistors, LDMOSFETs (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors, lateral diffusion MOSFETs) ) Etc. are used depending on the purpose and situation.

  In recent years, with the increase in the number of functions of mobile communication devices, there has been a strong demand for downsizing RF power modules, and a reduction in chip area is also required for amplification elements included in RF power modules. The present inventors are examining a technique for reducing the chip area of the LDMOSFET which is the amplifying element. Among them, the present inventors have found the following problems. The problem will be described with reference to FIGS.

  FIG. 38 is a plan view of a principal part of a chip on which an LDMOSFET studied by the present inventors is formed, and shows a basic cell of the LDMOSFET. FIG. 39 shows a cross section taken along line AA and line BB in FIG.

  The LDMOSFET studied by the present inventors has a structure in which a source electrode is a metal electrode 102 formed on the back surface of a semiconductor substrate (hereinafter simply referred to as a substrate) 101 and a source potential is obtained from the back surface of the substrate 101. Yes. Such a structure can reduce the parasitic inductance of the source and is excellent in terms of high-frequency characteristics such as power gain, as compared with the case where the source electrode is formed from a pad arranged on the main surface of the substrate. However, the punching layer 104 for electrically connecting the source region 103 on the main surface of the substrate 101 and the metal electrode 102 is required. The punched layer 104 is a region indicated by a broken line in FIGS. A drain region 105 formed on the main surface of the substrate 101 is electrically connected to upper wirings 106, 107, 108 and a drain pad (drain electrode) 109 which is a part of the wiring 108. The gate electrode 110 is electrically connected to a gate pad 111 formed in the same wiring layer as the wiring 108.

  The punching layer 104 is formed by introducing impurity ions into the substrate 101 with high concentration and high energy. When the punching layer 104 is formed by such a method, the energy and concentration at the time of introducing impurity ions are limited due to the apparatus for implanting impurity ions. Therefore, the subject that the parasitic resistance of the punching layer 104 becomes large arises. In order to suppress the deterioration of direct current characteristics such as an increase in on-resistance and a decrease in mutual conductance of the LDMOSFET, means for reducing the parasitic resistance by forming the punched layer 104 widely can be considered. However, the enlargement of the punched layer 104 causes a problem that prevents the chip area from being reduced.

  In view of this, it is conceivable to electrically reduce the source (source region 103) of the basic cell of the LDMOSFET so as to substantially reduce the parasitic resistance of the punched layer 104 and suppress the expansion of the punched layer 104. That is, the wirings 112, 113, 114 formed on each source region 103 and electrically connected to each source region 103 are electrically connected to each other via the wiring 113 </ b> A formed in the same layer as the wiring 113, Further, a peripheral punching layer 104A that is electrically connected to the wiring 113A is formed under the wiring 113A. Here, the peripheral punching layer 104A is the same as the punching layer 104 described above.

  However, when the chip area is reduced, the gate, drain, and source regions are reduced. As a result, the parasitic capacitance formed between the source and the drain increases, and among them, the parasitic capacitance formed between the wirings 112, 113, 114 serving as the source wiring and the wirings 106, 107, 108 serving as the drain wiring. The parasitic capacitance can be modeled in the same manner as the parallel plate type capacitance. That is, as shown in FIG. 40, the parasitic capacitance C1 between the source wiring and the drain wiring after the chip area reduction is larger than the parasitic capacitance C2 between the source wiring and the drain wiring before the chip area reduction.

  As shown in FIG. 41, when the distance between the source wiring and the drain wiring is narrowed, the source-drain capacitance (the output capacitance of the LDMOSFET) increases. Furthermore, as shown in FIG. 42, when the output capacitance increases, the LDMOSFET causes a problem that the power efficiency is lowered when used in a high frequency band.

  An object of the present invention is to provide a technique capable of reducing the area of a chip having an LDMOSFET without deteriorating high frequency characteristics.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
(1) A semiconductor device according to the present invention comprises:
A source region and a drain region of the second conductivity type formed on the main surface of the semiconductor substrate of the first conductivity type and spaced apart from each other across the channel formation region;
An LDMOSFET having a gate electrode formed on the channel formation region via a gate insulating film;
A source back electrode is formed on the back surface of the semiconductor substrate,
A first conductive layer mainly composed of polycrystalline silicon or metal that electrically connects the source region and the source back electrode is formed in the semiconductor substrate,
A plurality of layers of drain wiring electrically connected to the drain region and one or more layers of source wiring electrically connected to the source region are formed on the main surface of the semiconductor substrate,
The number of first wiring layers of the drain wiring is larger than the number of second wiring layers of the source wiring.
(2) The semiconductor device according to the present invention is
A source region and a drain region of the second conductivity type formed on the main surface of the semiconductor substrate of the first conductivity type and spaced apart from each other across the channel formation region;
An LDMOSFET having a gate electrode formed on the channel formation region via a gate insulating film;
A source back electrode is formed on the back surface of the semiconductor substrate,
A first conductive layer mainly composed of polycrystalline silicon or metal that electrically connects the source region and the source back electrode is formed in the semiconductor substrate,
In the main surface of the semiconductor substrate, a compound layer of silicon and metal is formed on the surface of the source region,
A drain electrode electrically connected to the drain region is formed on the main surface of the semiconductor substrate;
A first wiring electrically connected to the source back electrode is not disposed vertically above the compound layer.
(3) Further, the semiconductor device according to the present invention includes:
A source region and a drain region of the second conductivity type formed on the main surface of the semiconductor substrate of the first conductivity type and spaced apart from each other across the channel formation region;
A MOSFET having a gate electrode formed on the channel formation region via a gate insulating film;
The drain is formed of a second conductivity type drain low-concentration region and a drain conductivity region that is in contact with the drain low-concentration region and spaced apart from the channel formation region, and has a higher impurity concentration than the drain low-concentration region. A drain high concentration region,
The drain low concentration region is disposed between the gate electrode and the drain high concentration region in a plane,
The drain high concentration region is disposed apart from the gate electrode in a plane,
A source back electrode is formed on the back surface of the semiconductor substrate,
A first conductive layer mainly composed of polycrystalline silicon or metal that electrically connects the source region and the source back electrode is formed in the semiconductor substrate,
On the main surface of the semiconductor substrate, a first drain electrode electrically connected to the drain region, a first main surface source electrode electrically connected to the source region, the gate electrode, and the first drain An interlayer insulating film covering the electrode and the first main surface source electrode is formed;
A second drain electrode electrically connected to the first drain electrode is formed on the interlayer insulating film;
In the wiring layer in which the second drain electrode is disposed, the second main surface source electrode that is electrically connected to the first main surface source electrode is not disposed vertically above the first main surface source electrode.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the increase in parasitic capacitance between the source and the drain can be suppressed in the chip having the LDMOSFET, the area of the chip having the LDMOSFET can be reduced without deteriorating the high frequency characteristics.

1 is a circuit block diagram of an RF power module on which a semiconductor device according to a first embodiment of the present invention is mounted. It is a circuit diagram which shows the detection circuit of a Schottky barrier diode detection system. It is a top view which shows the structure of RF power module which is Embodiment 1 of this invention. It is sectional drawing along the AA line in FIG. It is a principal part top view explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing which shows the cross section along the BB line in FIG. FIG. 6 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 5; It is principal part sectional drawing which shows the cross section along the BB line in FIG. FIG. 8 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 7; It is principal part sectional drawing which shows the cross section along the BB line in FIG. FIG. 10 is an essential part plan view of the semiconductor device in manufacturing process, following FIG. 9; It is principal part sectional drawing which shows the cross section along the BB line in FIG. FIG. 12 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 11; It is principal part sectional drawing which shows the cross section along the BB line in FIG. FIG. 14 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 13; It is principal part sectional drawing which shows the cross section along the BB line in FIG. FIG. 16 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 15; It is principal part sectional drawing which shows the cross section along the BB line in FIG. It is explanatory drawing which compared the various characteristics of the semiconductor device which is Embodiment 1 of this invention, and the various characteristics of the semiconductor device which the present inventors examined. It is explanatory drawing which showed the relationship between the output electric power and power efficiency in the semiconductor device which is Embodiment 1 of this invention, and the semiconductor device which the present inventors examined. It is principal part sectional drawing of the semiconductor device which is Embodiment 2 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor device which is Embodiment 2 of this invention. It is explanatory drawing which compared the various characteristics of the semiconductor device which is Embodiment 2 of this invention, and the various characteristics of the semiconductor device which the present inventors examined. It is explanatory drawing which showed the relationship between the output electric power and power efficiency in the semiconductor device which is Embodiment 2 of this invention, and the semiconductor device which the present inventors examined. It is a principal part top view of the semiconductor device which is Embodiment 3 of this invention. It is a principal part top view explaining the manufacturing method of the semiconductor device which is Embodiment 3 of this invention. It is principal part sectional drawing which shows the cross section along the AA in FIG. 27, the BB line, and CC line. FIG. 28 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 27; It is principal part sectional drawing which shows the cross section along the AA in FIG. 29, the BB line, and CC line. FIG. 30 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 29; It is principal part sectional drawing which shows the cross section along the AA in FIG. 31, the BB line, and CC line. FIG. 32 is an essential part plan view of the semiconductor device in manufacturing process, following FIG. 31; It is principal part sectional drawing which shows the cross section along the AA in FIG. 33, the BB line, and CC line. FIG. 34 is a substantial part plan view of the semiconductor device during a manufacturing step following FIG. 33; It is principal part sectional drawing which shows the cross section along the AA in FIG. 35, the BB line, and CC line. FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36; It is a principal part top view of the chip | tip in which LDMOSFET which the present inventors examined was formed. It is sectional drawing in the position shown by the AA line in FIG. It is principal part sectional drawing of the chip | tip in which LDMOSFET which the present inventors examined was formed. It is explanatory drawing which showed the relationship between the source-drain wiring space | interval and output capacitance in the chip | tip in which LDMOSFET which the present inventors examined was formed. It is explanatory drawing which showed the relationship between the output capacity and power efficiency in the chip | tip in which LDMOSFET which the present inventors examined was formed.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, when referring to the constituent elements in the embodiments, etc., “consisting of A” and “consisting of A” do not exclude other elements unless specifically stated that only the elements are included. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  In the drawings used in the present embodiment, even a plan view may be partially hatched to make the drawings easy to see.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The semiconductor device according to the first embodiment is a chip mounted on, for example, an RF (Radio Frequency) power module used in a digital cellular phone (mobile communication device) that transmits information using a GSM network. is there.

  FIG. 1 is a circuit block diagram of the RF power module PM of the first embodiment. In FIG. 1, for example, two frequency bands of GSM900 and DCS1800 can be used (dual band system), and GMSK (Gaussian filtered Minimum Shift Keying) modulation system and EDGE (Enhanced Data GSM Environment) modulation system are used in each frequency band. The circuit block diagram (amplifier circuit) of the RF power module which can use two communication systems is shown.

  As shown in FIG. 1, the RF power module PM includes power amplifier circuits AMP1, AMP2, bias circuits BAC1, BAC2, power supply circuits PSC1, PSC2, matching circuits AJC1, AJC2, AJC3, AJC4, and detection circuits DEC1, DEC2, etc. Is included.

  The power amplification circuit AMP1 is a power amplification circuit for GSM900 including three amplification stages AMP11, AMP12, and AMP13.

  The power amplifier circuit AMP2 is a power amplifier circuit for the DCS 1800 including three amplifier stages AMP21, AMP22, and AMP23.

  The bias circuit BAC1 is a bias circuit that applies a bias voltage to the amplification stages AMP11 to AMP13 of the power amplifier circuit AMP1.

  The bias circuit BAC2 is a bias circuit that applies a bias voltage to the amplification stages AMP21 to AMP23 of the power amplifier circuit AMP2.

  The power supply circuit PSC1 is a power supply circuit that generates a power supply voltage to be applied to the drain terminal of the output LDMOSFET of each amplification stage AMP11 to AMP13 of the power amplifier circuit AMP1.

  The power supply circuit PSC2 is a power supply circuit that generates a power supply voltage that is applied to the drain terminal of the output LDMOSFET of each of the amplification stages AMP21 to AMP23 of the power amplifier circuit AMP2.

  The matching circuit AJC1 is a matching circuit between the input terminal IPT1 for GSM900 and the power amplifier circuit AMP1 (first amplification stage AMP11) for GSM900.

  The matching circuit AJC3 is an output matching circuit between the output terminal OPT1 for GSM900 and the power amplifier circuit AMP1 (third amplification stage AMP13) for GSM900.

  The matching circuit AJC2 is a matching circuit between the input terminal IPT2 for DCS1800 and the power amplifier circuit AMP2 (first amplification stage AMP21) for DCS1800.

  The matching circuit AJC4 is an output matching circuit between the output terminal OPT2 for DCS1800 and the power amplifier circuit AMP2 (third amplifier stage AMP23) for DCS1800.

  The detection circuit DEC1 is a detection circuit for detecting an output (output signal, output power) from the power amplification circuit AMP1 for GSM900.

  The detection circuit DEC2 is a detection circuit for detecting an output (output signal, output power) from the power amplification circuit AMP2 for DCS1800.

  Among these circuits, the power amplification circuit AMP1 (amplification stages AMP11 to AMP13) for GSM900, the power amplification circuit AMP2 (amplification stages AMP21 to AMP23) for DCS1800, the bias circuits BAC1 and BAC2, the detection circuits DEC1 and DEC2, It is formed in one chip CHP.

  Although not shown, a matching circuit (interstage matching circuit) may be provided between the amplification stages AMP12 to AMP13 and between the amplification stages AMP21 to AMP23.

  The RF input signal input to the input terminal IPT1 for GSM900 of the RF power module PM is input to the chip CHP via the matching circuit AJC1, and amplified by the power amplifier circuit AMP1 in the chip CHP, that is, the three amplification stages AMP11 to AMP13. Is output from the chip CHP, and output as an RF output signal from the output terminal OPT1 for GSM900 via the matching circuit AJC3.

  The RF input signal input to the DCS 1800 input terminal IPT2 of the RF power module PM is input to the chip CHP via the matching circuit AJC2, and amplified by the power amplifier circuit AMP2 in the chip CHP, that is, the three amplification stages AMP21 to AMP23. Is output from the chip CHP, and output as an RF output signal from the output terminal OPT2 for the DCS 1800 via the matching circuit AJC4.

  The bias control signal input to the bias control signal input terminal BIT1 for GSM900 of the RF power module PM is input to the bias circuit BAC1, and is applied to the amplification stages AMP11 to AMP13 of the power amplifier circuit AMP1 based on the bias control signal. The bias voltage is controlled.

  The bias control signal input to the bias control signal input terminal BIT2 for DCS 1800 of the RF power module PM is input to the bias circuit BAC2, and is applied to the amplification stages AMP21 to AMP23 of the power amplifier circuit AMP2 based on the bias control signal. The bias voltage is controlled.

  The output (output signal, output power) from the power amplifier circuit AMP1 for GSM900 is detected by the detection circuit DEC1, and the detection signal (output power detection signal) detected by the detection circuit DEC1 is for GSM900 of the RF power module PM. The output detection signal is output from the output terminal OPT3.

  The output (output signal, output power) from the power amplifier circuit AMP2 for DCS1800 is detected by the detection circuit DEC2, and the detection signal (output power detection signal) detected by the detection circuit DEC2 is for the DCS1800 of the RF power module PM. The output detection signal is output from the output terminal OPT4.

  Each of the power amplifier circuits AMP1 and AMP2 has a circuit configuration in which three n-channel LDMOSFETs are sequentially connected as the three amplification stages AMP11 to AMP13 and AMP21 to AMP23. That is, each amplification stage AMP11, AMP12, AMP13, AMP21, AMP22, AMP23 is formed by an n-channel LDMOSFET, and three n-channel LDMOSFETs are sequentially connected to form a power amplifier circuit AMP1, thereby forming three n-channels. The type LDMOSFETs are sequentially connected to form a power amplifier circuit AMP2.

  As one of methods for detecting the output power of the RF power module, there is an SBD detection method using a Schottky Barrier Diode (SBD). FIG. 2 is a circuit diagram showing a detection circuit of this SBD detection method. In the first embodiment, the detection circuits DEC1 and DEC2 of the RF power module PM use detection circuits of the SBD detection method as shown in FIG.

  By incorporating detection circuits DEC1 and DEC2 of the SBD detection system as shown in FIG. 2 in the RF power module PM, the output power amplified and output by the power amplification circuits AMP1 and AMP2 of the RF power module PM is detected by the detection circuit. It can be detected with high sensitivity by DEC1 and DEC2. In addition, a Schottky barrier diode having better turn-off characteristics than a PN junction diode is preferably used because it operates in a microwave band or the like.

  The detection circuits DEC1 and DEC2 of the SBD detection method are configured by a Schottky barrier diode element SD1, a capacitive element C22, and a resistance element R23. If these elements constituting the detection circuit of the SBD detection method are formed by chip components (chip diodes, chip capacitors, and chip resistors) and mounted on the wiring board (module board) constituting the RF power module. As a result, the planar size of the RF power module increases, resulting in a problem that the RF power module becomes larger.

  Here, in the first embodiment, the detection circuit (detection circuits DEC1, DEC2) of the SBD detection method as shown in FIG. 2 is formed (integrated) in the same chip CHP together with the power amplification circuits (AMP1, AMP2). The chip CHP is mounted on a wiring board (module board) to obtain an RF power module PM.

  However, the method for detecting the output power of the RF power module is not limited to the SBD detection method shown in the first embodiment, and there are a plurality of detection methods using MOSFETs, and the detection method is selected according to the application. Is possible.

  FIG. 3 is a top view (plan view) showing the structure of the RF power module PM of the first embodiment, and FIG. 4 shows a cross section taken along line AA in FIG.

  The RF power module PM of this embodiment shown in FIGS. 3 and 4 is mounted (mounted) on the wiring board MB1, the chip CHP mounted (mounted) on the wiring board MB1, and the wiring board MB. It has a passive component PP1 and a sealing resin MR1 that covers the upper surface of the wiring board MB1 including the chip CHP and the passive component PP1. The chip CHP and the passive component PP1 are electrically connected to the conductor layer (transmission line) of the wiring board MB1. Further, the RF power module PM can be mounted on, for example, an external circuit board or a mother board (not shown).

Wiring substrate MB1 is, for example, a multilayer substrate (multilayer wiring substrate) in which a plurality of insulating layers (dielectric layers) IL1 and a plurality of conductor layers or wiring layers (not shown) are stacked and integrated. In FIG. 4, four insulating layers IL1 are stacked to form the wiring board MB1, but the number of stacked insulating layers IL1 is not limited to this and can be variously changed. As a material for forming the insulating layer IL1 of the wiring board MB1, a ceramic material such as alumina (aluminum oxide, Al ₂ O ₃ ) can be used. In this case, the wiring board MB1 is a ceramic multilayer board. The material of the insulating layer IL1 of the wiring board MB1 is not limited to a ceramic material and can be variously changed. For example, a glass epoxy resin may be used.

  A conductor layer for wiring formation is formed on the upper surface MBU and the lower surface MBB of the wiring board MB1 and between the insulating layers IL1. A substrate-side terminal MBT made of a conductor is formed on the upper surface MBU of the wiring substrate MB1 by the uppermost conductor layer of the wiring substrate MB1, and a conductor is formed on the lower surface MBB of the wiring substrate MB1 by the lowermost conductor layer of the wiring substrate 3. The external connection terminal OCT consisting of is formed. The external connection terminal OCT corresponds to, for example, the input terminals IPT1 and IPT2, the output terminals OPT1 and OPT2, the bias control signal input terminals BIT1 and BIT2, and the output detection signal output terminals OPT3 and OPT4 in FIG. A conductor layer is also formed inside the wiring board MB1, that is, between the insulating layers IL1. Of the wiring patterns formed by the conductor layer of the wiring board MB1, a wiring pattern for supplying a reference potential (for example, the reference potential supplying terminal GNDT on the lower surface MBB of the wiring board MB1) is a wiring forming surface of the insulating layer IL1. The wiring pattern for the transmission line can be formed as a belt-like pattern.

  Each conductor layer (wiring layer) constituting the wiring board MB1 is electrically connected through a conductor or a conductor film in the via hole VH1 formed in the insulating layer IL1 as necessary. Accordingly, the board-side terminal MBT on the upper surface MBU of the wiring board MB1 is provided on the upper surface MBU of the wiring board MB1 and / or an internal wiring layer (wiring layer between the insulating layers IL1), a conductor film in the via hole VH1, etc. Is electrically connected to the external connection terminal OCT on the lower surface MBB of the wiring board MB1. Of the via holes VH1, the via holes VHC provided below the chip CHP can function as thermal vias for conducting heat generated in the chip CHP to the lower surface MBB side of the wiring board MB1.

  The chip CHP mounting region of the wiring board MB1 is provided with a planar rectangular recess HL1 called a cavity, and the chip CHP is bonded to the conductor layer CND1 on the bottom surface of the recess HL1 of the wiring board MB1 with, for example, a bonding material such as solder SLD. Is die-bonded face-up. For die bonding of the chip CHP, silver paste or the like can be used instead of the solder SLD. The electrode (bonding pad) BP1 formed on the surface (upper surface) of the chip CHP is electrically connected to the substrate-side terminal MBT of the upper surface MBU of the wiring substrate MB1 via the bonding wire BW1. Further, a back electrode ELB is formed on the back surface of the chip CHP, and the back electrode ELB of the chip CHP is connected (bonded) to the conductor layer CND1 on the bottom surface of the recess HL1 of the wiring board MB1 by a bonding material such as solder SLD. Further, it is electrically connected to the reference potential supply terminal GNDT on the lower surface MBB of the wiring board MB1 through a conductor film or the like in the via hole VH1.

  The passive component PP1 is a passive element such as a resistance element (for example, a chip resistor), a capacitance element (for example, a chip capacitor) or an inductor element (for example, a chip inductor), and is a chip part, for example. The passive component PP1 is mounted on a board-side terminal MBT on the upper surface MBU of the wiring board MB1 with a bonding material (adhesive) having good conductivity such as solder SLD2. The board-side terminal MBT on the upper surface MBU of the wiring board MB1 to which the chip CHP or the passive component PP1 is electrically connected is connected to the wiring board MB1 via a wiring layer inside the wiring board MB1 or a conductor film in the via hole VH1. The lower surface MBB is electrically connected to the external connection terminal OCT. In the first embodiment, since the Schottky barrier diode elements for the detection circuits DEC1 and DEC2 are formed in the chip CHP, the Schottky barrier diode elements other than the Schottky barrier diode formed in the chip CHP are connected to the wiring. It is not mounted on the upper surface MBU of the substrate MB1.

  The sealing resin MR1 is formed on the wiring board MB1 so as to cover the chip CHP, the passive component PP1, and the bonding wire BW1. The sealing resin MR1 is made of a resin material such as an epoxy resin, for example, and can contain a filler.

  Next, a manufacturing method of the LDMOSFET formed in the chip CHP will be described in the order of steps with reference to FIGS. Of the drawings for explaining the method of manufacturing the LDMOSFET according to the first embodiment, FIGS. 5, 7, 9, 11, 13, 15, and 17 are plan views of main parts during the manufacturing process. 6, 8, 10, 12, 14, 16, and 18 are respectively taken along line BB in FIGS. 5, 7, 9, 11, 13, 15, and 17. It is principal part sectional drawing which shows the cross section along.

  First, as shown in FIGS. 5 and 6, an epitaxial layer 2 made of p-type single crystal silicon is formed on the main surface of a substrate 1 made of p-type (first conductivity type) single crystal silicon by using a known epitaxial growth method. Form.

  Subsequently, a silicon oxide film having a thickness of about 150 nm is formed on the substrate 1, and the silicon oxide film is etched using a photoresist film patterned by a photolithography technique as a mask. Next, a part of the epitaxial layer 2 is etched using the remaining silicon oxide film as a mask to form a groove 3 having a depth of about 2.2 μm reaching the substrate 1.

Subsequently, after depositing a p-type polycrystalline silicon film doped with a p-type impurity (for example, B (boron)) at a high concentration on the substrate 1 including the inside of the groove 3 by the CVD method, By removing the crystalline silicon film by an etch back method, a p-type punching layer 4 made of a p-type polycrystalline silicon film is formed inside the groove 3. In the first embodiment, the amount of the p-type impurity contained in the p-type punching layer 4 can be exemplified as about 7 × 10 ²⁰ / cm ³ . Thus, by embedding the p-type polycrystalline silicon film doped with impurities at a high concentration in the trench 3, the p-type punching layer (first conductive layer) 4 having a low parasitic resistance can be formed. Further, instead of the polycrystalline silicon film, a metal film (for example, W (tungsten) film) may be embedded in the trench 3, and in this case, a punched layer having a smaller parasitic resistance can be formed.

  Subsequently, the epitaxial layer 2 is etched using a silicon nitride film patterned by photolithography as a mask to form a groove, and a silicon oxide film is buried in the groove to form an element isolation region. By forming this element isolation region, an active region L in which the LDMOSFET cell is formed is defined on the main surface of the substrate 1.

Next, as shown in FIGS. 7 and 8, boron is ion-implanted into a portion of the epitaxial layer 2 using the photoresist film as a mask, thereby forming a p-type well 5 for a punch-through stopper. The p-type well 5 is mainly formed in the source formation region and the channel formation region of the LDMOSFET. The ion implantation conditions are, for example, that the first time is an acceleration energy of about 200 keV and a dose amount of about 2.0 × 10 ¹³ / cm ² , and the second time is an acceleration energy of about 50 keV and a dose amount of about 1.0 × 10 ¹³ / cm ² . is there.

  Subsequently, after cleaning the surface of the epitaxial layer 2 with hydrofluoric acid, the substrate 1 is heat-treated at about 800 ° C. to form a gate insulating film 6 made of a silicon oxide film having a thickness of about 11 nm on the surface of the epitaxial layer 2. To do. The gate insulating film 6 may be a silicon oxide film containing nitrogen, a so-called oxynitride film, instead of the thermal oxide film. In this case, hot electron traps at the interface of the gate insulating film 6 can be reduced. Alternatively, a silicon oxide film may be deposited on the thermal oxide film by a CVD method, and the gate insulating film 6 may be constituted by these two oxide films.

  Next, a gate electrode 7 is formed on the gate insulating film 6. In order to form the gate electrode 7, for example, a non-doped polycrystalline silicon film having a thickness of about 250 nm is deposited on the gate insulating film 6 by the CVD method, and n-type impurities are introduced into the polycrystalline silicon film. After a cap insulating film 8 made of a silicon oxide film having a thickness of about 125 nm is deposited on the crystalline silicon film by CVD, the cap insulating film 8 and the polycrystalline silicon film are dry etched using the photoresist film as a mask.

Next, an n ⁻ type (second conductivity type) offset drain region (drain low concentration region) 9 is formed by ion implantation of P (phosphorus) into a part of the epitaxial layer 2 using the photoresist film as a mask. . The n ⁻ -type offset drain region 9 is terminated at the lower portion of the side wall of the gate electrode 7 so that the end thereof is in contact with the channel formation region. The ion implantation conditions for forming the n ⁻ type offset drain region 9 are, for example, an acceleration energy of 40 keV and a dose amount of 8.0 × 10 ¹² / cm ² . Thus, by reducing the impurity concentration of the n ⁻ -type offset drain region 9, a depletion layer spreads between the gate electrode 7 and the drain, and therefore, a feedback capacitance (Cgd) formed between the two. Is reduced.

Next, after removing the photoresist film, an n ⁻ type source region 10 is formed by ion-implanting As (arsenic) into the surface of the p-type well 5 using the new photoresist film as a mask. The ion implantation conditions at this time are, for example, acceleration energy of ¹⁵ keV and a dose of 3.0 × 10 ¹⁵ / cm ² . As described above, the impurity (As) is ion-implanted with low acceleration energy and the n ⁻ -type source region 10 is formed shallow, so that the spread of the impurity from the source to the channel formation region can be suppressed. The decrease can be suppressed.

Subsequently, B (boron) is ion-implanted into the surface of the p-type well 5 using the photoresist film as a mask, thereby forming a p-type halo region 11 under the n ⁻ -type source region 10. At this time, an oblique ion implantation method in which impurities are ion-implanted from an oblique direction of 30 degrees with respect to the main surface of the substrate 1 is performed, for example, with an acceleration energy of 15 keV and a dose amount of 8.0 × 10 ¹² / cm ^2. After that, the operation of rotating the substrate 1 by 90 degrees is repeated four times. The p-type halo region 11 is not necessarily formed. However, when the p-type halo region 11 is formed, the diffusion of impurities from the source to the channel formation region is further suppressed, and the short channel effect is further suppressed. The voltage drop can be further suppressed.

  Next, after removing the photoresist film, sidewall spacers 12 are formed on the sidewalls of the gate electrode 7. The sidewall spacer 12 is formed by depositing a silicon oxide film on the substrate 1 by a CVD method and then anisotropically etching the silicon oxide film. The silicon oxide film for the sidewall spacer 12 is specifically an HLD (High Temperature Low Pressure Decomposition) film formed by thermally decomposing TEOS (tetraethyl orthosilicate) which is an organic source. The HLD film is excellent in film thickness uniformity and has a feature that impurities hardly diffuse in the film.

Next, P (phosphorus) is ion-implanted into a part of the n ⁻ -type offset drain region 9 using a photoresist film having an opening above the drain forming region as a mask. The ion implantation conditions at this time are, for example, acceleration energy of 40 keV and a dose amount of 8.0 × 10 ¹² / cm ² . As a result, a part of the n ⁻ type offset drain region 9 is partially self-aligned with the side wall spacer 12 formed on the drain side wall of the gate electrode 7. Density region) 13 is formed.

Since the acceleration energy of the ion implantation is the same as the acceleration energy of ion implantation performed when forming the n ⁻ type offset drain region 9, the junction depth of the n type offset drain region 13 is the same as that of the n ⁻ type offset drain region 9. It becomes almost the same as the junction depth. Further, since the impurity implanted into the n-type offset drain region 13 is an impurity (P) having the same conductivity type as the impurity implanted into the n ⁻ -type offset drain region 9, the impurity concentration of the n-type offset drain region 13 is n ^It becomes higher than the impurity concentration of the ⁻ type offset drain region 9. That is, since the n-type offset drain region 13 has a lower resistance than the n ⁻ -type offset drain region 9, the on-resistance (Ron) can be reduced.

The n ⁻ -type offset drain region 9 is formed in a self-aligned manner with respect to the gate electrode 7, whereas the n-type offset drain region 13 is self-aligned with respect to the sidewall spacer 12 on the side wall of the gate electrode 7. Therefore, the n-type offset drain region 13 is formed away from the gate electrode 7 by an amount corresponding to the film thickness of the sidewall spacer 12 along the gate length direction. Therefore, even if the impurity concentration of the n-type offset drain region 13 is increased, the influence on the feedback capacitance (Cgd) is small.

Next, after removing the photoresist film used to form the n ⁻ -type offset drain region 9, a photo having an opening above each of a part of the n-type offset drain region 13 and the p-type well 5 in the source formation region. Using the resist film as a mask, As (arsenic) ions are implanted into a part of each of the n-type offset drain region 13 and the p-type well 5. The ion implantation conditions at this time are, for example, an acceleration energy of 60 keV and a dose of 8.0 × 10 ¹⁵ / cm ² .

By the above ion implantation, an n ⁺ type having a higher impurity concentration than the n-type offset drain region 13 and further away from the channel formation region than the n-type offset drain region 13 is partially formed in the n-type offset drain region 13. A drain region (drain high concentration region) 15 is formed. At this time, the parasitic capacitance between the source and the drain is formed by forming the n ⁺ -type drain region 15 having a high impurity concentration shallower than the n-type offset drain region 13 and the n ⁻ -type offset drain region 9 having a low impurity concentration. (Drain capacitance) can be reduced.

Furthermore, by ion implantation described above, the p-type well 5, the n ^- -type source region impurity concentration higher than 10, and n ^- -type source region n ⁺ -type source region 16 is deeper at the bottom than 10 forms Is done. Since the n ⁺ -type source region 16 is formed in a self-aligned manner with respect to the sidewall spacer 12 on the side wall of the gate electrode 7, channel formation is performed corresponding to the film thickness of the sidewall spacer 12 along the gate length direction. It is formed away from the region.

Thus, the n ⁺ -type source region 16 by self-alignment manner with the side wall spacers 12, it is possible to define the distance between the n ⁺ -type source region 16 and the channel formation region with high accuracy. On the other hand, if the n ⁺ -type source region 16 separated from the channel formation region is formed by ion implantation using the photoresist film as a mask without forming the sidewall spacer 12 on the sidewall of the gate electrode 7, the photomask is misaligned. As a result, the distance between the n ⁺ -type source region 16 and the channel formation region varies. In this case, if the end of the n ⁺ -type source region 16 gets too close to the channel formation region, the impurity in the n ⁺ -type source region 16 diffuses into the channel formation region and the threshold voltage varies. On the other hand, if the end portion of the n ⁺ -type source region 16 is too far from the channel formation region, the source resistance increases.

Therefore, according to the first embodiment in which the n ⁺ -type source region 16 is formed in a self-aligned manner with respect to the sidewall spacer 12, the above-mentioned problem can be avoided even when the LDMOSFET is miniaturized. Can be promoted.

Through the steps so far, the drain composed of the n ⁻ type offset drain region 9, the n type offset drain region 13 and the n ⁺ type drain region 15, and the source composed of the n ⁻ type source region 10 and the n ⁺ type source region 16. An LDMOSFET having is completed.

In the LDMOSFET, an n ⁻ type offset drain region (drain low concentration region) 9 is formed on one side (drain) side of the gate electrode 7 to enable high voltage driving with a short channel length, and the other side (source) side is formed. A p-type well 5 is formed in the source formation region and the channel formation region. Further, the amount of charge in the n ⁻ -type offset drain region 9 and the distance between the end of the gate electrode 7 and the n ⁺ -type drain region (drain high concentration region) 15 in the plane are the maximum breakdown voltage of the LDMOSFET. Must be optimized to be a value.

Next, after removing the photoresist film used to form the n ⁺ -type drain region 15 and the n ⁺ -type source region 16, the p-type punching layer is formed using the photoresist film having an opening on the p-type punching layer 4 as a mask. By ion-implanting boron fluoride (BF ₂ ) into the surface of 4, a p ⁺ type semiconductor region 17 is formed, and the resistance of the surface of the p type punching layer 4 is reduced. The ion implantation conditions are, for example, an acceleration energy of 60 keV and a dose of 2.0 × 10 ¹⁵ / cm ² .

Next, after removing the photoresist film used to form the p ⁺ -type semiconductor region 17, as shown in FIGS. 9 and 10, a silicon nitride film 20 and a film having a thickness of about 50 nm are formed on the substrate 1 by CVD. After the silicon oxide film 21 having a thickness of about 1400 nm is deposited, the surface of the silicon oxide film 21 is planarized using a chemical mechanical polishing method, and then the silicon oxide film 21 is formed using the photoresist film as a mask. And the silicon nitride film 20 are dry-etched to form the p-type punching layer 4 (p ⁺ -type semiconductor region 17), the source (n ⁺ -type source region 17), the drain (n ⁺ -type drain region 15), and the gate electrode 7 A contact hole 22 is formed in each upper part.

  Subsequently, a Ti (titanium) film having a thickness of about 10 nm and a TiN (titanium nitride) film having a thickness of about 50 nm are sequentially deposited on the substrate 1 including the inside of the contact hole 22 by a sputtering method. Next, a W (tungsten) film is deposited on the substrate 1 by the CVD method, and the contact hole 22 is filled with the W film. Next, the W film, the TiN film, and the Ti film on the substrate 1 are removed by CMP (Chemical Mechanical Polishing) method to leave the W film, the TiN film, and the Ti film in the contact hole 22, thereby leaving the contact hole 22 in the contact hole 22. A plug 23 made of a W film, a TiN film, and a Ti film is formed.

Next, as shown in FIGS. 11 and 12, a WN (tungsten nitride) film having a thickness of about 5 nm and a W film having a thickness of about 100 nm are sequentially deposited on the substrate 1 by sputtering. Subsequently, by etching this stacked film using the photoresist film as a mask, wiring (first main surface source electrode) 24A, n ⁺ electrically connected to the n ⁺ type source region 16 and the p ⁺ type semiconductor region 17 A wiring (first drain electrode) 24B electrically connected to the mold drain region 15 and a wiring 24C electrically connected to the gate electrode 7 are formed.

  Next, as shown in FIGS. 13 and 14, a silicon oxide film 26 having a thickness of about 1100 nm is deposited on the wirings 24A, 24B, and 24C by a CVD method, and then a part of the silicon oxide film 26 is etched. Through holes 27 reaching the wiring 24B and the wiring 24C are formed. Subsequently, the plug 28 is formed in the through hole 27 by a process similar to the process of forming the plug 23 (see FIGS. 9 and 10).

Subsequently, a Ti film having a thickness of about 10 nm, a TiN film having a thickness of about 50 nm, a Ti film having a thickness of about 10 nm, an Al film having a thickness of about 800 nm, and a thickness of about 10 nm are formed on the silicon oxide film 26 including the plug 28. A Ti film and a TiN film having a thickness of about 75 nm are sequentially laminated to form a laminated film. Next, this laminated film is patterned by etching using a photoresist film as a mask, and the drain (n ⁻ type offset drain region 9, n type offset drain region 13 and n ⁺ type drain region 15) of the LDMOSFET and the wiring 24B are electrically connected. A wiring (second drain electrode) 29B connected to, and a wiring 29C electrically connected to the gate electrode 7 and the wiring 24C are formed.

  Next, as shown in FIGS. 15 and 16, a silicon oxide film 30 having a thickness of about 1600 nm is deposited on the silicon oxide film 26 including the wirings 29B and 29C by the CVD method. Subsequently, a part of the silicon oxide film 30 is etched to form a through hole 31 reaching the wiring 29B and the wiring 29C. The through hole 31 reaching the wiring 29C is formed in a region not shown in FIGS. Subsequently, the plug 32 is formed in the through hole 31 by the same process as the process of forming the plugs 23 and 28.

Next, as shown in FIGS. 17 and 18, a Ti film having a thickness of about 10 nm, an Al film having a thickness of about 2000 nm, and a TiN film having a thickness of about 75 nm are sequentially formed on the silicon oxide film 30 including the plug 32. A laminated film is formed by laminating. Next, this laminated film is patterned by etching using a photoresist film as a mask, and the drain (n ⁻ type offset drain region 9, n type offset drain region 13 and n ⁺ type drain region 15) of the LDMOSFET and wirings 24 B and 29 B A wiring (second drain electrode) 33 to be electrically connected and wirings to be electrically connected to the gate electrode 7 and the wirings 24C and 29C are formed. Note that the wiring electrically connected to the gate electrode 7 and the wirings 24C and 29C is formed in a region not shown in FIGS. A part of the wiring 33 becomes a drain pad to be described later in a later process, and a part of the wiring electrically connected to the gate electrode 7 and the wirings 24C and 29C becomes a gate pad to be described later in a later process.

  Next, a silicon oxide film 34 having a thickness of about 800 nm and a nitridation having a thickness of 300 nm are formed on the silicon oxide film 30 including the wiring 33 and the gate electrode 7 and wirings electrically connected to the wirings 24C and 29C by a CVD method. A silicon film 35 is deposited.

  Subsequently, the silicon nitride film 35 and the silicon oxide film 34 are etched using the photoresist film as a mask, and openings are opened in the opening reaching the wiring 33 and the wiring electrically connected to the gate electrode 7 and the wirings 24C and 29C. To do. Thereby, a drain pad (drain electrode) 33A composed of a part of the wiring 33 and a gate pad (not shown) composed of a part of the wiring electrically connected to the gate electrode 7 and the wirings 24C and 29C are formed. .

  Next, the back surface of the substrate 1 is polished by about 280 nm, and then the source back electrode 36 is formed on the back surface of the substrate 1. The source back electrode 36 can be formed by depositing, for example, a Ni (nickel) -Cu (copper) alloy film having a thickness of about 600 nm by a sputtering method.

  Thereafter, the substrate 1 is cut along divided regions (not shown) to be separated into individual chips CHP, and then soldered to the wiring substrate MB1 via the source back surface electrode 36. 1 semiconductor device is manufactured.

According to the first embodiment, the p-type punching layer 4 is formed from a low-resistance p-type polycrystalline silicon film or a low-resistance metal film doped with impurities at a high concentration. Therefore, in order to substantially reduce the parasitic resistance of the p-type punching layer 4, a wiring (hereinafter referred to as a source) that electrically connects the sources (n ⁺ -type source region and p ⁺ -type semiconductor region 17) of the basic cells of the LDMOSFET. The wiring 24A is the only wiring 24A, and other source wiring (second main surface source electrode) need not be formed on the source. That is, the number of wiring layers (second wiring layer number) forming the source wiring is smaller than the number of wiring layers (first wiring layer number) forming the drain wiring (wirings 24B, 29B, 33). Thereby, the parasitic capacitance (output capacitance) between the drain wiring and the source wiring can be greatly reduced. According to experiments conducted by the present inventors, the structure of the first embodiment has an output capacity of about 30% of the LDMOSFET as compared with the structure in which the source wiring is formed also on the wiring 24A (conventional structure). This could be reduced (see FIG. 19).

  In the LDMOSFET which is an amplifying element, the parasitic capacitance has a large influence on the high-frequency output characteristics. If the output capacitance increases, the impedance value decreases in the operation in the high-frequency band, so that the current flowing into the LDMOSFET increases. . Further, since the LDMOSFET also has a parasitic resistance, the loss (power consumed) caused by the parasitic resistance increases as the flowing current increases. For this reason, when the output capacity increases, there is a problem in that the power efficiency of the amplifying element is reduced. On the other hand, if the output capacitance is reduced, the current flowing into the LDMOSFET is also reduced, so that the power efficiency as the amplifying element can be improved. Here, FIG. 20 shows the relationship of the power efficiency PAE (%) with respect to the output power Pout (dBm) in each of the LDMOSFET of the conventional structure and the LDMOSFET of the first embodiment, and the operating frequency f of the LDMOSFET is The graph in the case of 900 MHz is shown. As shown in FIG. 20, according to the LDMOSFET of the first embodiment, the output efficiency PAE (%) can be improved by about 2% as compared with the LDMOSFET having the conventional structure.

  Further, according to the first embodiment, the p-type punching layer 4 is formed from a low-resistance p-type polycrystalline silicon film or a low-resistance metal film doped with impurities at a high concentration. Therefore, the p-type punching layer 4 for electrically connecting the sources of the basic cells of the LDMOSFET can be omitted. Thereby, the chip CHP can be reduced in size. Further, even if the source and drain are brought closer to reduce the area of the chip CHP, there is no source wiring other than the wiring 24A, so that the parasitic capacitance between the source wiring and the drain wiring increases. Can be prevented. That is, according to the first embodiment, it is possible to reduce the size of the chip CHP without degrading the high frequency characteristics of the LDMOSFET.

(Embodiment 2)
FIG. 21 is a cross-sectional view of the main part in the chip CHP in the second embodiment.

In the second embodiment, the wiring 24A (see, for example, FIG. 18) and the plug 23 (see, for example, FIG. 18) connected to the wiring 24A in the first embodiment are omitted, and the n ⁺ -type source region 16 and the p ⁺ -type semiconductor. A silicide layer (compound layer) 24D made of, for example, Co (cobalt) and silicon is provided on the surface of the region 17. By providing such a silicide layer 24D, the wiring (first wiring) 24A and the plug (first wiring) 23 connected to the wiring 24A shown in the first embodiment can be provided via the silicide layer 24D. , Source current can flow from the n ⁺ type source region 16 to the p ⁺ type semiconductor region 17, from the p ⁺ type semiconductor region 17 to the p type punching layer 4, and from the p type punching layer 4 to the source back electrode 36. . Thereby, the height of the source wiring is lower than that of the first embodiment, and the area where the source wiring and the drain wiring are opposed to each other is smaller than that of the first embodiment. Therefore, the parasitic capacitance between the source wiring and the drain wiring can be reduced as compared with the first embodiment.

  In addition, the structure in which the sources are not electrically connected to each other by the source wiring between the basic cells of the LDMOSFET increases the parasitic resistance of the source, and the DC characteristics such as an increase in on-resistance and a decrease in mutual conductance of the LDMOSFET. There is a risk of the occurrence of problems that cause deterioration. However, according to the second embodiment, as in the first embodiment, the p-type punching layer 4 is formed from a low-resistance p-type polysilicon film or a low-resistance metal film doped with impurities at a high concentration. Therefore, the resistance value per unit area of the p-type punching layer 4 can be reduced. As a result, an increase in the parasitic resistance of the source can be suppressed, so that it is possible to prevent the direct current characteristics of the LDMOSFET from deteriorating.

In order to form the silicide layer 24D, after forming the p ⁺ type semiconductor region 17 (see FIG. 8), as shown in FIG. 22, the regions other than the n ⁺ type source region 16 and the p ⁺ type semiconductor region 17 are formed. The region is covered with a photoresist film RESI. Next, the oxide films on the surfaces of the n ⁺ type source region 16 and the p ⁺ type semiconductor region 17 are removed by etching using the photoresist film RESI as a mask. Next, after depositing, for example, a cobalt film 24E on the substrate 1 using the photoresist film RESI as a mask, the substrate 1 is subjected to heat treatment to cause the cobalt film 24E to react with silicon forming the substrate 1 (epitaxial layer 2). Thus, the silicide layer 24 ^< / b ^> D can be formed on the surfaces of the n ⁺ type source region 16 and the p ⁺ type semiconductor region 17.

In the description of the second embodiment, the case where the wiring 24A as the source wiring is omitted has been described, but the wiring 24A may be formed as shown in FIG. In this case, the parasitic resistance of the path from the n ⁺ type source region 16 to the p type punching layer 4 can be further reduced as compared with the structure shown in FIG. Also, the output capacity of the LDMOSFET can be reduced. According to experiments conducted by the present inventors, the output capacitance of the LDMOSFET is larger in the structure of the second embodiment as compared with the structure in which the source wiring is also formed on the wiring 24A (conventional structure). The reduction was about 34% (see FIG. 24).

  FIG. 25 shows the relationship of the power efficiency PAE (%) to the output power Pout (dBm) in each of the LDMOSFET having the conventional structure, the LDMOSFET of the first embodiment, and the LDMOSFET of the second embodiment. The graph in case the operating frequency f of LDMOSFET is 900 MHz is shown. As shown in FIG. 25, according to the LDMOSFET of the second embodiment, the output efficiency PAE (%) can be improved by about 2% as compared with the LDMOSFET having the conventional structure.

  According to the second embodiment described above, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
In the third embodiment, elements other than LDMOSFETs are formed in the chip CHP shown in the first and second embodiments.

  FIG. 26 is a plan view of the main part of the chip CHP of the third embodiment. In the third embodiment, an active element 41 such as an LDMOSFET and passive elements such as a capacitor 42 and a resistor 43 are formed in the chip CHP. The active element 41 and the passive element are the same as those in the above embodiment. The power amplifier circuits AMP1 and AMP2 (see FIG. 1) described in the first embodiment are formed. A bonding pad BP1 (see also FIG. 3) that is electrically connected to the active element 41 and the passive element is formed on the main surface of the chip CHP. The manufacturing process of the chip CHP of the third embodiment will be described with reference to FIGS. Of the drawings for explaining the manufacturing method of the chip CHP of the third embodiment, FIGS. 27, 29, 31, 33, and 35 are plan views of main parts during the manufacturing process, and FIGS. 32, FIG. 34, FIG. 36, and FIG. 37 are cross sections taken along lines AA, BB, and CC in FIGS. 27, 29, 31, 33, and 35, respectively. It is a principal part sectional view shown.

  The manufacturing process of the chip CHP of the third embodiment is the same up to the process 9 (see FIG. 8) for forming the gate insulating film 6 in the manufacturing process of the LDMOSFET of the first embodiment. Thereafter, as shown in FIGS. 27 and 28, for example, a non-doped polycrystalline silicon film having a thickness of about 250 nm is deposited on the gate insulating film 6 by the CVD method, and n-type impurities are introduced into the polycrystalline silicon film. Then, a cap insulating film 8 made of a silicon oxide film having a thickness of about 125 nm is deposited on the polycrystalline silicon film by CVD, and then the cap insulating film 8 and the polycrystalline silicon film are dry-etched using the photoresist film as a mask. To do. Thereby, the gate electrode 7 is formed on the active region L, and the resistor 43 is formed on the element isolation region DS.

Subsequently, the n ⁻ type offset drain region 9, the n ⁻ type source region 10, the p type halo region 11, the sidewall spacer 12, the n type offset drain region 13, and the n ⁺ type are performed in the same process as in the first embodiment. A drain region 15, an n ⁺ type source region and a p ⁺ type semiconductor region 17 are formed. The side wall spacer 12 is also formed on the side wall of the resistor 43.

Next, as shown in FIGS. 29 and 30, silicide is formed on the surfaces of the n ⁺ -type source region 16 and the p ⁺ -type semiconductor region 17 by a process similar to the process described with reference to FIG. Layer 24D is formed.

Subsequently, after depositing a silicon nitride film 20 and a silicon oxide film 21 on the substrate 1, the surface of the silicon oxide film 21 is planarized using a chemical mechanical polishing method. Next, by dry etching the silicon oxide film 21 and the silicon nitride film 20 using the photoresist film as a mask, the p-type punching layer 4 (p ⁺ -type semiconductor region 17), the source (n ⁺ -type source region 17), Contact holes 22 are formed above the drain (n ⁺ -type drain region 15), the gate electrode 7 and the resistor 43, respectively.

  Subsequently, a Ti film having a thickness of about 10 nm and a TiN film having a thickness of about 50 nm are sequentially deposited on the substrate 1 including the inside of the contact hole 22 by a sputtering method. Next, a W (tungsten) film is deposited on the substrate 1 by the CVD method, and the contact hole 22 is filled with the W film. Next, the W film, the TiN film, and the Ti film on the substrate 1 are removed by CMP to leave the W film, the TiN film, and the Ti film in the contact hole 22, whereby the W film, the TiN film are formed in the contact hole 22. Then, a plug 23 made of a Ti film is formed.

Subsequently, a WN (tungsten nitride) film having a thickness of about 5 nm and a W film having a thickness of about 100 nm are sequentially deposited on the substrate 1 by sputtering. Subsequently, the stacked film is etched using the photoresist film as a mask, so that the wiring 24A electrically connected to the n ⁺ type source region 16 and the p ⁺ type semiconductor region 17 and the n ⁺ type drain region 15 are electrically connected. A wiring 24B to be connected, a wiring 24C to be electrically connected to the gate electrode 7, a wiring 24F to be electrically connected to the resistor 43, and a lower electrode 24G to be a capacity electrode of the capacitor 42 are formed.

  Next, as shown in FIGS. 31 and 32, a silicon oxide film 26 having a thickness of about 1100 nm is deposited by CVD on the wirings 24A, 24B, 24C, 24F and the lower electrode 24G, and then the silicon oxide film 26 is deposited. A through hole 27 reaching the wirings 24B, 24C, 24F and the lower electrode 24G is formed by etching a part of the through hole 27. Subsequently, the plug 28 is formed in the through hole 27 by the same process as the process of forming the plug 23.

  Next, as shown in FIGS. 33 and 34, an opening 26A reaching the lower electrode 24G is formed in the silicon oxide film 26 on the lower electrode 24G by etching using a photoresist film as a mask. Subsequently, after a silicon nitride film is deposited on the silicon oxide film 26 including the inside of the opening 26A, the silicon nitride film is etched by etching using a photoresist film as a mask, and the silicon nitride film is formed in the opening 26A. The capacitor insulating film 26B of the capacitor 42 made of the silicon nitride film is formed in the opening 26A.

Next, as shown in FIGS. 35 and 36, a Ti film having a thickness of about 10 nm, a TiN film having a thickness of about 50 nm, and a film having a thickness of about 10 nm are formed on the silicon oxide film 26 including the plug 28 and the capacitor insulating film 26B. A Ti film, an Al film with a thickness of about 800 nm, a Ti film with a thickness of about 10 nm, and a TiN film with a thickness of about 75 nm are sequentially stacked to form a stacked film. Next, this laminated film is patterned by etching using the photoresist film as a mask. Thereby, the drain (n ⁻ type offset drain region 9, n type offset drain region 13 and n ⁺ type drain region 15) of the LDMOSFET and the wiring 29 B electrically connected to the wiring 24 B, and the gate electrode 7 and wiring 24 C are electrically connected. The wiring 29C electrically connected, the wiring 29D electrically connected to the resistor 43, the wiring 29E electrically connected to the lower electrode 24G, and the upper electrode of the capacitor 42 are formed. Through the steps so far, the capacitor 42 including the lower electrode 24G, the capacitor insulating film 26B, and the upper electrode 29F is completed.

  Thereafter, through the steps described with reference to FIGS. 15 to 18 in the first embodiment, the chip CHP of the third embodiment having a cross section as shown in FIG. 37 is formed, and the semiconductor of the third embodiment is formed. Manufacture equipment.

  According to the third embodiment described above, not only the LDMOSFET 41 but also the capacitor 42 and the resistor 43 are formed on the chip CHP. As a result, the power amplifier circuits AMP1 and AMP2 (see FIG. 1) can be formed from the LDMOSFET 41, the capacitor 42, and the resistor 43 in the chip CHP. As a result, the number of passive components PP1 (see FIGS. 3 and 4) mounted on the wiring board MB1 (see FIGS. 3 and 4) on which the chip CHP is mounted can be reduced. That is, the RF power module PM (see FIGS. 3 and 4) itself can be reduced in size.

  According to the third embodiment, the same effects as those of the first and second embodiments can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the second embodiment, the case where the silicide layer is formed using the Co film has been described. However, the silicide layer may be formed using a metal film other than the Co film, for example, a Ti film.

In the second embodiment, the case where a silicide layer is provided and the source region of the LDMOSFET and the p ⁺ type semiconductor region (p-type punched layer) are electrically connected via the silicide layer has been described. Instead of providing a silicide layer, a metal film (for example, a tungsten film) is formed on the source region and the p ⁺ type semiconductor region (on the p type punched layer), and the LDMOSFET source region and the p ⁺ type semiconductor region ( The p-type punching layer may be electrically connected.

  The semiconductor device of the present invention can be applied to a chip that includes, for example, an LDMOSFET and is mounted on an RF power module.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Epitaxial layer 3 Groove 4 P-type punching layer (first conductive layer)
5 p-type well 6 gate insulating film 7 gate electrode 8 cap insulating film 9 n ^- type offset drain region (drain low concentration region)
10 n ⁻ type source region 11 p type halo region 12 sidewall spacer 13 n type offset drain region (drain high concentration region)
15 n ⁺ type drain region (drain high concentration region)
16 n ⁺ type source region 17 p ⁺ type semiconductor region 20 Silicon nitride film 21 Silicon oxide film 22 Contact hole 23 Plug (first wiring)
24A wiring (first wiring, first main surface source electrode)
24B wiring (first drain electrode)
24C Wiring 24D Silicide layer (compound layer)
24E Cobalt film 24F Wiring 24G Lower electrode 26 Silicon oxide film 26A Opening 26B Capacitance insulating film 27 Through hole 28 Plug 29B Wiring (second drain electrode)
29C wiring 29D, 29E wiring 29F upper electrode 30 silicon oxide film 31 through hole 32 plug 33 wiring (second drain electrode)
33A Drain pad (drain electrode)
34 Silicon oxide film 35 Silicon nitride film 36 Source back electrode 41 Active element 42 Capacitance 43 Resistance 101 Substrate 102 Metal electrode 103 Source region 104 Punching layer 104A Peripheral punching layer 105 Drain region 106, 107, 108 Wiring (drain wiring)
109 Drain pad (drain electrode)
110 Gate electrode 111 Gate pad 112, 113, 114 Wiring (source wiring)
113A wiring AJC1, AJC2 matching circuit AMP1, AMP2 power amplification circuit AMP11-AMP13, AMP21-AMP23 amplification stage BAC1, BAC2 bias circuit BIT1, BIT2 bias control signal input terminal BP1, bonding pad BW1, bonding wire C1, C2 parasitic capacitance C22 capacitance element CHP Chip CND1 Conductor layer DEC1, DEC2 Detection circuit DS Element isolation region ELB Back surface electrode GNDT Reference potential supply terminal HL1 Depression IL1 Insulating layer IPT1, IPT2 Input terminal L Active region MB1 Wiring substrate MBB Lower surface MBT Substrate side terminal MBU Upper surface MR1 Sealing resin OCT External connection terminals OPT1 to OPT4 Output terminals PM RF power module PP1 Passive components PSC1, PSC2 Power supply circuit R23 Resistive element RESI Photo register Preparative layer SD1 Schottky barrier diode SLD, SLD2 solder VH1, VHC hole

Claims (6)

A first conductivity type semiconductor substrate;
A first semiconductor region and a second semiconductor region formed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;
The first conductivity type well formed in the semiconductor substrate at a position deeper than the first semiconductor region;
A gate electrode formed on the well on a region sandwiched between the first semiconductor region and the second semiconductor region;
A back electrode formed on the back surface of the semiconductor substrate;
A groove formed in the semiconductor substrate;
A punching layer formed in the groove, electrically connected to the back electrode, and in contact with the well;
A first insulating film formed on the semiconductor substrate;
A first plug formed in the first insulating film and connected to the second semiconductor region;
A first wiring formed on the first insulating film and connected to the first plug;
Have
A third semiconductor region of the first conductivity type is formed on a surface of the punched layer and the semiconductor substrate between the punched layer and the first semiconductor region;
A semiconductor device, wherein a silicide film is formed on the first semiconductor region and the third semiconductor region. The semiconductor device according to claim 1,
A semiconductor device, wherein a wiring is not formed on the first semiconductor region in plan view. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the punched layer is made of a polycrystalline silicon film. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the punched layer is made of a metal film. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device, wherein the silicide film is made of a compound obtained by reacting cobalt and silicon. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

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