WO2013051599A1 - Dispositif à semi-conducteur et son procédé de production - Google Patents

Dispositif à semi-conducteur et son procédé de production Download PDF

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Publication number
WO2013051599A1
WO2013051599A1 PCT/JP2012/075632 JP2012075632W WO2013051599A1 WO 2013051599 A1 WO2013051599 A1 WO 2013051599A1 JP 2012075632 W JP2012075632 W JP 2012075632W WO 2013051599 A1 WO2013051599 A1 WO 2013051599A1
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Prior art keywords
region
drain
pad
wires
pad electrode
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PCT/JP2012/075632
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English (en)
Japanese (ja)
Inventor
智明 下石
亮太 佐藤
靜城 中島
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株式会社村田製作所
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Publication of WO2013051599A1 publication Critical patent/WO2013051599A1/fr

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    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which a wire is connected to a pad of a semiconductor chip having an amplifying element and a technique effective when applied to the manufacturing thereof.
  • GSM registered trademark
  • PCS PCS method
  • PDC method PDC method
  • CDMA Code Division Multiple Access
  • this type of mobile communication device includes an antenna that emits and receives radio waves, a high-frequency power amplifier (RF power module) that amplifies a power-modulated high-frequency signal and supplies the signal to the antenna, and a high-frequency signal received by the antenna.
  • RF power module high-frequency power amplifier
  • a receiving unit that performs signal processing, a control unit that performs these controls, and a battery (battery) that supplies a power supply voltage thereto are configured.
  • Patent Document 1 describes a technique in which a bond pad has a probe region and a wire bond region that do not substantially overlap each other.
  • Patent Document 2 describes a technique in which a contact pad has a probe inspection region and a bonding region.
  • a semiconductor device such as a power amplification module is manufactured by mounting a semiconductor chip on a wiring board and electrically connecting pad electrodes of the semiconductor chip and terminals of the wiring board with wires.
  • a surface protective film and a pad electrode
  • a probe inspection is performed in the wafer state.
  • a probe probe
  • the semiconductor wafer is cut into individual pieces (chips) by dicing, and the obtained semiconductor chip is mounted on the wiring board, and wire bonding is performed between the pad electrode of the semiconductor chip and the terminal of the wiring board.
  • a probe mark which is a mark pressed by the probe, is formed on the pad electrode to which the probe for inspection is pressed.
  • wire bonding is performed after the semiconductor chip is mounted on the wiring board, if the wire is connected to the probe trace of the pad electrode, the wire is connected to an area where the flatness is lowered. Connection strength may be reduced. The reduction in the connection strength of the wires reduces the reliability of the manufactured semiconductor device.
  • the pad electrode it is also conceivable to divide the wire connection region and the region where the probe is pressed in the probe inspection process (probe mark).
  • the area of the semiconductor chip is increased by increasing the size of the pad electrode simply by separating the wire connection area and the area where the probe is pressed in the probe inspection process (probe marks). There is a risk of inviting.
  • An increase in the area of the semiconductor chip leads to an increase in manufacturing cost and is disadvantageous for downsizing of the semiconductor device.
  • An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.
  • an object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.
  • a semiconductor device is a semiconductor device including a semiconductor chip having a plurality of pad electrodes, and a plurality of wires connected to the plurality of pad electrodes.
  • This semiconductor chip has a first pad electrode connected to the output of the semiconductor element constituting the power amplifier circuit, and a plurality of first wires are connected to the first pad electrode.
  • Probe marks are formed between the connection regions of the plurality of first wires.
  • a plurality of pad electrodes of the semiconductor chip and a plurality of terminals of the wiring board are connected via a plurality of wires. Connect electrically.
  • This semiconductor chip has a first pad electrode connected to the output of the semiconductor element constituting the power amplifier circuit, and a plurality of first wires are connected to the first pad electrode in the wire bonding step. In the first pad electrode, a position where the probe is applied in the probe inspection process is located between positions where the plurality of first wires are connected in the Y bonding process.
  • the reliability of the semiconductor device can be improved.
  • the semiconductor device can be miniaturized.
  • FIG. 2 is a circuit block diagram schematically showing a configuration example of a power amplification module used in the digital mobile phone shown in FIG. 1. It is a top view which shows the power amplification module of one embodiment of this invention. It is a bottom view which shows the power amplification module of one embodiment of this invention. It is a plane perspective view which shows the power amplification module of one embodiment of this invention. It is sectional drawing which shows the power amplification module of one embodiment of this invention. It is a side view which shows the state which mounted the power amplification module of one embodiment of this invention on the mounting board
  • FIG. 10 is a cross-sectional view of the power amplification module during a manufacturing step following that of FIG. 9; It is sectional drawing in the manufacturing process of the power amplification module following FIG.
  • FIG. 12 is a cross-sectional view of the power amplification module during a manufacturing step following that of FIG. 11;
  • FIG. 13 is a cross-sectional view of the power amplification module during a manufacturing step following that of FIG. 12;
  • FIG. 6 is a partially enlarged plan view of FIG. 5.
  • FIG. 4 is an explanatory diagram showing probe marks formed on a drain pad of a semiconductor chip according to an embodiment of the present invention, and a wire connection region in the drain pad 3.
  • FIG. 4 is an explanatory diagram showing probe marks formed on a drain pad of a semiconductor chip according to an embodiment of the present invention, and a wire connection region in the drain pad 3.
  • FIG. It is sectional drawing which shows a mode that the probe for a test
  • hatching may be omitted even in a cross-sectional view in order to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.
  • a power amplification module such as a radio frequency (RF) power module
  • RF radio frequency
  • a digital mobile phone mobile communication device
  • a network such as the GSM system ( A semiconductor device) and a semiconductor chip (semiconductor device) used (mounted).
  • GSM Global System for Mobile Communication
  • GSM Global System for Mobile Communication
  • GSM900 Global System for Mobile Communication
  • GSM1800 the 1800 MHz band (1710 to 1910 MHz)
  • DCS Digital Cellular System
  • GSM1900 the 1900 MHz band
  • GSM1900 is mainly used in North America.
  • GSM850 in the 850 MHz band may also be used.
  • the power amplification module PA1 of the present embodiment is a power amplification module used in these frequency bands (high frequency bands), for example.
  • FIG. 1 is a block diagram (an explanatory diagram) showing an example of a standard digital cellular phone (digital cellular phone system, mobile communication device) DPS.
  • a signal received from an antenna ANT is amplified by a low noise amplifier LNA through an antenna switch ANT-SW, and an IF frequency of about 150 to 250 MHz by a reception mixer RX-MIX ( (Intermediate frequency), and further frequency converted by the IF circuit IFC, guided to the baseband unit BBP as a second IF frequency of about 455 kHz, and demodulated by the demodulation circuit DMDL.
  • code COD1 is an audio CODEC (codec)
  • code SP is a speaker
  • code MIC is a microphone
  • code COD2 is a channel CODEC (codec)
  • code MDL is a modulation circuit.
  • the digitalized signal is DA-converted (digital-analog conversion) by the D / A conversion circuit DAC of the baseband unit BBP, and is guided to the RF block unit RFBP as an I / Q signal, and is a quadrature modulator.
  • the digitalized signal After being modulated to an IF frequency by QMD and converted to a transmission signal by transmission mixer TX-MIX, it is amplified by power amplification module PA1 and transmitted from antenna ANT through antenna switch ANT-SW.
  • a local signal is supplied to the reception mixer RX-MIX and the transmission mixer TX-MIX from a synthesizer composed of an oscillator and a PLL (phase synchronization circuit).
  • a synthesizer composed of an oscillator and a PLL (phase synchronization circuit).
  • AGCAMP is an AGC (Automatic Gain Control) amplifier
  • symbol FPL1 is an RF-PLL (RF frequency phase synchronization circuit)
  • symbol FPL2 is an IF-PLL (IF frequency phase synchronization circuit).
  • the digital cellular phone DPS also includes a display / control unit CDP configured by a liquid crystal display LCD, a microcomputer MCN, a memory MRY, and the like.
  • FIG. 2 shows a power amplification module (semiconductor device, electronic device, power amplifier, high output amplifier, high frequency power amplifier, high frequency power amplification device) used in a mobile communication device such as the digital cellular phone DPS shown in FIG.
  • FIG. 2 is a circuit block diagram (explanatory diagram) schematically showing a configuration example of a power amplifier module, RF power module) PA1.
  • two frequency bands of GSM900 and DCS1800 can be used (dual band system), and GMSK (Gaussian filtered Minimum Shift Keying) modulation system and EDGE (Enhanced Data GSM Environment) modulation system in each frequency band.
  • the circuit block diagram (amplifier circuit) of the power amplification module which can use two communication systems is shown.
  • the GMSK modulation method is a method used for communication of audio signals, and is a method of shifting the phase of a carrier wave according to transmission data.
  • the EDGE modulation method is a method used for data communication and is a method in which an amplitude shift is further added to the phase shift of GMSK modulation.
  • the circuit configuration of the power amplifying module PA1 includes two power amplifying circuits (high frequency power amplifying circuits) LDML and LDMH, a peripheral circuit 103, matching circuits 105A, 105B, 107A, and 107B.
  • Low-pass filters (low-pass filter circuits) 108A and 108B and switch circuits 109A and 109B are provided.
  • the power amplifier circuit LDML is a power amplifier circuit for GSM900, and has a multi-stage configuration in which a plurality of amplifier stages (amplifier circuits), here, three amplifier stages (amplifier circuits) LDML1, LDML2, and LDML3 are connected in multistage.
  • the power amplifying circuit LDMH is a power amplifying circuit for DCS1800, and has a multi-stage configuration in which a plurality of amplifying stages (amplifying circuits), here, three amplifying stages (amplifying circuits) LDMH1, LDMH2, and LDMH3 are connected in multistage. Yes.
  • the matching circuit (input matching circuit) 105A is provided between the input terminal 104a for GSM900 and the power amplification circuit LDML (first amplification stage LDML1), and the matching circuit (input matching circuit) 105B is an input for DCS1800. It is provided between terminal 104b and power amplification circuit LDMH (first amplification stage LDMH1).
  • the matching circuit (output matching circuit) 107A is provided between the switch circuit 109A for GSM900 and the power amplifier circuit LDML (third amplifier stage LDML3), and the matching circuit (output matching circuit) 107B is a switch for DCS1800. It is provided between circuit 109B and power amplifier circuit LDMH (third amplifier stage LDMH3).
  • the low-pass filter 108A for GSM900 is provided between the matching circuit 107A and the switch circuit 109A for GSM900, and the output of the power amplifier circuit LDML is input via the matching circuit 107A.
  • the low pass filter 108B for DCS1800 is provided between the matching circuit 107B and the switch circuit 109B for DCS1800, and the output of the power amplifier circuit LDMH is input through the matching circuit 107B.
  • an interstage matching circuit 102AM1 is provided between the amplification stage LDML1 and the amplification stage LDML2 of the power amplification circuit LDML for GSM900, and an interstage matching circuit 102AM2 is provided between the amplification stage LDML2 and the amplification stage LDML3.
  • An interstage matching circuit 102BM1 is provided between the amplification stage LDMH1 and the amplification stage LDMH2 of the power amplification circuit LDMH for the DCS 1800, and an interstage matching circuit 102BM2 is provided between the amplification stage LDMH2 and the amplification stage LDMH3.
  • Each matching circuit is a circuit that performs impedance matching, and the low-pass filters 108A and 108B are circuits that attenuate harmonics (harmonic components generated by the power amplifier circuits LDML and LDMH).
  • the power amplification circuit LDML (amplification stages LDML1 to LDML3) for GSM900, the power amplification circuit LDMH for DCS1800 (amplification stages LDMH1 to LDMH3), and the peripheral circuit 103 are one semiconductor chip (semiconductor amplification element chip). , High frequency power amplifying element chip, semiconductor device) 2.
  • the amplification stages LDML1 to LDML3 constituting the power amplification circuit LDML and the amplification stages LDMH1 to LDMH3 constituting the power amplification circuit LDMH are formed in the semiconductor chip CP1, but the matching circuits 102AM1, 102AM2 for the stages are used.
  • 102BM1, 102BM2 may be formed inside the semiconductor chip CP1 or outside the semiconductor chip CP1.
  • the peripheral circuit 103 is a circuit for controlling and assisting the amplification operation of the power amplifier circuits LDML and LDMH, or controlling the switch circuits 109A and 109B, and the control circuits 103A and 103C, and the amplification stages LDML1 to LDML3 and LDMH1 to LDMH3. And a bias circuit 103B for applying a bias voltage to the.
  • the control circuit 103A is a circuit that generates a desired voltage to be applied to the power amplification circuits LDML and LDMH, and includes a power supply control circuit 103A1 and a bias voltage generation circuit 103A2.
  • the power supply control circuit 103A1 is a circuit that generates a first power supply voltage to be applied to the drain terminals of the output amplifying elements (in this case, LDMOSFETs) of the amplification stages LDML1 to LDML3 and LDMH1 to LDMH3.
  • the bias voltage generation circuit 103A2 is a circuit that generates a first control voltage for controlling the bias circuit 103B.
  • the bias voltage generation circuit 103A2 is generated by the power supply control circuit 103A1.
  • the first control voltage is generated based on the power supply voltage.
  • the baseband circuit is a circuit that generates the output level designation signal.
  • This output level designation signal is a signal that designates the output level of the power amplifier circuits LDML and LDMH, and is generated based on the distance between the mobile phone and the base station, that is, the output level corresponding to the strength of the radio wave. It is like that.
  • the control circuit 103C is a circuit that controls the switch circuits 109A and 109B.
  • the switch circuit 109A for transmission / reception switching of the GSM900 connects the terminal (output terminal) 106 to the output side of the low-pass filter 108A when transmitting the GSM900 and connects the terminal 106 when receiving the GSM900.
  • terminal 110a The switch circuit 109B for transmission / reception switching of the DCS 1800 connects the terminal 106 to the output side of the low-pass filter 108B during transmission of the DCS 1800, and connects the terminal 106 to the terminal 110b during reception of the DCS 1800 according to the switching signal from the control circuit 103C. Connect to.
  • the RF input signal input to the GSM900 input terminal 104a of the power amplifier module PA1 is input to the semiconductor chip CP1 via the matching circuit 105A, and the power amplifier circuit LDML in the semiconductor chip CP1, that is, the three amplification stages LDML1 to LDML3. And output as an RF signal (GSM900 RF signal) amplified from the semiconductor chip CP1.
  • the RF signal of GSM900 amplified and output from the semiconductor chip CP1 is input to the switch circuit 109A through the matching circuit 107A and the low-pass filter 108A.
  • the switch circuit 109A When the switch circuit 109A is switched so as to connect the terminal 106 to the output side of the low-pass filter 108A, the RF signal input to the switch circuit 109A via the low-pass filter 108A is output as an RF output signal of the GSM900 from the terminal 106. And transmitted from the antenna ANT.
  • the RF input signal input to the DCS 1800 input terminal 104b of the power amplifier module PA1 is input to the semiconductor chip CP1 through the matching circuit 105B, and the power amplifier circuit LDMH in the semiconductor chip CP1, that is, the three amplification stages LDMH1. Amplified by LDMH3 and output from the semiconductor chip CP1 as an RF signal (DCS1800 RF signal).
  • the RF signal of DCS 1800 amplified and output from the semiconductor chip CP1 is input to the switch circuit 109B through the matching circuit 107B and the low-pass filter 108B.
  • the switch circuit 109B switches so that the terminal 106 is connected to the output side of the low-pass filter 108B, the RF signal input to the switch circuit 109B via the low-pass filter 108B is output from the terminal 106 as the RF output signal of the DCS 1800. And transmitted from the antenna ANT.
  • an input signal (for example, a control signal) input to the input terminal 104c of the power amplification module PA1 is input to the peripheral circuit 103, and based on this, the peripheral circuit 103 controls the power amplification circuits LDML and LDMH.
  • the switch circuits 109A and 109B can be controlled.
  • the switch circuits 109A and 109B correspond to the antenna switch ANT-SW in FIG. 1, and the power amplification module PA1 shown in FIG. 2 is the same as the antenna switch ANT-SW in FIG. This corresponds to the case where it is built in PA1.
  • the antenna switch ANT-SW can be provided outside the power amplification module PA1, and in this case, the switch circuits 109A and 109B are provided outside the power amplification module PA1.
  • the low-pass filters (low-pass filter circuits) 108A and 108B can be provided outside the power amplification module PA1.
  • Each of the power amplifier circuits LDML and LDMH is composed of three n-channel LDMOSFETs (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor, lateral diffusion MOSFET) ) Are sequentially connected in cascade (multi-stage connection). That is, each amplification stage LDML1, LDML2, LDML3, LDMH1, LDMH2, and LDMH3 are formed by n-channel LDMOSFET elements.
  • n-channel LDMOSFETs that is, an n-channel LDMOSFET constituting the amplification stage LDML1, an n-channel LDMOSFET constituting the amplification stage LDML2, and an n-channel LDMOSFET constituting the amplification stage LDML3 are sequentially connected (multistage connection). ) To form a power amplifier circuit LDML.
  • the input terminal 104a for GSM900 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDML1 via the matching circuit 105A, and the n-channel LDMOSFET constituting the amplification stage LDML1 is electrically connected.
  • the drain is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDML2 through the matching circuit 102AM1.
  • the drain of the n-channel LDMOSFET constituting the amplification stage LDML2 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDML3 via the matching circuit 102AM2, and the n-channel constituting the amplification stage LDML3.
  • the drain of the type LDMOSFET is electrically connected to the low-pass filter 108A through the matching circuit 107A.
  • n-channel LDMOSFETs that is, an n-channel LDMOSFET constituting the amplification stage LDMH1, an n-channel LDMOSFET constituting the amplification stage LDMH2, and an n-channel LDMOSFET constituting the amplification stage LDMH3 are sequentially connected (multi-stage connection). ) To form a power amplifier circuit LDMH.
  • the input terminal 104b for DCS1800 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDMH1 via the matching circuit 105B, and the n-channel LDMOSFET constituting the amplification stage LDMH1 is connected.
  • the drain is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDMH2 through the matching circuit 102BM1.
  • the drain of the n-channel LDMOSFET constituting the amplification stage LDMH2 is electrically connected to the gate of the n-channel LDMOSFET constituting the amplification stage LDMH3 via the matching circuit 102BM2, and the n-channel constituting the amplification stage LDMH3.
  • the drain of the type LDMOSFET is electrically connected to the low-pass filter 108B through the matching circuit 107B.
  • each power amplifier circuit LDML, LDMH is subordinate to two or four or more n-channel LDMOSFETs. Connected circuit configuration.
  • FIG. 3 is a top view (plan view) of the power amplification module PA1 of the present embodiment
  • FIG. 4 is a bottom view of the power amplification module PA1
  • FIG. 5 is a plan perspective view of the power amplification module PA1.
  • FIG. 6 is a cross-sectional view (side cross-sectional view) of power amplification module PA1 of the present embodiment. 6 corresponds to a cross-sectional view
  • FIG. 5 corresponds to a plan view, both of which show a conceptual structure of the power amplification module PA1.
  • FIG. 6 is a cross-sectional view of the structure of FIG. Is not completely consistent with the cross-sectional view.
  • a power amplification module PA1 of the present embodiment shown in FIGS. 3 to 6 includes a wiring board (multilayer board, multilayer wiring board, module board) 11 and a semiconductor chip (semiconductor) mounted (mounted) on the wiring board 11.
  • a resin (sealing portion, sealing resin portion) 13 The semiconductor chip CP1 and the passive component 12 are electrically connected to the conductor layer (transmission line) of the wiring board 11.
  • the power amplification module PA1 can also be mounted on, for example, an external circuit board (not shown) or a motherboard.
  • the power amplification module PA1 can be regarded as a semiconductor device because it includes the semiconductor chip CP1, but can also be regarded as an electronic device.
  • the wiring board 11 is, for example, a multilayer wiring board (multilayer board) in which a plurality of insulator layers (dielectric layers) 14 and a plurality of conductor layers (wiring layers) are stacked and integrated.
  • the five insulating layers 14 are laminated to form the wiring board 11.
  • the number of the insulating layers 14 to be laminated is not limited to this and can be variously changed.
  • Each conductor layer (wiring layer) 15 constituting the wiring board 11 is electrically connected through a conductor (conductor film) in a via hole (through hole) 16 formed in the insulator layer 14 as necessary.
  • the wiring board 11 As a material for forming the insulator layer 14 of the wiring substrate 11, a ceramic material such as alumina (aluminum oxide, Al 2 O 3 ) can be used.
  • the wiring board 11 is a ceramic multilayer board.
  • the material of the insulator layer 14 of the wiring board 11 is not limited to a ceramic material and can be variously changed. For example, a glass epoxy resin may be used.
  • a conductor layer (wiring layer, wiring pattern, conductor pattern) 15 for wiring formation is formed on the upper surface (front surface) 11a and the lower surface (back surface) 11b of the wiring substrate 11 and between the insulator layers 14.
  • a conductor-side board (terminal, electrode) TE made of a conductor and a chip mounting conductor pattern 15 c are formed on the upper surface 11 a of the wiring board 11 by the uppermost conductor layer 15 of the wiring board 11, and the lowermost layer of the wiring board 11.
  • the conductor layer 15 forms an external connection terminal (terminal, electrode, module electrode) 15 a made of a conductor and a reference potential supply terminal 15 b on the lower surface 11 b of the wiring board 11.
  • the external connection terminal 15 a includes terminals corresponding to the input terminals 104 a, 104 b, and 104 c and terminals corresponding to the terminals (output terminals) 106.
  • a conductor layer (wiring layer, wiring pattern, conductor pattern) 15 is also formed in the wiring substrate 11, that is, between the insulator layers 14.
  • the wiring pattern for supplying the reference potential (for example, the reference potential supplying terminal 15 b on the lower surface 11 b of the wiring substrate 11) is the wiring of the insulator layer 14.
  • the wiring pattern for the transmission line can be formed as a band-shaped pattern, with a rectangular pattern covering most of the formation surface.
  • the semiconductor chip CP1 is formed by forming a semiconductor integrated circuit on a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like, and then grinding the back surface of the semiconductor substrate as necessary, and then dicing or the like to each semiconductor chip CP1. It is separated.
  • a plurality of pad electrodes (electrodes, bonding pads) PD are formed on the surface (upper surface) of the semiconductor chip CP1, and each pad electrode PD is electrically connected to a semiconductor element or a semiconductor integrated circuit formed in the semiconductor chip CP1. Connected.
  • the configuration of the semiconductor chip CP1 will be described in detail later.
  • the principal surface on the side where the pad electrode PD is formed is referred to as the surface of the semiconductor chip CP1
  • the principal surface on the side where the pad electrode PD is formed is referred to as the surface of the semiconductor chip CP1
  • the principal surface on the side where the pad electrode PD is formed is referred to as the back surface of the semiconductor chip CP1.
  • the semiconductor chip CP1 is die-bonded (bonded) to the chip mounting conductor pattern 15c on the upper surface 11a of the wiring substrate 11 with a bonding material (adhesive material) such as solder 18 face up.
  • a bonding material such as solder 18 face up.
  • a conductive paste adhesive such as silver paste can be used.
  • the pad electrode PD formed on the surface (upper surface) of the semiconductor chip CP1 is electrically connected to the substrate-side terminal TE on the upper surface 11a of the wiring substrate 11 through a conductive wire (bonding wire) WA.
  • a back electrode BE1 is formed on the entire back surface of the semiconductor chip CP1, and the back electrode BE1 of the semiconductor chip CP1 is electrically conductive such as solder 18 on the chip mounting conductor pattern 15c on the top surface 11a of the wiring substrate 11. Bonded by a bonding material and electrically connected, and further electrically connected to a reference potential supply terminal 15b on the lower surface 11b of the wiring substrate 11 via a conductor in the via hole 16 (16a).
  • the via hole 16a provided below the semiconductor chip CP1 can also function as a thermal via for conducting heat generated in the semiconductor chip CP1 to the lower surface 11b side of the wiring substrate 11.
  • the passive component 12 is composed of a passive element such as a resistive element (for example, a chip resistor), a capacitive element (for example, a chip capacitor), or an inductor element (for example, a chip inductor), for example, a chip component.
  • the passive component 12 is a passive component that constitutes the matching circuits 105A, 105B, 107A, 107B, 102AM1, 102AM2, 102BM1, and 102BM2, for example.
  • the electrodes of the passive component 12 are joined and electrically connected to the board-side terminal TE on the upper surface 11a of the wiring board 11 by a conductive joining material such as solder 18.
  • the board-side terminal TE on the upper surface 11a of the wiring board 11 to which the semiconductor chip CP1 or the passive component 12 is electrically connected is connected to the upper surface 11a of the wiring board 11 or an internal conductor layer (wiring layer) 15 or via hole 16 as necessary.
  • the wiring is connected via an internal conductor or the like, and is electrically connected to the external connection terminal 15a or the reference potential supply terminal 15b on the lower surface 11b of the wiring board 11 as necessary.
  • solder resist layer (not shown) is formed on the upper surface 11a and the lower surface of the wiring substrate 11.
  • the terminal TE is exposed from the opening of the solder resist layer.
  • the external connection terminal 15 a and the reference potential supply terminal 15 b are exposed from the solder resist layer.
  • the sealing resin 13 is formed on the upper surface 11a of the wiring board 11 so as to cover the semiconductor chip CP1, the passive component 12, and the wire WA.
  • the sealing resin 13 is made of, for example, a resin material such as an epoxy resin or a silicone resin, and can contain a filler or the like.
  • FIG. 7 is a side view schematically showing a state in which the power amplification module PA1 of the present embodiment is mounted on a mounting board (wiring board, motherboard, external circuit board) 21.
  • FIG. 7 is a side view schematically showing a state in which the power amplification module PA1 of the present embodiment is mounted on a mounting board (wiring board, motherboard, external circuit board) 21.
  • FIG. 7 is a side view schematically showing a state in which the power amplification module PA1 of the present embodiment is mounted on a mounting board (wiring board, motherboard, external circuit board) 21.
  • the power amplification module PA1 and other components 22 are mounted on the upper surface 21a of the mounting substrate 21.
  • the external connection terminal 15a of the power amplification module PA1 is joined and electrically connected to the terminal 23a of the mounting substrate 21 via a conductive joining material such as solder 24, and the reference of the power amplification module PA1.
  • the potential supply terminal 15b is joined to and electrically connected to a terminal (reference potential supply terminal) 23b of the mounting substrate 21 via a conductive joining material such as solder 24.
  • the electrodes of the component 22 are joined and electrically connected to the terminals 23 c of the mounting substrate 21 via a conductive joining material such as solder 24. Therefore, a reference potential (ground potential, ground potential) is supplied from the terminal (reference potential supply terminal) 23b of the mounting substrate 21 to the power amplification module PA1 via the solder 24 and the reference potential supply terminal 15b. it can.
  • FIG. 8 is a process flow diagram showing the manufacturing process of the power amplification module PA1.
  • 9 to 13 are cross-sectional views of the power amplification module PA1 according to the present embodiment during the manufacturing process.
  • the power amplification module PA1 of the present embodiment can be manufactured, for example, as follows.
  • a wiring board base (wiring board) 25 is prepared as a wiring board (step S1 in FIG. 8).
  • the wiring board base body 25 becomes the wiring board 11 after a cutting process described later, and can be manufactured using, for example, a printing method, a sheet lamination method, a build-up method, or the like. Further, the upper surface 25a of the wiring board base body 25 becomes the upper surface 11a of the wiring board 11 after a cutting process described later.
  • the semiconductor chip CP1 is prepared (Step S2 in FIG. 8).
  • the step of preparing the semiconductor chip CP1 in step S2 may be performed before, after, or simultaneously with the step of preparing the wiring board base 25 in step S1.
  • the preparation process of the semiconductor chip CP1 in step S2 includes steps S11, S12, and S13 described later.
  • the chip mounting conductor pattern 15c on which the semiconductor chip CP1 is to be mounted and the board-side terminal TE on which the passive component 12 is to be mounted are connected to solder or the like.
  • the bonding material is printed or applied as necessary.
  • the semiconductor chip CP1 and the passive component 12 are mounted (arranged) on the upper surface 25a of the wiring board mother body 25 (step S3 in FIG. 8).
  • the wiring board is arranged such that the back side (back side electrode BE1 side) faces downward (wiring board base 25 side) and the front side (pad electrode PD side) faces upward (face-up bonding).
  • the semiconductor chip CP1 and the passive component 12 are fixed (bonded, connected, fixed) to the wiring board base 25 via a bonding material such as solder 18 (step S4 in FIG. 8).
  • the solder melted and solidified by the solder reflow becomes the solder 18.
  • the mounting process of the passive component 12 on the wiring board base 25 and the mounting process of the semiconductor chip CP1 on the wiring board 25 can be performed separately.
  • the wiring board base 25 After the passive component 12 is mounted and fixed with a bonding material such as solder, the semiconductor chip CP1 can be mounted on the wiring board base 25 and fixed with a bonding material (such as solder or a conductive paste adhesive). .
  • a wire bonding step is performed to connect a plurality of pad electrodes PD on the surface of the semiconductor chip CP1 and a plurality of substrate-side terminals TE on the upper surface 25a of the wiring board base 25 to a plurality of wires ( Bonding wires) are electrically connected via WA (step S5 in FIG. 8).
  • the sealing resin (sealing part, sealing resin part) 13 is formed on the upper surface 25a of the wiring board base 25 so as to cover the semiconductor chip CP1, the passive component 12, and the wire WA.
  • the sealing resin 13 can be formed using, for example, a printing method or a mold for molding (for example, transfer mold) (step S6 in FIG. 8).
  • the power amplification module PA1 can be manufactured by cutting the wiring board base 25 and the sealing resin 13 by dicing or the like (step S7 in FIG. 8).
  • the wiring board matrix 25 after cutting becomes the wiring board 11.
  • FIG. 14 is a partially enlarged plan view of FIG. 5 and shows an enlarged view of the semiconductor chip CP1 mounted on the wiring board 11 and its peripheral region.
  • FIG. 15 is a plan view in which the wire WA and the substrate-side terminal TE are omitted from FIG. 14, and corresponds to a plan view (planar layout diagram) of the semiconductor chip CP1.
  • a region in which the LDMOSFET element constituting the first amplification stage LDML1 for GSM900 is formed is denoted as a LDMOSFET formation region REGL1 with a reference sign REGL1, and the region for GSM900 is used.
  • a region in which the LDMOSFET elements constituting the second amplification stage LDML2 are formed is denoted by a reference sign REGL2 and is indicated as an LDMOSFET formation region REGL2.
  • a region in which the LDMOSFET elements constituting the third (final) amplification stage LDML3 for GSM900 are formed is denoted by the reference numeral REGL3 and indicated as an LDMOSFET formation region REGL3.
  • the region where the LDMOSFET element constituting the first amplification stage LDMH1 for DCS1800 is formed is denoted by the reference numeral REGH1, and is indicated as LDMOSFET formation region REGH1, and the second amplification stage LDMH2 for DCS1800 is constituted.
  • a region where the LDMOSFET element is formed is indicated as a LDMOSFET formation region REGH2 with a reference sign REGH2.
  • a region in which the LDMOSFET elements constituting the third (final) amplification stage LDMH3 for DCS1800 are formed is denoted by reference numeral REGH3 and is indicated as an LDMOSFET formation region REGH3.
  • the semiconductor chip CP1 also has a region in which elements constituting the peripheral circuit 103 such as a capacitor element, a resistance element, or a control MOSFET are formed. This region is illustrated in FIGS. Is omitted.
  • a plurality of pad electrodes PD are formed on the surface of the semiconductor chip CP1.
  • the pad electrodes PD are drain pads (drain pad electrodes) PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 which are drain pad electrodes PD and gate pads (gate pad electrodes) PDG1, which are gate pad electrodes PD.
  • PDG2, PDG3, PDG4, PDG5, PDG6 are included.
  • the pad electrode PD includes a pad electrode PD1 for use in inputting a control signal, outputting a detection signal, and the like.
  • the gate pad PDG1 is an input pad electrode (pad electrode for inputting an RF signal through the matching circuit 105A) electrically connected to the gate electrode of the LDMOSFET formation region REGL1.
  • the drain pad PDD1 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGL1) electrically connected to the drain of the LDMOSFET formation region REGL1.
  • the gate pad PDG2 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit 102AM1) electrically connected to the gate electrode of the LDMOSFET formation region REGL2.
  • the drain pad PDD2 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGL2) electrically connected to the drain of the LDMOSFET formation region REGL2.
  • the gate pad PDG3 is an input pad electrode (pad electrode for inputting an RF signal through the matching circuit 102AM2) electrically connected to the gate electrode of the LDMOSFET formation region REGL3.
  • the drain pad PDD3 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGL3) electrically connected to the drain of the LDMOSFET formation region REGL3.
  • the gate pad PDG4 is an input pad electrode (pad electrode for inputting an RF signal through the matching circuit 105B) electrically connected to the gate electrode of the LDMOSFET formation region REGH1.
  • the drain pad PDD4 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGH1) electrically connected to the drain of the LDMOSFET formation region REGH1.
  • the gate pad PDG5 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit 102BM1) electrically connected to the gate electrode of the LDMOSFET formation region REGH2.
  • the drain pad PDD5 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGH2) electrically connected to the drain of the LDMOSFET formation region REGH2.
  • the gate pad PDG6 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit 102BM2) electrically connected to the gate electrode of the LDMOSFET formation region REGH3.
  • the drain pad PDD6 is an output pad electrode (pad electrode for outputting an RF signal amplified in the LDMOSFET formation region REGH3) electrically connected to the drain of the LDMOSFET formation region REGH3.
  • the regions where the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, and REGH3 are formed and the regions where the elements for the control circuit are formed are buried oxides formed between the regions. Each element is electrically isolated from other regions by element isolation regions (corresponding to element isolation regions 32 described later) made of a film or the like. Further, the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, REGH3 and the region where the elements for the control circuit are formed, and between them and the pad electrode PD, the inside of the semiconductor chip CP1 as necessary. It is electrically connected by wiring.
  • the semiconductor chip CP1 has a rectangular planar shape having the four sides (chip sides) SD1, SD2, SD3, and SD4.
  • the side SD1 and the side SD3 are parallel to and face each other, and the side SD2 And the side SD4 are parallel to each other and face each other, the side SD1 and the side SD2 are orthogonal, the side SD1 and the side SD4 are orthogonal, the side SD3 and the side SD2 are orthogonal, and the side SD3 and the side SD4 are orthogonal is doing.
  • the plurality of pad electrodes PD are arranged on the periphery of the surface of the semiconductor chip CP1.
  • the drain pad PDD3, the gate pad PDG3, the drain pad PDD2, the gate pad PDG2, the drain pad PDD1, and the gate pad PDG1 are arranged along the side SD1 in this order.
  • the drain pad PDD6, the gate pad PDG6, the drain pad PDD5, the gate pad PDG5, the drain pad PDD4, and the gate pad PDG4 are arranged along the side SD3 in this order.
  • the LDMOSFET formation regions REGL3, REGL2, and REGL1 are disposed on the side SD1 side, and the LDMOSFET formation regions REGH3, REGH2, and REGH1 are disposed on the side SD3 side.
  • the drain pad PDD3 is located between the LDMOSFET formation region REGL3 and the side SD1
  • the drain pad PDD2 is located between the LDMOSFET formation region REGL2 and the side SD1
  • a drain pad PDD1 is located between the two.
  • the drain pad PDD6 is located between the LDMOSFET formation region REGH3 and the side SD3
  • the drain pad PDD5 is located between the LDMOSFET formation region REGH2 and the side SD3
  • a drain pad PDD4 is located between SD3 and SD3.
  • FIG. 16 is a cross-sectional view of a main part of the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, and REGH3 in the semiconductor chip CP1.
  • 17 shows a cross-sectional position different from that in FIG. 16, and corresponds to a cross-sectional view of a region where the gate electrode 35 is pulled up to the gate wirings M1G and M2G on the element isolation region 32.
  • FIG. 18 shows a cross-sectional position different from that in FIGS.
  • FIG. 16 and 17 shows cross-sectional positions different from those in FIGS. 16 to 18, and corresponds to a cross-sectional view of a region where the gate pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6 are formed.
  • FIG. 20 shows a cross-sectional position different from that in FIGS. 16 to 19 and corresponds to a cross-sectional view of a region where the drain pads PDD3 and PDD6 are formed.
  • a semiconductor substrate (hereinafter simply referred to as a substrate) 31 constituting the semiconductor chip CP1 includes a substrate body (semiconductor substrate, semiconductor wafer) 31a made of p + -type single crystal silicon, and the like. And an epitaxial layer (semiconductor layer) 31b made of, for example, p ⁇ type single crystal silicon, formed on the main surface of the substrate body 31a. For this reason, the substrate 31 is a so-called epitaxial wafer.
  • the epitaxial layer 31b is a semiconductor layer
  • the impurity concentration of the epitaxial layer 31b is lower than the impurity concentration of the substrate body 31a
  • the resistivity of the epitaxial layer 31b is higher than the resistivity of the substrate body 31a.
  • An element isolation region 32 made of an insulator is formed in the epitaxial layer 31b. 16 corresponds to a cross-sectional view crossing an active region (corresponding to an active region AR1 described later) surrounded by the element isolation region 32, the element isolation region 32 is not shown in FIG. 17 to 20 correspond to cross-sectional views across the element isolation region 32 surrounding the active region, so that the element isolation region 32 is shown in FIGS. 17 to 20.
  • the element isolation region 32 is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method.
  • the element isolation region 32 defines an active region AR1 described later on the main surface of the substrate body 31a (main surface of the epitaxial layer 31b), and a plurality of LDMOSFET cells (unit LDMOSFET elements) are formed in the active region AR1.
  • the active region AR1 is surrounded by the element isolation region 32.
  • a p-type well 33 that functions as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET is formed on a part of the main surface of the epitaxial layer 31b.
  • a gate electrode 35 of the LDMOSFET is formed via a gate insulating film 34 made of silicon oxide or the like.
  • the gate electrode 35 is made of, for example, a single film of an n-type polycrystalline silicon film or a laminated film of an n-type polycrystalline silicon film and a metal silicide film, and a side wall made of silicon oxide or the like is formed on the side wall of the gate electrode 35.
  • a wall spacer (side wall insulating film) 36 is formed.
  • the source and drain of the LDMOSFET are formed in regions separated from each other across the channel formation region (region immediately below the gate electrode 35) inside the epitaxial layer 31b. Drain first n in contact with the channel forming region - -type drain region 37, the first n - -type drain region 38 - -type drain region in contact with the second n which is spaced apart from the channel forming region And an n + type drain region (drain high concentration region, high concentration n type drain region) 39 formed in contact with the second n ⁇ type drain region and further away from the channel formation region.
  • the first n ⁇ -type drain region 37 closest to the gate electrode 35 has the highest impurity concentration.
  • the n + -type drain region 39 which is low and is most distant from the gate electrode 35 has the highest impurity concentration.
  • the junction depth of the second n ⁇ -type drain region 38 is substantially the same as the junction depth of the first n ⁇ -type drain region 37, but the n + -type drain region 39 has the second n ⁇ -type drain. It is formed shallower than the drain region 38 and the first n ⁇ -type drain region 37.
  • the first n ⁇ -type drain region (first low-concentration n-type drain region, first n-type LDD region) 37 is formed in a self-aligned manner with respect to the gate electrode 35, and its end is a channel formation region It terminates at the bottom of the side wall of the gate electrode 35 so as to come into contact.
  • the second n ⁇ -type drain region (second low-concentration n-type drain region, second n-type LDD region) 38 is formed with respect to the side wall spacer 36 formed on the side wall on the drain side of the gate electrode 35. Therefore, it is formed so as to be separated from the gate electrode 35 by an amount corresponding to the film thickness of the sidewall spacer 36 along the gate length direction.
  • the source of the LDMOSFET is n ⁇ -type source region 40 in contact with the channel formation region, and is in contact with the n ⁇ -type source region 40, spaced apart from the channel formation region, and has an impurity concentration higher than that of the n ⁇ -type source region 40. And a + type source region 41.
  • the n ⁇ -type source region 40 is formed in a self-aligned manner with respect to the gate electrode 35, and terminates at the lower portion of the side wall of the gate electrode 35 so that the end thereof is in contact with the channel formation region.
  • a p-type halo region (not shown) can be formed below the n ⁇ -type source region 40, and this p-type halo region is not necessarily formed, but when formed, The spread of impurities from the source to the channel formation region is further suppressed, and the short channel effect is further suppressed, so that the threshold voltage can be further prevented from decreasing.
  • the n + type source region 41 is formed in a self-aligned manner with respect to the side wall spacer 36 formed on the source side wall of the gate electrode 35, the n + type source region 41 is an n ⁇ type source region. 40, and is spaced apart from the channel formation region by an amount corresponding to the film thickness of the sidewall spacer 36 along the gate length direction.
  • the position of the bottom of the n + -type source region 41 is deeper than the position of the bottom of the n ⁇ -type source region 40.
  • the lightly doped n-type drain region (n-type LDD region) interposed between the gate electrode 35 and the n + -type drain region 39 has a double structure, and the first n ⁇ -type closest to the gate electrode 35 is formed.
  • the impurity concentration of the drain region 37 is relatively low, and the impurity concentration of the second n ⁇ -type drain region 38 spaced from the gate electrode 35 is relatively high.
  • a depletion layer spreads between the gate electrode 35 and the drain.
  • the feedback capacitance (Cgd) formed between the gate electrode 35 and the first n ⁇ -type drain region 37 in the vicinity thereof is reduced. Get smaller.
  • the impurity concentration of the second n ⁇ -type drain region 38 is high, the on-resistance (Ron) is also reduced. Since the second n ⁇ -type drain region 38 is formed at a position separated from the gate electrode 35, the influence on the feedback capacitance (Cgd) is small. For this reason, since both the on-resistance (Ron) and the feedback capacitance (Cgd) can be reduced, the power added efficiency of the amplifier circuit can be improved.
  • the MOSFET or LDMOSFET is not only a MISFET using an oxide film (silicon oxide film) as a gate insulating film, but also a MISFET using an insulating film other than an oxide film (silicon oxide film) as a gate insulating film. Shall also be included.
  • the LDMOSFET is a MISFET (Metal-Insulator-Semiconductor-Field-Effect-Transistor) element, and is a MISFET element having the following characteristics (first to third characteristics).
  • MISFET Metal-Insulator-Semiconductor-Field-Effect-Transistor
  • the LDMOSFET has an LDD (Lightly doped drain) region formed on the drain side of the gate electrode 35 in order to enable a high voltage operation with a short channel length. That is, the drain of the LDMOSFET has a high impurity concentration n + -type region (here, n + -type drain region 39) and a lower impurity concentration LDD region (here, the first n ⁇ -type drain region 37 and the first n - type drain region 37). 2 n ⁇ -type drain region 38), and the n + -type region (n + -type drain region 39) is separated from the gate electrode 35 (or the channel formation region below the gate electrode 35) via the LDD region. Is formed.
  • LDD Lightly doped drain
  • Charge amount (impurity concentration) in the LDD region on the drain side, and distance along the plane (main surface of the epitaxial layer 31b) between the end of the gate electrode 35 and the n + -type drain region (drain high concentration region) 39 must be optimized to maximize the breakdown voltage of the LDMOSFET.
  • the LDMOSFET has a p-type well (p-type base region) for punch-through stoppers in a source-side source formation region (n ⁇ -type source region 40 and n + -type source region 41) and a channel formation region. ) 33 is formed.
  • the p-type well 33 is not formed, or is formed only in contact with a part of the drain formation region closer to the channel region.
  • the LDMOSFET has a source (here, a source region composed of an n ⁇ type source region 40 and an n + type source region 41) and a drain (here, a first n ⁇ type drain region 37, a second n ⁇ type source region 41).
  • the drain region composed of the ⁇ type drain region 38 and the n + type drain region 39) has an asymmetric structure with respect to the gate electrode 35.
  • the p-type punching layer 44 is a conductive layer for electrically connecting the source of the LDMOSFET and the substrate body 31a, and is formed of, for example, a p-type polycrystalline silicon film embedded in a groove formed in the epitaxial layer 31b.
  • the tip (bottom) of the p-type punching layer 44 reaches the substrate body 31a.
  • the p-type punching layer 44 can also be formed by a metal layer embedded in a groove formed in the substrate 31.
  • An insulating film (interlayer insulating film) 46 is formed on the main surface of the epitaxial layer 31b so as to cover the gate electrode 35 and the sidewall spacers 36.
  • the insulating film 46 is made of, for example, a laminated film of a thin silicon nitride film and a thick silicon oxide film thereon. The upper surface of the insulating film 46 is planarized.
  • a contact hole (opening, through hole, through hole) 47 is formed in the insulating film 46, and a plug (a buried conductor for connection) 48 mainly composed of a tungsten (W) film is embedded in the contact hole 47. It is.
  • the contact hole 47 and the plug 48 filling the contact hole 47 are formed of a p-type punch layer 44 (p + -type semiconductor region 45), a source (n + -type source region 41), a drain (n + -type drain region 39), and a gate electrode 35. It is formed at the top of each.
  • a wiring (first layer wiring) M1 made of a conductor film (tungsten film) mainly composed of tungsten (W) or the like is formed on the insulating film 46 in which the plug 48 is embedded.
  • the wiring M1 is formed by patterning a conductor film (tungsten film) formed on the insulating film 46 in which the plug 48 is embedded.
  • the wiring M1 is not limited to the tungsten wiring, and may be a wiring using another metal material such as an aluminum wiring.
  • the wiring M1 includes a source wiring (source electrode) M1S electrically connected to both the n + -type source region 41 and the p + -type semiconductor region 45 through the plug 48, and an n + -type drain region 39 through the plug 48.
  • a through hole (opening, through hole) 50 exposing a part of the wiring M1 at the bottom is formed.
  • a wiring M2 made of a conductor film mainly composed of aluminum (Al) or an aluminum alloy is formed on the insulating film 49 including the inside of the through hole 50.
  • the wiring M2 includes a barrier conductor film (for example, a laminated film of a titanium film and a titanium nitride film), an aluminum film (or an aluminum alloy film), and a barrier conductor film (for example, a titanium film) on the insulating film 49 including the inside of the through hole 50. And a titanium nitride film) is formed by patterning the conductor film.
  • the upper and lower barrier conductor films are thinner than the aluminum film as the main conductor film.
  • the barrier conductor film below the aluminum film in the laminated film has a function of suppressing a reaction between the aluminum film and the lower wiring M1, a function of improving the adhesion between the wiring M2 and the insulating film 49, and the like. Yes.
  • the barrier conductor film on the upper side of the aluminum film in the laminated film has a function of improving the adhesion between the wiring M2 and the insulating film (surface protective film) 52 and a function as an antireflection film at the time of exposure in the photolithography process. Etc.
  • the wiring M2 extends on the insulating film 49, partially fills the through hole 50, and is electrically connected to the wiring M1 at the bottom of the through hole 50. Therefore, the wiring M2 is integrally formed with a wiring portion extending on the insulating film 49 and a via portion (connecting portion) filling the through hole 50.
  • the wiring M2 is electrically connected to the drain wiring M2D that is electrically connected to the drain wiring M1D via the via portion (the portion that fills the through hole 50) and to the gate wiring M1G via the via portion (the portion that fills the through hole 50). And a source wiring M2S electrically connected to the source wiring M1S through a via portion (a portion filling the through hole 50).
  • a plug similar to the plug 48 is embedded in the through hole 50, a conductor film for forming the wiring M2 is formed on the insulating film 49 in which the plug is embedded, and the conductor film is patterned.
  • the wiring M2 can be formed.
  • the wiring M2 is electrically connected to the wiring M1 through a plug filling the through hole 50.
  • An insulating film (surface protective film) 52 is formed on the insulating film 49 so as to cover the wiring M2.
  • the insulating film 52 is made of, for example, a laminated film of a silicon oxide film and a silicon nitride film thereon, and can function as a protective film on the outermost surface of the semiconductor chip CP1.
  • An opening (through hole, through hole) 53 for a pad electrode is formed in the insulating film 52, and the wiring M ⁇ b> 2 is exposed at the bottom of the opening 53. That is, an opening 53 is formed on the wiring M2, and a part of the wiring M2 is exposed from the opening 53.
  • the wiring M2 exposed from the opening 53 corresponds to the pad electrode PD. That is, the pad electrode PD is formed by the wiring M2 exposed from the opening 53.
  • the opening 53 formed on the drain wiring M2D and exposing a part of the drain wiring M2D is referred to as a drain pad opening 53D.
  • the opening 53 is formed on the gate wiring M2G and is a part of the gate wiring M2G.
  • the opening that exposes is referred to as a gate pad opening 53G.
  • the drain wiring M2D exposed from the drain pad opening 53D corresponds to the drain pads PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6, and the gate wiring M2G exposed from the gate pad opening 53G is the gate. It corresponds to pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6.
  • the drain pad PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6 are formed by the drain wiring M2D exposed from the drain pad opening 53D, and the gate wiring M2G exposed from the gate pad opening 53G forms the gate.
  • Pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6 are formed.
  • the wire WA is connected to the wiring M2 exposed from the opening 53 (that is, the pad electrode PD) after the semiconductor chip CP1 is mounted on the wiring substrate 11 (wiring substrate base 25).
  • the wiring M2 has a pattern with a larger area than the opening 53. .
  • the wiring M2 is formed by patterning a conductor film made of a laminated film of a barrier conductor film, an aluminum film, and a barrier conductor film, an opening 53 is formed in the insulating film 52.
  • the uppermost barrier conductor film can also be removed by dry etching.
  • a portion of the wiring M2 exposed from the opening 53 (that is, a portion that becomes the pad electrode PD) is formed of a laminated film of a barrier conductor film and an aluminum film thereon, and the wiring M2 ( The surface of the aluminum film (or aluminum alloy film) constituting the pad electrode PD) is exposed, while the portion of the wiring M2 covered with the insulating film 52 includes a barrier conductor film, an aluminum film thereon, and It consists of a laminated film with the upper barrier conductor film.
  • a source back electrode (back electrode) 54 is formed on the back surface of the substrate 31 (the main surface opposite to the main surface on which the epitaxial layer 31b is formed).
  • the source back electrode (back electrode) 54 is formed on the entire back surface of the substrate 31 constituting the semiconductor chip CP1 (that is, the entire back surface of the substrate body 31a), and corresponds to the back electrode BE1.
  • the source (n ⁇ type source region 40 and n + type source region 41) of the LDMOSFET formed in the epitaxial layer 31b is a plug 48 (plug 48 disposed on the n + type source region 41), source wiring M1S, plug 48 (plug 48 disposed on p + type semiconductor region 45), p + type semiconductor region 45, p type punching layer 44, and substrate 31 are electrically connected to source back electrode 54 (ie, back electrode BE1). It is connected.
  • a metal silicide layer (for example, a cobalt silicide layer or a nickel silicide layer, not shown) is further formed on the surface (upper part) of the n + type source region 41 and the p + type semiconductor region 45, and this metal silicide is formed.
  • the n + -type source region 41 and the p + -type semiconductor region 45 can also be electrically connected through the layer, which can further reduce the source resistance.
  • the drain (first n ⁇ type drain region 37, second n ⁇ type drain region 38 and n + type drain region 39) of the LDMOSFET formed in the epitaxial layer 31b is connected to the plug 48 (on the n + type drain region 39).
  • a drain pad any one of drain pads PDD1, PDD2, PDD3, PDD4, PDD5, and PDD6 via a drain wiring M1D and a drain wiring M2D.
  • the gate electrode 35 of the LDMOSFET formed on the epitaxial layer 31b is connected to the gate pad (gate pads PDG1, PDG2, PDG3) via the plug 48 (plug 48 disposed on the gate electrode 35), the gate wiring M1G, and the gate wiring M2G. , PDG4, PDG5, PDG6).
  • FIG. 21 is a process flowchart showing the manufacturing process of the semiconductor chip CP1.
  • the epitaxial layer (semiconductor layer) 31b is formed on the main surface of the substrate body (semiconductor substrate, semiconductor wafer) 31a by using the epitaxial growth method, whereby the substrate body 31a and the substrate body are formed.
  • a substrate (semiconductor substrate) 31 composed of the epitaxial layer 31b on 31a is formed.
  • the substrate 31 at this stage is in a state of a substantially disk-shaped semiconductor wafer because a dicing process described later is not performed.
  • a part of the epitaxial layer 31b is etched using a photolithography technique and a dry etching technique to form a groove reaching the substrate body 31a, and then a CVD method or the like is formed on the epitaxial layer 31b including the inside of the groove.
  • the p-type polycrystalline silicon film is deposited using the p-type, the p-type polycrystalline silicon film outside the trench is removed by an etch back method or the like, thereby forming a p-type polycrystalline silicon film embedded in the trench.
  • a stamping layer 44 is formed.
  • the element isolation region 32 is formed in the epitaxial layer 31b by STI (Shallow Trench Isolation) method or LOCOS (Local Oxidization of Silicon) method.
  • a p-type well 33 is formed by ion-implanting p-type impurities into a part of the epitaxial layer 31b. Then, a gate insulating film 34 is formed on the surface of the epitaxial layer 31b, and a gate electrode 35 is formed on the gate insulating film 34.
  • a first n ⁇ -type drain region 37 is formed by ion-implanting an n-type impurity into a part of the epitaxial layer 31b. Then, an n ⁇ type source region 40 is formed by ion implantation of an n type impurity into a part of the p type well 33.
  • sidewall spacers 36 are formed on the side walls of the gate electrode 35.
  • a second n ⁇ type drain region 38 is formed by ion implantation of n type impurities.
  • an n + type drain region 39 and an n + type source region 41 are formed by ion implantation of an n type impurity.
  • a p + type semiconductor region 45 is formed by ion implantation of p type impurities.
  • an insulating film (interlayer insulating film) 46 is formed on the substrate 31 using a CVD method or the like, and the surface thereof is planarized using a CMP (Chemical Mechanical Polishing) method or the like as necessary. To do. Then, a contact hole 47 is formed in the insulating film 46 by using a photolithography technique and a dry etching technique, and then a plug 48 mainly composed of a tungsten (W) film is formed in the contact hole 47.
  • CMP Chemical Mechanical Polishing
  • the conductor film is patterned by using a photolithography technique and a dry etching technique to form the wiring M1.
  • an insulating film 49 is formed on the insulating film 46 so as to cover the wiring M1. Then, a through hole 50 is formed in the insulating film 49 using a photolithography technique and a dry etching technique.
  • a conductor film is formed on the insulating film 49 so as to fill the through hole 50, and then the conductor film is patterned by using a photolithography technique and a dry etching technique, so that the wiring M2 is formed. Form.
  • an insulating film (surface protective film) 52 is formed on the insulating film 49 so as to cover the wiring M2, and then an opening 53 is formed in the insulating film 49 using a photolithography technique and a dry etching technique. .
  • the wiring M2 is exposed from the opening 53, thereby forming the pad electrode PD including the drain pads PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 and the gate pads PDG1, PDG2, PDG3, PDG4, PDG5, PDG6. Is done.
  • the back surface of the substrate 31 (the main surface opposite to the side on which the epitaxial layer 31b is formed) is polished as necessary, and then the source back electrode 54 is formed on the entire back surface of the substrate 31 by sputtering or the like. To do.
  • the wafer process for the semiconductor wafer (substrate 31) is completed through the steps so far (step S11 in FIG. 21).
  • the wafer process is also called a pre-process, and generally, various elements (in this case, LDMOSFETs) and wiring layers are formed on the main surface of the semiconductor wafer (substrate 31), and a surface protective film (and a pad)
  • LDMOSFETs low-mobility metal-oxidation-oxide
  • a probe inspection process is performed on the semiconductor wafer (substrate 31) (step S12 in FIG. 21).
  • a probe probe
  • a probe is applied (pressed) to the pad electrode PD of each chip region (ie, semiconductor chip CP1) of the semiconductor wafer (substrate 31), and each chip region (ie, semiconductor) of the semiconductor wafer (ie, semiconductor chip CP1).
  • the electrical characteristics of the chip CP1) are inspected (tested).
  • the electrical characteristics of each chip region (that is, the semiconductor chip CP1) of the semiconductor wafer can be inspected.
  • the chip region determined to be defective in the probe inspection process is not used as the semiconductor chip CP1 after dicing, and is determined to be a non-defective product in the probe inspection process.
  • the chip area is used as the semiconductor chip CP1 after dicing.
  • step S13 can also be regarded as a process of obtaining the semiconductor chip CP1 by cutting the semiconductor wafer (substrate 31).
  • the preparation process of the semiconductor chip CP1 in step S2 includes these steps S11, S12, and S13.
  • the separated semiconductor chip CP1 is picked up in step S3 and mounted (mounted, die-bonded) on the wiring board base 25 (wiring board 11) as shown in FIG.
  • 22 to 24 are plan views of main parts of the semiconductor chip CP1, and plan views of the LDMOSFET formation region REGL3 in the semiconductor chip CP1 are shown. 22 to 24 show plan views of the same region, FIG. 22 shows a plan layout of the active region AR1, and FIG. 23 shows a wiring M1 (that is, a source wiring M1S and a drain wiring). A planar layout of M1D and gate wiring M1G) is shown, and FIG. 24 shows a planar layout of wiring M2 (that is, source wiring M2S, drain wiring M2D, and gate wiring M2G). 22 to 24, the drain pad opening 53D and the gate pad opening 53G are indicated by dotted lines in order to make it easy to compare the planar positions of FIGS.
  • FIG. 22 is a plan view, but in order to make the drawing easier to see, in FIG. 22, the active region AR1 is hatched.
  • the sectional view taken along the line A3-A3 in FIG. 24 substantially corresponds to FIG. 18, the sectional view taken along the line A4-A4 in FIG. 24 substantially corresponds to FIG. 19, and the sectional view taken along the line A5-A5 in FIG. Substantially corresponds to FIG.
  • FIG. 25 to 28 are main part plan views of the semiconductor chip CP1, and are enlarged views of a region 55 surrounded by a one-dot chain line in FIG. 25 to 28 show plan views of the same region (that is, the region 55 in FIG. 22).
  • FIG. 25 shows a plan layout of the active region AR1
  • FIG. The planar layout of the n + -type drain region 39, the n + -type source region 41 and the p-type punching layer 44 is shown.
  • 27 shows a planar layout of the wiring M1 (that is, the source wiring M1S, the drain wiring M1D, and the gate wiring M1G)
  • FIG. 28 shows the wiring M2 (that is, the source wiring M2S, the drain wiring M2D, and the gate wiring M2G).
  • Planar layout is shown.
  • the gate electrode 35 is indicated by a dotted line in order to make it easy to compare the planar positions of FIGS. 27 also shows the position of the contact hole 47 located below the wiring M1 (that is, the source wiring M1S, the drain wiring M1D, and the gate wiring M1G), and FIG. 28 shows the wiring M2 (that is, the source wiring M2S and the drain wiring).
  • the position of the through hole 50 located below M2D and the gate wiring M2G) is also illustrated.
  • 25 to 28 are plan views. To make the drawing easier to see, in FIG. 25, the active region AR1 is hatched with dots, and in FIG. 26, the gate electrode 35 is hatched with dots. Is attached.
  • the wiring M1 that is, the source wiring M1S, the drain wiring M1D, and the gate wiring M1G
  • the wiring M2 that is, the source wiring M2S, the drain wiring M2D, and the gate wiring. M2G
  • M2G is hatched with dots.
  • the sectional view taken along line A1-A1 in FIG. 25 substantially corresponds to FIG. 16
  • the sectional view taken along line A2-A2 in FIG. 28 substantially corresponds to FIG.
  • the X direction shown in the plan views of FIGS. 22 to 28 is a direction parallel to the side (chip side) SD1 on the side where the LDMOSFET formation region REGL3 and the drain pad PDD3 are formed in the semiconductor chip CP1.
  • the Y direction shown in the plan views of FIGS. 22 to 28 is a direction intersecting the X direction, and preferably a direction orthogonal to the X direction.
  • the element isolation region 32 defines an active region AR1 as shown in FIG. 22 and FIG. 25, and the active region AR1 is surrounded by the element isolation region 32.
  • the drain region of the LDMOSFET first n ⁇ type drain region 37, second n ⁇ type drain region 38 and n + type drain region 39
  • source region n ⁇ type source region 40 and n + type
  • a source region 41 is formed, and a gate electrode 35 is formed via a gate insulating film 34.
  • the gate electrode 35 of the LDMOSFET extends in the Y direction.
  • the drain region of the LDMOSFET (the first n ⁇ -type drain region 37, the second n ⁇ -type drain region 38 and the n + -type drain region 39) is a region between the adjacent gate electrodes 35 in the active region AR1. Formed in the Y direction.
  • the source region (n ⁇ type source region 40 and n + type source region 41) of the LDMOSFET is formed in a region between the other adjacent gate electrodes 35 in the active region AR1 and extends in the Y direction. Yes.
  • the p-type punching layer 44 is formed in a region between the n + type source regions 41 of adjacent LDMOSFETs.
  • One unit cell 60 forms two unit LDMOSFETs (unit LDMOSFET element, LDMOSFET cell, unit MISFET element) 60a. That is, the unit of repetition is the unit cell 60, but each unit cell 60 is configured by two unit LDMOSFETs 60a having a common n + -type drain region 39 and symmetrical in the X direction. Since the LDMOSFET is a MISFET element, the unit LDMOSFET 60a can be regarded as a unit MISFET element.
  • the structure (layout) of the unit cell 60 is repeated in the X direction, so that a large number (a plurality of) unit LDMOSFETs 60a are formed (arranged), and the large number (a plurality of) unit LDMOSFETs 60a are connected in parallel.
  • the unit LDMOSFETs 60a are repeatedly arranged in the X direction, and the plurality of unit LDMOSFETs 60a arranged in the LDMOSFET formation region REGL3 are connected in parallel.
  • the gate electrodes 35 of the plurality of unit LDMOSFETs 60a in the LDMOSFET formation region REGL3 are connected to each other via the plug 48 and the gate wirings M1G and M2G.
  • the drain regions (n + -type drain regions 39) are electrically connected to each other via the plug 48 and the drain wirings M1D and M2D.
  • the source regions are connected to each other by the plug 48, the source wiring M1S, M2S, the p + type semiconductor region 45, p.
  • the die punching layer 44, the substrate 31 and the source back electrode 54 are electrically connected to each other.
  • the LDMOSFET formation region REGL3 corresponds to a region in which the MISFET elements constituting the amplification stage LDML3 are formed, and a plurality of unit LDMOSFETs 60a formed in the LDMOSFET formation region REGL3 are connected in parallel to form the amplification stage LDML3. Is configured. Therefore, the MISFET element constituting the amplification stage LDML3 is configured by connecting a plurality of unit LDMOSFETs 60a in parallel.
  • the drain wiring M1D is formed on the drain region (n + -type drain region 39) of the LDMOSFET formed in the active region AR1, and the plug 48 disposed on the n + -type drain region 39 is interposed.
  • the drain wiring M1D and the drain region (n + -type drain region 39) of the LDMOSFET thereunder are electrically connected.
  • the drain wiring M1D also extends in the Y direction on the active region AR1, but on the element isolation region 32 between the active regions AR1.
  • the drain wiring M1D is not formed.
  • the drain wiring M1D is an isolated pattern formed only on each active region AR1, the upper portion of the drain wiring M1D extends in the Y direction as shown in FIGS.
  • the drain wiring M2D of the uppermost layer is electrically connected to the drain wiring M2D via a via portion (a portion filling the through hole 50).
  • the uppermost drain wiring M2D is a wiring portion (drain wiring) extending in the Y direction across a plurality of active regions AR1 (drain regions) arranged in the Y direction. Part) M2D1, and a connecting wiring part (drain wiring part) M2D2 that extends in the X direction and connects one ends of the plurality of wiring parts M2D1.
  • the plurality of wiring parts M2D1 and the connection wiring part M2D2 are integrally formed to constitute the drain wiring M2D. Accordingly, the drain wiring M2D has a so-called comb-like pattern.
  • Each wiring portion M2D1 extends in the Y direction so as to be positioned on each drain region of the plurality of unit LDMOSFETs 60a formed in the LDMOSFET formation region REGL3, and a plurality of unit LDMOSFETs 60a are connected via the drain wiring M1D and the plug 48. Are electrically connected to each drain region.
  • a drain pad opening 53D is formed above the connection wiring portion M2D2 of the drain wiring M2D, and the drain pad opening 53D is connected to the connection wiring portion M2D2 in a plane (in a plan view).
  • the wiring portion M2D2 has a larger area pattern than the drain pad opening 53D.
  • the drain pad PDD3 is formed by the drain wiring M2D exposed from the drain pad opening 53D, that is, the connection wiring M2D2 exposed from the drain pad opening 53D.
  • the drain region (n + -type drain region 39) of each unit cell 60 is pulled up to the wiring portion M2D1 of the uppermost drain wiring M2D through the plug 48 and the drain wiring M1D.
  • the drain wiring M2D is electrically connected to each other by the connecting wiring portion M2D2.
  • the drain pad PDD3 is formed by exposing a part of the drain wiring M2D (connection wiring portion M2D2) from the drain pad opening 53D.
  • the source region of LDMOSFET formed in the active region AR1 (n + -type source region 41) electrically connected to have been the source wiring M1S is, the source region (n + -type source region of the active region AR1 41) and the p + type semiconductor region 45.
  • the source wiring M1S since the source region extends in the Y direction, the source wiring M1S also extends in the Y direction on the active region AR1, but in the element isolation region 32 between the active regions AR1, The source wiring M1S is not formed. Therefore, the source line M1S is an isolated pattern formed only on each active region AR1, but as shown in FIGS. 16, 27, 28, etc., the upper part of the source line M1S extends in the Y direction.
  • the uppermost source wiring M2S is electrically connected to the source wiring M2S via a via portion (a portion filling the through hole 50).
  • the uppermost source line M2S extends in the Y direction across a plurality of active regions AR1 (source regions) arranged in the Y direction.
  • the source lines M2S are not connected to each other.
  • the pad electrode PD is not connected to the source wiring M2S because the source of the LDMOSFET is drawn from the source back electrode 54 on the back surface of the substrate 31 through the p-type punching layer 44 and the like. It is.
  • the gate electrode 35 extends in the Y direction and is buried in the contact hole 47 at a portion located on the element isolation region 32 around or between the active regions AR1.
  • the gate wiring M1G is electrically connected through the plug 48.
  • the gate wiring M1G extends in the X direction and the Y direction on the element isolation region 32 around and between the active regions AR1.
  • each gate electrode 35 extending in the Y direction is electrically connected to a portion extending in the X direction of the gate wiring M1G via a plug 48, and extends in the X direction of the gate wiring M1G.
  • the gate electrode 35 is electrically connected to each other via the gate wiring M1G by integrally connecting the portion to be extended and the portion extending in the Y direction.
  • the gate wiring M1G is a wiring in the same layer as the drain wiring M1D and the source wiring M1S. However, as shown in FIGS. 23 and 27, the drain wiring M1D and the source wiring M1S are formed on the element isolation region 32 between the active regions AR1. Is not formed, and the gate wiring M1G extends in the X direction. Therefore, the drain wiring M1D and the source wiring M1S extending in the Y direction are arranged between the portions of the gate wiring M1G extending in the X direction.
  • the gate wiring M1G is located on the opposite side of the drain wiring M2D from the connection wiring portion M2D2 (the side far from the connection wiring portion M2D2) and extends in the X direction.
  • the gate wiring M2G extending in the X direction on the element isolation region 32 is electrically connected to the via portion of the gate wiring M2G (the portion filling the through hole 50). That is, at least a portion of the gate wiring M2G extending in the X direction overlaps with the portion of the gate wiring M1G extending in the X direction in a plane, and the via portion (through hole) of the gate wiring M2G in the overlapping region. 50), the upper gate wiring M2G and the lower gate wiring M1G are electrically connected.
  • the gate electrode 35 of each unit LDMOSFET 60a is pulled up to the gate wiring M1G via the plug 48, and this gate wiring M1G is pulled up to the uppermost gate wiring.
  • the gate wiring M2G is connected to M2G, extends to the gate pad opening 53G, and a part of the gate wiring M2G is exposed from the gate pad opening 53G, thereby forming the gate pad PDG3.
  • FIG. 29 is a plan view of an essential part of the semiconductor chip CP1, and shows the same regions as those in FIGS. However, FIG. 29 shows the layout (arrangement) of the LDMOSFET formation region REGL3, the connection wiring portion M2D2 of the drain wiring M2D, the drain pad opening 53D, the gate wiring M2G, and the gate pad opening 53G, and other components. Is omitted. Accordingly, the source wiring M2S and the wiring portion M2D1 of the drain wiring M2D shown in FIG. 24 are not shown in FIG. Note that FIG.
  • FIG. 29 is a plan view, but the LDMOSFET formation region REGL3, the gate wiring M2G, and the connection wiring portion M2D2 of the drain wiring M2D are hatched for easy understanding of the drawing.
  • the gate pad opening 53G and the drain pad opening 53D are indicated by dotted lines, and the portion of the gate wiring M2G exposed from the gate pad opening 53G is the gate pad PDG3.
  • a portion of the drain wiring M2D (connection wiring portion M2D2) exposed from the opening 53D is the drain pad PDD3.
  • 30 and 31 are main part plan views of the power amplification module PA1 during the manufacturing process.
  • FIG. 30 shows a step after mounting the semiconductor chip CP1 on the wiring board matrix 25 (wiring board 11).
  • FIG. 31 shows the stage immediately after the wire bonding process (wire WA connection process) in step S5.
  • FIG. 32 is a perspective view (bird's eye view) of a main part during the manufacturing process of the power amplification module PA1, and a stage immediately after performing the wire bonding process (connection process of the wire WA) of step S5 to the semiconductor chip CP1 (that is, FIG. 31). The same stage) is shown.
  • 30 and 31 show a region corresponding to the region 56 surrounded by the two-dot chain line in FIG. 15, and FIG. 32 shows a part of FIG.
  • FIG. 33 is a plan view of the main part of the semiconductor chip CP101 of the first comparative example, and corresponds to FIG. 29 of the present embodiment.
  • the LDMOSFET formation region REGL103, the drain wiring M2D101, the drain pad opening 153D, the gate wiring M2G101, and the gate pad opening 153G are respectively the LDMOSFET formation region REGL3 and the drain wiring in this embodiment. This corresponds to M2D, drain pad opening 53D, gate wiring M2G, and gate pad opening 53G.
  • FIG. 34 and FIG. 35 are main part plan views during the manufacturing process of the power amplifying module of the first comparative example, and correspond to FIG. 30 and FIG. 31 of the present embodiment, respectively.
  • FIG. 34 shows a stage after mounting the semiconductor chip CP101 of the first comparative example on the wiring board base 25 and immediately before performing the wire bonding process (connection process of the wire WA101).
  • the stage immediately after performing the wire bonding process (connection process of the wire WA101) is shown.
  • FIG. 36 is a perspective view (bird's eye view) of the main part during the manufacturing process of the power amplifying module of the first comparative example, and corresponds to FIG. 32 of the present embodiment.
  • FIG. 36 shows a stage immediately after the wire bonding process (connection process of the wire WA101) to the semiconductor chip CP101 of the first comparative example (that is, the same stage as FIG. 35).
  • the gate pads PDG101, PDG102, PDG103, the drain pads PDD101, PDD102, PDD103, and the wire WA (bonding wire) 101 shown in FIGS. 34 to 36 are the gate pads PDG1, PDG2, PDG3 in the present embodiment, respectively. This corresponds to the drain pads PDD1, PDD2, PDD3 and the wire WA.
  • a plurality of are formed on the drain wiring M2D101 electrically connected to the drain of the LDMOSFET formed in the LDMOSFET formation region REGL103.
  • seven drain pad openings 153D are provided, and the drain pad PDD103 is formed by the drain wiring M2D101 exposed from each drain pad opening 153D. That is, in the semiconductor chip CP101 of the first comparative example, seven drain pads PDD103 are formed with respect to the LDMOSFET formation region REGL103, and these seven drain pads PDD103 are arranged in the X direction with a predetermined interval. Is arranged in.
  • one wire WA101 is connected to each of the seven drain pads PDD103. That is, the number of wires WA connected to one drain pad PDD103 is one. Therefore, in the semiconductor chip CP101 of the first comparative example, seven drain pads PDD103 are provided for the LDMOSFET formation region REGL103, and a total of seven wires WA101 are connected to these seven drain pads PDD103.
  • a probe inspection is performed after the wafer process.
  • a probe (probe) for inspection is pressed against the pad electrode in each chip area of the semiconductor wafer.
  • the pad electrode in each chip region becomes the pad electrode of each semiconductor chip after dicing of the semiconductor wafer.
  • the pad electrode is deformed in the area where the probe is pressed (contacted). Therefore, the probe is pressed against the pad electrode where the probe is pressed in the probe inspection.
  • Probe marks are formed (contacted) marks.
  • drain pads PDD103 are formed in the LDMOSFET formation region REGL103, and the wire WA101 is connected to each drain pad PDD103.
  • a probe mark PRB101 is formed on any of the seven drain pads PDD103 by pressing the probe in the probe inspection process.
  • FIG. 37 is an explanatory diagram (plan view) showing the probe mark PRB101 formed on the drain pad PDD103 of the semiconductor chip CP101 of the first comparative example and the connection region RGW101 of the wire WA101 on the drain pad PDD103.
  • FIG. 37 shows the drain pad PDD103 before the probe test, and (b) shows a probe (probe for inspection) on two drain pads PDD103 of the seven drain pads PDD103 in the probe test. A state in which the probe mark PRB101 is formed by pressing the needle) is schematically shown.
  • (c) shows a connection region RGW101 of the wire WA101 when the wire WA101 is connected to the drain pad PDD103 in the wire bonding step.
  • the first bonding is performed in the wire bonding process.
  • the bonding is performed on the pad electrodes (PDD3 and PDD103) of the chips CP1 and CP101, and the second bonding is performed on the substrate-side terminal TE.
  • ball bonding is preferably used for the wire bonding. For this reason, at the time of wire bonding, a metal ball at the tip of the wire (a gold ball when the wire is a gold wire) is connected to each pad electrode (PDD3, PDD103) of the semiconductor chips CP1, CP101 (specifically, , Crushed and connected or crimped).
  • a connection area RGW101 of the wire WA101, a connection area RGW201 of the wire WA101, which will be described later, and a connection area RGW of the wire WA are areas to which the metal balls (gold balls when the wires are gold wires) are connected.
  • the wires WA and WA101 are preferably wires (gold wires) made of gold, but when the gold wires (WA and WA101) are connected to the pad electrodes (PDD3 and PDD103) mainly made of aluminum (Al).
  • the gold ball at the tip of the wire (WA, WA101) is alloyed with the aluminum of the pad electrode (PDD3, PDD103), so that the wire (the gold ball at the tip thereof) is connected to the pad electrode (PDD3, PDD103).
  • the pad electrode (PDD3, PDD103) when connecting the wire (the metal ball at the tip of the wire) to the pad electrode (PDD3, PDD103), it is important that the surface state of the pad electrode (PDD3, PDD103) serving as the base is uniform. It is preferable that the pad electrode (PDD3, PDD103) to be formed has high flatness. If the wire (the metal ball at the tip thereof) is connected to the flat surface of the pad electrode, the connection strength of the wire to the pad electrode can be increased. However, since the semiconductor chips (CP1 and CP101) are used only for the production of a semiconductor device such as a power amplification module, contact of the probe to the pad electrodes (PDD3 and PDD103) by probe inspection is avoided. Therefore, probe marks (PRB, PRB101) are generated on the pad electrodes (PDD3, PDD103) to be wire-bonded.
  • connection region RGW101 of the wire WA101 overlaps the probe mark PRB101 as shown in FIG.
  • the connection strength between the PDD 103 and the wire WA101 is reduced.
  • the connection region RGW101 of the wire WA101 overlaps the probe mark PRB101 at two drain pads PDD103 of the seven drain pads PDD103, and the connection strength of the wire WA101 decreases at the two drain pads PDD103.
  • the connection region RGW101 of the wire WA101 becomes the probe mark PRB101 during wire bonding. This is because the wire (the metal ball at the tip thereof) is connected to a non-flat region due to the probe mark, and the connection strength of the wire WA101 is reduced. The decrease in the connection strength of the wire WA101 decreases the reliability of the manufactured power amplification module.
  • An example of the area of the probe mark PRB101 is, for example, about 40% of the area of the connection region RGW101 of the wire WA101.
  • FIG. 38 is an explanatory diagram (plan view) showing the probe mark PRB201 formed on the drain pad PDD203 of the semiconductor chip of the second comparative example and the connection region RGW201 of the wire WA101 in the drain pad PDD203.
  • FIG. 38 shows the drain pad PDD 203 before the probe test, and (b) shows a probe (probe for inspection) on two drain pads PDD 203 of the seven drain pads PDD 203 in the probe test.
  • a state in which the probe mark PRB201 is formed by pressing the needle) is schematically shown.
  • FIG. 38 is an explanatory diagram (plan view) showing the probe mark PRB201 formed on the drain pad PDD203 of the semiconductor chip of the second comparative example and the connection region RGW201 of the wire WA101 in the drain pad PDD203.
  • (c) shows a connection region RGW201 of the wire WA101 when the wire WA101 is connected to the drain pad PDD203 in the wire bonding step.
  • the drain pad PDD203 of the semiconductor chip of the second comparative example of FIG. 38 corresponds to the drain pad PDD103 of the semiconductor chip CP101 of the first comparative example of FIG.
  • the drain pad PDD203 of the semiconductor chip of the second comparative example shown in FIG. 38 has a larger dimension in the Y direction than the drain pad PDD103 of the semiconductor chip CP101 of the first comparative example. For this reason, in the semiconductor chip of the second comparative example, even if the wire WA101 is connected to the drain pad PDD203 to which the probe is pressed in the probe inspection in the wire bonding process, as shown in FIG. 38, the connection of the wire WA101 is performed.
  • the region RGW201 and the probe mark PRB201 can be shifted in the Y direction so that the connection region RGW201 of the wire WA101 and the probe mark PRB201 do not overlap.
  • the drain pad PDD203 of the semiconductor chip of the second comparative example shown in FIG. 38 is used to shift the position of the connection region RGW201 of the wire WA101 and the probe mark PRB201 in the drain pad PDD203 in the Y direction. It is necessary to enlarge the dimension in the Y direction. Therefore, the area required for the LDMOSFET formation region REGL103 and the drain pad PDD203 and the gate pad connected thereto is larger than that of the semiconductor chip CP101 of the first comparative example because the size of the drain pad PDD203 in the Y direction is larger. The semiconductor chip of the second comparative example to which the PDD 203 is applied becomes larger.
  • the semiconductor chip of the second comparative example to which the drain pad PDD203 is applied has a larger chip size (particularly the dimension in the Y direction) than the semiconductor chip CP101 of the first comparative example because the dimension of the drain pad PDD203 in the Y direction is larger. End up. This reduces the number of semiconductor chips that can be obtained from a single wafer, leading to an increase in manufacturing cost, and miniaturization of semiconductor devices (here, power amplification modules) on which semiconductor chips are mounted (planar dimensions). (Reduction) is disadvantageous.
  • a drain pad provided for the LDMOSFET formation region REGL3 that is, a drain pad electrically connected to the drain of the LDMOSFET formed in the LDMOSFET formation region REGL3.
  • a drain pad PDD3 having a larger dimension in the X direction than a dimension in the Y direction is formed.
  • the dimension in the X direction of the drain pad PDD3 is at least twice the dimension in the Y direction of the drain pad PDD3, and the drain pad PDD3 has a substantially rectangular planar shape (however, the rectangular corners are rounded). Can also be held).
  • One of the main features of the present embodiment is that a plurality of wires WA are connected to the one drain pad PDD3.
  • the drain pad PDD3 has a rectangular planar shape, and the long side direction (X direction) of the rectangle is the side (chip side) on the surface of the semiconductor chip CP1 where the drain pad PDD3 is disposed.
  • the direction is preferably parallel to SD1. That is, of the four sides (chip sides) SD1, SD2, SD3, and SD4 of the semiconductor chip CP1, the drain pad PDD3 is aligned in a direction parallel to the chip side (here, the side SD1) located closest to the drain pad PDD3. It is preferable to set the long side direction.
  • the drain pads PDD1, PDD2, and PDD3 and the gate pads PDG1, PDG2, and PDG3 are arranged along the side SD2 instead of the side SD1, and the LDMOSFET formation regions REGL1, REGL2, and REGL3 are When arranged on the side SD2 side instead of the SD1 side, the long side direction (X direction) of the drain pad PDD3 is parallel to the side SD2.
  • the drain pad PDD3 in FIGS. 29 to 32 is connected to the seven drain pads PDD103 arranged in the X direction in FIGS. It corresponds to. That is, in FIGS. 33 to 36, seven drain pads PDD103 and a region between drain pads PDD103 adjacent in the X direction are added to form one drain pad as a whole. It corresponds to PDD3.
  • FIG. 39 is an explanatory view (plan view) showing the probe mark PRB formed on the drain pad PDD3 of the semiconductor chip CP1 of this embodiment and the connection region RGW of the wire WA in the drain pad PDD3.
  • FIG. 39 shows the drain pad PDD3 before the probe test, and (b) shows a probe (probe for inspection) at two locations on the drain pad PDD3 in the probe test (corresponding to step S12). A state in which the probe mark PRB is formed by pressing the needle) is schematically shown.
  • (c) shows a connection region RGW of the wire WA when the wire WA is connected to the drain pad PDD3 in the wire bonding step (corresponding to step S5).
  • FIG. 40 is an explanatory diagram showing the probe mark PRB formed on the drain pad PDD3 of the semiconductor chip CP1 of this embodiment and the connection region RGW of the wire WA in the drain pad PDD3. ) Shows an enlarged view of a region 57 surrounded by a two-dot chain line in FIG. 39, and FIG. 40 (b) shows a cross-sectional view taken along line B1-B1 of FIG. 40 (a).
  • FIG. 40A is a plan view, but the probe mark PRB and the connection region RGW of the wire WA are hatched for easy viewing of the drawing.
  • FIG. 41 is a cross-sectional view showing a state in which the probe (probe) 58 for inspection is pressed against the drain pad PDD3 in the probe inspection (corresponding to step S12 above), and FIG. 42 shows the probe 58 in FIG.
  • FIG. 19 is a cross-sectional view showing a state in which a probe mark PRB is formed on the drain pad PDD3 by being pressed against the drain pad PDD3, and each shows a cross-section corresponding to FIG.
  • the surface (upper surface) of the drain pad PDD3 is substantially flat before the probe test.
  • FIG. 41 when the probe 58 is pressed against the drain pad PDD3 in the probe test (step S12), as shown in FIG.
  • the conductor film constituting the M2S is deformed to form a depression (concave part), and in some cases, a convex part is formed together with the depression (concave part).
  • a probe mark PRB is formed by a portion where the flatness is lost (a portion where a recess is formed or a portion where a recess and a projection are formed).
  • a plurality of wires WA are connected to the drain pad PDD3 and, as can be seen from FIGS. 39 and 40, a plurality of wires WA are connected in the drain pad PDD3.
  • the probe mark PRB is formed between the regions RGW. That is, in the pad electrode PDD3, a plurality of (here, seven) positions where the probe is applied (contacted) in the probe inspection in step S12 (that is, the position where the probe mark PRB is formed) are formed in the wire bonding step in step S5. ) Between the positions where the wire WA is connected. That is, in the drain pad PDD3, the region where the probe is pressed in the probe inspection (that is, the probe mark PRB) is located between the connection region RGW of a certain wire WA and the connection region RGW of the adjacent wire WA. is there.
  • the dimension in the X direction of the drain pad PDD3 is larger than the dimension in the Y direction of the drain pad PDD3, and a plurality of (in this case, seven) wires WA are connected to the drain pad PDD3.
  • the connection regions RGW of the wires WA in the drain pad PDD3 are aligned (arranged) in the X direction.
  • the connection regions RGW of the wires WA are adjacent to each other in the X direction, and probe traces are connected between the connection regions RGW adjacent in the X direction.
  • the PRB that is, the position where the probe is applied in the probe inspection in step S12
  • the connection region RGW of the adjacent wires WA and the probe mark PRB between the connection regions RGW of the adjacent wires WA are arranged in the X direction.
  • a plurality of wires WA are connected to the drain pad PDD3, and a region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) is located between the connection regions RGW of the plurality of wires WA in the drain pad PDD3.
  • the region where the probe is pressed by the probe inspection (that is, the probe mark PRB) is located between the connection regions RGW of the adjacent wires WA, so that the connection of the wire WA is performed in the drain pad PDD3.
  • the overlap between the region RGW and the probe mark PRB can be reduced, and preferably, the connection region RGW of the wire WA and the probe mark PRB can be prevented from overlapping (not overlapping in plan view).
  • the wire WA can be connected to the flat portion of the drain pad PDD3 (the portion where the probe mark PRB is not formed), so that the connection strength between the drain pad PDD3 and the wire WA can be improved. For this reason, the reliability of manufactured power amplification module PA1 can be improved.
  • a region where the probe is pressed in the probe inspection (that is, the probe mark PRB) is positioned between the connection regions RGW of the adjacent wires WA.
  • the planar area for securing does not contribute to an increase in the chip size of the semiconductor chip CP1, and is advantageous in terms of reducing the planar dimension (planar area) of the semiconductor chip CP1.
  • an empty space between the connection regions RGW of the adjacent wires WA is assigned to a region where the probe is pressed in the probe inspection (that is, a region where the probe mark PRB is formed). That is, in the semiconductor chip CP101 of the first comparative example of FIGS. 33 to 37, the region between the adjacent drain pads PDD103 (the region where the insulating film 52 as the surface protective film is formed) In the semiconductor chip CP1 of the present embodiment shown in FIGS.
  • a part of the drain pad PDD3 is used, and this is a region where the probe is pressed in the probe inspection (that is, the region where the probe mark PRB is formed).
  • a region that is not used as a pad electrode or a circuit region that is, a region between adjacent drain pads PDD103
  • FIGS. 32, 39 and 40 it is used as a region where the probe is pressed in the probe inspection (that is, a region where the probe mark PRB is formed).
  • the connection region RGW201 of the wire WA101 and the probe mark PRB201 are shifted in the Y direction. It is necessary to enlarge the probe mark PRB201.
  • the semiconductor chip CP1 of the present embodiment since the probe mark PRB is arranged between the connection regions RGW of the wires WA101 adjacent in the X direction, the dimension of the drain pad PDD3 in the Y direction is the same as that of the wire WA101. It is only necessary to set a dimension that can secure the connection region RGW, and it is not necessary to increase the dimension in the Y direction of the drain pad PDD3 in consideration of the area of the probe mark PRB.
  • the dimension in the Y direction of the drain pad PDD3 of the semiconductor chip CP1 of the present embodiment can be approximately the same as the dimension in the Y direction of the drain pad PDD103 in the semiconductor chip CP101 of the first comparative example. It can be made smaller than the dimension in the Y direction of the drain pad PDD203 in the semiconductor chip of the second comparative example. Therefore, in the present embodiment, the planar dimension (planar area) of the semiconductor chip CP1 can be reduced compared with the case where the drain pad PDD203 of FIG. 38 is applied, and the manufacturing cost can be reduced and the semiconductor chip CP1 can be manufactured.
  • the mounted semiconductor device here, power amplification module PA1 can be reduced in size (reduction in planar dimensions).
  • the connection strength between the drain pad PDD3 and the wire WA can be improved, and the manufactured power amplification The reliability of the module PA1 can be improved.
  • the planar dimension (planar area) of the semiconductor chip CP1 can be reduced. The manufacturing cost can be reduced, and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted can be downsized (planar dimensions can be reduced).
  • the drain pad PDD3 has a long planar shape along the chip side (here, the side SD1) on the side where the drain pad PDD3 is disposed, the dimension of the drain pad PDD3 in the short side direction (Y direction) (
  • the length L1 depends on the size of the metal ball at the tip of the wire WA to be connected, but can be, for example, about 65 ⁇ m (the dimension L1 is shown in FIG. 40).
  • the connection pitch (connection interval) P1 of the wires WA in the drain pad PDD3 (the connection pitch P1 is shown in FIG. 40) is set to 1 of the dimension L1 in the short side direction of the drain pad PDD3 in consideration of the arrangement of the probe marks PRB.
  • the diameter L2 (diameter L2 is a figure of the connection region RGW of the wire WA from the viewpoint of area saving). 40) is set to be 60% or more of the dimension L1 in the short side direction of the drain pad PDD3 (that is, L2 ⁇ L1 ⁇ 0.6), and the dimension L1 in the short side direction of the drain pad PDD3 is set. It is preferable.
  • the thickness of the conductor film (corresponding to the source line M2S) constituting the drain pad PDD3 can be set to, for example, about 0.3 to 3 ⁇ m.
  • the probe mark PRB is arranged between the connection regions RGW of the wires WA adjacent in the X direction, the probe mark PRB is partially overlapped with the connection region RGW of the wire WA. Even if it exists, since the overlapping area of the probe mark PRB and the connection region RGW of the wire WA can be reduced, the effect of improving the connection strength of the wire WA to the drain pad PDD3 can be obtained.
  • the probe mark PRB is arranged between the connection regions RGW of the wires WA adjacent in the X direction, but the probe mark PRB overlaps with the connection region RGW of the wire WA. It is more preferable that they are not overlapped (in a plan view).
  • the plurality of wires WA are connected to the drain pad PDD3 at a position that does not overlap the probe mark PRB in plan view. Since the probe mark PRB and the connection region RGW of the wire WA do not overlap (does not overlap in plan view), the wire WA is connected to the drain pad PDD3 in a flat portion where the probe mark PRB is not formed.
  • the connection strength of the wire WA to the drain pad PDD3 can be improved more accurately, and the reliability of the power amplification module PA1 can be improved more accurately.
  • connection regions RGW of the plurality of wires WA in the drain pad PDD3 are arranged in a line (on a straight line). That is, in the wire bonding process of step S5, it is preferable that the positions where the plurality of wires WA are connected in the drain pad PDD3 are arranged in a line (on a straight line). More specifically, the connection regions RGW of the plurality of wires WA in the drain pad PDD3 are preferably arranged in a line (on a straight line) along the long side direction (X direction) of the drain pad PDD3.
  • connection region RGW of the wires WA is not arranged in a so-called staggered arrangement (without shifting in the Y direction), as shown in FIGS.
  • the connection regions RGW of the plurality of wires WA are arranged in a line (on a straight line) in the X direction (that is, the long side direction of the drain pad PDD3).
  • planar dimension (planar area) of the semiconductor chip CP1 can be reduced, the manufacturing cost can be reduced, and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted is reduced (the planar dimension is reduced). ).
  • FIG. 31 In FIG. 31, FIG. 32 and FIG. 39, seven wires WA are connected to the drain pad PDD3.
  • the number of wires WA connected to the drain pad PDD3 is not limited to seven. Or more).
  • the number of regions in which the probe is pressed against the drain pad PDD3 in the probe inspection process that is, the number of probe marks PRB formed on the drain pad PDD3, or the number of probes pressed against the drain pad PDD3 in the probe inspection process).
  • FIG. 39 the number of regions in which the probe is pressed against the drain pad PDD3 in the probe inspection process (that is, the number of probe marks PRB formed on the drain pad PDD3, or the number of probes pressed against the drain pad PDD3 in the probe inspection process). ) Is two (two places), but is not limited to this, and may be one or more (one or
  • the region between the connection regions RGW of the wires WA in the drain pad PDD3 includes a region where the probe mark PRB is arranged and a region where the probe mark PRB is not arranged.
  • the region where the probe mark PRB is arranged there are six locations between the seven connection regions RGW.
  • a region where the probe is pressed in the probe inspection ie, the probe mark PRB
  • the other ends of the plurality of wires WA whose one ends are connected to the drain pad PDD3 are connected to one terminal TE of the wiring substrate 11.
  • One end of the WA may be connected to the drain pad PDD3, and the other ends of the plurality of wires may be connected to the plurality of terminals TE, respectively.
  • the resistance component due to the wires WA can be further reduced as compared with the case of two wires WA (that is, the power loss reduction effect can be further increased).
  • the number of regions where the probe is pressed against the drain pad PDD3 in the probe inspection process that is, the number of probe marks PRB formed on the drain pad PDD3
  • the reliability of the probe inspection is further improved than the case of one. Can be improved.
  • the drain pad PDD3 electrically connected to the drain of the LDMOSFET formation region REGL3 is connected to the connection region RGW of the wire WA and the region where the probe is pressed in the probe inspection (that is, the probe mark PRB).
  • connection strength between the drain pad PDD6 and the wire WA can be improved, and the reliability of the power amplification module PA1 can be improved.
  • chip size of the semiconductor chip CP1 can be suppressed, so that the manufacturing cost can be reduced and the semiconductor device (here, the power amplification module PA1) on which the semiconductor chip CP1 is mounted can be downsized (planar dimensions are reduced). it can.
  • the semiconductor chip CP1 has a plurality of power amplifier circuits (in this case, the amplifier stages LDML1, LDML2, and LDML3 and the amplifier stages LDMH1, LDMH2, and LDMH3) connected in multiple stages.
  • the pad electrodes PD connected to the outputs of the semiconductor elements (here, LDMOSFETs) constituting the amplification stages (LDML3, LDMH3) are drain pads PDD3, PDD6.
  • the pad electrode (drain pad PDD3, PDD6) connected to the output of the semiconductor element (here LDMOSFET) constituting the final stage power amplification circuit (here amplification stage LDML3, LDMH3) has a large output current
  • the number of wires WA to be connected to be plural (increase) the effect of reducing the resistance component by the wires WA and reducing the power loss is extremely great. Therefore, like the drain pad PDD3 in FIGS. 39 and 40, a plurality of wires WA are connected to the pad electrode PD, and a probe inspection is performed between the connection regions RGW of the plurality of wires WA in the pad electrode PD.
  • the above-described feature of locating the region where the is pressed is particularly effective when applied to the pad electrodes (here, drain pads PDD3 and PDD6) connected to the output of the power amplifier circuit in the final stage. .
  • the pad electrodes (drain pads PDD3 and PDD6) connected to the output are rectangular. Even if a plurality of wires WA are connected to the pad electrode, it is difficult to increase the area of the semiconductor chip CP1.
  • pad electrodes PD (here, drain pads PDD1, PDD2) connected to the outputs of the semiconductor elements (here, LDMOSFETs) constituting the amplification stages LDML1, LDML2, LDMH1, and LDMH2 prior to the last amplification stages LDML3 and LDMH3.
  • PDD4, PDD5 when connecting a plurality of wires WA to the pad electrode PD, the features of the drain pad PDD3 of FIGS. 39 and 40 can be applied. That is, also in the pad electrode PD, the region where the probe is pressed in the probe inspection (that is, the probe mark PRB) can be positioned between the connection regions RGW of the plurality of wires WA. For example, as shown in FIGS.
  • a plurality (two in the case of FIG. 14) of wires WA are connected to the drain pad PDD2, and also in this drain pad PDD2, like the drain pad PDD3 in FIG. Between the connection regions RGW of the plurality of wires WA, a region where the probe is pressed in the probe inspection (that is, the probe mark PRB) can be positioned. Further, as shown in FIGS. 14 and 15, a plurality (two in the case of FIG. 14) of wires WA are connected to the drain pad PDD5, and also in this drain pad PDD5, as in the drain pad PDD3 of FIG. Between the connection regions RGW of the plurality of wires WA, a region where the probe is pressed in the probe inspection (that is, the probe mark PRB) can be positioned.
  • the pad electrode PD (here, drain pad) connected to the output of the semiconductor element (here, LDMOSFET) constituting the power amplifier circuit.
  • a plurality of wires WA are connected to any one of PDD1, PDD2, PDD3, PDD4, PDD5 and PDD6).
  • region (namely, probe mark PRB) which pressed the probe by the probe test
  • FIG. 43 is an explanatory diagram of the first modified example and corresponds to FIG. 39 described above.
  • (a) shows the drain pad PDD3 before the probe inspection
  • (b) shows the probe (probing for inspection) at two locations on the drain pad PDD3 in the probe inspection (corresponding to step S12).
  • a state in which the probe mark PRB is formed by pressing the needle) is schematically shown.
  • (c) shows a connection region RGW of the wire WA when the wire WA is connected to the drain pad PDD3 in the wire bonding step (corresponding to step S5).
  • three or more wires WA are connected to the drain pad PDD3 and are connected at equal intervals. That is, in the drain pad PDD3, a plurality of wires WA are connected at an equal pitch (equal interval), and an interval (a distance in the X direction) between the connection region RGW of the wire WA and the connection region RGW of the adjacent wire WA.
  • the pitch P1) is the same for any wire WA connected to the drain pad PDD3. This is because in the wire bonding step of step S5, three or more wires WA are connected to the drain pad PDD3, and these three or more wires WA are connected to the drain pad PDD3 at equal pitches (equal intervals). is there.
  • a region where the probe mark PRB is arranged and a region where the probe mark PRB is not arranged are mixed.
  • the plurality of wires WA are not connected at an equal pitch (equal interval). That is, in the drain pad PDD3, the interval (pitch, distance) P5 between the connection regions RGW between which the probe marks PRB are disposed is the interval (pitch, distance) between the connection regions RGW between which the probe marks PRB are not disposed. Distance) is larger than P6 (that is, P5> P6).
  • intervals P5 and P6 are shown in FIG. 43, and the interval P5 indicates a plurality of wires WA connected to the drain pad PDD3 in the connection region RGW of adjacent wires WA with the probe mark PRB interposed therebetween. It corresponds to the interval (pitch, distance).
  • the interval P6 corresponds to the interval (pitch, distance) between the connection regions RGW of adjacent wires WA without interposing the probe mark PRB between the plurality of wires WA connected to the drain pad PDD3.
  • the interval between the connection regions RGW of the wires WA is set to a wire bonding apparatus (bonding tool).
  • Bonding tool can be set to the minimum interval (pitch) that needs to be set, and the number of wires WA connected to the pad electrode PD (here, the drain pad PDD3) can be efficiently increased.
  • the resistance component by wire WA can be reduced efficiently and a power loss can be reduced efficiently.
  • the dimension of the pad electrode PD in the long side direction can be suppressed, and the chip size of the semiconductor chip CP1 can be reduced.
  • the interval P5 between the connection regions RGW of the wires WA between which the probe traces PRB are arranged is arranged, and the probe trace PRB is arranged therebetween.
  • P5> P6 the distance between the connection areas RGW of the unwired wires WA is larger (P5> P6), the following advantages can be obtained. That is, if the interval P5 is too small, the connection region RGW of the wire WA and the probe mark PRB overlap with each other, and the connection strength of the wire WA tends to decrease.
  • the connection region RGW of the wire WA and the probe mark PRB do not overlap with each other, and the connection strength of the wire WA does not decrease.
  • the pad electrode PD Here, the number of wires WA that can be connected to the drain pad PDD3) decreases, or the size of the pad electrode PD (here, the drain pad PDD3) in the long side direction (here, the X direction) increases. For this reason, by making the interval P5 larger than the interval P6 (P5> P6), the connection region RGW of the wire WA and the probe trace PRB are more accurately suppressed or prevented and the connection strength of the wire WA is improved.
  • the number of wires WA that can be connected to the pad electrode PD can be increased, and the dimension of the pad electrode PD in the long side direction can also be increased. Can be suppressed.
  • the number of wires WA that can be connected to the pad electrode PD (here, the drain pad PDD3) is increased while the overlapping of the connection region RGW of the wire WA and the probe mark PRB is more accurately suppressed or prevented.
  • the resistance component due to the wire WA can be efficiently reduced, the power loss can be efficiently reduced, and the size of the pad electrode PD in the long side direction is also suppressed, so that the chip size of the semiconductor chip CP1 can be reduced. Reduction is also possible.
  • FIG. 44 is a plan perspective view of the power amplification module PA1 using the semiconductor chip CP1a of the second modified example instead of the semiconductor chip CP1, and shows a state where the sealing resin 13 is seen through.
  • FIG. 45 is a partially enlarged plan view of FIG. 44, in which the semiconductor chip CP1a mounted on the wiring board 11 and its peripheral region are enlarged.
  • FIG. 46 is a plan view in which the wires WA and the substrate-side terminals TE are omitted from FIG. 45, and corresponds to a plan view (planar layout diagram) of the semiconductor chip CP1a.
  • the semiconductor chip CP1 has two systems of power amplification circuits LDML and LDMH.
  • the semiconductor chip CP1a of the second modified example has two systems of power amplification in addition to the two systems of power amplification circuits LDML and LDMH.
  • a circuit is added, and a total of four power amplifier circuits are provided. That is, the semiconductor chip CP1a has four-system power amplifier circuits corresponding to the four frequency bands, and the power amplifier module PA1 of FIG. 44 using the semiconductor chip CP1a corresponds to the four frequency bands.
  • the semiconductor chip CP1a has LDMOSFET formation regions REGM1, REGM2, REGN1, and REGN2 in addition to the LDMOSFET formation regions REGL1, REGL2, REGL3, REGH1, REGH2, and REGH3.
  • the first power amplifier circuit LDML is formed by the LDMOSFETs formed in the LDMOSFET formation regions REGL1, REGL2, and REGL3, respectively
  • the second system is formed by the LDMOSFETs formed in the LDMOSFET formation regions REGH1, REGH2, and REGH3, respectively.
  • the semiconductor chip CP1a is the same as the semiconductor chip CP1 in that the power amplifier circuit LDMH is formed.
  • the first amplification stage constituted by the LDMOSFET formed in the LDMOSFET formation region REGM1 and the second amplification stage constituted by the LDMOSFET formed in the LDMOSFET formation region REGM2 are connected.
  • a third system power amplifier circuit is formed.
  • the first stage amplification stage configured by the LDMOSFET formed in the LDMOSFET formation region REGN1 and the second stage amplification stage configured by the LDMOSFET formed in the LDMOSFET formation region REGN2 are connected, and the fourth system power is connected.
  • An amplifier circuit is formed.
  • the semiconductor chip CP1a has, as the pad electrode PD, in addition to the drain pads PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 and the gate pads PDG1, PDG2, PDG3, PDG4, PDG5, PDG6, and further drain pads PDD7, PDD8, PDD9, PDD10 and gate pads PDG7, PDG8, PDG9, PDG10 are also provided.
  • the gate pad PDG7 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGM1
  • the drain pad PDD7 is an output pad electrically connected to the drain of the LDMOSFET formation region REGM1.
  • the pad electrode is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGM1
  • the drain pad PDD7 is an output pad electrically connected to the drain of the LDMOSFET formation region REGM1.
  • the gate pad PDG8 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGM2, and the drain pad PDD8 is electrically connected to the drain of the LDMOSFET formation region REGM2.
  • This is a pad electrode for output.
  • the gate pad PDG9 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGN1
  • the drain pad PDD9 is an output pad electrically connected to the drain of the LDMOSFET formation region REGN1. It is a pad electrode.
  • the gate pad PDG10 is an input pad electrode electrically connected to the gate electrode of the LDMOSFET formation region REGN2, and the drain pad PDD10 is an output pad electrically connected to the drain of the LDMOSFET formation region REGN2. It is a pad electrode.
  • the semiconductor chip CP1a When the semiconductor chip CP1a is used instead of the semiconductor chip CP1, not only the drain pads PDD1, PDD2, PDD3, PDD4, PDD5 and PDD6 but also one or more of the drain pads PDD7, PDD8, PDD9 and PDD10.
  • the relationship between the pad electrode, the connection region RGW of the wire WA, and the probe mark PRB described with reference to FIGS. 29 to 32 and 39 can also be applied. That is, in FIG. 44 to FIG. 46, a plurality of wires WA are connected to the drain pad PDD7. However, similarly to the drain pad PDD3 in FIG. A region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned between the regions RGW.
  • a plurality of wires WA are connected to the drain pad PDD8.
  • a plurality of wires WA are connected to the drain pad PDD8.
  • a region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned between the regions RGW.
  • a plurality of wires WA are connected to the drain pad PDD9.
  • the drain pad PDD9 similarly to the drain pad PDD3 in FIG. 39 or 43, the drain pad PDD9 also has a connection region RGW of the plurality of wires WA.
  • the region where the probe is pressed in the probe inspection process that is, the probe mark PRB
  • a plurality of wires WA are connected to the drain pad PDD10. However, similarly to the drain pad PDD3 in FIG. 39 or 43, a plurality of wires WA are connected to the drain pad PDD7.
  • a region where the probe is pressed in the probe inspection process (that is, the probe mark PRB) can be positioned between the regions RGW.
  • the power amplification module has been described as a preferred application example of the present invention.
  • various semiconductor devices in which wires are connected to pad electrodes of a semiconductor chip having an amplification element, and manufacturing methods thereof Can be applied to.
  • the present invention is effective when applied to a semiconductor device and its manufacturing technology.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

L'objet de la présente invention est d'améliorer la fiabilité d'un dispositif à semi-conducteur, ainsi que d'obtenir une échelle plus petite du dispositif à semi-conducteur. Un composant passif et une puce de semi-conducteur sont montés sur une carte de circuit imprimé, une pluralité d'électrodes de plage de connexion de la puce de semi-conducteur sont électriquement connectées par des fils électriques à une pluralité de bornes de la carte de circuit imprimé, et l'ensemble est encapsulé au moyen d'une résine de manière à fabriquer un module d'amplification de puissance. La puce de semi-conducteur est dotée d'une plage de connexion de drain (PDD3) qui est connectée au drain d'un LDMOASFET constituant le circuit d'amplification de puissance, et une pluralité de fils électriques sont connectés à la plage de connexion de drain (PDD3). Dans la plage de connexion de drain (PDD3), une marque de sonde (PRB) qui est formée par une inspection de sonde est positionnée entre les régions de connexion (RGW) de la pluralité de fils électriques.
PCT/JP2012/075632 2011-10-06 2012-10-03 Dispositif à semi-conducteur et son procédé de production WO2013051599A1 (fr)

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Cited By (2)

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US20210151845A1 (en) * 2014-12-01 2021-05-20 Murata Manufacturing Co., Ltd. Electronic apparatus and electrical element
US20210306018A1 (en) * 2020-03-31 2021-09-30 Murata Manufacturing Co., Ltd. Radio frequency module and communication device

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JP6476000B2 (ja) * 2015-02-17 2019-02-27 三菱電機株式会社 半導体装置および半導体モジュール

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JP2008235431A (ja) * 2007-03-19 2008-10-02 Nec Electronics Corp 半導体装置
JP2010153901A (ja) * 2002-11-26 2010-07-08 Freescale Semiconductor Inc ボンディングパッドを有する半導体装置及びその形成方法

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JP2008235431A (ja) * 2007-03-19 2008-10-02 Nec Electronics Corp 半導体装置

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Publication number Priority date Publication date Assignee Title
US20210151845A1 (en) * 2014-12-01 2021-05-20 Murata Manufacturing Co., Ltd. Electronic apparatus and electrical element
US11605869B2 (en) * 2014-12-01 2023-03-14 Murata Manufacturing Co., Ltd. Electronic apparatus and electrical element
US20210306018A1 (en) * 2020-03-31 2021-09-30 Murata Manufacturing Co., Ltd. Radio frequency module and communication device
US11528044B2 (en) * 2020-03-31 2022-12-13 Murata Manufacturing Co., Ltd. Radio frequency module and communication device

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