TW464960B - Method of forming a semiconductor thin film - Google Patents
Method of forming a semiconductor thin film Download PDFInfo
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- TW464960B TW464960B TW089114692A TW89114692A TW464960B TW 464960 B TW464960 B TW 464960B TW 089114692 A TW089114692 A TW 089114692A TW 89114692 A TW89114692 A TW 89114692A TW 464960 B TW464960 B TW 464960B
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- 239000010409 thin film Substances 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims description 46
- 239000010408 film Substances 0.000 claims abstract description 49
- 239000013078 crystal Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 239000011521 glass Substances 0.000 claims description 7
- 238000002425 crystallisation Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000008025 crystallization Effects 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 17
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 5
- 238000007796 conventional method Methods 0.000 abstract description 2
- 238000005286 illumination Methods 0.000 abstract 3
- 239000013081 microcrystal Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- 230000001678 irradiating effect Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004090 dissolution Methods 0.000 description 3
- 238000010951 particle size reduction Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007715 excimer laser crystallization Methods 0.000 description 2
- 230000033001 locomotion Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02678—Beam shaping, e.g. using a mask
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- Condensed Matter Physics & Semiconductors (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Description
464960 五、發明說明(1) 發明背景 發明之領述 本發明係關於一種對非單社 射光進行回火之半導體薄膜之體】膜,射脈衝雷 成在液晶顯示器或密著型影別是關於於形 主办像城測器等絕緣性基板上之客 結晶樣電晶體之活性層之雷射回火製程之構成。 習知拮術 乂 近年,藉由使用複晶矽(以下#p〇ly_Si表示)薄臈 晶體之製造技術,而可形成於廉價之玻璃基驅 電路之液晶顯示裝置。P〇iy-Si薄膜之形成法’由製程溫動 度之低溫化及產能化之觀點而言,使用準分子雷射結晶化 法L其藉由照射準分子雷射光,使非晶矽(以下簡稱為 a - S ΐ )薄膜結晶,而得到p 〇 1 y _ g j薄膜。 ^準分子雷射結晶化法之缺點為:因雷射光為脈衝雷射 光,故薄膜之熱處理時間有限制,使所得之結晶粒之大小 亦被制限。因此,poly —Si薄膜電晶體(TFT)之载子之電場 效果移動度停留於I00cm2/Vs左右,故即使可製成液晶顯琢 不裝置等,亦無法製成DRAM等高頻驅動之高積體電路。 、,poly —Si薄膜之大粒徑化技術之第1技術,如日本特開 平1 0-2 7578 1號公報或第42回應用物理學關係連合演講會开 演講草稿集第2分冊694頁(作者,石原等)所揭示,為以合 成複數脈衝雷射而照射之技術。 又’大粒徑化技術之第2技術,如MRS會刊21期(1 9 96 年)3月號89頁(著者,1爪等)所揭示’為於形成為島狀之非
第5頁
464960 五,發明說明(2) 晶質矽薄膜上’藉由將寬為5 # m之極微細之線狀光束以〇. 7 5 μ m間距掃瞄照射,而形成結晶粒界約成行排列之單方 向生長多結晶矽薄膜之技術。 #明欲解決之誤題 然而’大粒徑化技術之第1技術中,雖然於各雷射照 射領城中進行大粒徑化,但於用於液晶顯示裝置之數百公 釐見方面積之基板中’要均勻地達成大粒徑化極為困難。 又,大粒徑化技術之第2技術中’亦有產能下降之問題, 及為了確保次微米之平台動作精度而使搬送系統複雜化之 問題。 有鑑於上述問題’本發明之目的係在於提供於大面積 基板上高產能,高均一且高移動度之半導體薄膜之製造方 法, 、 解決锞顳之方法 本發明之半導體薄膜之 半導體薄膜以複數脈衝雷射 結晶或單結晶半導體薄膜, 不超過藉由該非單結晶半導 結晶化之能量密度臨界值, 之能量密度,較該非單結晶 而微結晶化之能量密度臨界 衝雷射之前後之脈衝雷射中 後脈衝雷射之能量密度,該 之和超過該能量密度臨界值 製造方法,為藉由對非單結晶 連續於相同處照射,而製造多 其特徵為各脈衝之能量密度, 體薄膜之脈衝雷射之照射而微 該複數脈衝雷射之各脈衝雷射 半導體薄膜藉由脈衝雷射照射 值為低’而於連續之該複數脈 ’别脈衝雷射之能量密度大於 複數脈衝雷射之全部能量密度 ’而該前後脈衝雷射之照射間
五、發明說明(3) 隔’為該前脈衝雷紐 該前後脈衝雷射之寬之脈衝寬之6倍以下,最好 脈衝寬之丨倍以上隔’為該前脈衝雷射之半值宽之 半導該雷射之照射’該多結晶或單結晶 晶粒長度之2 H且# 晶粒長度超過短軸方向之結 之組織,料:罝缺Λ 含於該短軸方向成列並排 行之照射,係為於該非單結晶半導; 轴方向之結晶粒之長度以下之間距,於該 古 丨”: 移動而重覆進行之掃瞄照射。 、 p ^述半導體薄臈之製造方法中,㈣單結晶半導 二ΐνΐΛ壓化學氣相生瞻㈣)法、電漿化學氣相生 ,(PECVD)法、濺鍍法之任—方法而形成,或該多社 早結晶半導體薄膜可形成於玻璃基板上。 、° aa或 較佳實施例之詳細說明 首先,於說明本發明之半導體薄膜之製造方法 之基本的構成前,參考圖3(a),說明成為本發明: 晶化現象。 η京之結 非晶質薄膜及多結晶薄膜等非單結晶構造之薄膜, 稱為非單結晶薄膜’而非單結晶薄膜之微結晶化之產生' 一般係認為藉由薄膜之溶解狀態之變化,使再結晶’ 核產生機構由以基板薄膜界面做為核產生區段之不均一 產生,轉變成均一核產生。此核產生機構之變化,與 ^ 之到達溫度與冷卻速度相關。 … 、
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對非單結晶矽薄膜’以照射如圖3 (a)之具有超過欲結 晶化臨界值Ευ之能量密度之光束形狀之長線狀雷射光時, 於光束形狀上之成為微結晶化臨界值以之正下方之地點, 形成粗大結晶粒。亦即’若見其平面之結晶粒徑分布,則 可於微結晶化區域9之鄰接地點形成粗大結晶粒丨〇。因 此’將光束形狀為非單結晶矽薄膜之微結晶化臨界值以上 之雷射光’照射於非單結晶矽薄膜時,可將所形成之結晶 粒之粒徑及產生位置控制為一次元。特別是將形成於光束 後半部81中之粗大結晶粒1 〇做為種結晶,而以其粒徑以下 掃瞄雷射光時’種.結晶可不間斷地連續生長。因包含以光 束前半部8 0所形成之粗大結晶粒之多結晶組織,藉由其後 之掃瞄照射而微結晶化,故不會妨礙以光束後半部8 1所形 成£種結晶之粒生長。亦即’藉由利用微結晶化現象,可 避免脈衝雷射光掃瞄照射法中之結晶組織不均勻性β 在此,為了得到高產能,最好擴大以光束後半部8丨所 形成之種結晶之結晶粒徑’此可使用於相同處使複數個脈 衝雷射同步,於脈衝寬左右之時間内連續照射之雙重脈衝 法為有效。薄膜藉由於先發脈衝雷射之溶解中,照射次發 脈衝雷射,而延長薄膜之溶解時間,且亦降低凝固速度, 而可擴大結晶粒徑。 本發明之半導體薄膜之製造方法中,如圖1所示,此 雙重脈衝法中,於將η設為1以上之整數時,將第η發之脈 衝能量密度設為Εη ’脈衝寬設為Wn,第(η+1)發之脈衝能 量密度設為Εη+1,第η發之脈衝與第(η + 1)發之脈衝之照
第8頁 464960
Eu>EngEn + l、tnS6Wn、El+E2 + ...+En + En + l>Eu 之條件進 行掃猫照射’而可將具有大粒徑之半導體薄膜大面積均勻 地形成。因此,藉由本發明,可將具有高均一、高移動度 之薄膜電晶體元件形成於大面積基板上。 以下以具體實施型態’說明上述本發明之基本構成。 首先’參考圖2〜5,說明本發明之半導體薄膜之製造 方法之第1實施形態。 射間隔設為tη,薄膜之微結晶化臨界值設為Eu時,藉由將 於玻璃基板1上,藉由電漿化學氣相生長(PECVD)法形 成膜厚為200nm之氧化矽膜2,於其上形成a-Si薄膜8。成 膜法可使用減壓化學氣相生長(LPCVD)法、PECVD法、濺鍍 法等,在此係使用於膜中不含氣體之LPCVD法。膜厚設為 5 Οηίή(圖 5 (a)) 〇 其次,於膜厚50nm之a-Si膜3上,照射具有長邊方向 如為lOOram短邊方向為10〜20 之範圍之波長308nm、脈 衝寬(W1 ) 5 0 n s之X e C1雷射光5 0,此時之微結晶化臨界值 (Eu)為470mJ/cm2。在此,以控制裝置6,使圖2所示之2個 光源4、5同步,透過光學系7,而對設置於反應室8内之玻 璃基板1之a-Si薄膜3,進行雙重脈衝照射。雙重脈衝照射 條件設為:將第1雷射光之能量密度(E1)設為400mJ/cm2、 第2雷射光之能量密度(E2)設為240mJ/cin2、照射間隔(tl) 設為 100ns(tl = 2Fl)。 結果,如圖3 ( a )所示,若進行上述條件之雙重脈衝照 射,則形成具有異向性之橢圓形狀之粗大結晶粒1 〇,其鄰
464960 五、發明說明(6) 接區域成為微結晶化區域9。粗大結 方向11為2.8 βπι,於短軸方士19以9 於長軸 番晰偷昭μ政批尽姐軸方向丨2為1.2 //m。藉由使用本雙 重脈衝照射條件,以粗大結晶粒徑以下之以㈣ 距13進打掃瞒照#,而V得到h圖3(b)所示之連續生長之 ::曰: =67。此時之平台動作精度若考慮粒徑與照射間 此,則寓為ϋ. 7 # m以下。 另一方面,圖3 (c)係為說明本實施形態優點之比較 例。使用雷射結晶化法於以單發照射5〇〇mJ/cm2之雷射光 時,如圖3(c)所示,淤微結晶區域丨9之邊界部形成粒徑 〇, 8私m之約等軸之結晶粒2〇 β為了以此條件連續生長,必 須將掃瞄間距設為〇 · 6 # m以下,而使產能下降。又,因平 台動作精度必須為〇. 2以m以下’故不易穩定地得到於照射 距離全區域連續生長之結晶粒之穩定再現性。 其次’圖4係為改變雷射光之能量密度E1、E2及^ 時’所得之具有異向性之粗大結晶粒之長軸方向之粒徑。 當E1超過Eu時’不論E2及tl為何,其粒徑擴大效果小(圖 4 (a ))。此係由於藉由E丨已使基板界面附近之溫度達到過 份抑制核產生之溫度。為了使當地保持於基板界面之核產 生’以促進粒生長,並將a_Si薄膜之上層溶解,以成為粗 大結晶粒,必須使E1成為Eu以下(圖4 (b )、( c))。又,當 (E1+E2)為Eu以下時,因照射條件,而產生不產生微結晶 化而阻礙連續生長之問題,及因a-Si薄膜上層之溶解不足 而使粒徑擴大效果變小之問題。 其次’參考圖5(b),說明本發明之半導體薄膜之製造
第10頁
464960 五、發明說明(7) 方法之第2實施形態。 於玻璃基板1上’以PECVD法形成lOOnm.之氮化石夕膜22 做為覆膜,接著,以LPCVD法形成膜厚為75iim之a-Si膜 23。對a-Si膜23以波長248nm脈衝寬(W1、W2)為38ns之KrF 雷射光60照射,此時其Eu為500m J/cm2 (圖5(b))。在此, 於以El = 380mJ/cm2、E2 = 260mJ/cni2、E3 = 200mJ/cm2、 tl=80ns、t2 = 50ns(tl=2.1Wl、t2=1.3W2)之條件照射時, 粗大結晶粒之長軸及短軸方向之粒徑,分別為3. 3以m及i. 4#ηι,於長軸方向與短軸方向皆得到較第1實施形態為大 之粒徑。因此,可以較第1實施形態為寬之掃瞄間距進行 掃瞄照射,而使對於平台動作精度之要求較第1實施形態 更為緩和。 **其次,參考圖5(c),說明本發明之半導體薄膜之製造 方法之第3實施形態。 於玻璃基板1,藉由PECVD法形成膜厚為lOOnm之氧化 矽膜42後,同樣地以PECVD法形成膜厚為50nm之a-Si膜 43。在此,因以PECVD法所形成之a-Si膜43較第1、2實施 形態之a-Si膜含有較多量之氫,故進行30分鐘之400 °C之 回火,而進行a-Si膜33之脫氫處理。對a-Si膜43以波長 248nm照射脈衝寬(Wl)38ns之KrF雷射光70,此時其Eu為 460mJ/cm2(圖 5(c))。將KrF 雷射光70 對a-Si 膜43,以 El = 350mJ/cm2、E2 = 200mJ/cm2、tl=60ns(tl = 1.6Wl)之條件 進行照射時,粗大結晶粒之長軸及短軸方向之粒徑,分別 為2.5/zm及l,2"m。於本實施形態中,使用以PECVD法所
第11頁 五、發明說明(8) 形成之a-Si膜時,亦可得到與第1、2實施形態中相同之粗 大結晶粒。因此,可亦約接近第1實施形態之掃瞄間距進 行掃目苗照射’而平台動作精度亦較習知技術大幅改善。 上說明 而言, 衝雷射 佳之關 上所述 ,藉由 向超過 上以大 ,藉由 亦可使 習知更 以 之經驗 於與脈 點,更 發明教 如 a-Si 膜 長轴方 廣範圍 r又 晶粒’ 求,較 之實施形態,僅介紹3個實 用於本發明之複數脈衝雷射之照射間隔t η, 之寬度之關係,滿足t η S 6 W η之關係為重 係則為滿足Wn S tn S4Wn之關係。 ’藉由本發明之半導體薄膜之製造方法,對 照射滿足前述條件之複數脈衝雷射,而得到 短軸方向2倍之粗大結晶粒,而可於基板 掃瞄=距進行掃瞄照射,可得到高產能。 使用前述條件之脈衝雷射照射而得= 將基板對脈衝雷射移動之平台動 声、,、》 大幅緩和,而可大幅減少平台之製;2。
第12頁 464960 圖式簡單說明 圖1 :表示為本發明之半導體薄膜之製造方法之基本構成 部分之互為前後之脈衝雷射之相互關係之脈衝形狀圖。 圖2 :表示使用本發明之半導體薄膜之製造方法之脈衝雷 射之照射裝置及被照射物樣子之模式構成圖。 圖3(a)、圖3(b)、圖3(c):表示藉由本發明之半導體薄膜 之製造方法所得之半導體薄膜之結晶狀態之半導體薄膜之 擴大頂視圖。 圖4(a)、圖4(b)、圖4(c):本發明之半導體薄膜之製造方 法中,將藉由脈衝雷射照射所得之粗大結晶粒之長軸方向 之粒徑與脈衝雷射間隔之關係,以脈衝雷射之能量密度做 為參數表示之圖表。 圖5(a)、圖5(b)、圖5(c):表示使用本發明之半導體薄膜 之製造方法之脈衝雷射之被照射物之樣子之剖面圖。 符號說明 I 玻璃基板 2、 42 氧化矽膜 3、 23、43 a-Si 膜 4 ' 5 光源 6 控制裝置 7 光學系 8 反應室 9、1 9 微結晶化區域 10 粗大結晶粒 II 長軸方向
第13頁 4-6496 Ο 圖式簡單說明 12 短軸方向 13 掃描間距 1 6 結晶粒領城 2 0 結晶粒 22 氮化矽膜 50 XeCl雷射光 60、70 KrF雷射光 80 光束前半部 81 光朿後半部
Claims (1)
- 464960六、申請專利範圍 _ 1· -種半導體薄臈之製造方法 膜以複數脈衝雷射連續於相同處昭:斜非早結晶H 由該非單結晶半導之能量密度,不超:; 能量密度臨界值。、之脈衝雷射之照射而微結晶化之 2.如申請專利範圍第!項之半導體其 中,^數脈衝雷射之各脈衝雷射之能量密度較該#單 結晶半導體薄膜藉由脈衝雷射照射而微結晶:之能量密度 臨界值為低,而於連續之該複數脈 L 衡雷 ;中=衝雷射之能量密度大於後脈能量密 =界:複數脈衝雷射之全部.能量密度之和超過該能量密度 圍第2項之半導體薄膜之製造方法,其 β 之照射間隔,為該前脈衝雷射之半值 寬之脈衝寬之6倍以下。 4·如申請專利範圍第2項之半導體薄膜之製造方法,其 =,該前後脈衝雷射之照射間㈤,為肖前脈冑雷射之半值 寬之脈衝寬之〗倍以上4倍以下。 · 5 *如申明專利範圍第1至4項中任一項之半導體薄膜之製造 =法,其中,藉由該複數脈衝雷射之照射,令該多結晶或 單結晶半導體薄膜中,長軸方向之結晶粒長度超過短軸方 向之結晶粒長度之2倍,且該結晶教包含於該短韩方向成 列並排之組織。 6.如申請專利範園第5項之半導體薄膜之製造方法,其 第15頁 4 3 6 0 六、申請專利範圍 中,對該非單結晶半導體薄膜以該複數脈衝雷射連續於相 同處所進行之照射,係為於該非單結晶半導體薄膜上,依 結晶粒之長度以下之間距,沿該長軸方向移動,而重覆進 行之掃瞄照射。 7. 如申請專利範圍第5項之半導體薄膜之製造方法,其 中,該非單結晶半導體薄膜可藉由減壓化學氣相生長 (LPCVD)法、電漿化學氣相生長(PECVD)法、濺鍍法之任一 方法而形成。 8. 如申請專利範圍第5項之半導體薄膜之製造方法,其 中,該多結晶或單結晶半導體薄膜可形成於玻璃基板上。第16頁
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Also Published As
Publication number | Publication date |
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US6800541B2 (en) | 2004-10-05 |
JP2001035806A (ja) | 2001-02-09 |
US20030032222A1 (en) | 2003-02-13 |
KR20010029978A (ko) | 2001-04-16 |
KR100364944B1 (ko) | 2002-12-16 |
JP3422290B2 (ja) | 2003-06-30 |
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