TW459300B - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

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TW459300B
TW459300B TW089112611A TW89112611A TW459300B TW 459300 B TW459300 B TW 459300B TW 089112611 A TW089112611 A TW 089112611A TW 89112611 A TW89112611 A TW 89112611A TW 459300 B TW459300 B TW 459300B
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insulating layer
layer
item
metal pattern
patent application
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TW089112611A
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Jin-Hyun Kim
In-Haeng Lee
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Hyundai Electronics Ind
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31625—Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Description

^ 459300 五、發明說明（1) 發明領域 本發明係關於一種製造半導體裝置的方法，比較特別是 關於一種改良方法，可製造一種整合一絕緣層為防止金屬 圖樣之間橋接的半導體裝置。 - ' 先前技藝之敘述 近年來，當動態隨機截取記憶體（DRAM)的整合，越來越 at夠達到較尚的層次時，一個單元的大小也傾向於降低的 更多。然而，為了改善對軟性錯誤的容忍度，電容必須確 保一矽基底上的一特定區域。 一種具有三度空間結構的圓柱體電容，引進解決此問 題。 圖1A和1B顯示一種先前技藝的方法，可製造一種半導體 裝置’其在一矽基底2的一單元區域24，有數個圓柱體電 谷。一開始，在矽基底2的單元區域24上，形成一多重數 目的閘極6和多數的接合處4。之後，圓柱體電容分別經由 多數的插座10，電連接到接合處4。每一個圓柱體電容有 一下方電極12，在下方電極12附近形成一側面壁14，在下 方電極12的上方形成一電介質層16，而在該電介質層16的 上方形成一上方電極18 ^接著下一個步驟中，在矽基底2 上圓柱體電容的上方電極18和週邊區域26的上方，沉積一 侧磷碎酸鹽玻璃（BPSG)層20。一般而言，BPSG層20是位於 金屬圖樣間的夾層作為絕緣層。將BpsG層2〇來回流動，以 平面化所在的表面。然後，週邊區域26的BpsG層2〇上方形 成一光阻層22，如圖1A所示。
丄r'4 59 3 U Ο 五、發明說明（2) '^ 為了要使單元區域24和週邊區域26之間的一階梯輪廟γ 平整，必須將BPSG層20的一部份27，蝕回至一理想的厚、 度。在圖1 A中，該理想厚度是以一虛線來代表。 週邊區域2 6的BPSG層20上方，形成一多晶矽插座28。最 後，在已平面化的BPSG層20上方形成一冗長的字元線3〇y 並一直延伸至多晶矽插座2 8。 上述製造該半導體裝置的方法，在平面化的製程中引發 幾個缺點。例如：要蝕刻BPSG層20的部份27，但不曝露出 上位電極18的一邊緣部份32是困難的。因為在邊緣部份32 處BPSG層20的厚度，比在插座1 〇上方部份27的厚度要小一 些，所以在上位電極18的邊緣部份32和該冗長的字元^3〇 之，，經常發生一橋接。繼而降低了半導體裝置的整個功 能品質。 圖示之簡述 本發明上述及其他的目的和特性’將在下面的較佳具體 實施例，及配合相關的圖示解釋，明顯地表現出來，^ 圖示有： μ 圖1Α和1Β顯示的縱向截面繪示圖，呈現製造整合多重數 目圓拄體電容的半導體裝置之先前技藝； 圖2Α至2F提供的縱向截面繪示圖，呈現根據本發明的一 第一較佳具體實施例’製造半導體裝置的方法；以及. 圖3Α至3D呈現的縱向截面繪示圖，是根據本發明的一第 二較佳具體實施例，製造半導體裝置的方法。 ’ 發明簡述
Λ593 Ο Ο 五、發明說明（3) 本發明的目的在於提供一種製造爭導體裝置的方法 防止金屬圖樣之間的橋接。 其 根據本發明的一方面，提供一耩製造半導體的方法 步驟包括：製備一半導體基底，分成/週邊區域-和一」，… 區域，並在上面形成一第一金屬圖檬，其中週邊和單元兩 區域彼此相鄰；至少在該第一金屬圖樣的一部份上覆蓋一 第一絕緣層；在該第一絕緣層上以及該單元區域的剩餘部 份和週邊區域上，形成一第二絕緣詹’其中該第一絕緣層 的蝕刻速率比該第二絕緣層的飯刻速率要慢一點；將該第 = 3化至一事先決定的厚度’以平整該單元區域 和該週邊&域之間的—階梯輪靡.、 域1 二絕緣声上，#+ 也 re ，从及在已平面化的該第 7- 圖％，如此以防止該第-和 弟一金屬圖樣間的橋接。 根據本發明的另一方面，所提 ^ ^ ^ 邊區迠— lS-广，丄、 吟的一 +導體裝置有一週 導體F置包括\品二其上形成〜三度空間的電容°該半 樣後空間電容的-上方電極；-金屬圖 =和ίΐ: 形成一第一絶緣以及在該第-絕 層之間形成一第二絕緣層，④中該第- 該第二絕緣層的㈣速率要慢-些。 m佳具體1施例之詳細敘述 參考圖2和圖3，顯示根據本發之 造半導體裝置的方法。 月的較佳具體實施例之製 圖2A至2F顯示的縱向截面圖， 具體實施例，製造一半導體裳置 是根據本發明一第一較 的依循步驟。 佳
459300 五、發明說明（4) 製造該半導體裝置的步驟，開始於製作一半導體基底 一 110，分成一週邊區域126和一單元區域124，其上形成了 一多重數目的圓柱體電容，如圖2A所示。每一個圓柱體電 容包括一下方電極112，該下方電極112附近形成一侧面壁 1 1 4，該下方電極1 1 2和該側面壁1 1 4的上方形成一電介質— 層116 ’以及該電介質層116上方的一上方電極118。每一 圓柱體電容經由一接合處1 〇 4連接到一閘極1 〇 6，以儲存電 .荷和放電。 接下來的步驟中，在圓柱體電容的上方電極118上，利 用化學蒸艘法（CVD)形成一第一絕緣層140，如圖2B所示。 根據本發明之第一較佳具體實施例，該第一絕緣層丨4 〇最 好由一物質像是原矽酸四乙基酯（TE〇s)，一溫度媒介的氧 化物（ΜΤ0) ’和類似物質組成。該第一絕緣層14〇的蝕刻速 率要出其上面物質的蝕刻速率慢—些。第一較佳具體實施 命J中’該第一 '絕緣層14〇的厚度大約在5〇埃到丨，5〇〇埃的範 圍。 下二個步驟中’在該第一絕緣層1 40和該矽基底1 10的週 邊區域1 2 6上’沉.積—第二絕緣層1 2 0，也就是硼磷矽酸鹽 玻璃（BPSG)沉積的過程最好是在大約攝氏35〇度至6〇〇度 的'里度下進订。沉積步驟之後，將該第二絕緣層1 2 0置於 :約攝氏600度至1，_度的火爐内，纟回流動以進行加熱 處理。加熱處理的舟_ 旧步驟’可以快速熱步驟（RTP)執行。該 第二絕緣層120的展, 厚度最好大約是3，0 0 0埃到1 5, 0 0 0埃。然 後利用一溶液，將哕钕 + t ^ — τ邊第二絕緣層1 2 0濕蝕刻至一事先決定
O:\64\649S5.PTD
459300 五、發明說明（5) ^厚ί 到二平面化的第二絕緣層120，如圖2C所' 蝕刻遠浴液可以心㈣混合製備，麵刻過程也可以是乾 圖=步驟中，在該週邊區域126上形成一溝渠142，如 一之後，將-絕緣物質144填入該溝渠142内如圖冗所 7\\ 〇 ，後，在該第二絕緣層120和該絕緣物質144上，形成一 ^屬層’而且該金屬層印上一事先決定的架構，以得到如 几長字70線似一有圖樣的金屬層i 4 6。 和先則技藝中製造半導體裝置的方法比較，該第一較佳 具體實施例能夠將該第二絕緣層平面化至一理想的平整 度，而不會在上方電極11 8的邊緣部份丨5 〇和冗長的字元線 146之間產生橋接’這是由於形成的第一絕緣層Η。，並且 其钱刻速率比在上方電極11 8上形成的第二絕緣層之蝕刻 速率要慢而完成的。 θ 或者是圖3 Α至3 D ’顯示根據本發明一第二較佳具體實施 例中，製造半導體裝置的縱向截面靖示圖β該第^較佳具 體實施例中，圖3 Α製備半導體基底2 1 〇的步驟，和圖2 Α顯 示的第一較佳具體實施例步驟很類似。 接下來的步驟中，以控制一BPSG層220的沉積狀況，形 成一未摻雜的石夕玻璃（USG)層240。也就是在一預設時間 内，形成的該BPSG層220為防止硼（Β)和磷（Ρ)反應氣體流 入，並控制輪送皮帶的速度’如圖3Β所示。如果第二絕緣
O:\64\64965.PTD 第 10 頁 159300 五、發明說明（6) 層2 2 0的厚度大約是3,00 0埃到15,〇〇〇埃，那麼該USG層24『 的厚度最好是大約5 0埃到I，5 0 0埃。 之後，圖3C和3D顯示的該第二較佳具體實施例中其他步 驟，和圖2D至2F顯示該第一較佳具體實施例的步驟相類 似。 -— S亥第二較佳具體實施例中，既然在形成該BpSG層22〇的 . 同時，也形成該USG層240，就不需要額外的製程來沉積— 第一絕緣層1 4 0，像是相較於該第一較佳具體實施例的— MTO。 雖然僅以相關特定的較佳具體實施例來敘述，本發明可 以做其他的修正和變化，而沒有偏離下列專利申請範圍中 所述之本發明的精神和範圍。
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Claims (1)

  1. 459300 六、申請專利範圍 1_ 一種製造半導體裝置的方法，該方法包括下列步驟：-製備一半導體基底，分成一週邊區域和一單元區域， 該單元區域上並提供一第一金屬圖樣，其中該區域彼此相 鄰， 至少在該第一金屬圖樣的一部份上覆蓋—第一絕緣— 層； 於該第一絕緣層上以及該單元區域的剩餘部份和該週 邊區域上，形成一第二絕緣層，其中該第—絕緣層的姓刻 速率比該第二絕緣層的蝕刻速率要慢一些； 將該第二絕緣層平面化至一事先決定的厚度，以平整 該單元區域和該週邊區域之間的一階梯輪廓；以及 在已平面化的該第二絕緣層上，形成一第二金屬圖 樣，如此以防止該第一和第二金屬圖樣間的橋接。 2.如申請專利範圍第1項之方法，其中部份的該第一絕 緣層，是形成於該第一金屬圖樣的一邊緣。 3，如申請專利範圍第2項之方法’其中部份的該第—絕 緣層，延伸至該單元區域的整個上表面β 4_如申請專利範圍第1項之方法，其中該第一金屬圖樣 是一電容的一上方電極，而一第二金屬圖樣是—冗長的字 元線。 、 5.如申請專利範圍第4項之方法，其中該第二絕緣層是 由一棚磷矽鹽玻璃（BPSG)所組成。 6 _如申請專利範圍第5項之方法，其中該第一絕緣層是 從一組包括一原矽酸四乙基酯（Τ Ε 0 S )和一溫度媒介氧化物
    O:\64\64965.PTD 第12頁 4 593 00 六、申請專利範圍 (MT0)的物質中選取而組成。 一 7. 如申請專利範圍第5項之方法’其中形成該第二絕緣 層的步驟還包括，在大約攝氏600度至1，000度下來回流動 該BPSG，利用一快速熱製程進行加熱處理。 8. 如申請專利範圍第5項之方法’其中該BPSG層的厚度一 大約在3, 0 00埃到1 5, 00 0埃的範圍。 9. 如申請專利範圍第5項之方法，其中該BPSG層内百分 之w t的硼（B)和百分之w的磷（P )約為2到6。 I 0 ·如申請專利範圍第6項之方法，其中該第一絕緣層的 厚度大約在50埃到1, 500埃的範圍。 II ·如申請專利範圍第1項之方法，其中該第一絕緣層是 利用從該BPSG層的一底部萃取出的B和P雜質所組成。 1 2 ·如申請專利範圍第1 〇項之方法，其中該萃取層是在 預設的時間内’以控制該BPSG層的沉積狀況而得到。 13. 如申請專利範圍第11項之方法，其中該bpsg層中該 底部的厚度大約在5 0埃到1，5 0 0埃的範圍。 14. 如申請專利範圍第11項之方法，其中該BPSG層的沉 積溫度大約是攝氏350度至6 0 0度。 1 5 ·如申請專利範圍第1項之方法，其中該蝕刻是以濕蝕 刻方式進行。 1 6，如申請專利範圍第1項之方法，其中該蝕刻是以乾蝕 刻方式進行。 17. —種半導體裝置，具有一週邊區域和一單元區域， 該單元區域上形成一三度空間電容’該半導體裝置包括：
    O:\64\64965.PTD 第13頁 λ 5 9 3 0 0 六、申請專利範圍 該三度空間電容的一上方電極； _ 一金屬圖樣層； 在該上方電極上形成的一第一絕緣層；以及 在該第一絕緣層和該金屬圖樣層中間形成的一第二絕 緣層，其中該第一絕緣層的蝕刻速率比該第二絕緣層的蛀 刻速率要慢一些。 18. 如申請專利範圍第17項之半導體裝置，其中該三度 空間的電容是一圓柱體的形狀。 19. 如申請專利範圍第18項之半導體裝置，其中該金屬 圖樣層是一冗長的字元線。 2 0.如申請專利範圍第1 9項之半導體裝置，其中該第二 絕緣層是由一 B P S G組成，以及該第一絕緣層是由一 Μ Τ 0組 成。
    O:\64\64965.PTD 第14頁
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