TW457555B - Surface passivation using silicon oxynitride - Google Patents

Surface passivation using silicon oxynitride Download PDF

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Publication number
TW457555B
TW457555B TW088103302A TW88103302A TW457555B TW 457555 B TW457555 B TW 457555B TW 088103302 A TW088103302 A TW 088103302A TW 88103302 A TW88103302 A TW 88103302A TW 457555 B TW457555 B TW 457555B
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layer
hydrogen
passivation
surface state
silicon
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TW088103302A
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Donna Rizzone Cote
William Joseph Cote
Son Van Nguyen
Markus Kirchhoff
Max G Levy
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Siemens Ag
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Description

总§7555 A7 B7 一- ----------—......... ..... 五、發明说明（j ) 發明之領域 本發明係有關於裝置及裝置製造，並且更特別地是有關 於具有促成表面狀態鈍化用之層的裝匱及製造該裝置的製 程。 發明之背景 在裝置製造中，絕緣性、半導體性與導電性等諸層係被 製作並刻劃於一基板上以形成諸如.電晶體、電容以及電阻 等裝置結構。這些裝置將被相互連結以獲得所欲之電功能 。各裝置層的製作及刻割係使用諸如氧化、植入、沈積' 矽的磊晶成長、微影及蝕刻等傳統製造技術而獲得。該技 術係說明於 S.M.Sze 所著的 “VLSI Technology" ,2nd ed., New York, McGiaw-Hi丨1, 19 88 »在此倂入本案以爲參考 資料。 經濟部中央標準局J工消費合作社印製 (請先閱讀背面之注意事一.：填寫本頁) 傳統製造技術將使裝置中的諸層產生缺陷及損傷•例如 ，在半導體界面之化學鍵的損傷將形成表面或界面狀態的 懸空鍵。表面狀態將促成電子電洞對的再結合。再結合係 爲電子電洞對相消的現象。特別是發生於諸如隔離周圍及 閘極氧化物等重要的裝置界面上的在結合將產生漏電流·» 漏電流將改變閘極啓始電壓、資料遲滯及裝置的待機電源 消耗。因此，界面狀態對於裝置功能有負面影W。 表面狀態係藉由提供氫原子以鈍化懸空鍵而修復。典型 地在大約400 -600 °C的含氫氣氛中之高溫退火係用以供應 氫而鈍化懸空鍵。鈍化退火通常於裝置製:造程序後段執行
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J 本紙張尺度%用中國國家標準（CNS ) Μ規格（210X297公釐）‘ ' ’':…r ν' 457555 A7 B7 五、發明説明u ) ，諸如包含金屬化或互連層等諸層形成後。此舉將減少修 復先前製程所形成之懸空鍵所需的鈍化退火數。減少鈍化 退火數將節省製程成本。 然而，目前的互連組織及裝置結構易於阻礙氫原子到達 再結合位置以鈍化懸空鍵的能力。故將減少鈍化退火的效 益及效率。例如，以低壓化學氣相沈積法（LPCVD )所沈積之 作爲移動離子及過度金屬阻障的氮.化矽將阻止氫擴散。該 LPCVD氮化矽膜將阻止氫滲入下層，而鈍化存在於該層中 的表面狀態》在鎢柱結構中，鎢將壓制氫，而產生類似於 氮化矽層的效果。鈍化退火的效益將進一步減少，因爲氮 氣通常係用以稀釋氫（形成氣體），以減少氫氣的爆炸性。 如上述，有效地鈍化爲裝匱製造技術所引起的表面狀態 係爲所需。 發明之槪要 經濟部中央標隼局員工消费合作社印裝 (诗先閏讀背面之注意事¾也寫本頁) 本發明係有關於裝置製造。如本技藝所熟知，傳統裝置 製造技術將損傷化學鍵，而於半導體界面形成表面狀態》 這些表面狀態係藉由在氫氣退火期間供應氫原子而被修復 或鈍化》然而，目前的裝置結構易於使氫無法到達及鈍化 表面狀態》 爲克服目前裝置結構所存在的鈍化問題，一用於製造裝 置的製程係被掲示》該製程包含製造促成表面狀態鈍化之 裝置結構的步驟*該裝置結構包含氮氧化物層。在一實施 例中，該氮氧化物層係以電漿輔肋化學氣孭許積法（PECVD) Ί !
• I -4- ' 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 457555 Α7 Β7 五、發明説明（3 ) 形成。 圖式之簡略說明 第1圖係說明具有隔離之簡化的傳統電晶體裝置結構： 第2圖係說明具有鈍化層之簡化的電晶體裝置結構： 第3圖係說明具有爲複合閘極之部分的鈍化.層之簡化的 電晶體裝置結構； 第4圖係表示氮氧化物之折射係數與蝕刻選擇性間的關 係： 第5A-B圖係表示以ΑΜΕ及Nove 1 lus加工系統所製作的 氮氧化物膜周邊漏電： 第6圖係爲比較具有傳統氮化物膜之裝置與具有富氫 < Η - R )氮化物膜之裝置的漏電流的圖式： 第7圖係爲比較傳統低壓化學氣相沈積氮化膜與H-R氮 化物膜特徵的圖式：以及 第8圖示鍵結於氫之矽百分比對ND周邊漏電間的關係。 發明詳細說明 經濟部中央標準局員工消費合作社印掣 (請先閲讀背面之注意事功填寫本頁) 本發明係有關於裝置製造期間所形成之表面狀態的鈍化 «爲用於作爲舉例的目的，本發明將以動態隨機存取記憶 體（DRAM )單元做說明。然而，本發明係明顯地更爲廣泛並 延伸至諸如雙載體裝置、BiCMOS、薄膜電晶體、異質接面 裝置及相似者等裝置之製造。 在第1圖中，其係表示形成於諸如半導體晶圓等基板100 的DRAM單元101。該晶圓包含諸如以Czochralski技術所 形成的矽β晶圓的主表面並不重要，而諸如,（l〇Q )(11〇)或
Λ I 本纸張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐）
4 5 7 5 5S A7 B7 五、發明説明（4* ) (m)等任何適當的取向皆可使用。該晶圓係典型地具有 (100)取向，因爲該晶圓具有低表面狀態及高載體移動而常 被使用B其他諸如鍺、砷化鎵及ΠΙ-ν族化合物等其他半 導體晶圓亦可使用《此外，包括複數材料層之晶圓亦可使 用。這些基板包含諸如形成於另一種單晶材料上的一單晶 材料（例如，矽茌藍寶石上（SOS ))，或著在非晶質材料層 上再結晶的非晶質或多晶材料C例如，矽在絕緣體上（S0J) )·其係得以以諸如硼'磷、砷或銻等雜質原子大量或微 量植入，以獲得所欲的電性。 如所示，該DRAM單元包含用以儲存代表資料位元之電荷 的電容器105。在所舉例的實施例中，該電容器係爲彤成 於基板中的溝渠電容器》諸如堆疊電容器等其他形式的電 容器亦可用於儲存電荷•包含閘極110、源極120及汲極 130的電晶體106係電連接至電容器。一淺溝渠隔離區140 係被設置以將DRAM單元與陣列中的其他單元或裝置隔離
D 經濟部中夬標準局貝工消費合作社印製 (诗先閱讀背面之注^唞寫本頁) 複數個記憶胞係成橫豎排列以形成DRAM陣列。橫列係稱 爲字元線而縱欄係稱爲位元線。通常，源極120係連接至 位元線，而閘極110係連接至或代表DRAM陣列的字元線。 藉由加諸適當的電壓於位元線及字元線，該電晶體係被開 啓而連接至電容器。 電晶體的閘極區典型地包含形成於閛極氧化物Π1上的 多晶矽層1 1 2 ·在部份應用中，一矽化物層1 1 4係甩以形
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__________________ I 本紙張尺度適用中國國家標牟（CNS > A4現格（210X297公釐} 4 5 7 5 b ΐ： A 7 B7 五、發明説明U ) 成一複合閘極堆疊。包含矽化鉬（MoSix)、矽化鉅（TaSix) ，矽化鎢（WS ί X )、矽化鈦（T i S i X )或矽化鈷（CoS i X )的矽化 物皆被用以形成層11 4 β此外’鋁或諸如鎢與鉬等耐火金 屬係單獨被使用或著結合矽化物或多晶矽使用。複合閘極 係爲所欲，因使用其可減少閘極區的片電阻’而減少沿其 傳遞之訊號的R-C延遲。 一氮化物覆蓋1】6係以低壓化學.氣相沈積法（LPCVD )沈 積於閘極上。該覆蓋係作爲後序製程用的蝕刻阻絕，諸如 形成無邊際位元線接觸於源極時。一間隔160係沈積於閘 極上，以限制源極與汲極區的向上擴散進入閘極區，其將 減少重叠電容。間隔形成後，一氮化物層1 70係沈積於閛 極邊緣以及源極' 汲極與ST1區上，以提供移動離子阻障 並作爲蝕刻阻絕。一介電層（未示）係形成於裝置結構上 ，以提供導電層間的絕緣（除非接觸係爲所欲），或作爲 保護層以將裝置結構與雜質、水氣及刮傷隔絕。該介電層 包含諸如磷矽酸鹽玻璃（PSG)或硼磷矽酸鹽玻璃（BPSG)等 摻磷二氧化矽· 經濟部中央橾準局員工消費合作社印製 (請先閲讀背面之注意事-"$寫本頁) 當然，如第1圖所示的裝置結構因作爲舉例的目的而被 簡化。例如，使用於DRAM單元中的實際裝置結構包含諸如 井、接觸及局部互連等其他區域。裝置結構之各區域的形 成係爲所熟知，並說明於諸如Kenney等人所著的ABuried Plate Trench Cell For a 64M DRAM , VLSI Tech . Di g( 1992 ) ，在此倂入本案以爲參考資料。 .. 本紙張尺度適用中國國家標隼（CNS ) AMU ( 210X297公釐） 45755 經濟部中央樣準局負工消費合作社印製 Α7 Β7 五、發明説明（6) 在裝置結構諸層製造期間所形成的表面狀態係以“” 號表示。如所示，該表面狀態係位於閘極氧化物及ST1周 圍。這些表面狀態需加以鈍化。氫退火通常係用以鈍化該 表面狀態。在退火期間，氣氛中的氫原子將穿過閛極而達 結構主體。然而，目前大部份的裝置結構皆以LPCVD氮化 矽層覆蓋。如上述，該氮化物層將阻礙氫原子穿透其以鈍 化表面狀態。 爲克服由使用傳統LPCVD氮化物層所引起的問題，一鈍 化層係被設置以完成在製造期間所產生之表面狀態的修復 。該鈍化結構包含混入裝置的一富氫（H-R)氮化矽層。如本 技藝所熟知1傅統的LPCVD氮化矽層包含大約3-5«的氫原 子（本掲示中所有的組成百分比皆以原子％表示）> 詳閱 Habraken 等人所著的 Silicon Nitride and Oxynitride Films, Mat. Sci. and Eng.， R12 No.3(July 1994)，以 及 C h o w 等人所著的 H y d r o g e n C ο n t e n t o f a V a r i e t y o f Plasma-DepositedSiliconNitrides, J. Appl. Phys., Vol 53, No. 8(August 1 982 )，在此倂入本案以爲參考資料。 在此所使用的"富氫"意指氫比例大於傳統LPCVD氮化矽 層。實驗顯示使用H-R氮化矽層可減少接面漏電流，亦即 成功的表面狀態鈍化。 H-R氮化矽層如何促成表面狀態鈍化的機構並不得而知 a然而，其確信H-R氮化物層係作爲氫原子源或允許氫穿 過的結構或二考的結合》所增加的氫百分比將增加H-R氮 本紙張尺度適用中國國家標準（CNS ) A4C格（2I0X 297公釐） (請先閲讀背面之注意事項 哄寫本頁) 、ye 4 5 7:: 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（7 ) 化矽層中的氫原子量，而形成氫原子振散源以鈍化表面狀 態。此外’由於氫百分比增加，故氮化物層密度將減少。 密度減少將使氫原子明顯地滲透氮化物層，並進入表面狀 態鈍化用的裝置結構· 第2圖係表示諸如具有H-R矽層之DRAM單元中所使用的 —簡化裝置結構200。如所示^該11-1?氮化矽層係混入裝 置結構，以做爲裝置互連界面的阻.障或襯墊層260。裝置 結構200包含一閘極210、一汲極220、~源極230及STI 區240。閘極210包含一多晶矽層212，一諸如WSix的矽 化物層及一氮化矽覆蓋層218。此外，該裝置結構包含間 隔層250。汲極、源極，閘極、ST1區及間隔係使用傳統 技術形成。 其次，H-R層260係形成於裝置結構上。H-R層係使用傳 統電漿輔助化學氣相沈積法（PECVD)形成*該技術係說明於 Gupta 等人所著的 The Preparation, Properties and Application of Silicon Nitride Thin Films Deposited By Plasraa-Enhanced Chemical Vapor Deposition, Thin SolidFiUs，2(M(1991)，在此倂入本案以爲參考資料。執 行PECVD的溫度通常在大約300 -500 eC間。電子迴旋加速 器共振式化學氣相沈積（ECRCVD)技術係用以形成該H-R層 。ECRCVD技術係說明於Kotecki等人所著的Hydrogen Incorporated In Silicon Nitride Films Deposited By Remote El ect ron-Cyc lot ron-Resonance. Cheraica1 Vapor * I . i -9- :, (請先閱讀背面之注意事通 Ϋ寫本頁)
本紙張尺度適用中國國家標隼（CNS ) A4现格（2〗0 X 297公釐） 厂:: 4 57t A 7 B7 五、發明説明（名）
Deposition, J.AppI. Phys.77(3)(Feb. 1,1995)，在此倂 入本案以爲參考資料。 該H-R層包含較傳統LPCVD氮化矽更高比例的氫。在一 實施例中，氫比例係大於5%並小於或等於3 9¾。超過大約 3 9%的氫會使氮化矽膜性質劣化，諸如其作爲阻障的能力 。氫比例最好在大約1 0 · 3 5 %間|大約1 2 5 %更佳，大約 12-2 5%則更好，而最好爲15-20%。. 如上述，H-R層的PECVD係於大約300 -5 0(TC間的溫度執 行。在較低溫下形成該Η - R層係爲有利的。例如，Η - R層 的氮原子將於後續執行溫度較PECVD溫度爲高的製程期間 ，擴散通過裝置結構。在部份案例中，後續的較高溫製.程 係足以鈍化表面狀態，而無須鈍化退火。經鈍化的表面狀 態係以“ + "表示。 鈍化退火可用以鈍化表面狀態。傳統鈍化退火通常係於 大約400 °C的氫氣或氫氣/氮氣（形成氣體）氣氛中執行 大約30- 60分鐘。然而，使用H-R層將提供即時的氫源， 經濟部中央橾準局I工消費合作社印製 {請先閲讀背面之注$項If A寫本頁) 因而減少或消除對於含氫退火的需求，以有效地鈍化表而 狀態。 參考第3圖，一 H-R層315係形成部份的閘極結構，以鈍 化表面狀態。如所示，該H-R層315係形成於複合閘極310 的矽化物層314與氮化矽覆蓋層318間》H-R層315可單獨 使用或與如第2圖所述之H-R層260共用。額外的H-R層或 諸層可被形成於裝置中，以增強表面狀態的鈍化。 · 1 ·-...... .
m I -ίο- ' ! 本紙張尺度適用中國國家榡卒（CNS ) A4規格（210X297公釐） ί 4575; A7 B7 五、發明説明（q ) 在該H-R氮化矽層沈積於諸如鎢柱結構或矽化鎢複合閘 極等鎢層的應用中，一黏著性改良層係爲所需。該黏著性 改良層因氮化物通常無法緊密地黏著於鎢而爲所需。爲改 良鎢與氮化物間的黏著性，一薄矽層係於H-R層沈積前形 成於錫上？ 在另一實施例中，但氮氧化物係用於取代H-R氮化矽’ 以做爲諸如阻障層等鈍化結構。該氮氧化物係以諸如電漿 輔助化學氣相沈積法（PECVD)沈積》以PECVD沈積氮氧化物 係說明於Habraken與Kuiper等人所著的“ Silicon Nitride and Oxynitride Films ， Material Science and E n g i n e e r i n g，R 1 2 N o . 3，J u 1 y 1 9 9 4 , p p . 1 2 3 1 7 5，在此 併入本案以爲參考資料。諸如矽烷（SiH4)、氨氣（NH3)和/ 或氮氣（N2)及氧化亞氮（N20)等預製體將引入反應器中以 形成氮氧化物層，該氮氧化物的沈積.條件係爲諸如大約300 - 1000W的功率，大約2-10 Torr的壓力及大約300,500 t 的溫度。該氮氧化物的沈積條件最好爲諸如大約300 - 800W 的功率、大約2-6 Tor r的壓力及大約350 -480 °C的溫度· 經濟部中央標準局負工消費合作社印裝 (請先閱讀背面之注意事項〖<寫本頁) 在一實施例中* PECVD係於諸如Applied Materials公 司所製造的ΑΜΕ 5000單晶圓設備中執行*或著諸如 Novellus System 公司所製造的 Novellus Concept-Ι 多站 晶圓設備中執行。該單晶圓與多站晶圓設備用的典型製程 條件係表示於表1中6當然h些參數可爲特定的設備或製 程而做最佳化。 -11- i 本紙张尺度適用中國國家標隼（CNS )八4現格（210X29"?公釐） 45/555 Α7 Β7 五、發明説明（丨ο ) 表1實驗 單 晶圓加工製程條件 含 2 ft矽烷的氮氣流量 :3000sccra NH3流量：15 sccra N20流量：10-40 sccra(將改變氧氣含量） 流量：1050-1020 sccra n2 +n2o總流量定値爲 1060 seem 功 率：3 4 0 w a t t s 溫 度：4 8 0。。 間 隔：3 50 - 380 rai Is 壓 力：5 . 7 5 t 0 r r (請先閱讀背面之注意^5.-it·寫本頁) 多站加工 製程條件 矽院流量 • 0.15 s1m nh3流量 :1 . 8 s 1 ra N2o流量 :0 2-2 s 1m(將改變氧氣含量） N2流量： 11.8-10 si !L n2+n2o總流量定値爲 12 ε 1 ra 功率：0 . 7 Itw(HF)及 0.10kw(LF ) 溫度：4 0 0 t 壓力：5 . 7 5 t 〇 r r 經濟部中央標隼局貝工消费合作社印製 此外，該氣氮化物係以LPCVD沈積。LPCVD氮氧化物的 典型製程條件係表示於表2中。當然這些參數可爲特定的 加工或製程而做最佳化。 表2 _ 典型製程條件 -LPCVD氮氧化物 二氯矽烷的流 量：135 seem Ν Η 3流量：9〇 seem Ν 2流量· 4 5 〇 seem 溫度：77 0 °C 壓力：2 50 ni t 0 r r -12- 本紙張又度適用中國國家標準（CNS ) A4規格（公釐） 5 7 5 5 5 A7 B7 五、發明説明（丨丨） 形成保護層後，將裝置結構退火以鈍化表面狀態。該退 火係於諸如含氫氣氛中進行*此外’該退火可被整合爲部 份的後續製程。 使用該氮氧化物層作爲阻障襯墊時將產生極低的N與P 擴散之可再現性STI接合接面漏電流°參考第5Α·Β圖，其 係由單晶圓及多站晶圓加工所製作之氮氧化物的STI接合 接面漏電流（意指NL，ND與PD周邊漏電流）與折射係數 的關係圖。如所示，漏電流係相當低’由單站加工所形成 的氮氧化物係低於1.4 namps而由多站加工所形成的氧氛 化物係低於0.9 namps 。此外，使用氮氧化物作爲阻障保 護層將使同一批或不同批的晶圓間的漏電流分佈相當均.勻 b 經濟部中央標準局貝工消费合作杜印製 (讀先閲讀背面之注意事名填寫本頁} 如第8圖所示，其已發現吸附於H-R氮化物與氮氧化物 膜中之矽<SiH或SiH/<SiH + NH)的氫比例與接面漏電流的 關係。其已發現較低比例之氫對矽的吸附將降低接面漏電 流，而較高的比例將增加接面漏電流。氫吸附於矽的比例 與接面漏電流間的關係指出較低比例的S i Η或 SiH/(SiH + NH)將改良鈍化結構的鈍化特性。其確信較低比 例將使氫較易穿透該鈍化結構，因而允許氣氛中的氫穿過 並鈍化表面狀態β此外，其確信較低比例的S i Η將降低膜 的電子捕捉，因而改良其漏電特性《詳閱Smith所著之“ Controlling the plasma chemistry of silicon nitride and oxide deposition from silane ’ J . V a c . S c i . Tech.,. -13- ' 本紙張尺度適用中國國家標準（CNS ) A4規格（210>〇97公釐） ~~' 457555 Α7 Β7 五、發明説明（丨l )
An(4)Jul/Aug, 1 993 P1 843，在此併入本案以爲參考資 料"所以，該鈍化結構將形成具有較高或更均勻遲滯時間 的記憶晶片。在一實施例中，S i Η的比例大約爲0 - 3 9 %，最 好爲大約3 - 2(Η，而3 - 8¾則更佳。 在部份應用中，該阻障層係作爲蝕刻阻絕，諸如用於形 成無邊際接觸《在該應用中|諸如硼磷矽酸鹽玻璃（BPSG) 或其他氧化物等中間介電質對氧氮.化物的選擇性或蝕刻速 率比例應夠高，而使該氮氧化物可作爲蝕刻阻絕。第4圖 係繪製使用氟碳化學物質之氮氧化膜對氧化物的選擇性》 線41代表在多站晶圓加工中所形成的氮氧化物，而線42 代表在單晶圓加工中所形成的氮氧化物。對多站晶圓加工 而言，該氮氧化物選擇性範圍係由折射係數1.66時的13:1 至折射係數爲1.9時的24:1。對單晶圓加工而言*該氮氧 化物選擇性範圍係由折射係數1 . 7 1時的1 3 : 1至折射係數 爲1 . 98時的29 : 1。該選擇性係足以使該氮氧化物作爲蝕 刻阻絕。特定應用所選擇的實際選擇性係取決於諸如設計 參數。 經濟部中央標準局員工消费合作社印裝 (請先閲讀背面之注意事¾讲寫本頁) 在ND，PD及NL裝置中量測STI接合接面漏電流的實驗 係使用由具有STI梳狀周邊的擴散盤曲管所組成之巨構'予 以執行。0 . 2um的擴散間距係被提供，且該STI係以閘極 導體覆蓋。該擴散線寬係爲大約0 . 55urn，且該GC梳狀物 係爲大約2 . 5um寬。盤曲管長度係爲大約58400ura，而形 成具有32〗20umz之面積的周邊長1 16800um。第5A圖係:繪. -14- 本紙張尺度適用中國國家榡车i CNS )八4洗格（210X297公釐} 457555 A7 B7 五、發明説明（15 ) 製爲形成於單晶圓加工中之氧氮化物折射係數之函數的NL * ND及PD漏電流*而第5B圖係繪製爲形成於多站加工中 之氧氮化物折射係數之函數的ML，ND及PD漏電流。如所 示’具有1.7-1.9折射係數之形成於單晶圓加工中之氧氮 化物的裝置的漏電流係小於1 . 5 namp，而具有1 . 66 - 1 . 9 折射係數之形成於多站晶圓加工中之氮氧.化物的裝置的漏 電流係小於1 n a no p。 範例1 經濟部中央標準局貝工消費合作社印製 (請先閲績背面之注意升填寫本頁) 進行一實驗以比較具有H-K氮化矽層之裝置與具有傳統 氮化矽層之裝置的漏電流。具有裝置製造於其上的八組試 件（試件A - Η )係被製備。該八組試件係以二種不同的方法 加工。A - D組試件包含以傳統LPCVD氮化矽層所製造的裝 罝結構，該氮化矽係作爲裝置互連界面的阻障或襯墊層。 在A-D組試件中的裝置結構係類似於第1圖所述者。該傳 統LPCVD氮化矽膜係藉由氨（NH3)與二氯矽烷（SicUH2)在 大約720 °C與200 raTorr的爐中反應而被沈積-NH3對 SiCl2H2的比例係爲大約10 : 1。在E-Η組試件，該LPCVD氮 化物層係以H-R氮化矽層取代，諸如第2圖所述者。該H-R 層係於大約480 °C、5.75 Torr與340 Watts之反應器中以 PECVD法沈積。反應物的製程參數如下：大約3000 seem 之包含2%砂院的氮氣、大約1060sccra的氣氣及大約！5sccra 的 NH;。 二組試件的漏電流係使用SZE所著之Physics - j 15- : 本紙張尺度適用中國國家標準（cns )A4現格（210x297公釐） 4 5 7 5 5 5 A7 B7 五、發明説明（/4 ) S e m i c ο n d u c t 〇 r D e v i c e s，W i 1 e y ( 1 9 6 9 )中所述的標準接面 漏電流測試法，在此倂入本案以爲參考資料。參考第6圖 ’各組試件之ST I接合接面漏電流測試係以任意尺度表示 ° A-D組試件代表具有LPCVD氮化物層的晶圓，而E-Η組試 件代表具有LPCVD H-R氮化物層的晶圓。具有傅統LPCVD 氮化物層的試件明顯地較具有PECVD H-R氮化矽層的試件 有更高的漏電流。 範例2 經濟部中央標準扃貝工消費合作社印焚 (請先閲讀背面之注意事«.填寫本頁) 在第7圖中，PEC VD Η · R氮化物膜（試件A · C)的特性係與 LPCVD氮化物膜做比較。試件A係爲在NovellusConcept-1 係統中以PECVD法所沈積的標準氮化矽。試件b係爲在 Novellus Concept-Ι系統中所沈積的低SiH/UV PECVD氮化 物膜。二試件A與B係於Novellus所要求的相似條件下形 成’如 “ Users guide to 200ram PECVD processing for the Novellus Concept One - 200rara Dielectric System n (爲 Novellus System, Inc.，of San Jose, CA.1 992 )所述，在 此倂入本案以爲參考資料。試件C係爲於Appl i ed Materials of Santa Clara, CA 所製造的 ΑΜΕ 5000 系統中 ，以PECVD法沈積的Η _ R氮化矽膜，其作業條件係與試件1 的PECVD氮化物膜（E-Η)相似。試件D係爲以LPCVD法所沈 積的LPCVD氮化物膜*其作業條件係與試件1的LPCVD膜 (A - D )相似* 形成該膜後，該試件係被加熱至720 °C。，參考第.7圖， -16- :; Λ紙張尺度適用中國國家標隼（CNS > A4規格（2l〇x297公釐） 45755 A7 B7 五、發明説明（π ) 試件的氫含量係於試件被加熱至7 20 °C後量測。由第7圖 觀之，在加熱至720 °C後，PECVD H-R膜的氫含量（試件 A-C )將減少，而LPCVD氮化物膜（試件D)僅微量或無 變化。此舉證明Η - R層係有效地提供氫以鈍化表面狀態。 範例3 進行一實驗以分析SiH/(SiH + NH)與ND周邊漏電流間之 關係’其係使用與第5A-B圖相似的巨模。實驗數據係繪製 成第8圖。由第8圖明顯地看出，較低的氧氮化物膜SiH/ (SiH + NH)濃度將產生較低的ND周邊漏電流。在SiH/(SiH + NH) 濃度大約爲0 - 3 5%時，該ND漏電流的範圍則大約爲〇 . 63 narop 至 1.72 narop ° 經濟部中央榇隼局貞工消費合作社印製 (讀先閲讀背面之注意事ί ‘填寫本頁) 雖然本發明已被特別地揭示並參考不同的實施例做說明 ，但在不違背本發明之範嗦下對本發明所做的改良與改變 將可爲熟習本技藝之人士所辨別。例如，該鈍化層可作爲 一單一膜閫極介電質覆蓋物、包含諸如LPCVD氮化物和/ 或各種氧化物膜等其他膜的一複合閘極覆蓋物、單獨使用 或與其他介電材料結合之作爲最終晶片鈍化材料的閘極導 體間隔膜、移動離子和/或金屬污染物阻絕或一接觸蝕刻 阻絕。因此，本發明之範疇並非取決於參考上述說明，而 係取決於參考所附之申請專利範圍與其所有相當的範_。 主要元件之對照表： 100 基板 101 DRAM 單元 v
I -17- !
I 本纸張尺度速用中國國家標準（CNS ) A4规格（210X 297公釐） 4575 A7 B7 五、發明説明（ A ) 經濟部中央標準局員工消費合作社印製 105 電 容 器 106 電 晶 體 110 閘 極 111 閘 極 氧 化 物 112 多 晶 矽 114 矽 化 物 116 氮 化 物 覆 蓋 120 源 極 130 汲 極 140 淺 溝 渠 隔 魁 離 160 間 隔 170 氛 化 物 層 200 裝 匱 結 構 210 閘 極 212 多 晶 矽 層 214 砂 化 物 層 218 氮 化 矽 覆 蓋 層 230 源 極 240 ST1區 250 間 隔 層 260 -ΜΞ 墊 層 310 複 合 閘 極 314 矽 化 物 層 3 15 Η - R層 318 氮 化 矽 覆 蓋 層 -18- 本紙張尺度適用中國國家椋準< CNS ) A4規格（210X297公釐） P I . . ί I—~、τ~_ —i : (請先閲讀背面之注意事这 填寫本頁) ί

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  1. A8 BS CS D8 4 5 7 5 5 六、申請專利範圍 第88 103302號「利用氮氧化矽之表面鈍化」專利案 (90年6月修正） 六申請專利範圍： 1. 一種在半導體裝置製造中，用於在裝置中易於鈍化表 面狀態的製程，其包含的步驟爲： 形成包含有氮氧化矽層的一鈍化層於裝置中；以及 在氫氣氣氛中加熱該裝置，使該氮氧化矽層含豐富氫 以鈍化表面狀態而減少漏電流。 ---------：---'裝--------訂--------線 ί 一 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度遇用中阀囡家楳準（CNS)A4規格（2〗0 X ；W公《 )
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US11335799B2 (en) 2015-03-26 2022-05-17 Chih-Shu Huang Group-III nitride semiconductor device and method for fabricating the same

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