TW423120B - Semiconductor device having a sub-chip-scale package structure and method for forming same - Google Patents

Semiconductor device having a sub-chip-scale package structure and method for forming same Download PDF

Info

Publication number
TW423120B
TW423120B TW087117327A TW87117327A TW423120B TW 423120 B TW423120 B TW 423120B TW 087117327 A TW087117327 A TW 087117327A TW 87117327 A TW87117327 A TW 87117327A TW 423120 B TW423120 B TW 423120B
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor
semiconductor die
dimension
semiconductor device
Prior art date
Application number
TW087117327A
Other languages
English (en)
Inventor
Iii Leo M Higgins
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW423120B publication Critical patent/TW423120B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

五、發明說明（ι) 先前申請之參考 本申請曾於1997年12月1曰以專利申請號碼08/980 ,783 於美國提出申請。 本發明之範疇 本發明乃關於供一半導體裝置用之封裝半導體裝置及方 法。特別關於晶片級封裝。 發明之背景 晶片級封裝（CSPs)為現代半導體封裝之主要興趣所在。 晶片級封裝係一種相當新的封裝技術，由此技術，半導體 晶粒結合在基質上，如塑膠或陶質基質，基質之大小約與 半導體晶粒大小相同，或者較半導體晶粒稍大。目前對晶 片級封裝之重視主要由於該封裝所提供之降低之足跡，其 可使電子裝置之最後裝配器得以在一固定空間併入最多半 導體裝置而改進其功能性。 依據現代科技，晶片級封裝相當昂貴並有許多可靠性問 題，主要是由於此種封裝之相當複雜性。此外，晶片級封 裝之可靠性與任何其他封裝之半導體裝置一樣，與模具之 尺寸成正比例。如半導體製造者併入更多功能於單一模具 中，模具尺寸之增加無法使科技降低模具之特性尺寸之降 低。當模具尺寸增加，在半導體晶粒及基質間之互連之可 靠度（即第一位準封裝互聯）成為令人懷疑之事。此外，當 封裝之半導體裝置之尺寸增加，（因而增加足跡尺寸），封 裝之半導體裝置及印刷電路板（即第二位準封裝互聯間之 互聯之可靠度成為令人關切之事°此一可靠度問題主要由
D:\Y87\55387.ptd 第5頁
於半導體 係數不同 在互聯上 晶粒之材料，基質及印刷電 之故’此種不同引起在溫度 W起應力。 路板枒料間之熱膨脹 改變及功率週期期間 晶圓Z: 封裝尺寸及保持可靠度問題之外’尚有曰增之 導體晶ίί裝之問題：…圓形式，在單-化之前將半 成本5 g 、。吾人認為晶圓位準封裝可改進可靠度及降低 成。作p降低必須以自動機器處理之個別組件之數目而達 褒，其利用傳統封裝技術之低成本方法以產生晶片級封 恥知'η可靠地將半導體晶粒及封裝基質間之熱膨脹不既 3匕解除，4 ’、 並可保證BGA (球柵陣列）可靠度尚未發展以達成 曰s圓位準封裝。 因f ’此技術中仍然需要改進之晶片級封裝，此種封裝 ’用標準裝配裝置可降低成本，可靠度高及可達成晶圓位 準封裝。 圖說之簡略說明 本發明之較佳了解可經由以下之詳細敘述及配合附圖而 達成，其中： 、 、圖1及2說明本發明之一具體實例，其中一模具與一基質 連接及以不滿之密封層填充； 圖3為本發明—具體實例之平面圖，其中許多模具係同 時封裝在一晶圓位準級上；及 圖4、5及6說明本發明另一旦體實例指出有關半導體晶 粒/基質尺寸之差異。 為了簡單及清楚地說明，圖中之元件並非與實際大小成
D:\Y87\55387.ptd 第6頁 ^2312〇
五、發明說明（3) 比例。例如’有些元件之尺寸已加時大以蛊 比 應 '、丹他元件料 以便清晰。此外’必要時元件參考號碼重複以 ’τ 或類比之元件。 胃出為對 如圖1所示，其中備有—半導體晶粒1 〇，包括— 分11及一中間位準電介質（ILD)層12位於主動部分主動部 其如此構造可使電路接觸墊1 4之形成於模具外周圍’ 近。吾人注意主動部分1 1包括一硅基質，其卜二 附 置以構成主動表面11a’主動表面11a由較高位進八s 裝 (未示出）互聯，此點在此技藝中已久所熟知，在此二 均了解，較高位準金屬層稱為Ml (金屬層丨）至料（金t中 6)。主動部分11之細節已為此技藝人士所了解，對二=層 之完全了解並非十分重要。再分布軌跡16連接至電路 墊1 4以路由内向方向電連接至半導體晶粒之中央部分。如 圖式，再分布軌跡1 6在下部沖擊金屬墊丨5處終止°。:如 鈍化層18沉積在UBM墊15之上，其圖案並留有開口於墊15 上，及焊接沖擊20在UBM墊1 5上分別形成。 依照上述之半導體晶粒1 〇，焊接沖擊2 〇與半導體晶粒】〇 之主動表面成電連接。如本技藝已知者，圖1中之半導體 晶粒被認為是“被沖擊”。被沖擊之模具為倒裝以便會主 動表面向下（如圖示）以便備隨後之接合至一基質。此種焊 接沖擊可根據已知之控制崩潰晶片連接（C4)技術形成，或 以他種沖擊技術形成（即型板印刷或焊接喷射應用）。此 外，切割衔102說明於模具外圍30，此切割將於圖3再予詳
五、發明說明（4) --- f。ILD層12可由任何適合之電介質材料形成，如二氧化 5 化硅，氮氧化硅及聚亞硫胺等。鈍化層1 8之提供係 保護，動表面之用，其形式可為一混合結構包括磷硅玻 璃，氮化硅，聚亞硫胺層等。此外，為澄清圖】中所用之 名稱:焊接沖擊20與UBM墊15組合稱為一電接點，形成於 半導晶粒之表面上。吾人了解此種電接點可為其他形成。 例如’烊接沖擊2 0可由其他金屬沖擊，如金線柱沖擊及無 電極鎳/鍍金沖擊’或導電之聚合物沖擊。電接點亦可為 未沖擊之金屬墊’該未沖擊之金屬墊與含有導電組件之聚 合物層’如鎳粉末或鍍金聚合物墊圈成層以熱固或熱塑薄 膜或膏狀消散其争。如此藝中已知，電連接係由在半導體 晶粒及基質之間加壓力而成以便保留一薄的導體組件層於 未沖擊金屬接觸墊及基質上結合之軌跡之間（即直接晶片 連接（DCA)接合墊）。此種聚合物村料通常稱為各向異性導 電膠合物。此種膠合物亦可與上述之金線柱沖擊及無電極 鎳/金沖擊及相似結構共用。 現在參考圖1及2中之基質50，其中之包括一絕緣層51之 結構最好形成於一有機聚合物上。但絕緣層5 1亦可在一絕 緣陶質材料之上，此點在本技藝中久為人知，以及一含有 絕緣薄膜之金屬層形成於反面表面上及經由通路延伸。根 據本發明之一具體實例，形成絕緣層5 1之有機聚合物可由 聚亞硫胺軟性電路，或纖維玻瑀強力之環氧層組成。有機 加強物如A R A ΜI D纖維亦可用來代替纖維玻璃成分。如圖1 所示’在絕緣層5 1之第一表面上（即頂表面）有許多直接晶
D:\Y87\55387. ptd 苐8頁 4-^3 12〇 五、發明說明（5) 片連接（DC A )結合墊5 2形成’此等墊分別與半導體晶粒i 〇 之焊接沖擊20對齊成一直線。備有一焊接罩53以防止不要 之3 4接塊2 0之物質流在棊質5 〇與半導體晶粒丨〇間連接時 =再流動步驟中出現。如圖式，許多以通路54方式或電鍍 通孔方式之電内聯將DCA接合墊5 2連接至備於基質第二 底表面上之球柵陣列（BGA)接合墊56。在BGA墊56上備有一 第二焊接罩57 ’其上形成球栅陣列（BGA)球58，通常由焊 接1料形成。參考號碼60說明基質之外圍表面。此處所用 之 基質’’一詞表示一機械組件，用來載負半導體晶粒及 其有（即支撐）電連接元件（此處為元件52，54，56及58)以 提供自半導體晶粒至次位準之内聯如經由—印刷電路板之 電連接。 現在參考圖2，其中顯示一完全封裝之半導體裝置1，其 中之基質50與半導體晶粒1〇連接。基質5〇置於半導體1〇之 上 在半導體晶粒1〇及基質之間有一不滿之密封層7〇。 不滿之密封層包括一平邊72，將基質所暴露之半導體晶粒 之主動表面及基質外圍表面60跨接。此平邊72由未滿之密 封層70之材料之濕潤行為沿基質外圍表面6〇而成。電連接 之實施可與不滿密封層7 〇形成之同時，或在未滿之密封層 7 0形成之前實施，由再流動實施°不滿密封層之材料通常 係由球狀熔硅顆料填充之環氧樹脂構成，再由一般技術凝 固（即加熱）β此不滿密封層70可由已知之技術沉積，如在 至少在模具之一邊緣沉積此種材料，再依靠毛細管作用以 使材料進入半導體晶粒1 0及基質5 0之間之介面。
D:\Y87\55387.ptd 第9頁 423120 五、發明說明（6) 此外，所有多個電接點（即焊接沖擊2〇及UBM墊1 5 )均位 於基質50之外周圍之内。本發明之特殊特點在絕緣所有自 封裝半導體裝置以外之環境上特別優異。此外，本發明亦 可使在半導體晶粒及基質間之以CSP而非周圍結合之陣列 結合。此外，本發明之陣列結合（與利用周圍結合之CSPs 相比較）可有較大之尺寸差異於半導體晶粒及基質之間。 在已知之CSPs中，基質之尺寸之降低會引起模‘具及基質間 之不尋常長度之結合引線。此種長結合引線較目前使用之 周圍結合塑CSPs缺少相當短結合引線之熱穩定性，並且易 於損壞。 在圖1及2中之具體實例中’ A 5 8係在連接在半導體晶 粒10之前備於基質50之上’吾人了解㈣A球58可在連接在 半導體晶粒1 〇之後以較佳之晶圓格式或在模具單獨化之後 再連接在基質5 0上。根據圖1及2中之一具體實例，焊接沖 擊？0用來在以不滿之密封材料填充後，實施基質50與半導 體晶粒1 0間之電連接。不滿密封可同時形成作為電連接。 在此具體實例中，形成不滿密封層7 0之材料在放置基質之 後首先沉積於半導體晶粒之上。在隨後之程序中，沖擊2 〇 及D C A接合墊5 2 (以再流動方式）間之電連接及不滿密封層 7 0之安裝於是完成（即由凝固）。再流動及凝固可同時進 行。 參考圖3 ’其中顯示以晶圓形式封裝許多半導體晶粒之 平面圖。如圖3所示，許多半導體晶粒（此實例中為丨3 )均 同時封裝。基質之X’及Y，尺寸及半導體晶粒之χ及¥尺寸彼
D:\Y87\55387. ptd 第〗0頁 -23120
此垂直。此圖式中 之X尺寸，及（ii)技（ί)基質之Χ，尺寸小於半導體晶粒 但根據本發明，—質之γ’尺寸小於半導體晶粒之Υ尺寸。 導體晶粒之)ί或γ尺或另一χ’ ’尺寸可使其小於對應之半 1 0 2單獨化期間，寸。在此具體實例中，在模具沿切割街 時切割而離開與其延紐伸超過模具1 0邊緣之基質邊緣將被同 及Υ，尺寸均較ϋ質之邊緣對齊之模具邊緣。但，最好χ， 如圖3所示，半卜導體/曰粒之⑴尺寸為小。 模具彼此分開。晶粒10〇有一切割街102，其將個別 圖㈤之虛線所=刻衝102之材料實質上已被除去 如 練f6顯不本發明之另-具體實例，與圖卜3中之具 體：：相似。圖“中之半導體晶粒1〇為1〇 _平方，其有 T又為0.4 mm ’及有1〇〇個電接點。此基質之厚度為0.5 mm。雖然圖4-6實質上說明一相同之半導體晶粒丄〇，但有 三個不同之再分布計劃如所示者。 瓦先圖4中’顯示—進取之再分布計劃，其中有81個BGA 球5 8於一0 5 mm間距於5平方_基質上。圖5說明12〇個bga 球58安排在一7. 5平方mm之〇. 65 _間距上。最後，圖6說 明144個BGA球58安排在9·5平方·基質之080 mm間距間。 根據圖4，其中顯示一進取之再分布計劃，在基質5 〇上之 足跡最小化觀點上亦頗為優異。基質5 〇上之足跡最小化之 結果可使基質與連於其上之印刷電路板之間的連接可靠性 有大改進。如圖示，半導體晶粒丨〇之部分延伸超過及包圍 基質50並未造成BGA球與電路板限定之接點上之應力，該
D:\Y87\55387.ptd 第11頁 4 2 3 ’丨 2 Ο 五、發明說明（8) 應力係由於熱膨脹係數之不呸配而引起。延伸超過基質5 0 之邊緣之模具區域由圖3中所示之不滿密封層7〇之平邊72 所熱機械耦合至基質5 0。儘管此一優點’假定電路接點墊 在半導體晶粒1 0之外圍附近形成，如圖卜2之具體實例所 示，必須有一相當長之再分布網’其可能感應不理想之寄 生損失，亦可能在自半導體晶粒至基質之熱傳輸正有 不良景彡響。吾人應注意銷數目亦自1 〇 〇個電接點減為81個 電接點（模具與基質間）°此一降低之電接點數目係由使用 共同電源及接地平面’或基質中之平面片斷而達成Q 與圖1之進取性再分布計劃有關之設計上限制問題，較 高頻率及/或較高電源裝置需要較少之圖5及6中之進取性 再分布計劃。圖5及6提供數目增加之BGA球’其可改進電 性能及功率損耗。吾人注意所有具體實例均可與現代科括 之吸熱設備相容’如可連接在半導體晶粒10之無溽表面上 吸熱設備。 ' 如以上讨論者，非常明顯，本發明可提供一改進之-Λ>曰 片级封裝，其已根據現代科技提出數項需求。根據本^晶 明，不但在模具與基質間之互聯可靠性已獲得大幅改進， 基質與電路板間之互聯可靠性亦由於基質足跡之減少 舉提高◊關於此點，_真晶片級封裝不同，其中之基大 半導體晶雜之尺寸却同大小，本發明提供構成一不滿六〜 平片，其 < 將延伸超過基質邊緣之模具之區域覆蓋住/封 不會使基質之月斷在典型CSP中之此區域中與模具重疊’。而 此改進可顯杀出在基質與模具間’由於熱膨脹係赵 取 < 不匹
五、發明說明（9) 配而引起之應力降低。此外，與現代科技之次晶片級封裝 不同，本發明在製造上及實施上由於所揭示者之簡單結構 而合乎成本妹益。此外，因為基質尺寸已減小本發明提供 一方法可降低基質成本約%。尤有進者，本發明不需 要半導體製造者額外或更多設備費用，因為根據本發明之 原理，傳統之倒裝片封裝設備可以併入以構成封裝之半導 體裝置。本發明尚可作晶圓位準封裝’因此在—晶圓上之 所有半導體晶粒皆可同時封裝。 此外，本發明可在封裝期間提供增加之較高產量之輪 出。特別是與以往技藝不同，本發明之一具體實例之基質 係在單獨化為晶圓形式之前置於半導體晶粒上°由於半導 體晶粒在一晶圓上形成之精碟性，在晶圓上可形成高度準 確之基準，該晶圓與在其上之模具有確切之關係。一個適 切之圖像系統可偵出晶圓上之全面標準’因而可僅利用全 面標準即可提供極準破之基質放置於一錢別模具上。反 之’依照以在技藝’備有準備單獨化為許多基質之印刷電 路板’單獨化模具即連接其上^但，依照以往技藝，印刷 電路板係由相當低準確度全球標準而製成，其不能像本發 明一樣提供之晶圓之全球標準之對齊程度。由於视界系統 必須找出基質上之模具及本地標準。 吾人了解不同之改變均可實行而不致有悖本發明申請專 利範圍内之精神及範疇。例如，雖未示於圖式中，基質可 用單片方式，或數個多單元片斷方式連接一起，再與一全 晶圓重疊°順序之切割將可使基質'彼此分開。較偏愛使用
D:\Y87\55387.ptd 第13頁 423120 五、發明說明（ίο) 單基質係其可消除浪費及放置在先前測試之晶圓上基質之 成本。 1__1 D:\Y87\55387. ptd 第14頁

Claims (1)

  1. 4 23 12 0 ^ 索號^Ϊ87117327 巧年：？月^日 修正 _，、 六、申請專利範圍 1. 一種半導體裝置，包含： —半導體晶粒（10)，具有一表面、外圍X及外圍Υ尺 寸，半導體晶粒之外圍X及外圍Υ尺寸係彼此垂直； 多個位於半導體晶粒表面上之電接點（2 0 ); —封裝基質（5 0 )，重疊於半導體晶粒且與多個電接 點電氣連接； 其中：封裝基質具有彼此垂直之外圍X’及外圍Υ’尺 寸，至少符合下列二個條件之一（i )封裝基質之外圍X ’尺 寸小於半導體晶粒之外圍X尺寸，及（i i )封裝基質之外圍 Y ’尺寸小於半導體晶粒之外圍Y尺寸，及多個電接點係位 於封裝基質之外圍X尺寸及外圍Y尺寸之内。 2. 如申請專利範圍第1項之半導體裝置，尚包含一未充 滿之密封層（7 0 )位於半導體晶粒與基質之間。 3. 如申請專利範圍第2項之半導體裝置，其中之基質有 —外圍表面，及未充滿之密封層形成一平板圓角（7 2)沿基 質之外圍表面延伸。 4. 如申請專利範圍第1項之半導體裝置，其中半導體晶 粒尚包含許多安排在外圍附近之電接點及許多再分布執跡 自許多電路接點墊延伸至半導體晶粒之中央部分。 5. —種半導體裝置，包含： 一半導體晶粒，具有一表面、X及Y尺寸，半導體晶 粒之X、Y尺寸係彼此垂直； 多個位於半導體晶粒表面上電接點：及 一基質，於一第一外表面之導電部份與一第二外表 面之導電部份之間具有許多電氣連接，第一外表面位於第
    O:\55\55387.ptc 第1頁 2000.03. 28.015 ^ ^ Θ案號87117327_年j月^曰 修正_1_ 六、申請專利範圍 二外表面及半導體晶粒之表面之間且靠近第二外表面，其 中多個基質電氣連接之一係電氣連接至位於半導體晶粒表 面上多個電接點之至少一接點，其中基質之第一外表面有 彼此垂直之X’及Y’尺寸，且至少符合下列二個條件之一 (i)第一外表面基質之X’尺寸係小於半導體晶粒之X尺寸， 且（i i)第一外表面基質之Y’尺寸係小於半導體晶粒之Y尺 寸，此外，基質有一外周圍，且多個電接點係位於基質之 外周圍内。 6. 如申請專利範圍第5項之半導體裝置，其中許多電接 點位於該基質之外周圍之内。 7. 如申請專利範圍第5項之半導體裝置，尚包括一不滿 之密封層位於該基質及該半導體晶粒之間。 8. —種半導體裝置，包含： 沿著垂直於裝置表面之一第一線之第一截面成分， 及一沿著垂直於裝置表面之一第二線之第二載面成分； 自第一表面至第二表面，第一截面成分包含以下各 層： 一第一導電墊； 一絕緣層： 一密封層材料；及 一半導體晶粒；以及 自第一表面至第二表面，第二截面成分包含以下各 層： 形成第一表面之一部分之密封層材料：及 緊靠於密封層材料之半導體晶粒。
    O:\55\55387.ptc 第2頁 2000.03.28. 016
TW087117327A 1997-12-01 1998-10-20 Semiconductor device having a sub-chip-scale package structure and method for forming same TW423120B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/980,783 US6064114A (en) 1997-12-01 1997-12-01 Semiconductor device having a sub-chip-scale package structure and method for forming same

Publications (1)

Publication Number Publication Date
TW423120B true TW423120B (en) 2001-02-21

Family

ID=25527845

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087117327A TW423120B (en) 1997-12-01 1998-10-20 Semiconductor device having a sub-chip-scale package structure and method for forming same

Country Status (7)

Country Link
US (2) US6064114A (zh)
JP (1) JP4343296B2 (zh)
KR (1) KR100572813B1 (zh)
CN (1) CN1147928C (zh)
HK (1) HK1019819A1 (zh)
MY (1) MY123187A (zh)
TW (1) TW423120B (zh)

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6127245A (en) * 1997-02-04 2000-10-03 Micron Technology, Inc. Grinding technique for integrated circuits
US6403882B1 (en) * 1997-06-30 2002-06-11 International Business Machines Corporation Protective cover plate for flip chip assembly backside
JP3065010B2 (ja) * 1997-12-26 2000-07-12 日本電気株式会社 半導体装置
JPH11312749A (ja) * 1998-02-25 1999-11-09 Fujitsu Ltd 半導体装置及びその製造方法及びリードフレームの製造方法
JP3610787B2 (ja) * 1998-03-24 2005-01-19 セイコーエプソン株式会社 半導体チップの実装構造体、液晶装置及び電子機器
JP3941262B2 (ja) * 1998-10-06 2007-07-04 株式会社日立製作所 熱硬化性樹脂材料およびその製造方法
US6266249B1 (en) * 1998-10-20 2001-07-24 Lsi Logic Corporation Semiconductor flip chip ball grid array package
US6429530B1 (en) * 1998-11-02 2002-08-06 International Business Machines Corporation Miniaturized chip scale ball grid array semiconductor package
US7169643B1 (en) * 1998-12-28 2007-01-30 Seiko Epson Corporation Semiconductor device, method of fabricating the same, circuit board, and electronic apparatus
US6707159B1 (en) * 1999-02-18 2004-03-16 Rohm Co., Ltd. Semiconductor chip and production process therefor
JP3423897B2 (ja) * 1999-04-01 2003-07-07 宮崎沖電気株式会社 半導体装置の製造方法
US6191483B1 (en) * 1999-05-06 2001-02-20 Philips Electronics North America Corporation Package structure for low cost and ultra thin chip scale package
JP3872648B2 (ja) * 1999-05-12 2007-01-24 株式会社ルネサステクノロジ 半導体装置およびその製造方法並びに電子装置
JP3494593B2 (ja) * 1999-06-29 2004-02-09 シャープ株式会社 半導体装置及び半導体装置用基板
JP2001358250A (ja) * 2000-06-12 2001-12-26 Nec Corp 半導体装置
US6518097B1 (en) * 2000-08-29 2003-02-11 Korea Advanced Institute Of Science And Technology Method for fabricating wafer-level flip chip package using pre-coated anisotropic conductive adhesive
US7271491B1 (en) 2000-08-31 2007-09-18 Micron Technology, Inc. Carrier for wafer-scale package and wafer-scale package including the carrier
GB0021596D0 (en) * 2000-09-02 2000-10-18 Vlsi Vision Ltd Mounting electronic components
US6630725B1 (en) 2000-10-06 2003-10-07 Motorola, Inc. Electronic component and method of manufacture
US6312974B1 (en) * 2000-10-26 2001-11-06 Industrial Technology Research Institute Simultaneous bumping/bonding process utilizing edge-type conductive pads and device fabricated
US6611055B1 (en) * 2000-11-15 2003-08-26 Skyworks Solutions, Inc. Leadless flip chip carrier design and structure
JP4549366B2 (ja) * 2000-12-15 2010-09-22 イビデン株式会社 多層プリント配線板
TW472372B (en) * 2001-01-17 2002-01-11 Siliconware Precision Industries Co Ltd Memory module with direct chip attach and the manufacturing process thereof
KR100364635B1 (ko) * 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6737295B2 (en) * 2001-02-27 2004-05-18 Chippac, Inc. Chip scale package with flip chip interconnect
US7498196B2 (en) 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
US7115986B2 (en) * 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6657133B1 (en) * 2001-05-15 2003-12-02 Xilinx, Inc. Ball grid array chip capacitor structure
KR20020091327A (ko) * 2001-05-31 2002-12-06 삼성전자 주식회사 측면 몸체부가 형성되어 있는 웨이퍼 레벨 패키지 및 그제조 방법
US6869831B2 (en) * 2001-09-14 2005-03-22 Texas Instruments Incorporated Adhesion by plasma conditioning of semiconductor chip surfaces
US7323360B2 (en) * 2001-10-26 2008-01-29 Intel Corporation Electronic assemblies with filled no-flow underfill
US6963142B2 (en) * 2001-10-26 2005-11-08 Micron Technology, Inc. Flip chip integrated package mount support
KR100429856B1 (ko) * 2001-11-15 2004-05-03 페어차일드코리아반도체 주식회사 스터드 범프가 있는 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
SG104293A1 (en) 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
US6975035B2 (en) 2002-03-04 2005-12-13 Micron Technology, Inc. Method and apparatus for dielectric filling of flip chip on interposer assembly
SG115456A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
SG115459A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Flip chip packaging using recessed interposer terminals
SG121707A1 (en) 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
SG111935A1 (en) * 2002-03-04 2005-06-29 Micron Technology Inc Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
AU2003236251A1 (en) * 2002-04-17 2003-10-27 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for assembling the same
US20040036170A1 (en) * 2002-08-20 2004-02-26 Lee Teck Kheng Double bumping of flexible substrate for first and second level interconnects
US20040088855A1 (en) * 2002-11-11 2004-05-13 Salman Akram Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US20050012225A1 (en) * 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
US20050176233A1 (en) * 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US6906598B2 (en) 2002-12-31 2005-06-14 Mcnc Three dimensional multimode and optical coupling devices
US6885108B2 (en) * 2003-03-18 2005-04-26 Micron Technology, Inc. Protective layers formed on semiconductor device components so as to reduce or eliminate the occurrence of delamination thereof and cracking therein
US6946744B2 (en) * 2003-04-24 2005-09-20 Power-One Limited System and method of reducing die attach stress and strain
JP3906921B2 (ja) * 2003-06-13 2007-04-18 セイコーエプソン株式会社 バンプ構造体およびその製造方法
WO2005014374A1 (en) * 2003-08-08 2005-02-17 Motivation Design Llc Tire cover & carrier
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US20050104187A1 (en) * 2003-10-31 2005-05-19 Polsky Cynthia H. Redistribution of substrate interconnects
US20050133571A1 (en) * 2003-12-18 2005-06-23 Texas Instruments Incorporated Flip-chip solder bump formation using a wirebonder apparatus
WO2005088696A1 (en) * 2004-02-11 2005-09-22 Infineon Technologies Ag Semiconductor package with contact support layer and method to produce the package
US7185799B2 (en) * 2004-03-29 2007-03-06 Intel Corporation Method of creating solder bar connections on electronic packages
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
KR100609334B1 (ko) * 2005-06-13 2006-08-08 삼성전자주식회사 감광성 폴리머가 갭필된 적층 회로부재 및 그의 제조 방법
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
DE102005059189B3 (de) * 2005-12-12 2007-03-08 Infineon Technologies Ag Anordnung von Halbleiterspeichereinrichtungen sowie Halbleiterspeichermodul mit einer Anordnung von Halbleiterspeichereinrichtungen
CN100413067C (zh) * 2006-01-06 2008-08-20 日月光半导体制造股份有限公司 芯片封装结构与其晶圆级封装形成方法
US20080048321A1 (en) * 2006-08-24 2008-02-28 Ati Technologies Inc. Flip chip semiconductor assembly with variable volume solder bumps
KR100843213B1 (ko) * 2006-12-05 2008-07-02 삼성전자주식회사 메모리 칩과 프로세서 칩이 스크라이브 영역에 배열된관통전극을 통해 연결된 다중 입출력 반도체 칩 패키지 및그 제조방법
US20080205816A1 (en) * 2007-02-26 2008-08-28 Lu Daoqiang Daniel Integrating electrical layer on optical sub-assembly for optical interconnects
US7659151B2 (en) * 2007-04-12 2010-02-09 Micron Technology, Inc. Flip chip with interposer, and methods of making same
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
WO2009004522A1 (en) * 2007-06-29 2009-01-08 Koninklijke Philips Electronics N.V. Electrical contact for a cadmium tellurium component
JP5372346B2 (ja) * 2007-07-18 2013-12-18 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US7473586B1 (en) 2007-09-03 2009-01-06 Freescale Semiconductor, Inc. Method of forming flip-chip bump carrier type package
TWI394260B (zh) * 2007-10-31 2013-04-21 Adl Engineering Inc 具有多晶粒之半導體元件封裝結構及其方法
KR100979237B1 (ko) * 2008-01-08 2010-08-31 주식회사 하이닉스반도체 Ｂｇａ 패키지용 기판 및 그의 제조방법
US8169065B2 (en) * 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
JP2011146519A (ja) * 2010-01-14 2011-07-28 Panasonic Corp 半導体装置及びその製造方法
US8558392B2 (en) * 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
TWI460834B (zh) * 2010-08-26 2014-11-11 Unimicron Technology Corp 嵌埋穿孔晶片之封裝結構及其製法
US8368202B2 (en) * 2010-11-24 2013-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package having the same
US20120168956A1 (en) * 2011-01-04 2012-07-05 International Business Machines Corporation Controlling density of particles within underfill surrounding solder bump contacts
US8957518B2 (en) 2012-01-04 2015-02-17 Mediatek Inc. Molded interposer package and method for fabricating the same
US9237648B2 (en) 2013-02-25 2016-01-12 Invensas Corporation Carrier-less silicon interposer
JP6394052B2 (ja) 2013-05-13 2018-09-26 日亜化学工業株式会社 発光装置及びその製造方法
TWI544593B (zh) * 2013-09-09 2016-08-01 矽品精密工業股份有限公司 半導體裝置及其製法
US9240381B2 (en) * 2013-09-24 2016-01-19 Nanya Technology Corporation Chip package and method for forming the same
US9474162B2 (en) 2014-01-10 2016-10-18 Freescale Semiocnductor, Inc. Circuit substrate and method of manufacturing same
JP6316731B2 (ja) * 2014-01-14 2018-04-25 新光電気工業株式会社 配線基板及びその製造方法、並びに半導体パッケージ
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
US9484227B1 (en) * 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
US10211160B2 (en) 2015-09-08 2019-02-19 Invensas Corporation Microelectronic assembly with redistribution structure formed on carrier
US10516092B2 (en) * 2016-05-06 2019-12-24 Qualcomm Incorporated Interface substrate and method of making the same
US10120971B2 (en) * 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
US10522440B2 (en) * 2017-11-07 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148265A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5148266A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
JP2763020B2 (ja) * 1995-04-27 1998-06-11 日本電気株式会社 半導体パッケージ及び半導体装置
JP3387282B2 (ja) * 1995-08-03 2003-03-17 日産自動車株式会社 半導体装置の構造及びその製造方法
US5866939A (en) * 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
US5909056A (en) * 1997-06-03 1999-06-01 Lsi Logic Corporation High performance heat spreader for flip chip packages
US5847936A (en) * 1997-06-20 1998-12-08 Sun Microsystems, Inc. Optimized routing scheme for an integrated circuit/printed circuit board
US5866943A (en) * 1997-06-23 1999-02-02 Lsi Logic Corporation System and method for forming a grid array device package employing electomagnetic shielding
US5898223A (en) * 1997-10-08 1999-04-27 Lucent Technologies Inc. Chip-on-chip IC packages
JP3939847B2 (ja) * 1998-01-09 2007-07-04 シチズンホールディングス株式会社 半導体装置の製造方法
US5939783A (en) * 1998-05-05 1999-08-17 International Business Machines Corporation Electronic package
JP2000091880A (ja) * 1998-09-11 2000-03-31 Japan Radio Co Ltd フリップチップ型弾性波デバイス及びその製造方法

Also Published As

Publication number Publication date
US6064114A (en) 2000-05-16
JPH11233687A (ja) 1999-08-27
US6294405B1 (en) 2001-09-25
KR100572813B1 (ko) 2006-09-11
KR19990062634A (ko) 1999-07-26
CN1147928C (zh) 2004-04-28
MY123187A (en) 2006-05-31
JP4343296B2 (ja) 2009-10-14
HK1019819A1 (en) 2000-02-25
CN1219763A (zh) 1999-06-16

Similar Documents

Publication Publication Date Title
TW423120B (en) Semiconductor device having a sub-chip-scale package structure and method for forming same
US6291884B1 (en) Chip-size semiconductor packages
TWI357663B (en) Multiple chip package module having inverted packa
CN101221936B (zh) 具有晶粒置入通孔之晶圆级封装及其方法
TWI482261B (zh) 三維系統級封裝堆疊式封裝結構
US7560302B2 (en) Semiconductor device fabricating method
US7078264B2 (en) Stacked semiconductor die
TWI272705B (en) Heat spreader and package structure utilizing the same
CN107768351A (zh) 具有热机电芯片的半导体封装件及其形成方法
US20110209908A1 (en) Conductor package structure and method of the same
TW200905755A (en) Wafer level package structure and fabrication methods
US7498203B2 (en) Thermally enhanced BGA package with ground ring
US9548220B2 (en) Method of fabricating semiconductor package having an interposer structure
JP2001320013A (ja) 半導体装置およびその製造方法
CN104716103A (zh) 具有间隙的底部填充图案
TW200845343A (en) Semiconductor device package having multi-chips with side-by-side configuration and the method of the same
US6911737B2 (en) Semiconductor device package and method
TWI488270B (zh) 半導體封裝件及其製法
JP2004079716A (ja) 半導体用ｃｓｐ型パッケージ及びその製造方法
US6373125B1 (en) Chip scale package with direct attachment of chip to lead frame
WO2023241304A1 (zh) 芯片封装方法及芯片
US20110031607A1 (en) Conductor package structure and method of the same
JP3547303B2 (ja) 半導体装置の製造方法
JPH0855875A (ja) 半導体装置
TW201405733A (zh) 半導體封裝件及其製法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees