TW421883B - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

Info

Publication number
TW421883B
TW421883B TW088111875A TW88111875A TW421883B TW 421883 B TW421883 B TW 421883B TW 088111875 A TW088111875 A TW 088111875A TW 88111875 A TW88111875 A TW 88111875A TW 421883 B TW421883 B TW 421883B
Authority
TW
Taiwan
Prior art keywords
circuit
voltage
wiring
power supply
semiconductor integrated
Prior art date
Application number
TW088111875A
Other languages
English (en)
Chinese (zh)
Inventor
Yoshirou Toho
Kiyoshi Nakai
Hidekazu Egawa
Yukie Suzuki
Isamu Fujii
Original Assignee
Hitachi Ulsi Sys Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ulsi Sys Co Ltd, Hitachi Ltd filed Critical Hitachi Ulsi Sys Co Ltd
Application granted granted Critical
Publication of TW421883B publication Critical patent/TW421883B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW088111875A 1998-08-27 1999-07-13 Semiconductor integrated circuit device TW421883B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24160798A JP4079522B2 (ja) 1998-08-27 1998-08-27 半導体集積回路装置

Publications (1)

Publication Number Publication Date
TW421883B true TW421883B (en) 2001-02-11

Family

ID=17076844

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088111875A TW421883B (en) 1998-08-27 1999-07-13 Semiconductor integrated circuit device

Country Status (4)

Country Link
US (2) US6411160B1 (https=)
JP (1) JP4079522B2 (https=)
KR (1) KR100646209B1 (https=)
TW (1) TW421883B (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002016238A (ja) * 2000-06-29 2002-01-18 Mitsubishi Electric Corp 半導体装置
KR100400311B1 (ko) * 2001-06-29 2003-10-01 주식회사 하이닉스반도체 반도체 메모리 소자의 신호 지연 제어 장치
US6664589B2 (en) * 2001-08-30 2003-12-16 Micron Technology, Inc. Technique to control tunneling currents in DRAM capacitors, cells, and devices
JP3786608B2 (ja) * 2002-01-28 2006-06-14 株式会社ルネサステクノロジ 半導体集積回路装置
US7055069B2 (en) * 2002-08-23 2006-05-30 Infineon Technologies Ag Spare input/output buffer
US6969909B2 (en) 2002-12-20 2005-11-29 Vlt, Inc. Flip chip FET device
US7615822B1 (en) 2002-12-23 2009-11-10 Volterra Semiconductor Corporation Diffused drain transistor
US7038917B2 (en) * 2002-12-27 2006-05-02 Vlt, Inc. Low loss, high density array interconnection
FR2853475B1 (fr) * 2003-04-01 2005-07-08 Atmel Nantes Sa Circuit integre delivrant des niveaux logiques a une tension independante de la tension d'alimentation, sans regulateur associe pour la partie puissance, et module de communication correspondant
US7163856B2 (en) 2003-11-13 2007-01-16 Volterra Semiconductor Corporation Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor
US7220633B2 (en) * 2003-11-13 2007-05-22 Volterra Semiconductor Corporation Method of fabricating a lateral double-diffused MOSFET
US7074659B2 (en) * 2003-11-13 2006-07-11 Volterra Semiconductor Corporation Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor
JP4364226B2 (ja) * 2006-09-21 2009-11-11 株式会社東芝 半導体集積回路
US7663908B2 (en) * 2007-03-12 2010-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method for increasing retention time in DRAM
US7663953B2 (en) * 2007-03-12 2010-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method for high speed sensing for extra low voltage DRAM
US8830784B2 (en) 2011-10-14 2014-09-09 Taiwan Semiconductor Manufacturing Co., Ltd. Negative word line driver for semiconductor memories
US8624632B2 (en) 2012-03-29 2014-01-07 International Business Machines Corporation Sense amplifier-type latch circuits with static bias current for enhanced operating frequency
US9196375B2 (en) 2013-07-05 2015-11-24 Kabushiki Kaisha Toshiba Semiconductor storage device
US20200350263A1 (en) * 2019-04-30 2020-11-05 Nxp B.V. Semiconductor devices with security features

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05174578A (ja) * 1991-12-24 1993-07-13 Mitsubishi Electric Corp 半導体装置
JP3869045B2 (ja) * 1995-11-09 2007-01-17 株式会社日立製作所 半導体記憶装置
JP2919365B2 (ja) * 1996-06-27 1999-07-12 日本電気アイシーマイコンシステム株式会社 Ｍｏｓトランジスタの容量設計方法
JP2000049305A (ja) * 1998-07-28 2000-02-18 Hitachi Ltd 半導体記憶装置

Also Published As

Publication number Publication date
KR100646209B1 (ko) 2006-11-17
JP4079522B2 (ja) 2008-04-23
KR20000017436A (ko) 2000-03-25
US20020130714A1 (en) 2002-09-19
US6518835B2 (en) 2003-02-11
US6411160B1 (en) 2002-06-25
JP2000077623A (ja) 2000-03-14

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MK4A Expiration of patent term of an invention patent